Dynamic Memory Offline and Voltage Scaling

Abstract

This application relates to dynamic memory offline and voltage scaling. Embodiments of a semiconductor packaging device may include techniques to independently bring a first memory power node into one of online and offline based on a runtime memory control signal, and to independently bring a second memory power node into one of online and offline based on the runtime memory control signal. Other embodiments are disclosed and claimed.

Description

Technical Field

[0001] Embodiments generally relate to memory systems, and more particularly, embodiments relate to dynamic memory offline and voltage scaling. Background Art

[0002] A memory subsystem may include a dual in-line memory module (DIMM). In a server, the number of DIMMs in a memory subsystem may consume a large amount of power. Brief Description of the Drawings

[0003] By reading the following description and the appended claims and by referring to the following drawings, various advantages of embodiments will become apparent to those of ordinary skill in the art, in which:

[0004] Figure 1 is a block diagram of an example of a memory system according to an embodiment;

[0005] Figure 2 is a block diagram of an example of a semiconductor package device according to an embodiment;

[0006] Figures 3A to 3C is a flowchart of an example of a method of controlling a memory according to an embodiment;

[0007] Figure 4 is a block diagram of an example of a memory controller device according to an embodiment;

[0008] Figures 5A to 5B is a block diagram of an example of an electronic processing system according to an embodiment;

[0009] Figure 6 is a flowchart of an example of a method of taking a memory power node offline according to an embodiment;

[0010] Figure 7 is a flowchart of an example of a method of bringing a memory power node online according to an embodiment;

[0011] Figure 8 is a flowchart of an example of a method of voltage scaling a memory power node according to an embodiment; and

[0012] Figure 9 is an illustrative diagram of an example of a memory power state configuration table according to an embodiment. Detailed Description

[0013] The various embodiments described herein may include memory components and / or interfaces to memory components. Such memory components may include volatile and / or non-volatile memory. Non-volatile memory may be a storage medium that does not require power to maintain the state of data stored by the medium. In one embodiment, the memory device may include a block-addressable memory device, such as a memory device based on NAND or NOR technology. The memory device may also include: next-generation non-volatile devices such as three-dimensional cross-point memory devices, or other byte-addressable write-in-place non-volatile memory devices. In one embodiment, the memory device may be or may include: a memory device using chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), PCM with switches (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory with hybrid memristor technology, resistive memory including metal-oxide-based, oxygen-vacancy-based, and conductive-bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, devices based on spin-transfer-torque magnetic junction memory, devices based on magnetic tunnel junctions (MTJs), devices based on DW (domain wall) and SOT (spin-orbit transfer), thyristor-based memory devices, or any combination of the above, or other memories. The memory device may refer to the die itself and / or to a packaged memory product. In a particular embodiment, a memory component having non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standards (the JEDEC standards cited herein are available at jedec.org).

[0014] A volatile memory can be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memories can include various types of random access memories (RAMs), such as dynamic random access memories (DRAMs) or static random access memories (SRAMs). A specific type of DRAM that can be used in a memory module is synchronous dynamic random access memory (SDRAM). In a particular embodiment, the DRAM of the memory component can comply with standards promulgated by JEDEC, such as JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for low power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) can be referred to as DDR-based standards, and the communication interface of a storage device that implements such standards can be referred to as a DDR-based interface.

[0015] Turning now to Figure 1 , an embodiment of the memory system 10 can include a first memory power node (MPN) 11 (e.g., including a first set of one or more memory devices 11a to 11n), a first power source 12 coupled to the first MPN 11, a second MPN 13 (e.g., including a second set of one or more memory devices 13a to 13n), a second power source 14 coupled to the second MPN 13, and logic 15 that is coupled to the first MPN 11 and the second MPN 13 to independently bring the first MPN 11 online or offline based on a runtime memory control signal 16 and independently bring the second MPN 13 online or offline based on the runtime memory control signal 16. For example, the first power source 12 can be coupled to the first MPN11 with a first voltage rail, and the second power source 14 can be coupled to the second MPN 13 with a second voltage rail. In some embodiments, a memory power node (MPN) can refer to a set of memory devices that are all connected to the same voltage rail (e.g., and can power and / or control the set of memory devices independently of other MPNs).

[0016] In some embodiments of the memory system 10, the logic 15 may be further configured to scale the voltage provided to one or more of the first MPN 11 and the second MPN 13 based on the runtime memory control signal 16, and / or scale the operating frequency provided to one or more of the first MPN 11 and the second MPN 13 based on the runtime memory control signal 16. For example, the runtime memory control signal 16 may be based on the memory power state (e.g., as described in more detail herein). In some embodiments, the memory device may include a non-volatile memory (NVM) device, such as a non-volatile random access memory (NVRAM) device. Some embodiments of the memory system 10 may include additional third MPNs 17c to Nth MPNs 17 N independently powered by respective power sources 18c to 18 N (e.g., N>2, where each additional MPN includes one or more memory devices). The logic 15 may be further configured to bring the additional MPNs 17c to 17 N online / offline based on the runtime memory control signal 16, and / or also scale the voltage and / or operating frequency for the additional MPNs 17c to 17 N . For example, each of the first MPN 11, the second MPN 13, the third MPN 17c to the Nth MPN 17 N may be located on the same substrate (e.g., the same printed circuit board).

[0017] Embodiments of each of the above MPNs, power sources, logic 15, and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, a hardware implementation may include configurable logic, such as a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or fixed functional logic hardware using circuit technologies such as application specific integrated circuits (ASICs), complementary metal oxide semiconductors (CMOS), or transistor-transistor logic (TTL) technologies or any combination thereof.

[0018] Alternatively or additionally, all or part of these components may be implemented as a set of logic instructions in one or more modules, which are stored in a machine or computer-readable storage medium such as RAM, read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc. for execution by a processor or computing device. For example, the computer program code for performing the operations of the components can be written in any combination of one or more operating system (OS)-applicable / appropriate programming languages, including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and traditional procedural programming languages such as the "C" programming language or similar programming languages. For example, a memory device, a permanent storage medium, or other system memory may store a set of instructions that, when executed by a processor, cause the memory system 10 to implement one or more components, features, or aspects of the system 10 (e.g., logic 15, bringing a power memory node online, bringing a power memory node offline, voltage scaling, frequency scaling, etc.).

[0019] Turning now to Figure 2 , an embodiment of the semiconductor package device 20 may include a substrate 21 and logic 22 coupled to the substrate 21, where the logic 22 is implemented at least in part in one or more of configurable logic and fixed functional hardware logic. The logic 22 coupled to the substrate may be configured to: independently bring a first MPN into one of online and offline based on a runtime memory control signal, and independently bring a second MPN into one of online and offline based on a runtime memory control signal. In some embodiments, the logic may be further configured to: scale the voltage provided to one or more of the first and second MPNs based on a runtime memory control signal, and / or scale the operating frequency provided to one or more of the first and second MPNs. For example, the runtime memory control signal may be based on the memory power state. In some embodiments, the first and second MPNs may each include one or more NVM devices (e.g., NVRAM devices). For example, the first MPN may be coupled to a first voltage rail, while the second MPN may be coupled to a second voltage rail. The logic 22 may be configured (e.g., or configurable) to control additional power memory nodes for online, offline, voltage scaling, and / or frequency scaling.

[0020] Embodiments of the logic 22 of the apparatus 20 and other components may be implemented in hardware, software, or any combination thereof that at least includes a partial implementation using hardware. For example, a hardware implementation may include configurable logic, such as, for example, a PLA, FPGA, CPLD, or fixed functional logic hardware using circuit technologies, such as, for example, ASIC, CMOS, or TTL technology or any combination thereof. Additionally, portions of these components may be implemented as a set of logic instructions in one or more modules that are stored in a machine or computer-readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code for performing the operations of the components may be written in any combination of one or more OS-applicable / suitable programming languages, which include object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., as well as traditional procedural programming languages such as the "C" programming language or similar programming languages.

[0021] Turning now to Figures 3A to 3C , embodiments of a method 30 for controlling a memory may include: at block 31, independently introducing a first MPN into one of online and offline based on a runtime memory control signal, and at block 32, independently introducing a second MPN into one of online and offline based on a runtime memory control signal. The method 30 may further include: at block 33, scaling a voltage provided to one or more of the first and second MPNs based on a runtime memory control signal, and at block 34, scaling an operating frequency provided to one or more of the first and second MPNs based on a runtime memory control signal. For example, at block 35, the runtime memory control signal may be based on a memory power state. Some embodiments of the method 30 may include: at block 36, providing one or more NVM devices for each of the first and second MPNs, at block 37, coupling the first MPN to a first voltage rail, and at block 38, coupling the second MPN to a second voltage rail.

[0022] Embodiments of method 30 can be implemented in systems, apparatuses, computers, devices, etc. (e.g., such as those described herein). More particularly, hardware implementations of method 30 can include configurable logic, such as, for example, PLA, FPGA, CPLD, or in fixed functional logic hardware using circuit technologies (such as, for example, ASIC, CMOS, or TTL technology or any combination thereof). Alternatively or additionally, method 30 can be implemented in one or more modules as a set of logic instructions stored in a machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. to be executed by a processor or computing device. For example, computer program code for performing the operations of the execution components can be written in any combination of one or more OS-applicable / suitable programming languages, including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and traditional procedural programming languages such as the "C" programming language or similar programming languages.

[0023] For example, method 30 can be implemented on a computer-readable medium as described in Examples 19 to 24 below. Embodiments or portions of method 30 can be implemented with firmware, an application (e.g., via an application programming interface (API)), or driver software running on an operating system (OS).

[0024] Turning now to Figure 4 , some embodiments can be logically or physically arranged as one or more modules. For example, an embodiment of memory controller 40 can include a power controller 41, a voltage scaler 42, and a frequency scaler 43. Power controller 41 can be configured to: based on the runtime memory control signal 44, independently bring any one of the N MPNs (e.g., where N>1) online or offline. Voltage scaler 42 can be configured to: based on the runtime memory control signal 44, scale the voltage supplied to one or more of the N MPNs. Frequency scaler 43 can be configured to: based on the runtime memory control signal 44, scale the operating frequency supplied to one or more of the N MPNs. For example, the runtime memory control signal 44 can be based on the memory power state. In some embodiments, each of the N MPNs can include one or more NVRAM devices. For example, each of the N MPNs can be coupled to N voltage rails respectively.

[0025] Embodiments of the power controller 41, voltage scaler 42, frequency scaler 43, and other components of the memory controller 40 may be implemented using hardware, software, or any combination thereof that at least includes a hardware-implemented portion. For example, a hardware implementation may include configurable logic such as, for example, a PLA, FPGA, CPLD, or fixed-functional logic hardware using circuit technologies such as, for example, ASIC, CMOS, or TTL technology or any combination thereof. Additionally, portions of these components may be implemented as a set of logic instructions stored in a machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. for execution by a processor or computing device. For example, computer program code for performing the operations of the components may be written in any combination of one or more OS-applicable / suitable programming languages, including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and traditional procedural programming languages such as the "C" programming language or similar programming languages.

[0026] By taking the memory device offline and / or voltage scaling the memory device, some embodiments may advantageously provide memory power savings for 3D cross-point memory technologies (e.g., INTEL 3D XPOINT). By voltage scaling and / or frequency scaling the memory device (e.g., where such a device supports voltage / frequency scaling), some embodiments may also advantageously provide better 3D XPOINT performance. Similarly, by taking the DRAM memory device offline and / or voltage scaling the memory device, some embodiments may advantageously provide memory power savings for other DRAM memory technologies. By voltage scaling and / or frequency scaling the DRAM device (e.g., where such a device supports voltage / frequency scaling), some embodiments may also advantageously provide better DRAM performance.

[0027] Without being limited to a particular application, some memory subsystems of large memory servers can have high power consumption during runtime and in the idle power state. For example, servers for a business or enterprise that operates primarily during business hours (e.g., 9 to 5) can spend a significant percentage of time idle. Memory that is not used by the operating system can also consume excessive power while the system is running. Some embodiments can advantageously organize and / or arrange 3D XPOINT integrated circuits (ICs) hierarchically and power that hierarchy with independent voltage rails (e.g., all voltage rails can be generated from a monolithic multi-rail integrated voltage regulator). A control signal bus (e.g., a serial voltage identification (SVID) bus) can then provide appropriate control signals to a memory controller to perform 3D XPOINT offlining, voltage scaling, and / or frequency scaling. For example, the memory controller can coordinate voltage scaling with clock frequency scaling to increase memory throughput or reduce power consumption. Advantageously, some embodiments can increase the long-term reliability of 3D XPOINT technology memory devices.

[0028] In some embodiments, a dual in-line memory module (DIMM) can be configured to: take offline unwanted 3D XPOINT DRAM ICs (e.g., grouped hierarchically) based on an OS request during runtime, turn the 3D XPOINT ICs back online as needed, and scale the 3D XPOINT IC operating voltage / clock frequency to reduce power consumption or improve performance. As described in more detail herein, the DIMM can include a power architecture to power individual or groups of 3D XPOINT ICs to enable voltage / frequency scaling and offlining / onlining.

[0029] Now turning to Figures 5A to 5B, an embodiment of the electronic processing system 50 may include a DIMM 51 communicatively coupled to a central processing unit (CPU) 52 via a management bus 53 (e.g., SVID bus). The DIMM may include a plurality of 3D XPOINT (3DXP) ICs 54a - 54k organized into four ranks. The first rank may include ICs 54a, 54b, and 54c. The second rank may include ICs 54d and 54e. The third rank may include ICs 54f, 54g, and 54h. The fourth rank may include ICs 54i, 54j, and 54k. For example, each of the first through fourth ranks may correspond to an MPN as discussed above. The DIMM 51 may include power pins, including a 12V pin 55 coupled to a 12V power supply and a 12V standby power supply, respectively. The 12V power pin 55 may be coupled to a voltage regulator 56 (e.g., a monolithic multi - rail integrated voltage regulator) configured to provide a standby rail voltage and individual rail voltages (e.g., rail voltages #1 - #4) for each rank. The management bus 53 may be connected to a pin 57 (e.g., a pin reserved for future use (RFU)) that may be coupled to the voltage regulator 56. The DIMM 51 may further include a memory controller 58 (e.g., configured to implement one or more aspects of the embodiments described herein).

[0030] In some embodiments, the OS may decide during runtime to free up unneeded memory space and may notify the basic input / output system (BIOS) to take the associated rank on a given memory controller offline. All 3DXP ICs on that rank may then be powered off or enter a low - power mode where only the IC I / O buffers are powered by the standby rail. The monolithic multi - rail integrated voltage regulator may supply power to each rank (e.g., which may include one or more 3DXP ICs). The DIMM 51 may alternatively be implemented with a single IC per rail or other quantities of multiple 3DXP ICs per voltage rail (e.g., if those ICs are powered up together to maintain functionality, maximize performance, etc. for space efficiency). A standby rail may be provided in some embodiments to power only the I / O buffers in the offline mode and thus consume reduced or minimal power. In some embodiments, a low - current standby rail (e.g., <1mA / IC) may be routed from the motherboard to the DIMM 51.

[0031] Now turning to Figure 6, embodiments of method 60 for dynamically taking an MPN offline may include: at block 61, the OS estimates the workload and determines that some memory allocations may be freed. Method 60 may then at block 62 determine whether the memory addresses to be freed contain any data, and if so, at block 63, cause the OS to migrate the data from the memory space to be taken offline to other memory segments. If the memory to be taken offline at block 62 (or after migrating the data at block 63) does not contain data, at block 64, the OS may issue a command to the BIOS to take the memory offline. For example, the Advanced Configuration and Power Interface (ACPI) specification (e.g., version 6.2, published in May 2017 at www.uefi.org / sites / default / files / resources / ACPI_6_2.pdf) may define the format for configuration tables. In some embodiments, at block 64, the offline command may be issued via an extension specified in a configuration table such as an ACPI table. This may invoke a System Management Interrupt (SMI) to complete the offline process. At block 65, the BIOS may then configure the memory controller to enact the specified power state. This may involve reconfiguring the system address decoder to remove the relevant memory portions residing in the offline 3D XPOINT IC from the system address map. At block 66, the BIOS may then communicate with the CPU, and the CPU may send commands via the power management bus (e.g., SVID) to take the voltage regulator rails associated with one or more target 3DXP ICs offline. At block 67, the BIOS may then interact with platform components to prepare the memory sub - section for

[0032] removal of power (e.g., disable the clock, assert a reset to the affected components, etc.), and simultaneously at block 68, the BIOS may notify the Baseboard Management Controller (BMC) that the memory is being taken offline so that the BMC can adjust thermal parameters.

[0033] Now turning to Figure 7 , embodiments of method 70 for dynamically bringing an MPN online may include: at block 71, the OS estimates the workload and determines that additional memory is needed. At block 72, the OS may issue a command to the BIOS (e.g., via an extension defined in an ACPI table) to bring the offline memory (e.g., one or more 3DXP ICs) back to the active memory state. At block 73, the BIOS may communicate with the CPU to enable the associated voltage regulator rails. At block 74, the CPU may also optionally enable a fast pre - charge circuit to pre - charge the output of the voltage rails to reduce turn - on time. At block 75, the BIOS may then re - initialize the MPN as needed to bring the MPN back to the active state, configure the system address decoder at block 76 to put the MPN back into the system map, and at block 77 notify the OS (e.g., via the ACPI mailbox) that the MPN is ready for use.

[0034] Now turning to Figure 8 ,an embodiment of method 80 for voltage scaling for MPN may include: at block 81, the OS estimates the workload and determines whether a power saving feature can be invoked. At block 82, the OS may issue a command to the BIOS to enter a special memory power state (e.g., as described in more detail below). For example, the memory power state may be defined in a configuration table such as an extension to the ACPI table. For example, the extension to the memory power state may define voltage / frequency states at a granularity of one rank / MPN to reduce power and / or increase throughput. In some embodiments, the command from the CPU to the BIOS may invoke an SMI to change the memory power state. At block 83, the BIOS may then configure the memory controller to enact the specified memory power state, and at block 84, the CPU may communicate with the DIMM voltage regulator controller (e.g., via SVID or other protocol) to scale the voltage. At block 85, the CPU may also communicate with the DIMM voltage regulator controller to indicate a new voltage level for marginalized MNPs.

[0035] Some embodiments may advantageously provide power management for implementations in a data center. For example, some embodiments may provide reduced idle memory power (e.g., or even reduced power during full operation when the workload does not require all of the memory). In certain applications, a server may spend a significant amount of time in an idle mode. Selectively taking some memory offline according to some embodiments may provide significant power savings in a data center. If the data center includes DIMMs with 3D cross-point technology, some embodiments may increase the mean time between failures (MTBF) of the DIMMs and thus provide long-term reliability and service life. When the data center workload warrants increased performance, some embodiments may support voltage / frequency scaling to increase memory throughput.

[0036] Some embodiments may advantageously provide a memory power state structure for 3D XPOINT-based DIMMs. As noted above, due to the significant power consumption by the memory subsystem (e.g., the memory subsystem may represent approximately half of the idle power in a 4-slot server), the idle power consumption in a server with a high memory footprint may be relatively high. Some embodiments may advantageously provide a structure for the memory power state (MPS) that can reduce the granularity of memory power management to the level of one rank or MPN (e.g., relative to the entire CPU integrated memory controller for the full memory subsystem, riser, half-riser, etc.).

[0037] As discussed herein, the MPN structure can have a finer granularity, which can descend to the level of the memory hierarchy (e.g., a single 3DXP IC or a collection of 3DXP ICs). Advantageously, in some embodiments, the MPN can be power managed by hardware independent of the OS or integrated into an OS-booted configuration and power management (OSPM) environment.

[0038] Turning now to Figure 9 , embodiments of the configuration table can define one or more MPSs. State values can be associated with the corresponding cases. For example, the MPS0 state can correspond to a case where the MPN is online and the memory voltage can be set to its nominal operating voltage. In the MPS0 state, the clock frequency bin can be set to the same value as the power-on reset (POR) value. The MPS0 state can represent a normal operation mode, without performance boost or offline (or power saving). The MPS1 state can correspond to a case where the MPN is offline and one or more ICs can be used in the persistent mode. For example, when the MPN returns online, the data stored in the NVM can be retrieved. Since one or more ICs can be powered off (or in a low-power standby mode), the MPS1 state can provide some power savings. In some embodiments, the latency for transitioning from the MPS1 state to the MPS0 state can be a few milliseconds (e.g., <3ms). The MPS2 to MPS4 states can be reserved for future use and may not have defined associated cases. The MPS5 state can correspond to a case where the MPN is offline and the data is not saved. For example, one or more ICs can be used in the memory mode (e.g., which can correspond to the system S5 state). Since one or more ICs can be powered off (or in a low-power standby mode), the MPS5 state can provide some power savings. In some embodiments, the latency for transitioning from the MPS5 state to the MPS0 state can be on the order of milliseconds (e.g., <2ms). Some embodiments can include more or fewer states, and / or can have different cases associated with the states.

[0039] In some embodiments, the MPN can represent the smallest storage block in a 3D XPOINT-based DIMM (e.g., the smallest number of 3D XPOINT ICs that can be powered off and on independently) that can be offline, online, or marginalized. All MPNs can be powered by separate voltage rails and controlled according to the MPS. DIMM 51 is an example of a space-optimized arrangement of individually powered 3DXPOINT ICs with individual voltage rails. Fine-grained power management for the MPN can be allocated on a per-node basis in combination with Figure 9The MPS being discussed. In some embodiments, the MPS configuration table can be an extension of or linked to the ACPI memory power structure and is processed with the same considerations for all ACPI MPST features (e.g., each 3D XPOINT-based MPN can be powered on in any ACPI state (self-refresh, CKE, etc.)).

[0040] Some embodiments can advantageously provide finer-grained control of memory power in the idle state (or in the case of reduced workload). In some traditional four-slot (4S) servers, the minimum power consumed by a DIMM can be approximately 8W. Some embodiments can organize DIMMs in MPNs and can advantageously place many or all MPNs in the MPS1 state that can consume approximately 0.5W when idle or under low load (e.g., saving approximately 7.5W). Some embodiments can also reduce the voltage under low workload for additional power savings. Voltage margining can be done within tens of millivolts (e.g., approximately 30mV) to stay within the specifications required by the DDR4 physical layer.

[0041] Additional annotations and examples:

[0042] Example 1 can include a memory system including: a first memory power node including a first group of one or more memory devices, a first power source coupled to the first memory power node, a second memory power node including a second group of one or more memory devices, a second power source coupled to the second memory power node, and logic coupled to the first memory power node and the second memory power node to independently bring the first memory power node into one of online and offline based on a runtime memory control signal and independently bring the second memory power node into one of online and offline based on the runtime memory control signal.

[0043] Example 2 can include the system of Example 1, wherein the logic is further configured to: scale the voltage provided to one or more of the first and second memory power nodes based on the runtime memory control signal.

[0044] Example 3 can include the system of Example 1, wherein the logic is further configured to: scale the operating frequency provided to one or more of the first and second memory power nodes based on the runtime memory control signal.

[0045] Example 4 can include the system of any one of Examples 1 to 3, wherein the runtime memory control signal is based on the memory power state.

[0046] Example 5 can include the system of any one of Examples 1 to 3, wherein the memory devices include non-volatile memory devices.

[0047] Example 6 may include the system of any one of Examples 1 to 3, wherein the first power source is coupled to the first memory power node with a first voltage rail, and wherein the second power source is coupled to the second memory power node with a second voltage rail.

[0048] Example 7 may include a semiconductor package device including a substrate and logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic and fixed functional hardware logic, and the logic is coupled to the substrate to independently bring the first memory power node online or offline based on a runtime memory control signal and independently bring the second memory power node online or offline based on a runtime memory control signal.

[0049] Example 8 may include the device of Example 7, wherein the logic is further configured to: scale the voltage supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

[0050] Example 9 may include the device of Example 7, wherein the logic is further configured to: scale the operating frequency supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

[0051] Example 10 may include the device of any one of Examples 7 to 9, wherein the runtime memory control signal is based on a memory power state.

[0052] Example 11 may include the device of any one of Examples 7 to 9, wherein each of the first and second memory power nodes includes one or more non-volatile memory devices.

[0053] Example 12 may include the device of any one of Examples 7 to 9, wherein the first memory power node is coupled to a first voltage rail, and wherein the second memory power node is coupled to a second voltage rail.

[0054] Example 13 may include a method of controlling a memory, including: independently bringing the first memory power node online or offline based on a runtime memory control signal, and independently bringing the second memory power node online or offline based on a runtime memory control signal.

[0055] Example 14 may include the method of Example 13, further including: scaling the voltage supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

[0056] Example 15 may include the method of Example 13, further including: scaling the operating frequency supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

[0057] Example 16 may include the method of any one of Examples 13 to 15, wherein the runtime memory control signal is based on the memory power state.

[0058] Example 17 may include the method of any one of Examples 13 to 15, further comprising: providing one or more non-volatile memory devices for each of the first and second memory power nodes.

[0059] Example 18 may include the method of any one of Examples 13 to 15, further comprising: coupling the first memory power node to a first voltage rail and coupling the second memory power node to a second voltage rail.

[0060] Example 19 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to: independently bring the first memory power node into one of online and offline based on the runtime memory control signal, and independently bring the second memory power node into one of online and offline based on the runtime memory control signal.

[0061] Example 20 may include the at least one computer-readable medium of Example 19, comprising a further set of instructions that, when executed by a computing device, cause the computing device to: scale the voltage supplied to one or more of the first and second memory power nodes based on the runtime memory control signal.

[0062] Example 21 may include the at least one computer-readable medium of Example 19, comprising a further set of instructions that, when executed by a computing device, cause the computing device to: scale the operating frequency supplied to one or more of the first and second memory power nodes based on the runtime memory control signal.

[0063] Example 22 may include the at least one computer-readable medium of any one of Examples 19 to 21, wherein the runtime memory control signal is based on the memory power state.

[0064] Example 23 may include the at least one computer-readable medium of any one of Examples 19 to 21, comprising a further set of instructions that, when executed by a computing device, cause the computing device to: provide one or more non-volatile memory devices for each of the first and second memory power nodes.

[0065] Example 24 may include the at least one computer-readable medium of any one of Examples 19 to 21, comprising a further set of instructions that, when executed by a computing device, cause the computing device to: couple the first memory power node to a first voltage rail and couple the second memory power node to a second voltage rail.

[0066] Example 25 may include a memory controller device including: means for independently bringing a first memory power node into one of online and offline based on a runtime memory control signal, and means for independently bringing a second memory power node into one of online and offline based on a runtime memory control signal.

[0067] Example 26 may include the apparatus of Example 25, further including: means for scaling a voltage supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

[0068] Example 27 may include the apparatus of Example 25, further including: means for scaling an operating frequency supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

[0069] Example 28 may include the apparatus of any one of Examples 25 to 27, wherein the runtime memory control signal is based on a memory power state.

[0070] Example 29 may include the apparatus of any one of Examples 25 to 27, further including: means for providing one or more non-volatile memory devices for each of the first and second memory power nodes.

[0071] Example 30 may include the apparatus of any one of Examples 25 to 27, further including: means for coupling the first memory power node to a first voltage rail, and means for coupling the second memory power node to a second voltage rail.

[0072] Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of such IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoC), SSD / NAND controller ASICs, and the like. Additionally, in some of the figures, signal conductors are represented by lines. Some may be different to indicate more component signal paths, have number labels to indicate the numbers of the component signal paths, and / or have arrows at one or more ends to indicate the primary information flow direction. However, this should not be construed in a limiting manner. Rather, such added details may be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuitry. Any represented signal line, whether or not having additional information, may actually include one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, such as digital or analog lines implemented with differential pairs, fiber optic lines, and / or single-ended lines.

[0073] Exemplary dimensions / models / values / ranges may have been given, but the embodiments are not limited thereto. As manufacturing technologies (e.g., lithography) mature over time, it is expected that devices of smaller dimensions may be manufactured. Additionally, for the sake of simplicity of illustration and discussion, and in order not to obscure certain aspects of the embodiments, well-known power / ground connections to the IC chip and other components may or may not be shown in the figures. Further, the arrangements may be shown in block diagram form to avoid obscuring the embodiments, and also in view of the fact that details regarding the implementation of such block diagram arrangements highly depend on the platform within which the embodiments are to be implemented, i.e., such details should be within the knowledge of those skilled in the art. In cases where specific details (e.g., circuits) are set forth to describe exemplary embodiments, it should be apparent to those skilled in the art that the embodiments may be practiced without the specific details or with variations of these specific details. The description is, accordingly, to be regarded as illustrative rather than restrictive.

[0074] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components being discussed, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, the terms "first", "second", etc. may be used herein merely for convenience of discussion and, unless otherwise specified, do not carry a particular temporal or chronological significance.

[0075] As used in this application and in the claims, a list of items joined by the phrase "one or more of" may mean any combination of the listed terms. For example, both the phrases "one or more of A, B, and C" and "one or more of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0076] Those skilled in the art will understand from the foregoing description that the broad techniques of the embodiments can be implemented in various forms. Thus, although the embodiments have been described in connection with specific examples of the embodiments, the true scope of the embodiments should not be so limited since other modifications will become apparent to those skilled in the art upon study of the drawings, the specification, and the following claims.

Claims

1. A memory system, comprising: A first memory power node including a first group of one or more memory devices; A first power source coupled to the first memory power node; A second memory power node including a second group of one or more memory devices; A second power source coupled to the second memory power node; And Logic coupled to the first memory power node and the second memory power node, the logic being configured to: Independently bring the first memory power node into one of online and offline based on a runtime memory control signal; Independently bring the second memory power node into one of online and offline based on a runtime memory control signal; Based on the online or offline state of the first memory power node or the second memory power node, reconfigure a system address decoder to place the first memory power node or the second memory power node back into the system address map or remove the first memory power node or the second memory power node from the system address map, and Scale an operating frequency provided to one or more of the first and second memory power nodes based on a runtime memory control signal, Wherein a memory power node refers to a group of memory devices, and all of the group of memory devices are connected to the same voltage rail.

2. The system according to claim 1, wherein the logic is further configured to: Scale a voltage provided to one or more of the first and second memory power nodes based on a runtime memory control signal.

3. The system according to any one of claims 1 to 2, wherein the runtime memory control signal is based on a memory power state.

4. The system according to any one of claims 1 to 2, wherein the memory devices include non-volatile memory devices.

5. The system according to any one of claims 1 to 2, wherein the first power source is coupled to the first memory power node with a first voltage rail, and wherein the second power source is coupled to the second memory power node with a second voltage rail.

6. A semiconductor package device, comprising: A substrate; And Logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic and fixed functional hardware logic, the logic being coupled to the substrate to: Independently bring the first memory power node into one of online and offline based on a runtime memory control signal; Independently bring the second memory power node into one of online and offline based on a runtime memory control signal; Based on the online or offline state of the first memory power node or the second memory power node, reconfigure a system address decoder to place the first memory power node or the second memory power node back into the system address map or remove the first memory power node or the second memory power node from the system address map, and Scale an operating frequency provided to one or more of the first and second memory power nodes based on a runtime memory control signal, Wherein the first memory power node includes a first group of one or more memory devices; the second memory power node includes a second group of one or more memory devices; and A memory power node refers to a group of memory devices, all of which are connected to the same voltage rail.

7. The apparatus according to claim 6, wherein the logic is further operative to: Scale the voltage supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

8. The apparatus according to any one of claims 6 to 7, wherein the runtime memory control signal is based on a memory power state.

9. The apparatus according to any one of claims 6 to 7, wherein each of the first and second memory power nodes includes one or more non-volatile memory devices.

10. The apparatus according to any one of claims 6 to 7, wherein the first memory power node is coupled to a first voltage rail and wherein the second memory power node is coupled to a second voltage rail.

11. A method of controlling a memory, comprising: Independently bringing a first memory power node online or offline based on a runtime memory control signal; Independently bringing a second memory power node online or offline based on a runtime memory control signal; Reconfiguring a system address decoder to place a first memory power node or a second memory power node back into a system address map or remove a first memory power node or a second memory power node from the system address map based on the online or offline state of the first memory power node or the second memory power node, and Scaling an operating frequency supplied to one or more of the first and second memory power nodes based on a runtime memory control signal, wherein the first memory power node includes a first group of one or more memory devices; the second memory power node includes a second group of one or more memory devices; and A memory power node refers to a group of memory devices, all of which are connected to the same voltage rail.

12. The method according to claim 11, further comprising: Scaling the voltage supplied to one or more of the first and second memory power nodes based on a runtime memory control signal.

13. The method according to any one of claims 11 to 12, wherein the runtime memory control signal is based on a memory power state.

14. The method according to any one of claims 11 to 12, further comprising: Providing one or more non-volatile memory devices for each of the first and second memory power nodes.

15. The method according to any one of claims 11 to 12, further comprising: Coupling the first memory power node to a first voltage rail; And Coupling the second memory power node to a second voltage rail.

16. A memory controller apparatus, comprising: Means for independently bringing a first memory power node online or offline based on a runtime memory control signal; Means for independently bringing a second memory power node online or offline based on a runtime memory control signal; Apparatus for reconfiguring a system address decoder based on the online or offline state of a first memory power node or a second memory power node to place the first memory power node or the second memory power node back into the system address map or remove the first memory power node or the second memory power node from the system address map; And Apparatus for scaling the operating frequency provided to one or more of the first and second memory power nodes based on a runtime memory control signal, wherein the first memory power node includes a first group of one or more memory devices; the second memory power node includes a second group of one or more memory devices; and A memory power node refers to a group of memory devices that are all connected to the same voltage rail.

17. The apparatus according to claim 16, further comprising: Apparatus for scaling the voltage provided to one or more of the first and second memory power nodes based on a runtime memory control signal.

18. The apparatus according to any one of claims 16 to 17, wherein the runtime memory control signal is based on a memory power state.

19. The apparatus according to any one of claims 16 to 17, further comprising: Apparatus for providing one or more non-volatile memory devices for each of the first and second memory power nodes.

20. The apparatus according to any one of claims 16 to 17, further comprising: Apparatus for coupling the first memory power node to a first voltage rail; And Apparatus for coupling the second memory power node to a second voltage rail.

21. A computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform the method according to any one of claims 11 - 15.

22. A computer program product having instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 11 - 15.

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