Method for depositing doped germanium-tin semiconductor and related semiconductor device structures

Abstract

Disclosed is a method for depositing germanium tin (Ge 1‑x Sn x ) semiconductor. The method may include: providing a substrate in a reaction chamber; heating the substrate to a deposition temperature; and exposing the substrate to a germanium precursor and a tin precursor. The method may further include: 1‑x Sn x ) semiconductor is deposited on the surface of the substrate; and the germanium tin (Ge 1‑x Sn x ) semiconductor is exposed to a boron dopant precursor. Also provided is a germanium tin (Ge) semiconductor formed by the method of the present disclosure. 1‑x Sn x )Semiconductor device structure of a semiconductor.

Description

Technical Field

[0001] The present disclosure generally relates to methods for depositing germanium tin (Ge 1-x Sn x ) semiconductor method and method containing germanium tin (Ge 1-x Sn x ) semiconductor device structures. The present disclosure also generally relates to devices for doping germanium tin (Ge 1-x Sn x ) semiconductor method. Background Art

[0002] People are paying more and more attention to the 1-x Sn x ) are used in many applications, such as high-mobility channels and strain engineering for advanced microelectronics, direct-bandgap Group IV materials for photonic devices, or GeSn alloys for photovoltaic devices.

[0003] Single crystal germanium tin (Ge 1-x Sn x ) semiconductor materials can be deposited or grown using various techniques. For example, vacuum processes including molecular beam epitaxy and chemical vapor deposition can be used to form single crystal germanium tin (Ge 1-x Sn x )semiconductor.

[0004] In some semiconductor device applications, Germanium Tin (Ge 1-x Sn x ) semiconductors can be doped with selected impurities to obtain the desired conductivity. For example, Germanium Tin (Ge 1-x Sn x ) semiconductors can be obtained by incorporating boron into germanium tin (Ge 1-x Sn x ) semiconductor and doped into p-type. However, in some applications, it may be necessary to deposit or grow germanium tin (Ge 1-x Sn x ) semiconductor, which not only has a high p-type doping concentration, but also has a significant tin (Sn) composition. For example, for germanium tin (Ge) with a tin (Sn) composition greater than x = 0.03 1-x Sn x ) semiconductors, it may be difficult to obtain more than 1×10 20 Therefore, when depositing or growing germanium tin (Ge 1-x Sn x ) semiconductor materials, there is a trade-off between Sn composition and doping concentration. Therefore, it is necessary to form GeSn with significant Sn composition and high doping concentration. 1-x Sn x) semiconductor method. Summary of the Invention

[0005] According to at least one embodiment of the present disclosure, a method for depositing doped germanium tin (Ge 1-x Sn x ) semiconductor. The method may include: providing a substrate in a reaction chamber; heating the substrate to a deposition temperature; and exposing the substrate to a germanium precursor and a tin precursor. The method may further include: 1-x Sn x ) semiconductor is deposited on the surface of the substrate; and the germanium tin (Ge 1-x Sn x ) semiconductor is exposed to a boron dopant precursor. Embodiments of the present disclosure may also include semiconductor device structures that may include doped germanium tin (Ge 1-x Sn x )semiconductor.

[0006] For the purpose of summarizing the present invention and the advantages achieved over the prior art, certain objects and advantages of the present invention have been described above. Of course, it should be understood that not all such objects or advantages may be achieved according to any particular embodiment of the present invention. Thus, for example, those skilled in the art will recognize that the present invention may be implemented or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein, but not necessarily achieves other objects or advantages as may be taught or suggested herein.

[0007] All such embodiments are intended to be within the scope of the invention disclosed herein. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying drawings, the invention not being limited to any particular embodiment disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] While this specification concludes with claims that expressly point out and distinctly claim to be considered a part of embodiments of the present disclosure, advantages of the embodiments of the present disclosure may be more readily ascertained from the description of certain examples of the embodiments of the present disclosure when read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 illustrating a process flow diagram illustrating an exemplary deposition method according to an embodiment of the present disclosure;

[0010] Figure 2 The invention discloses a germanium tin (Ge 1-x Sn x )Semiconductor device structure of a semiconductor.

[0011] It will be understood that the elements in the drawings are illustrated for simplicity and clarity only and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the embodiments described in the present disclosure. DETAILED DESCRIPTION

[0012] Although certain embodiments and examples are disclosed below, those skilled in the art will appreciate that the invention extends beyond the specifically disclosed embodiments and / or uses of the invention and obvious modifications and equivalents thereof. Therefore, it is intended that the scope of the invention disclosed should not be limited by the specific disclosed embodiments described below.

[0013] As used herein, the term "substrate" may refer to any underlying material that may be used, or on which a device, circuit, or film may be formed.

[0014] As used herein, the term "epitaxial layer" may refer to a substantially single crystalline layer on an underlying substantially single crystalline substrate.

[0015] As used herein, the term "chemical vapor deposition" may refer to any process in which a substrate is exposed to one or more volatile precursors that react and / or decompose on the substrate surface to produce the desired deposit.

[0016] As used herein, the term "germanium tin" may refer to a semiconductor material including germanium and tin, and may be represented as Ge 1- x Sn x , where 1≥x≥0.

[0017] Embodiments of the present disclosure may include methods for forming germanium tin (Ge 1-x Sn x ) semiconductor materials and in particular for depositing germanium tin (Ge 1-x Sn x ) semiconductor. The embodiments of the present disclosure may also include methods for doping a germanium tin semiconductor material with a p-type dopant while incorporating a significant tin (Sn) component into the germanium tin (Ge 1-x Sn x ) method in a semiconductor material, wherein the p-type dopant may be provided by a boron dopant precursor.

[0018] Stress engineering has proven to be crucial to achieving improved Si-CMOS device performance at each successive technology node. The incorporation of Group IV semiconductors and their alloys, and in particular, Germanium Tin (Ge 1-x Sn x ) semiconductor materials can significantly expand the design space to continue bandgap engineering and stress engineering on platforms compatible with silicon (Si). 1-xSn x ) semiconductor alloys offer the largest lattice constants of Group IV semiconductors, thereby providing additional flexibility beyond silicon (Si) and silicon germanium (SiGe) for use in stress-engineered germanium (Ge) and silicon germanium (SiGe) based devices. For example, germanium tin (Ge 1-x Sn x ) semiconductor material can be used not only as a channel material for a pMOSFET device, but also, the source / drain regions of the pMOSFET device can also include germanium tin (Ge 1-x Sn x ) semiconductor materials.

[0019] However, in order to impart significant stress to the semiconductor device structure being fabricated (ie, FinFET device), Germanium Tin (Ge 1-x Sn x ) semiconductor materials may require a significant tin (Sn) composition; for example, germanium tin (Ge) in the source / drain regions 1- x Sn x ) semiconductor material may have a composition greater than x=0.08. Conversely, the source / drain regions of the transistor structure may need to be highly doped so that the electrical contact resistance to the source / drain regions is kept to a minimum, thereby improving the efficiency of the device. Therefore, a germanium tin (Ge) semiconductor material that is highly doped (to provide low contact resistance) and includes a significant tin (Sn) composition (to provide stress to the device structure) is desirable. 1-x Sn x ) methods and device structures of semiconductor materials.

[0020] The method disclosed herein can be referred to Figure 1 To understand, Figure 1 Description of the method for forming germanium tin (Ge 1-x Sn x ) are non-limiting example embodiments of methods for producing semiconductor materials. For example, Figure 1 It can be explained that the formation of germanium tin (Ge 1-x Sn x ) semiconductor material, may include process block 110, wherein a substrate may be provided to a reaction chamber and the substrate may be heated to a processing temperature within the reaction chamber. As a non-limiting example, the reaction chamber may include a reaction chamber of a chemical vapor deposition system. Embodiments of the present disclosure may be available from ASM International NV under the name Intrepid TM XP or However, it is also contemplated that embodiments of the present disclosure may also be performed using other reaction chambers and alternative chemical vapor deposition systems from other manufacturers.

[0021] In some embodiments of the present disclosure, the substrate may include a planar substrate or a patterned substrate. A patterned substrate may include a substrate that may include semiconductor device structures formed into or on a substrate surface. For example, a patterned substrate may include partially fabricated semiconductor device structures, such as transistors and memory elements. The substrate may contain a single crystal surface and / or one or more subsurfaces, which may include non-single crystal surfaces, such as polycrystalline surfaces and amorphous surfaces. The single crystal surface may include, for example, one or more of: silicon (Si), silicon germanium (SiGe), germanium tin (GeSn), or germanium (Ge). The polycrystalline or amorphous surface may include a dielectric material, such as an oxide, an oxynitride, or a nitride.

[0022] In some embodiments of the present disclosure, a substrate may include a "virtual substrate," where the virtual substrate may include two or more materials disposed on top of each other. For example, a germanium virtual substrate may include an upper, mostly exposed germanium growth surface, where the virtual substrate may include a layer of germanium deposited on another material, such as a silicon substrate.

[0023] Continue to refer Figure 1 , method 100 may continue by heating the substrate to a desired processing temperature within the reaction chamber. In some embodiments of the present disclosure, method 100 may include heating the substrate to a temperature of less than about 400° C., or less than about 350° C., or less than about 300° C., or even less than about 250° C. In some embodiments of the present disclosure, the method may include heating the substrate to a temperature between about 275° C. and about 400° C. In some embodiments of the present disclosure, an optional pre-deposition bake may be performed on the substrate after loading the substrate into the reaction chamber and before heating the substrate to the processing temperature. For example, the substrate may be subjected to a pre-deposition bake at a temperature between about 350° C. and about 500° C.

[0024] Once the substrate is heated to the desired processing temperature, method 100 may continue by exposing the substrate to a germanium precursor and a tin precursor, such as by Figure 1 100 sccm, or greater than 200 sccm. Furthermore, in some embodiments, the flow rate of the tin precursor into the reaction chamber may be greater than 0.1 mg / min, or greater than 1 mg / min, or even greater than 5 mg / min.

[0025] In some embodiments of the present disclosure, exposing the substrate to a germanium precursor may further include selecting the germanium precursor to include at least one of germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), or germanylsilane (GeH6Si). In some embodiments of the present disclosure, the germanium precursor may include a Si-Ge-hydride precursor, such as (H3Ge) x SiH 4-x , where x = 1 to 4, or (H3Si) X Ge 4-x , where x = 1 to 4. In some embodiments of the present disclosure, it may be advantageous to further incorporate silicon into the deposition process. For example, the precursor stream may further include a silicon precursor such as, but not limited to, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or higher-order silane compounds. In some embodiments of the present disclosure, exposing the substrate to a tin precursor may further include selecting the tin precursor to include at least one of tin tetrachloride (SnCl4) or tin deuteride (SnD4).

[0026] It should be understood that when the substrate is heated to the deposition temperature and the germanium precursor and the tin precursor are simultaneously introduced into the reaction chamber, the reaction chamber can be maintained at atmospheric pressure or at a reduced pressure. For example, in some embodiments, the pressure of the reaction chamber can be less than 760 Torr, or even less than 100 Torr, or even less than 10 Torr.

[0027] In some alternative embodiments of the present disclosure, exposing the substrate to a germanium precursor and a tin precursor may further include exposing the substrate to an initial boron dopant precursor. For example, the germanium precursor, the tin precursor, and the initial boron dopant precursor may be introduced into the reaction chamber simultaneously, i.e., in a "co-flow" process. In some embodiments of the present disclosure, the initial boron dopant precursor may include at least one of diborane (B2H6) or boron trichloride (BCl3). The initial boron dopant precursor may be introduced into the reaction chamber at a flow rate greater than 0.01 sccm, greater than 0.1 sccm, or even greater than 1 sccm.

[0028] The method 100 may continue with process block 130, where the method includes adding germanium tin (Ge 1-x Sn x ) semiconductor material is deposited on the surface of the substrate. In some embodiments of the present disclosure, germanium tin (Ge 1-x Sn x ) semiconductor material may include tin (Sn), wherein x is greater than 0.01 or greater than 0.05 or even greater than 0.08. In some embodiments, germanium tin (Ge 1-x Sn x ) semiconductor material is deposited on the surface of the substrate further comprising germanium tin (Ge 1-x Sn x) semiconductor material is deposited to a thickness between about 1 nanometer and about 50 nanometers.

[0029] In embodiments where an initial boron dopant precursor is not utilized, ie, no initial boron dopant is introduced into the reaction chamber during process block 120, germanium tin (Ge 1-x Sn x ) semiconductor material may be initially deposited as an undoped material. It should be noted that herein, the term "undoped" may also refer to "unintentionally doped" because the deposited germanium tin (Ge 1-x Sn x ) semiconductor may include impurities and / or defects that may result in unintentional doping of the germanium tin semiconductor. In embodiments utilizing an initial boron dopant precursor, i.e., introducing an initial boron dopant into the reaction chamber during process block 120, the germanium tin (Ge 1-x Sn x ) semiconductor can be initially deposited as a p-type germanium-tin semiconductor with an initial carrier concentration greater than 1×10 18 Dopant / cm3 or greater than 1×10 19 dopant / cm3 or even greater than 1×10 20 Dopant / cubic centimeter.

[0030] Deposit p-type doped germanium tin (Ge 1-x Sn x ) semiconductor material can continue after process block 130, i.e., after depositing the germanium tin semiconductor on the surface of the substrate, by stopping the flow of all precursor gases into the reaction chamber. For example, in some embodiments, the method can further include depositing the germanium tin (Ge 1-x Sn x The germanium precursor and the tin precursor are removed from the reaction chamber after the semiconductor is deposited on the surface of the substrate. In addition to stopping the flow of the germanium precursor and the tin precursor, the germanium precursor and the tin precursor remaining in the reaction chamber after the germanium-tin deposition can be evacuated from the reaction chamber by a vacuum system fluidly connected to the reaction chamber.

[0031] Method 100 may continue with process block 140, which includes depositing the germanium tin (Ge 1-x Sn x ) semiconductor material is exposed to a boron dopant precursor. For example, in some embodiments, the method may include selecting the boron dopant precursor to include at least one of diborane (B2H6) or boron trichloride (BCl3). Furthermore, in some embodiments, the boron dopant precursor may be introduced into the reaction chamber at a flow rate greater than 0.01 sccm, or greater than 0.1 sccm, or even greater than 1 sccm. In some embodiments of the present disclosure, germanium tin (Ge 1-x Sn x) semiconductor material to the boron dopant precursor may further include germanium tin (Ge 1- x Sn x ) semiconductor material is exposed to a boron dopant precursor for a period of time between about 1 second and about 60 seconds. It should be noted that in the case of germanium tin (Ge 1-x Sn x ) During exposure of the semiconductor material to the boron dopant precursor, no germanium precursor or tin precursor is introduced into the reaction chamber, that is, the boron dopant precursor is introduced into the reaction chamber separately and alone.

[0032] The method 100 may continue at process block 150 where a decision gate determines whether the method 100 continues or exits. The decision gate at process block 150 is based on the deposited germanium tin (Ge 1-x Sn x ) semiconductor material, for example, if the thickness of the germanium tin semiconductor is insufficient for the desired device structure, the method 100 may return to process block 120 and may repeat two or more of the following processes: exposing the substrate to a germanium precursor and a tin precursor, depositing a germanium tin semiconductor on the surface of the substrate, and exposing the germanium tin semiconductor to a boron dopant precursor. In other words, the method 100 may include a deposition cycle, wherein the deposition cycle includes: exposing the substrate to a germanium precursor and a tin precursor, depositing a germanium tin semiconductor on the surface of the substrate, and exposing the germanium tin semiconductor to a boron dopant precursor. 1-x Sn x ) semiconductor materials, and the germanium tin (Ge 1-x Sn x ) semiconductor material is exposed to a boron dopant precursor. In some embodiments of the present disclosure, method 100 may include performing two or more deposition cycles until a desired thickness of p-type doped germanium tin (Ge 1-x Sn x ) semiconductor materials.

[0033] In some embodiments of the present disclosure, performing two or more deposition cycles further comprises: 1- x Sn x ) semiconductor material to a thickness between about 40 nanometers and about 60 nanometers. In addition, performing two or more deposition cycles may include depositing p-type germanium tin (Ge 1-x Sn x ) semiconductor material is deposited to a desired thickness with a desired dopant concentration. Thus, the method of the present disclosure may include depositing germanium tin (Ge 1-x Sn x ) semiconductor material to a boron dopant precursor, and may further include germanium tin (Ge 1-x Sn x ) semiconductor material is doped to a value greater than about 1×10 20 dopant / cm3 or greater than about 5×1020 dopant / cm3 or even greater than about 1×10 21 It will be appreciated that the method of the present disclosure enables the deposition of germanium tin (Ge) with a significant tin (Sn) composition. 1-x Sn x ) semiconductor material while maintaining a high doping concentration. Therefore, in some embodiments of the present disclosure, the method may include depositing tin (Sn) with a composition greater than x=0.01 and a dopant concentration greater than 1×10 21 Dopant / cubic centimeter of germanium tin (Ge 1-x Sn x ) semiconductor material. In other embodiments of the present disclosure, the method may include depositing tin (Sn) with a composition greater than x=0.04 and a dopant concentration greater than 1×10 20 Dopant / cubic centimeter of germanium tin (Ge 1-x Sn x ) semiconductor materials.

[0034] Once germanium tin (Ge 1-x Sn x ) semiconductor material has been deposited to the desired thickness, composition, and dopant concentration, the process may exit 160 and the substrate may be removed from the reaction chamber for further device fabrication processes. However, in some embodiments of the present disclosure, the substrate may be subjected to a post-growth annealing process prior to removal from the reaction chamber to potentially further activate the p-type dopant and / or redistribute the p-type dopant to the germanium tin (Ge 1-x Sn x ) semiconductor material throughout its entire thickness. In some embodiments, the germanium tin (Ge 1-x Sn x ) semiconductor material after growth annealing can be performed after completing two or more deposition cycles and can further include heating the substrate to a temperature between about 350° C. and about 650° C. In an alternative embodiment, the substrate can be formed on a germanium tin (Ge 1-x Sn x ) An annealing process is performed during each individual deposition cycle after the semiconductor material has been exposed to the boron dopant precursor.

[0035] In some embodiments, germanium tin (Ge 1-x Sn x) The semiconductor material may include less than about 20 at-%, less than about 10 at-%, less than about 7 at-%, less than about 5 at-%, less than about 3 at-%, less than about 2 at-%, or less than about 1 at-% of impurities other than Ge or Sn. In some embodiments, the germanium-tin layer including germanium and tin includes less than about 20 at-%, less than about 10 at-%, less than about 5 at-%, less than about 2 at-%, or less than about 1 at-% of hydrogen. In some embodiments, the germanium-tin layer including germanium and tin may include less than about 10 at-%, less than about 5 at-%, less than about 2 at-%, less than about 1 at-%, or less than about 0.5 at-% of carbon. In some embodiments, the germanium-tin layer including germanium and tin may include less than about 5 at-%, less than about 2 at-%, less than about 1 at-%, less than about 0.5 at-%, or less than about 0.2 at-% of nitrogen. In some embodiments, the germanium tin layer may include less than about 15 at-%, less than about 10 at-%, less than about 5 at-%, less than about 3 at-%, less than about 2 at-%, or less than about 1 at-%. In some embodiments, the germanium tin layer may include less than about 30 at-%, less than about 20 at-%, less than about 10 at-%, less than about 5 at-%, or less than about 3 at-% oxygen on average at the surface, where the surface is defined as a thickness less than about 20 nm from the topmost surface. In some embodiments, a thin film comprising germanium and tin may include greater than about 80 at-%, greater than about 90 at-%, greater than about 93 at-%, greater than about 95 at-%, greater than about 97 at-%, or greater than about 99 at-%.

[0036] Embodiments of the present disclosure may also provide germanium tin (Ge 1-x Sn x ) semiconductor device structure of semiconductor material. For example, Figure 2 A non-limiting example of a semiconductor device structure 200 is illustrated, wherein the semiconductor device structure 200 includes a partially fabricated dual-gate MOSFET, commonly referred to as a FinFET. The semiconductor device structure 200 may include a substrate 202, which may include a bulk silicon (Si) substrate or may include a "virtual substrate" including a germanium virtual substrate on which a Si-Ge-Sn alloy is grown. The substrate 202 may be doped with a p-type dopant (for an NMOS type FinFET device) or with an n-type dopant (for a PMOS type FinFET device). Figure 2 In the non-limiting example semiconductor device structure of FIG. 1 , substrate 202 may include n-type dopants, and semiconductor device structure 200 may include a PMOSFET or, in particular, a PMOS FinFET.

[0037] The semiconductor device structure 200 may further include an isolation region 204, which may include a shallow trench isolation (STI) region. The semiconductor device structure 200 may further include a fin structure 206 disposed between the two isolation regions 204. The semiconductor device structure 200 may include an epitaxially regrown source region 208A and a drain region 208B, which may be deposited using the methods disclosed herein. For example, the source region 208A and the drain region 208B may include tin (Sn) with a composition of x=0.08 and a boron doping concentration greater than approximately 1×10 19 Dopant / cubic centimeter of germanium tin (Ge 1-x Sn x ) semiconductor material. The semiconductor device structure 200 may further include a channel region 210 formed by the embodiments of the present disclosure. For example, the channel region 210 may include tin (Sn) with a composition of x=0.04 and a boron doping concentration greater than about 1×10 18 Dopant / cubic centimeter of germanium tin (Ge 1-x Sn x ) semiconductor materials.

[0038] In some embodiments of the present disclosure, a p-type germanium tin (Ge2Sn) including a source region 208A and a drain region 208B may be obtained. 1-x Sn x ) semiconductor material. In some embodiments, the electrical contacts (not shown) may include a silicide, such as titanium silicide (TiSi2). Embodiments of the present disclosure allow for a high concentration of active p-type carriers in the source region 208A and the drain region 208B, which in turn may result in reduced electrical contact resistance to the source and drain regions. For example, the method of the present disclosure may include forming electrical contacts to the p-type source region 208A and the drain region 208B, wherein the electrical contacts have a resistance of less than 1×10 -8 Ohm.cm 2 or less than 5×10 -9 Ohm.cm 2 Or even less than 1×10 -9 Ohm.cm 2 resistivity.

[0039] The example embodiments of the present disclosure described above do not limit the scope of the present invention, because these embodiments are merely examples of embodiments of the present invention, and the present invention is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the present invention. In fact, in addition to the content of the alternative applicable combination of the described elements shown and described herein, various modifications of the present disclosure will become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims

1. A method of depositing doped germanium tin (Ge 1-x Sn x ) a semiconductor method comprising: providing a substrate within a reaction chamber; heating the substrate to a deposition temperature; exposing the substrate to a germanium precursor and a tin precursor; Germanium tin (Ge 1-x Sn x ) a semiconductor is deposited on the surface of the substrate; In the case of the germanium tin (Ge 1-x Sn x ) removing the germanium precursor and the tin precursor from the reaction chamber after the semiconductor is deposited on the surface of the substrate; The germanium tin (Ge 1-x Sn x ) exposing the semiconductor to a boron dopant precursor; as well as In the case of the germanium tin (Ge 1-x Sn x ) semiconductor is exposed to a boron dopant precursor, and then the germanium tin (Ge 1-x Sn x )semiconductor, wherein the germanium tin (Ge1-xSnx) semiconductor is exposed to a boron dopant precursor before depositing the germanium tin (Ge 1-x Sn x ) is carried out in a semiconductor reaction chamber. 2 . The method of claim 1 , wherein exposing the substrate to a germanium precursor and a tin precursor further comprises exposing the substrate to an initial boron dopant precursor.

3. The method of claim 1, wherein heating the substrate to a deposition temperature further comprises heating the substrate to a deposition temperature between 275°C and 400°C.

4. The method of claim 1, further comprising selecting the germanium precursor to include at least one of: germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), or germanylsilane (GeH6Si). 5 . The method of claim 1 , further comprising selecting the tin precursor to include at least one of tin tetrachloride (SnCl 4 ) or tin deuteride (SnD 4 ).

6. The method of claim 1, further comprising selecting the boron dopant precursor to comprise at least one of diborane (B2H6) or boron trichloride (BCl3). 7 . The method of claim 1 , wherein exposing the substrate to the germanium precursor and the tin precursor further comprises co-flowing the germanium precursor and the tin precursor into the reaction chamber.

8. The method according to claim 1, wherein the germanium tin (Ge 1-x Sn x ) semiconductor is deposited on the surface of the substrate further comprising the step of depositing the germanium tin (Ge 1-x Sn x ) semiconductors are deposited to a thickness between 1 nm and 15 nm.

9. The method of claim 1, further comprising a pre-deposition bake, wherein the pre-deposition bake comprises heating the substrate to a temperature between 350°C and 500°C.

10. The method of claim 1 , wherein the deposition cycle comprises: The substrate is exposed to the germanium precursor and the tin precursor, and the germanium tin (Ge 1-x Sn x ) semiconductor and the germanium tin (Ge 1-x Sn x ) semiconductor is exposed to the boron dopant precursor. The method of claim 10 , further comprising performing two or more deposition cycles.

12. The method of claim 11, wherein performing two or more deposition cycles further comprises depositing the germanium tin (Ge 1-x Sn x ) semiconductor is deposited to a thickness between 40 nanometers and 60 nanometers.

13. The method according to claim 1, wherein the germanium tin (Ge 1-x Sn x ) semiconductor to the boron dopant precursor further comprising exposing the germanium tin (Ge 1-x Sn x ) semiconductor doped to greater than 1×10 21 Dopant concentration in 1 / cm3 of dopant.

14. The method according to claim 11, wherein The annealing is performed at a temperature between 350°C and 650°C.

15. The method according to claim 1, wherein the germanium tin (Ge 1-x Sn x ) semiconductor deposited on the surface of the substrate further includes depositing the germanium tin (Ge) with a tin (Sn) content greater than x=0.05 1-x Sn x ).

16. A semiconductor device structure comprising the germanium tin (Ge 1- x Sn x )semiconductor.

17. The semiconductor device structure of claim 16, wherein the germanium tin (Ge 1-x Sn x ) The semiconductor includes at least one of a source region or a drain region of a transistor structure.

18. The semiconductor device structure of claim 17, wherein the transistor structure comprises a PMOSFET.

19. The semiconductor device structure of claim 17, further comprising an electrical contact formed to the source region or the drain region of the transistor structure, wherein the electrical contact has a capacitance less than 1×10 -9 Ohm.cm 2 resistivity.

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