RC oscillator circuit and RC oscillator device

Abstract

The RC oscillator circuit and RC oscillator device provided by the present application relate to the field of circuit technology. Among them, the RC oscillator circuit includes: a first oscillation unit having a first comparator; a second oscillation unit having a second comparator; and a logic gate unit respectively connected to the first oscillation unit and the second oscillation unit. After the first oscillation unit is charged and the second oscillation unit is discharged for a preset time, the first comparator flips to allow the logic gate unit to control the first oscillation unit to discharge and the second oscillation unit to charge, and after a preset time, the second comparator flips to allow the logic gate unit to control the first oscillation unit to charge and the second oscillation unit to discharge. Through the above-mentioned setting, the problem of complex circuit structure caused by the need to set different flipping voltages for the two comparators in the prior art can be improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an RC oscillator circuit and an RC oscillator device. Background Art

[0002] The low-frequency oscillation signal is generally generated by an RC oscillation circuit. Among them, the existing RC oscillation circuit generally has two comparators, and the two comparators obtain the same input voltage and then compare the input voltage with their own flip voltage (such as Figure 1 By setting different flip voltages for the two comparators, the two comparators are flipped in a certain order, thereby controlling the charging or discharging of the capacitor to generate an oscillation signal.

[0003] The inventors have found that in the existing RC oscillation circuit, since the two comparators need to be set with different flip voltages, different power supply circuits need to be set to provide different flip voltages, which leads to the problem of complex circuit structure. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an RC oscillator circuit and an RC oscillator device to improve the problem in the prior art that the circuit structure is complicated because two comparators need to set different flip voltages.

[0005] To achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] An RC oscillator circuit, comprising:

[0007] A first oscillation unit, the first oscillation unit having a first comparator, an output end of the first comparator serving as an output end of the first oscillation unit;

[0008] A second oscillation unit, the second oscillation unit having a second comparator, an output end of the second comparator serving as an output end of the second oscillation unit;

[0009] a logic gate unit, wherein an input end of the logic gate unit is connected to an output end of the first oscillation unit and an output end of the second oscillation unit respectively, a first output end is connected to a control end of the first oscillation unit, and a second output end is connected to a control end of the second oscillation unit, and a level signal output by the first output end has a polarity opposite to that of a level signal output by the second output end;

[0010] Wherein, after the first oscillation unit is charged and the second oscillation unit is discharged for a preset time period, the first comparator flips to allow the logic gate unit to control the first oscillation unit to discharge and the second oscillation unit to charge, and after a preset time period, the second comparator flips to allow the logic gate unit to control the first oscillation unit to charge and the second oscillation unit to discharge.

[0011] In a preferred embodiment of the present application, in the above RC oscillator circuit, the first oscillator unit further includes:

[0012] A first field effect transistor, the gate of which is connected to the first input terminal of the first comparator, wherein after the gate capacitor of the first field effect transistor is charged by a charging current for a preset time period, the voltage of the gate capacitor is greater than the flipping voltage of the first comparator, so that the first comparator flips.

[0013] In a preferred embodiment of the present application, in the above RC oscillator circuit, the first oscillator unit further includes:

[0014] a second field effect transistor, wherein one of a source and a drain of the second field effect transistor is used to obtain the charging current, and the other is connected to a gate of the first field effect transistor, and the gate is connected to a first output terminal of the logic gate unit;

[0015] a third field effect transistor, one of a source and a drain of the third field effect transistor is connected to the gate of the first field effect transistor, the other is grounded, and the gate is connected to the first output terminal of the logic gate unit;

[0016] Among them, the polarity of the second field effect tube is opposite to that of the third field effect tube, so that one of them is turned on and the other is turned off based on the level signal output from the first output end of the logic gate unit, and when the second field effect tube is turned on, the gate capacitance of the first field effect tube is charged by the charging current, and when the third field effect tube is turned on, the gate capacitance of the first field effect tube is discharged.

[0017] In a preferred embodiment of the present application, in the above RC oscillator circuit, the first oscillator unit further includes:

[0018] a fourth field effect transistor, wherein one of the source and the drain of the fourth field effect transistor is used to obtain a bias current, the other is connected to the bias current terminal of the first comparator, and the gate is connected to the first output terminal of the logic gate unit;

[0019] A fifth field effect transistor with opposite polarity to the fourth field effect transistor, wherein one of the source and the drain of the fifth field effect transistor is used to obtain the bias current, the other is connected to the bias current terminal of the first comparator, and the gate is connected to the second output terminal of the logic gate unit.

[0020] In a preferred embodiment of the present application, in the above RC oscillator circuit, a mirror current source unit is further included for generating the charging current and the bias current respectively according to a reference current, and the mirror current source unit includes:

[0021] A mirror current module, used for copying the reference current to generate a mirror current, and generating proportional charging current and bias current respectively by copying the mirror current;

[0022] A plurality of gating modules are used to control the magnitude of the mirror current after different numbers of gating modules are turned on.

[0023] In a preferred embodiment of the present application, the RC oscillator circuit further includes a reference current source unit for generating the reference current, and the reference current source unit includes:

[0024] A positive temperature coefficient current module, comprising a first fixed current submodule and a plurality of first unit current modules connected in parallel with the first fixed current submodule;

[0025] A negative temperature coefficient current module connected in parallel with the positive temperature coefficient current module comprises a second fixed current submodule and a plurality of second unit current modules connected in parallel with the second fixed current submodule;

[0026] The number of the first unit current modules that are turned on and the number of the second unit current modules that are turned on are adjusted so that the coefficient of variation of the reference current is the same as the temperature coefficient of the gate capacitance of the first field effect transistor.

[0027] In a preferred embodiment of the present application, in the above RC oscillator circuit, the first comparator further includes:

[0028] A second input terminal, the second input terminal is used to obtain a flip voltage;

[0029] A third input terminal is connected to the first output terminal of the logic gate unit to set the output of the first comparator when the gate capacitance of the first field effect transistor starts to charge.

[0030] In a preferred embodiment of the present application, in the above RC oscillator circuit, the second oscillator unit further includes:

[0031] A sixth field effect transistor, the gate of which is connected to the first input terminal of the second comparator, wherein after the gate capacitor of the sixth field effect transistor is charged by a charging current for a preset time period, the voltage of the gate capacitor is greater than the flipping voltage of the second comparator, so that the second comparator flips.

[0032] In a preferred embodiment of the present application, in the above RC oscillator circuit, the second oscillator unit further includes:

[0033] a seventh field effect transistor, wherein one of the source and the drain of the seventh field effect transistor is used to obtain the charging current, the other of the source and the drain is connected to the gate of the sixth field effect transistor, and the gate is connected to the second output terminal of the logic gate unit;

[0034] an eighth field effect transistor, one of a source and a drain of the eighth field effect transistor is connected to the gate of the sixth field effect transistor, the other is grounded, and the gate is connected to the second output terminal of the logic gate unit;

[0035] Among them, the polarity of the seventh field effect tube is opposite to that of the eighth field effect tube, so that one of them is turned on and the other is turned off based on the level signal output from the second output end of the logic gate unit, and when the seventh field effect tube is turned on, the gate capacitance of the sixth field effect tube is charged by the charging current, and when the eighth field effect tube is turned on, the gate capacitance of the sixth field effect tube is discharged.

[0036] In a preferred embodiment of the present application, in the above RC oscillator circuit, the second oscillator unit further includes:

[0037] a ninth field effect transistor, wherein one of the source and the drain of the ninth field effect transistor is used to obtain a bias current, the other is connected to the bias current terminal of the second comparator, and the gate is connected to the second output terminal of the logic gate unit;

[0038] A tenth field effect transistor having a polarity opposite to that of the ninth field effect transistor, wherein one of the source and the drain of the tenth field effect transistor is used to obtain the bias current, the other is connected to the bias current terminal of the second comparator, and the gate is connected to the first output terminal of the logic gate unit.

[0039] In a preferred choice of an embodiment of the present application, in the above-mentioned RC oscillation circuit, when the first oscillation unit includes a fourth field effect transistor and a fifth field effect transistor, the polarity of the fourth field effect transistor is the same as that of the ninth field effect transistor, and the polarity of the fifth field effect transistor is the same as that of the tenth field effect transistor.

[0040] In a preferred embodiment of the present application, in the above RC oscillator circuit, the second comparator further includes:

[0041] A second input terminal, the second input terminal is used to obtain a flip voltage;

[0042] A third input terminal is connected to the second output terminal of the logic gate unit to set the output of the second comparator when the gate capacitance of the sixth field effect transistor starts to charge.

[0043] In a preferred embodiment of the present application, in the above RC oscillation circuit, the logic gate unit is composed of two RS flip-flops and four inverters.

[0044] On the basis of the above, an embodiment of the present application further provides an RC oscillation device, including a circuit board and the above RC oscillation circuit, wherein the RC oscillation circuit is integrated with the circuit board.

[0045] The RC oscillator circuit and RC oscillator device provided by the present application are configured by the coordination of the first oscillator unit, the second oscillator unit and the logic gate unit so that the first comparator and the second comparator are alternately in the charging state and the discharging state, so that even if the flip voltages of the first comparator and the second comparator are the same, the input voltage of the first comparator and the input voltage of the second comparator are not the same, which causes the flipping of the first comparator and the second comparator to be not synchronized, and the generation of the oscillation signal can be realized. In other words, through the above configuration, the same flip voltage can be set for the first comparator and the second comparator, so as to improve the problem in the prior art that different power supply circuits need to be set to provide different flip voltages because the two comparators need to set different flip voltages, thereby causing a complex circuit structure, and the circuit has extremely high practical value.

[0046] Furthermore, by using the gate capacitor of the field effect transistor to replace the on-chip capacitor in the prior art, on the one hand, the problem of low accuracy of the oscillation signal caused by the influence of ambient temperature can be reduced; on the other hand, the area of ​​the integrated chip can be reduced, which has extremely high economic characteristics.

[0047] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a circuit schematic diagram of an existing RC oscillation circuit.

[0049] Figure 2 A circuit schematic diagram of an RC oscillator circuit provided in an embodiment of the present application.

[0050] Figure 3 A circuit schematic diagram of a mirror current source unit provided in an embodiment of the present application.

[0051] Figure 4 A circuit schematic diagram of a reference current source unit provided in an embodiment of the present application.

[0052] Icon: 100-RC oscillation circuit; 110-first oscillation unit; U1-first comparator; Q1-first field effect transistor; Q2-second field effect transistor; Q3-third field effect transistor; Q4-fourth field effect transistor; Q5-fifth field effect transistor; 130-second oscillation unit; U2-second comparator; Q6-sixth field effect transistor; Q7-seventh field effect transistor; Q8-eighth field effect transistor; Q9-ninth field effect transistor; Q10-tenth field effect transistor; 150-logic gate unit; 170-mirror current source unit; 171-mirror current module; 173-select module; 190-reference current source unit; 191-positive temperature coefficient current module; 192-first fixed current submodule; 193-first unit current module; 195-negative temperature coefficient current module; 196-second fixed current submodule; 197-second unit current module. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0055] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In the description of this application, the terms "first", "second", "third", "fourth", etc. are only used to distinguish the description and cannot be understood as just or implying relative importance.

[0056] In the description of this application, unless otherwise clearly specified and limited, the terms "disposed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0057] like Figure 2As shown, the embodiment of the present application further provides an RC oscillation circuit 100 , which may include a first oscillation unit 110 , a second oscillation unit 130 and a logic gate unit 150 .

[0058] In detail, the first oscillation unit 110 has a first comparator U1, and the output end of the first comparator U1 serves as the output end of the first oscillation unit 110. The second oscillation unit 130 has a second comparator U2, and the output end of the second comparator U2 serves as the output end of the second oscillation unit 130. The input end of the logic gate unit 150 is connected to the output end of the first oscillation unit 110 and the output end of the second oscillation unit 130 respectively, the first output end is connected to the control end of the first oscillation unit 110, the second output end is connected to the control end of the second oscillation unit 130, and the polarity of the level signal output by the first output end is opposite to that of the level signal output by the second output end.

[0059] Furthermore, after the first oscillation unit 110 is charged and the second oscillation unit 130 is discharged for a preset period of time, the first comparator U1 flips to enable the logic gate unit 150 to control the first oscillation unit 110 to discharge and the second oscillation unit 130 to charge, and after a preset period of time, the second comparator U2 flips to enable the logic gate unit 150 to control the first oscillation unit 110 to charge and the second oscillation unit 130 to discharge.

[0060] It should be noted that “the first oscillation unit 110 is charged and the second oscillation unit 130 is discharged for a preset time period” means that within the preset time period, the first oscillation unit 110 is charged and the second oscillation unit 130 is discharged. “Control the first oscillation unit 110 to discharge and the second oscillation unit 130 to charge” means that the first oscillation unit 110 is controlled to discharge and the second oscillation unit 130 is controlled to charge. That is to say, in this embodiment, the first oscillation unit 110 and the second oscillation unit 130 are alternately charged and discharged, so that the input voltage of the first comparator U1 and the input voltage of the second comparator U2 are not the same, so that even if the flip voltages of the first comparator U1 and the second comparator U2 are the same, the flipping of the first comparator U1 and the second comparator U2 can be made asynchronous, thereby generating an oscillation signal.

[0061] That is to say, through the above setting, the same flipping voltage can be set for the first comparator U1 and the second comparator U2, so as to improve the problem in the prior art that different power supply circuits need to be set to provide different flipping voltages because the two comparators need to be set with different flipping voltages, thereby causing a complex circuit structure. This has extremely high practical value.

[0062] Optionally, the number and type of electrical components included in the first oscillation unit 110 are not limited and can be set according to actual application requirements. In this embodiment, on the basis that the first oscillation unit 110 includes the first comparator U1, the first oscillation unit 110 may further include a first field effect transistor Q1.

[0063] In detail, the gate of the first field effect transistor Q1 is connected to the first input terminal of the first comparator U1. After the gate capacitor of the first field effect transistor Q1 is charged by a charging current for a preset time, the voltage of the gate capacitor is greater than the flip voltage of the first comparator U1, so that the first comparator U1 flips.

[0064] It should be noted that, in addition to having a first input terminal, the first comparator U1 may also have a second input terminal. The second input terminal is used to obtain the flip voltage of the first comparator U1, that is, when the voltage of the first input terminal of the first comparator U1 is greater than the voltage of the second input terminal, the first comparator U1 flips. The first input terminal of the first comparator U1 may be the negative electrode of the first comparator U1, and the second input terminal may be the positive electrode of the first comparator U1.

[0065] Furthermore, in order to control the charging or discharging of the gate capacitance of the first field effect transistor Q1, in this embodiment, the first oscillation unit 110 may further include a second field effect transistor Q2 and a third field effect transistor Q3.

[0066] In detail, one of the source and drain of the second field effect transistor Q2 is used to obtain the charging current, and the other is connected to the gate of the first field effect transistor Q1, and the gate is connected to the first output terminal of the logic gate unit 150. One of the source and drain of the third field effect transistor Q3 is connected to the gate of the first field effect transistor Q1, and the other is grounded, and the gate is connected to the first output terminal of the logic gate unit 150.

[0067] Among them, the polarity of the second field effect transistor Q2 is opposite to that of the third field effect transistor Q3, so that one of them is turned on and the other is turned off based on the level signal output from the first output end of the logic gate unit 150, and when the second field effect transistor Q2 is turned on, the gate capacitance of the first field effect transistor Q1 is charged by the charging current, and when the third field effect transistor Q3 is turned on, the gate capacitance of the first field effect transistor Q1 is discharged.

[0068] Furthermore, in order to control whether the first comparator U1 is working, in this embodiment, the first oscillation unit 110 may further include a fourth field effect transistor Q4 and a fifth field effect transistor Q5.

[0069] In detail, the fourth field effect transistor Q4 has opposite polarity to the fifth field effect transistor Q5. In addition, one of the source and drain of the fourth field effect transistor Q4 is used to obtain bias current, the other is connected to the bias current terminal of the first comparator U1, and the gate is connected to the first output terminal of the logic gate unit 150. One of the source and drain of the fifth field effect transistor Q5 is used to obtain the bias current, the other is connected to the bias current terminal of the first comparator U1, and the gate is connected to the second output terminal of the logic gate unit 150.

[0070] That is, when the fourth field effect transistor Q4 and the fifth field effect transistor Q5 are both turned off, the first comparator U1 cannot obtain the bias current and cannot work to reduce power consumption. When at least one of the fourth field effect transistor Q4 and the fifth field effect transistor Q5 is turned on, the first comparator U1 obtains the bias current to work based on the bias current.

[0071] Furthermore, in order to perform a setting process on the output of the first comparator U1, in this embodiment, the first comparator U1 may further include a third input terminal.

[0072] In detail, the third input terminal of the first comparator U1 is connected to the first output terminal of the logic gate unit 150, so as to set the output of the first comparator U1 when the gate capacitance of the first field effect transistor Q1 begins to discharge. For example, if the output of the first comparator U1 is 0, the output of the first comparator U1 is set to 1.

[0073] Optionally, the number and type of electrical components included in the second oscillation unit 130 are not limited and can be selected according to actual application requirements, for example, they can be the same as or different from the electrical components included in the first oscillation unit 110. In this embodiment, the second oscillation unit 130 can include a sixth field effect transistor Q6.

[0074] In detail, the gate of the sixth field effect transistor Q6 is connected to the first input terminal of the second comparator U2, wherein, after the gate capacitor of the sixth field effect transistor Q6 is charged by a charging current for a preset period of time, the voltage of the gate capacitor is greater than the flipping voltage of the second comparator U2, so that the second comparator U2 flips.

[0075] It should be noted that the second comparator U2 may have a second input terminal in addition to the first input terminal. The second input terminal is used to obtain the flip voltage of the second comparator U2, that is, when the voltage of the first input terminal of the second comparator U2 is greater than the voltage of the second input terminal, the second comparator U2 flips. The first input terminal of the second comparator U2 may be the negative electrode of the second comparator U2, and the second input terminal may be the positive electrode of the second comparator U2.

[0076] By setting the second field effect transistor Q2 and the sixth field effect transistor Q6, the gate capacitor is used to replace the on-chip capacitor in the prior art, which can reduce the influence of ambient temperature on the one hand and reduce the area of ​​the integrated chip on the other hand, and has extremely high economic characteristics.

[0077] Furthermore, in order to control the charging or discharging of the gate capacitance of the sixth field effect transistor Q6, in this embodiment, the second oscillation unit 130 may further include a seventh field effect transistor Q7 and an eighth field effect transistor Q8.

[0078] In detail, one of the source and the drain of the seventh field effect transistor Q7 is used to obtain the charging current, and the other is connected to the gate of the sixth field effect transistor Q6, and the gate is connected to the second output terminal of the logic gate unit 150. One of the source and the drain of the eighth field effect transistor Q8 is connected to the gate of the sixth field effect transistor Q6, and the other is grounded, and the gate is connected to the second output terminal of the logic gate unit 150.

[0079] Among them, the polarity of the seventh field effect transistor Q7 is opposite to that of the eighth field effect transistor Q8, so that one of them is turned on and the other is turned off based on the level signal output from the second output end of the logic gate unit 150, and when the seventh field effect transistor Q7 is turned on, the gate capacitance of the sixth field effect transistor Q6 is charged by the charging current, and when the eighth field effect transistor Q8 is turned on, the gate capacitance of the sixth field effect transistor Q6 is discharged.

[0080] Furthermore, in order to control whether the second comparator U2 is working, in this embodiment, the second oscillation unit 130 may further include a ninth field effect transistor Q9 and a tenth field effect transistor Q10.

[0081] In detail, the polarity of the ninth field effect transistor Q9 is opposite to that of the tenth field effect transistor Q10. In addition, one of the source and drain of the ninth field effect transistor Q9 is used to obtain the bias current, the other is connected to the bias current terminal of the second comparator U2, and the gate is connected to the second output terminal of the logic gate unit 150. One of the source and drain of the tenth field effect transistor Q10 is used to obtain the bias current, the other is connected to the bias current terminal of the second comparator U2, and the gate is connected to the first output terminal of the logic gate unit 150.

[0082] That is, when the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are both turned off, the second comparator U2 cannot obtain the bias current and cannot work to reduce power consumption. When at least one of the ninth field effect transistor Q9 and the tenth field effect transistor Q10 is turned on, the second comparator U2 obtains the bias current to work based on the bias current.

[0083] It should be noted that, in the above example, to ensure that the first comparator U1 and the second comparator U2 work alternately in sequence, the fourth field effect transistor Q4 and the ninth field effect transistor Q9 have the same polarity, and the fifth field effect transistor Q5 and the tenth field effect transistor Q10 have the same polarity.

[0084] That is to say, when the first comparator U1 can obtain the bias current (the fourth field effect transistor Q4 and the fifth field effect transistor Q5 are turned on), the second comparator U2 cannot obtain the bias current (the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are turned off); when the second comparator U2 can obtain the bias current (the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are turned on), the first comparator U1 cannot obtain the bias current (the fourth field effect transistor Q4 and the fifth field effect transistor Q5 are turned off).

[0085] Through the above configuration, the problem of high power consumption in the prior art due to the first comparator U1 and the second comparator U2 being in working state at the same time can be improved.

[0086] Furthermore, in order to perform a setting process on the output of the second comparator U2, in this embodiment, the second comparator U2 may further include a third input terminal.

[0087] In detail, the third input terminal of the second comparator U2 is connected to the second output terminal of the logic gate unit 150, so as to set the output of the second comparator U2 when the gate capacitance of the sixth field effect transistor Q6 begins to discharge. For example, if the output of the second comparator U2 is 0, the output of the second comparator U2 is set to 1.

[0088] Optionally, the type and quantity of logic devices included in the logic gate unit 150 are not limited and can be selected according to actual application requirements. For example, in an alternative example, it can be composed of an RS flip-flop and two inverters.

[0089] For another example, in another alternative example, the logic gate unit 150 can be composed of two RS flip-flops and four inverters. In detail, the first input terminal and the second input terminal of the first RS flip-flop are respectively connected to the output terminal of the first comparator U1 and the output terminal of the second comparator U2, and the first output terminal and the second output terminal are respectively connected to the first input terminal and the second input terminal of the second RS flip-flop. The first output terminal and the second output terminal of the second RS flip-flop are respectively connected to the input terminal of the first inverter and the input terminal of the second inverter. The output terminal of the first inverter serves as the first output terminal of the logic unit, and the output terminal of the second inverter serves as the second output terminal of the logic unit. In addition, the input terminal of the third inverter can be connected to the output terminal of the first inverter, and the output terminal serves as an output terminal of the oscillation signal. The input terminal of the fourth inverter can be connected to the output terminal of the second inverter, and the output terminal can serve as another output terminal of the oscillation signal.

[0090] It should be noted that, in the present embodiment, the specific types of the first field effect transistor Q1, the second field effect transistor Q2, the third field effect transistor Q3, the fourth field effect transistor Q4, the fifth field effect transistor Q5, the sixth field effect transistor Q6, the seventh field effect transistor Q7, the eighth field effect transistor Q8, the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are not restricted and can be selected according to actual application requirements. For example, they can be either N-type field effect transistors or P-type field effect transistors.

[0091] In this embodiment, a feasible example is provided, wherein the first field effect transistor Q1 may be a P-type field effect transistor, the second field effect transistor Q2 may be a P-type field effect transistor, the third field effect transistor Q3 may be an N-type field effect transistor, the fourth field effect transistor Q4 may be a P-type field effect transistor, the fifth field effect transistor Q5 may be an N-type field effect transistor, the sixth field effect transistor Q6 may be a P-type field effect transistor, the seventh field effect transistor Q7 may be a P-type field effect transistor, the eighth field effect transistor Q8 may be an N-type field effect transistor, the ninth field effect transistor Q9 may be a P-type field effect transistor, and the tenth field effect transistor Q10 may be an N-type field effect transistor.

[0092] In the above example, in the initial state, the output of the first comparator U1 is 0, the output of the second comparator U2 is 1, the output of the first output terminal of the logic gate unit 150 is 1, and the output of the second output terminal is 0.

[0093] Based on the above initial state, the second field effect transistor Q2 is turned off and the third field effect transistor Q3 is turned on, so that the gate capacitance of the first field effect transistor Q1 is grounded through the third field effect transistor Q3 to discharge, the fourth field effect transistor Q4 and the fifth field effect transistor Q5 are turned off, so that the first comparator U1 does not work and the output is set to 1 through the third input terminal. The seventh field effect transistor Q7 is turned on and the eighth field effect transistor Q8 is turned off, so that the gate capacitance of the second field effect transistor Q2 obtains the charging current through the seventh field effect transistor Q7 to charge, and the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are turned on, so that the second comparator U2 works.

[0094] After the gate capacitor of the second field effect transistor Q2 is charged for a preset period of time, the voltage of the gate capacitor is greater than the flip voltage of the second comparator U2, and the output of the second comparator U2 becomes 0. Correspondingly, the output of the first output terminal of the logic gate unit 150 becomes 0 and the output of the second output terminal becomes 1.

[0095] Based on the above-mentioned changed state, the seventh field effect transistor Q7 is turned off and the eighth field effect transistor Q8 is turned on, so that the gate capacitance of the sixth field effect transistor Q6 is grounded through the eighth field effect transistor Q8 to discharge, the ninth field effect transistor Q9 and the tenth field effect transistor Q10 are turned off, so that the second comparator U2 does not work and the output is set to 1 through the third input terminal. The second field effect transistor Q2 is turned on and the third field effect transistor Q3 is turned off, so that the gate capacitance of the first field effect transistor Q1 obtains the charging current through the second field effect transistor Q2 to charge, and the fourth field effect transistor Q4 and the fifth field effect transistor Q5 are turned on, so that the first comparator U1 works.

[0096] After the gate capacitor of the first field effect transistor Q1 is charged for a preset period of time, the voltage of the gate capacitor is greater than the flip voltage of the first comparator U1, and the output of the first comparator U1 becomes 0. Correspondingly, the output of the first output terminal of the logic gate unit 150 becomes 1, and the output of the second output terminal becomes 0.

[0097] By repeating the above steps, the oscillation signal can be generated. Specifically, the status value of each port can refer to the following table:

[0098]

[0099] Among them, R is the state of the output end of the first comparator U1, S is the state of the output end of the second comparator U2, Q is the state of the first output end of the logic gate unit 150, and QB is the state of the second output end of the logic gate unit 150.

[0100] In the above example, if the gate capacitance of the first field effect transistor Q1 and the gate capacitance of the sixth field effect transistor Q6 have the same capacitance value, the charging time of the gate capacitance of the first field effect transistor Q1 and the gate capacitance of the sixth field effect transistor Q6 are the same; the charging current of the gate capacitance of the first field effect transistor Q1 and the gate capacitance of the sixth field effect transistor Q6 are the same, and the flip voltage of the first comparator U1 and the flip voltage of the second comparator U2 are the same, then the period of the output oscillation signal is:

[0101]

[0102] Among them, t d is the charging time of the gate capacitance of the first field effect transistor Q1 or the gate capacitance of the sixth field effect transistor Q6, V REF is the flip voltage of the first comparator U1 or the second comparator U2, C is the capacitance value of the gate capacitance of the first field effect transistor Q1 or the gate capacitance of the sixth field effect transistor Q6, and I1 is the charging current of the gate capacitance of the first field effect transistor Q1 or the gate capacitance of the sixth field effect transistor Q6.

[0103] From the above formula, we can know that when the flip voltage comes from the reference voltage, the accuracy of the period of the oscillation signal is affected by the capacitance value and charging current of the gate capacitor. In other words, the accuracy of the period of the oscillation signal is affected by the ambient temperature and process angle changes.

[0104] Therefore, in order to overcome the problem that the process angle change affects the period of the oscillation signal, in this embodiment, Figure 3 The RC oscillator circuit 100 may further include a mirror current source unit 170, which is used to generate the charging current and the bias current respectively according to a reference current.

[0105] In detail, the mirror current source unit 170 may include a mirror current module 171 and a plurality of gating modules 173. The mirror current module 171 is used to copy the reference current to generate a mirror current, and to generate proportional charging current and bias current respectively by copying the mirror current. The plurality of gating modules 173 are used to control the magnitude of the mirror current after different numbers of gating modules 173 are turned on.

[0106] It should be noted that the mirror current refers to the current flowing through Figure 3 The current of P1 is shown. Moreover, the mirror current is obtained by replicating the reference current through three mirror structures. Then, P2 and P3 also form corresponding mirror structures with P1 respectively, so as to respectively replicate the mirror current to generate the charging current and the bias current.

[0107] By coordinating the mirror current module 171 and the plurality of gating modules 173, the reference current can be adjusted, thereby adjusting the charging current and the bias current to compensate for the deviation of the frequency of the oscillation signal caused by the process angle. Moreover, by using the same reference current to generate the charging current and the bias current, the complexity of the circuit structure can be effectively reduced, and the integrated processing of the circuit can be utilized.

[0108] Optionally, the number of the gating modules 173 is not limited and can be selected according to actual application requirements. In this embodiment, in an alternative example, the gating modules 173 can be four. The specific circuit structure can refer to Figure 3 shown.

[0109] Furthermore, in order to overcome the problem that the capacitance of the gate capacitor changes with the ambient temperature and thus causes the period accuracy of the oscillation signal to be low, in this embodiment, Figure 4 The RC oscillation circuit 100 may further include a reference current source unit 190 for generating the reference current.

[0110] In detail, the reference current source unit 190 may include a positive temperature coefficient current module 191 and a negative temperature coefficient current module 195 connected in parallel with the positive temperature coefficient current module 191. The positive temperature coefficient current module 191 includes a first fixed current submodule 192 and a plurality of first unit current modules 193 connected in parallel with the first fixed current submodule 192. The negative temperature coefficient current module 195 includes a second fixed current submodule 196 and a plurality of second unit current modules 197 connected in parallel with the second fixed current submodule 196.

[0111] The number of the first unit current modules 193 that are turned on and the number of the second unit current modules 197 that are turned on are adjusted so that the coefficient of change of the reference current is the same as the temperature coefficient of the gate capacitance of the first field effect transistor Q1. That is, when the change in the capacitance value of the gate capacitance is the same as the change in the reference current, the ratio of the capacitance value to the current value is fixed, and correspondingly, the calculated period value is also a fixed value.

[0112] Optionally, the number of the first unit current modules 193 and the number of the second unit current modules 197 are not limited and can be selected according to actual application requirements. For example, in an alternative example, the number of the first unit current modules 193 and the number of the second unit current modules 197 are both 4. The specific circuit structure can refer to Figure 4 shown.

[0113] In such Figure 4 In the circuit shown, the following relationship exists:

[0114] IPTAT=I3+n1*I p ;

[0115] ICTAT=I4+n2*I n ;

[0116] Among them, I PTAT is the current of the positive temperature coefficient current module 191, I CTAT is the current of the negative temperature coefficient current module 195, I3 is the current of the first fixed current submodule 192, I4 is the current of the second fixed current submodule 196, I P is the current of the first unit current module 193, I n is the current of the second unit current module 197 , n1 is the number of the first unit current modules 193 that are turned on, and n2 is the number of the second unit current modules 197 that are turned on.

[0117] Since I3 and I P have the same positive temperature coefficient, and is K p , I4 and I n have the same negative temperature coefficient, and is K n , therefore, the following relationship exists:

[0118] I3=K p *T+I a1 ;

[0119] I p =K p *T+I b1 ;

[0120] I4=K n *T+I a2 ;

[0121] I n =K n *T+I b2 ;

[0122] Among them, I a1 ,I b1 ,I a2 and I b2 are the initial currents of the corresponding modules respectively. Correspondingly, the reference current has the following relationship:

[0123] I BIAS =I PTAT +I CTAT ;

[0124] I PTAT +I CTAT =K p *T+I a1 +n1*(Kp *T+I b1 )+K n *T+I a2 +n2*(K n *T+I b2 );

[0125] Then, taking the derivative of the reference current with respect to temperature, we get:

[0126]

[0127] From the above formula, we can know that due to K p and K n The size of depends on the process and structure, therefore, by configuring n1 and n2, the period (frequency) of the oscillation signal can be made independent of temperature.

[0128] The embodiment of the present application further provides an RC oscillator device for generating an oscillation signal, wherein the RC oscillator device may include a circuit board and the above-mentioned RC oscillator circuit 100 .

[0129] In detail, the RC oscillator circuit 100 is integrated into the circuit board to form the RC oscillator device. The circuit board may be a PCB board or a silicon wafer. When the RC oscillator circuit 100 is integrated into the silicon wafer, a chip may be obtained through a series of packaging operations.

[0130] In summary, the RC oscillator circuit 100 and the RC oscillator device provided by the present application are arranged in coordination with the first oscillator unit 110, the second oscillator unit 130 and the logic gate unit 150 so that the first comparator U1 and the second comparator U2 are alternately in a charging state and a discharging state, so that even if the flip voltages of the first comparator U1 and the second comparator U2 are the same, the first comparator U1 and the second comparator U2 are not synchronously flipped due to the different input voltages of the first comparator U1 and the second comparator U2, and the generation of the oscillation signal can be realized. In other words, through the above arrangement, the same flip voltage can be set for the first comparator U1 and the second comparator U2 to improve the problem that different power supply circuits need to be set to provide different flip voltages because the two comparators need to set different flip voltages in the prior art, thereby causing a complex circuit structure, and it has extremely high practical value. Secondly, by using the gate capacitor of the field effect tube to replace the on-chip capacitor in the prior art, on the one hand, the problem of low precision of the oscillation signal caused by the influence of the ambient temperature can be reduced; on the other hand, the area of ​​the integrated chip can be reduced, and it has extremely high economic characteristics. Furthermore, by setting the fourth field effect transistor Q4 to have the same polarity as the ninth field effect transistor Q9, and the fifth field effect transistor Q5 to have the same polarity as the tenth field effect transistor Q10, the first comparator U1 and the second comparator U2 can not obtain the bias current at the same time, so that the first comparator U1 and the second comparator U2 work alternately, thereby effectively reducing the power consumption of the circuit. Then, by the coordinated setting of the mirror current module 171 and the plurality of gating modules 173, the reference current size can be adjusted, thereby adjusting the size of the charging current and the bias current to compensate for the deviation of the frequency of the oscillation signal caused by the process angle. Finally, by the coordinated setting of the positive temperature coefficient current module 191 and the negative temperature coefficient current module 195, the problem of deviation in the frequency of the oscillation signal generated due to the influence of the ambient temperature on the capacitor can be avoided.

[0131] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An RC oscillator circuit, characterized in that: include: A first oscillation unit, the first oscillation unit having a first comparator, an output end of the first comparator serving as an output end of the first oscillation unit; A second oscillation unit, the second oscillation unit having a second comparator, an output end of the second comparator serving as an output end of the second oscillation unit; a logic gate unit, wherein an input end of the logic gate unit is connected to an output end of the first oscillation unit and an output end of the second oscillation unit respectively, a first output end is connected to a control end of the first oscillation unit, and a second output end is connected to a control end of the second oscillation unit, and a level signal output by the first output end has a polarity opposite to that of a level signal output by the second output end; wherein, after the first oscillation unit is charged and the second oscillation unit is discharged for a preset time, the first comparator flips to enable the logic gate unit to control the first oscillation unit to discharge and the second oscillation unit to charge, and after a preset time, the second comparator flips to enable the logic gate unit to control the first oscillation unit to charge and the second oscillation unit to discharge; The first oscillation unit further comprises: a first field effect transistor, wherein a gate of the first field effect transistor is connected to a first input terminal of the first comparator, wherein after a gate capacitor of the first field effect transistor is charged by a charging current for a preset time period, a voltage of the gate capacitor is greater than a flip voltage of the first comparator, so that the first comparator flips; The first oscillation unit further comprises: a second field effect transistor, wherein one of a source and a drain of the second field effect transistor is used to obtain the charging current, and the other is connected to a gate of the first field effect transistor, and the gate is connected to a first output terminal of the logic gate unit; a third field effect transistor, one of a source and a drain of the third field effect transistor is connected to the gate of the first field effect transistor, the other is grounded, and the gate is connected to the first output terminal of the logic gate unit; The polarity of the second field effect tube is opposite to that of the third field effect tube, so that one of them is turned on and the other is turned off based on the level signal outputted from the first output terminal of the logic gate unit, and when the second field effect tube is turned on, the gate capacitance of the first field effect tube is charged by the charging current, and when the third field effect tube is turned on, the gate capacitance of the first field effect tube is discharged; The logic gate unit is composed of one RS flip-flop and two inverters.

2. The RC oscillator circuit according to claim 1, characterized in that: The first oscillation unit further comprises: a fourth field effect transistor, wherein one of the source and the drain of the fourth field effect transistor is used to obtain a bias current, the other is connected to the bias current terminal of the first comparator, and the gate is connected to the first output terminal of the logic gate unit; A fifth field effect transistor with opposite polarity to the fourth field effect transistor, wherein one of the source and the drain of the fifth field effect transistor is used to obtain the bias current, the other is connected to the bias current terminal of the first comparator, and the gate is connected to the second output terminal of the logic gate unit.

3. The RC oscillator circuit according to claim 2, characterized in that: The device further includes a mirror current source unit for generating the charging current and the bias current according to a reference current, wherein the mirror current source unit includes: A mirror current module, used for copying the reference current to generate a mirror current, and generating proportional charging current and bias current respectively by copying the mirror current; A plurality of gating modules are used to control the magnitude of the mirror current after different numbers of gating modules are turned on.

4. The RC oscillator circuit according to claim 3, characterized in that: Also included is a reference current source unit for generating the reference current, the reference current source unit comprising: A positive temperature coefficient current module, comprising a first fixed current submodule and a plurality of first unit current modules connected in parallel with the first fixed current submodule; A negative temperature coefficient current module connected in parallel with the positive temperature coefficient current module comprises a second fixed current submodule and a plurality of second unit current modules connected in parallel with the second fixed current submodule; The number of the first unit current modules that are turned on and the number of the second unit current modules that are turned on are adjusted so that the coefficient of variation of the reference current is the same as the temperature coefficient of the gate capacitance of the first field effect transistor.

5. The RC oscillator circuit according to claim 1, characterized in that: The first comparator further comprises: A second input terminal, the second input terminal is used to obtain a flip voltage; A third input terminal is connected to the first output terminal of the logic gate unit to set the output of the first comparator when the gate capacitance of the first field effect transistor starts to charge.

6. The RC oscillator circuit according to any one of claims 1 to 5, characterized in that: The second oscillation unit further comprises: A sixth field effect transistor, the gate of which is connected to the first input terminal of the second comparator, wherein after the gate capacitor of the sixth field effect transistor is charged by a charging current for a preset time period, the voltage of the gate capacitor is greater than the flipping voltage of the second comparator, so that the second comparator flips.

7. The RC oscillator circuit according to claim 6, characterized in that: The second oscillation unit further comprises: a seventh field effect transistor, wherein one of the source and the drain of the seventh field effect transistor is used to obtain the charging current, the other of the source and the drain is connected to the gate of the sixth field effect transistor, and the gate is connected to the second output terminal of the logic gate unit; an eighth field effect transistor, one of a source and a drain of the eighth field effect transistor is connected to the gate of the sixth field effect transistor, the other is grounded, and the gate is connected to the second output terminal of the logic gate unit; Among them, the polarity of the seventh field effect tube is opposite to that of the eighth field effect tube, so that one of them is turned on and the other is turned off based on the level signal output from the second output end of the logic gate unit, and when the seventh field effect tube is turned on, the gate capacitance of the sixth field effect tube is charged by the charging current, and when the eighth field effect tube is turned on, the gate capacitance of the sixth field effect tube is discharged.

8. The RC oscillator circuit according to claim 7, characterized in that: The second oscillation unit further comprises: a ninth field effect transistor, wherein one of the source and the drain of the ninth field effect transistor is used to obtain a bias current, the other is connected to the bias current terminal of the second comparator, and the gate is connected to the second output terminal of the logic gate unit; A tenth field effect transistor having a polarity opposite to that of the ninth field effect transistor, wherein one of the source and the drain of the tenth field effect transistor is used to obtain the bias current, the other is connected to the bias current terminal of the second comparator, and the gate is connected to the first output terminal of the logic gate unit.

9. The RC oscillator circuit according to claim 8, characterized in that: When the first oscillation unit includes a fourth field effect transistor and a fifth field effect transistor, the fourth field effect transistor has the same polarity as the ninth field effect transistor, and the fifth field effect transistor has the same polarity as the tenth field effect transistor.

10. The RC oscillator circuit according to claim 6, characterized in that: The second comparator further comprises: A second input terminal, the second input terminal is used to obtain a flip voltage; A third input terminal is connected to the second output terminal of the logic gate unit to set the output of the second comparator when the gate capacitance of the sixth field effect transistor starts to charge.

11. An RC oscillator device, characterized in that: It comprises a circuit board and the RC oscillator circuit according to any one of claims 1 to 10, wherein the RC oscillator circuit is integrated in the circuit board.

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