semiconductor devices

Abstract

The present disclosure relates to a semiconductor device. The performance of the semiconductor device is enhanced. The semiconductor device is obtained by sealing a first, second, and third semiconductor chip, each including a power transistor for high-side switching; a fourth, fifth, and sixth semiconductor chip, each including a power transistor for low-side switching; and a semiconductor chip including a control circuit for controlling these chips in a sealed portion. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. When viewed in a plane, the lead LD9 intersects with the edge MRd4 of the sealed portion, and the lead LD10 intersects with the edge MRd2 of the sealed portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2017-180379 filed on September 20, 2017 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and is advantageously applicable to a semiconductor device obtained by, for example, sealing three semiconductor chips each including a power transistor for high-side switching, three semiconductor chips each including a power transistor for low-side switching, and a semiconductor chip that controls these chips. Background Art

[0004] An inverter circuit, widely used as an example of a power supply circuit, has a configuration in which a power MOSFET for a high-side switch and a power MOSFET for a low-side switch are coupled in series between a terminal supplied with a power supply voltage and a terminal supplied with a ground voltage. By controlling the gate voltages of the power MOSFET for the high-side switch and the gate voltages of the power MOSFET for the low-side switch using a control circuit, the power supply voltage can be converted using the inverter circuit.

[0005] Japanese Unexamined Patent Application Publication No. 2007-012857 (Patent Document 1) describes a technique related to an HSOP 46 for driving a three-phase motor obtained by sealing three first semiconductor chips 30 including pMISFETs and three second semiconductor chips 31 including nMISFETs with a sealing portion 44 .

[0006] Japanese Unexamined Patent Application Publication No. 2013-149730 (Patent Document 2) describes a power semiconductor module 100B including six semiconductor chips 120c to 120h as IGBT chips and six semiconductor chips 140c to 140h as diode chips, as shown in FIG. Figures 9 to 12 As shown in .

[0007] [Related technical literature]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2007-012857

[0010] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2013-149730 Summary of the Invention

[0011] It is desirable to enhance the performance of a semiconductor device obtained by encapsulating three semiconductor chips, each including a power transistor for high-side switching, three semiconductor chips, each including a power transistor for low-side switching, and a semiconductor chip for controlling these chips. Alternatively, it is desirable to reduce the size of the semiconductor device. Alternatively, it is desirable to enhance the performance of the semiconductor device and further reduce the size of the semiconductor device.

[0012] Other problems and novel features will be apparent from the description in this specification and the accompanying drawings.

[0013] According to an embodiment, a semiconductor device is obtained by sealing first, second, and third semiconductor chips, each including a power transistor for a high-side switch, fourth, fifth, and sixth semiconductor chips, each including a power transistor for a low-side switch, and a seventh semiconductor chip including a control circuit for controlling these chips, with a sealing body. The first, second, and third semiconductor chips are mounted on a first chip mounting portion, and the fourth, fifth, sixth, and seventh semiconductor chips are mounted on a second, third, fourth, and fifth chip mounting portions, respectively. The semiconductor device includes a plurality of first leads electrically coupled to a first electrode of the first semiconductor chip, a plurality of second leads electrically coupled to a second electrode of the second semiconductor chip, and a plurality of third leads electrically coupled to a third electrode of the third semiconductor chip. The semiconductor device also includes: a plurality of fourth leads electrically coupled to a fourth back electrode of the fourth semiconductor chip; a plurality of fifth leads electrically coupled to a fifth back electrode of the fifth semiconductor chip; and a plurality of sixth leads electrically coupled to a sixth back electrode of the sixth semiconductor chip. The semiconductor device also includes a plurality of seventh leads and a plurality of eighth leads electrically coupled to the first, second, and third back electrodes of the first, second, and third semiconductor chips; and a plurality of ninth leads and a plurality of tenth leads electrically coupled to the fourth, fifth, and sixth electrodes of the fourth, fifth, and sixth semiconductor chips through the first metal plate. When viewed in a plane, the seal includes a first side extending along a first direction, a second side extending along a second direction intersecting the first direction, a third side extending along the first direction and located on the opposite side of the first side, and a fourth side extending along the second direction and located on the opposite side of the second side. When viewed in a plane, the first lead, the second lead, and the third lead intersect with the third side of the seal, and the fourth lead, the fifth lead, and the sixth lead intersect with the first side of the seal. When viewed in a plane, the eighth lead and the tenth lead intersect with the second side of the seal, and the seventh lead and the ninth lead intersect with the fourth side of the seal.

[0014] According to the embodiment, the performance of the semiconductor device can be enhanced.

[0015] Alternatively, the size of the semiconductor device can be reduced.

[0016] Alternatively, the performance of the semiconductor device can be enhanced, and the size of the semiconductor device can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit diagram schematically illustrating a circuit formed in a control board for controlling a 12-phase BLDC motor;

[0018] Figure 2 This is an explanatory diagram illustrating a rack-and-pinion steering mechanism of an automobile;

[0019] Figure 3A is an explanatory diagram illustrating how the control panel rotates together with the steering shaft;

[0020] Figure 3B is an explanatory diagram illustrating how the control panel rotates together with the steering shaft;

[0021] Figure 4 is a circuit diagram illustrating an inverter circuit using a semiconductor device in an embodiment;

[0022] Figure 5 is a top view of a semiconductor device in an embodiment;

[0023] Figure 6 is a bottom view of the semiconductor device in the embodiment;

[0024] Figure 7 is a plan perspective view of a semiconductor device in an embodiment;

[0025] Figure 8 is a plan perspective view of a semiconductor device in an embodiment;

[0026] Figure 9 is a plan perspective view of a semiconductor device in an embodiment;

[0027] Figure 10 is a cross-sectional view of a semiconductor device in an embodiment;

[0028] Figure 11 is a cross-sectional view of a semiconductor device in an embodiment;

[0029] Figure 12 is a cross-sectional view of a semiconductor device in an embodiment;

[0030] Figure 13 is a cross-sectional view of a semiconductor device in an embodiment;

[0031] Figure 14 is a cross-sectional view of a semiconductor device in an embodiment;

[0032] Figure 15 is a cross-sectional view of a semiconductor device in an embodiment;

[0033] Figure 16 is a plan view of a semiconductor device in an embodiment during manufacturing;

[0034] Figure 17 Then Figure 16 a plan view of a semiconductor device during manufacturing;

[0035] Figure 18 Then Figure 17 a plan view of a semiconductor device during manufacturing;

[0036] Figure 19 Then Figure 18 a plan view of a semiconductor device during manufacturing;

[0037] Figure 20 Then Figure 19 a plan view of a semiconductor device during manufacturing;

[0038] Figure 21 Then Figure 20 a plan view of a semiconductor device during manufacturing;

[0039] Figure 22 is with Figure 21 a cross-sectional view of the same semiconductor device during fabrication;

[0040] Figure 23 is a plan view illustrating implementation of a semiconductor device in an embodiment;

[0041] Figure 24 is a cross-sectional view illustrating implementation of a semiconductor device in an embodiment;

[0042] Figure 25 is a cross-sectional view illustrating implementation of a semiconductor device in an embodiment;

[0043] Figure 26 is a cross-sectional view illustrating implementation of a semiconductor device in an embodiment;

[0044] Figure 27 is a cross-sectional view illustrating implementation of a semiconductor device in an embodiment;

[0045] Figure 28 is a cross-sectional view illustrating implementation of a semiconductor device in an embodiment;

[0046] Figure 29 is a cross-sectional view illustrating implementation of a semiconductor device in an embodiment;

[0047] Figure 30It is the wiring of the circuit board superimposed on it. Figure 5 A plan view of a semiconductor device in FIG.

[0048] Figure 31 is a top view of the semiconductor device in the study example;

[0049] Figure 32 is a bottom view of the semiconductor device in the study example;

[0050] Figure 33 is a plan perspective view of a semiconductor device in a study example;

[0051] Figure 34 is a plan perspective view of a semiconductor device in a study example; and

[0052] Figure 35 This is a plan perspective view of a semiconductor device in the study example. DETAILED DESCRIPTION

[0053] In the following description of each embodiment, for convenience, if necessary, the embodiment is divided into multiple parts or embodiments. Unless otherwise clearly stated, these parts and embodiments are not unrelated to each other, and a part and embodiment is a modification of the detailed description or supplementary explanation of part or all of another part and embodiment. When the number of components, etc. (including number of pieces, numerical value, quantity, range, etc.) is mentioned in the following description of each embodiment, unless otherwise clearly stated or the description principle is obviously limited to this specific number, the description is not limited to this specific number. Any quantity not less than or greater than this specific number is acceptable. In the following description of each embodiment, unless otherwise clearly stated or it is obviously considered to be indispensable in principle, it goes without saying that each of its constituent elements (including constituent steps, etc.) is not always indispensable. Similarly, when mentioning the shape, positional relationship, etc. of each constituent element, etc., unless otherwise clearly stated or it is obviously considered not to be so in principle, it includes a shape that is substantially similar or similar to the shape, etc. The same applies to the above-mentioned quantity and range.

[0054] Hereinafter, a detailed description of the embodiments will be given with reference to the accompanying drawings. In all drawings illustrating the following embodiments, components having the same functions will be labeled with the same reference numerals, and their repeated description will be omitted. With respect to the following embodiments, the description of the same or similar items will not be repeated unless particularly necessary.

[0055] In the drawings referred to in conjunction with the following embodiments, even if the drawings are cross-sectional views, hatching may be omitted to make the drawings more visible. Even plan views may be hatched to make the drawings more visible.

[0056] In this specification, field effect transistors will be referred to as MOSFETs (metal oxide semiconductor field effect transistors) or simply MOS, but non-oxide films are not excluded from the gate insulating film. That is, when MOSFET is referred to in this specification, it includes not only MISFETs (metal insulator semiconductor field effect transistors: MIS type field effect transistors) using an oxide film (silicon oxide film) as a gate insulating film but also MISFETs using an insulating film other than an oxide film (silicon oxide film) as a gate insulating film.

[0057] Study Details

[0058] In recent years, with an eye toward enhancing functionality and safety for practical applications in autonomous vehicles, design and development efforts have been underway to replace the three-phase BLDC motors of related art with six-phase or 12-phase BLDC motors. Since BLDC motors are not self-commutating and are generally considered complex to control, six-phase BLDC motors utilize two sets of the three phases of related art (U-phase, V-phase, and W-phase), while 12-phase BLDC motors utilize four sets of the three phases of related art (U-phase, V-phase, and W-phase). Consequently, if a fault occurs in any one set, the fault may not be immediately apparent.

[0059] The present inventors have been considering using a SiP (system-in-package) to control the three phases of a BLDC motor. The SiP includes three semiconductor chips CP1, CP2, and CP3, each including a power MOSFET for a high-side switch, three semiconductor chips CP4, CP5, and CP6, each including a power MOSFET for a low-side switch, and a semiconductor chip CPC that controls these semiconductor chips. Three inverter circuits are formed by this SiP, and the AC power supplied from the three inverter circuits is supplied to each of the three-phase coils of the BLDC motor. To this end, the present inventors have been considering using two or four of the above-mentioned SiPs mounted on a circuit board (corresponding to the circuit board PB1 described later) as a control board (corresponding to the control board PB described later) for controlling a six-phase BLDC motor or a 12-phase BLDC motor. The semiconductor device PKG described later corresponds to this SiP.

[0060] Figure 1 FIG. 1 is a circuit diagram schematically illustrating a circuit (motor drive system) formed in a control board for controlling a 12-phase BLDC motor.

[0061] Figure 1 The motor MOT shown in FIG is a 12-phase BLDC motor and has 12 coils CL, each of which is coupled to an inverter circuit INV. That is, an inverter circuit INV is provided for each of the 12 coils of the motor MOT; therefore, Figure 1The circuit in FIG has a total of 12 inverter circuits INV. Since three inverter circuits INV are formed by the above-mentioned SiP (semiconductor device PKG), Figure 1 The circuit in FIG. 1 requires four SiPs. The four SiPs are coupled to and controlled by a control circuit CT, which in turn controls each inverter circuit INV. AC power is supplied from each inverter circuit INV to each coil CL coupled to the inverter circuit INV, driving the motor MOT.

[0062] Figure 2 The present inventors consider using the space around the steering shaft SF to set up a control board (electronic device, module) PB, wherein Figure 1 The circuit in Figure 2 That is, the inventors considered making the steering shaft SF pass through the control plate PB.

[0063] exist Figure 2 In the steering mechanism shown in FIG, a rack and pinion mechanism RP is located at the top of a steering shaft SF, which is coupled to a steering wheel (steering disc) HN. When the steering wheel HN is turned, the steering shaft SF also rotates. This rotational motion is converted into horizontal movement by the rack and pinion mechanism RP and transmitted to the tire TY via the connecting rod TR and kingpin KP. Thus, the tire TY can be steered to change its direction by operating (turning) the steering wheel HN.

[0064] When the steering wheel HN is turned, the steering shaft SF also rotates; therefore, in a case where the steering shaft SF penetrates the control board PB, the control board PB also rotates together with the steering shaft SF. Figure 3A and Figure 3B It is an explanatory diagram (plan view) illustrating how the control board PB rotates together with the steering shaft SF. Figure 3A The case where the planar shape of the control board PB is a rectangle is shown, and Figure 3B The case where the planar shape of the control board PB is circular is shown.

[0065] When the planar shape of the control board PB is circular, the space required for the rotation of the control board PB is least wasted. Figure 3A When the rectangular shape is shaped like a circle, the circular area with a diameter equal to the length of the diagonal line of the rectangle is the space required for the control board PB to rotate. As a result, the space required for the control board PB to rotate is larger than the size of the control board PB. At the same time, when the planar shape of the control board PB is as follows Figure 3BWhen the control board PB is circular, the space required to rotate the control board PB is substantially the same as the size of the control board PB. Therefore, by making the control board PB circular in plan view, it is possible to effectively minimize the increase in the space required to install and rotate the control board PB. To this end, the inventors have considered using a circular control board PB with four SiPs mounted thereon as the control board PB for controlling a 12-phase BLDC motor.

[0066] Circuit system

[0067] Figure 4 1 is a circuit diagram illustrating an inverter circuit using a semiconductor device PKG in this embodiment. A region surrounded by alternating long and short dashed lines is formed within the semiconductor device PKG.

[0068] Used for Figure 4 The semiconductor device PKG of the inverter circuit shown in FIG. 1 includes six power MOSFETs 1, 2, 3, 4, 5, and 6 and a control circuit CLC. Control circuit CLC is formed within semiconductor chip CPC. Power MOSFET 1 is formed within semiconductor chip CP1; power MOSFET 2 is formed within semiconductor chip CP2; and power MOSFET 3 is formed within semiconductor chip CP3. Power MOSFET 4 is formed within semiconductor chip CP4; power MOSFET 5 is formed within semiconductor chip CP5; and power MOSFET 6 is formed within semiconductor chip CP6. The seven semiconductor chips CP1 to CP6 and CPC are sealed together to form the semiconductor device PKG.

[0069] Power MOSFETs 1 and 4 and control circuit CLC form one inverter circuit INV. Power MOSFETs 2 and 5 and control circuit CLC form another inverter circuit INV. Power MOSFETs 3 and 6 and control circuit CLC form yet another inverter circuit INV. Thus, three inverter circuits INV are formed by one semiconductor device PKG.

[0070] The control circuit CLC is a circuit that controls the potential of each respective gate of the power MOSFETs 1 to 6 and controls the operation of each of the power MOSFETs 1 to 6 in response to a signal or the like supplied to the control circuit CLC from the control circuit CT outside the semiconductor device PKG. Each gate of the power MOSFETs 1 to 6 is coupled to a driver circuit in the control circuit CLC.

[0071] The source (S1) of power MOSFET 1 is coupled to terminal TE1; the source (S2) of power MOSFET 2 is coupled to terminal TE2; and the source (S3) of power MOSFET 3 is coupled to terminal TE3. The drain (D4) of power MOSFET 4 is coupled to terminal TE4; the drain (D5) of power MOSFET 5 is coupled to terminal TE5; and the drain (D6) of power MOSFET 6 is coupled to terminal TE6. The drain (D1) of power MOSFET 1, the drain (D2) of power MOSFET 2, and the drain (D3) of power MOSFET 3 are coupled to terminal TE7 and terminal TE8. The source (S4) of power MOSFET 4, the source (S5) of power MOSFET 5, and the source (S6) of power MOSFET 6 are coupled to terminal TE9 and terminal TE10.

[0072] Terminals TE1 to TE12 are all external connection terminals of the semiconductor device PKG and are formed by the lead LD described later. Among these terminals, terminals TE7 and TE8 are terminals for supplying a power supply potential, and lead LD7 described later corresponds to terminal TE7, and lead LD8 described later corresponds to terminal TE8. Terminals TE9 and TE10 are terminals for supplying a reference potential, and lead LD9 described later corresponds to terminal TE9, and lead LD10 described later corresponds to terminal TE10. Terminals TE7 and TE8 (leads LD7 and LD8) are supplied with the high-potential side potential (power supply potential) VIN of the power supply (input power supply) external to the semiconductor device PKG, and terminals TE9 and TE10 (leads LD9 and LD10) are supplied with a reference potential, for example, a ground potential (ground potential) GND that is lower than the potential VIN supplied to terminals TE7 and TE8. Lead LD1 described later corresponds to terminal TE1; lead LD2 described later corresponds to terminal TE2; lead LD3 described later corresponds to terminal TE3; lead LD4 described later corresponds to terminal TE4; lead LD5 described later corresponds to terminal TE5; lead LD6 described later corresponds to terminal TE6.

[0073] Terminal TE1 (lead LD1) and terminal TE4 (lead LD4) are electrically coupled to each other outside the semiconductor device PKG. That is, the source (S1) of power MOSFET 1 and the drain (D4) of power MOSFET 4 are electrically coupled to each other via a conductive path provided outside the semiconductor device PKG. Therefore, power MOSFET 1 and power MOSFET 4 are coupled in series between terminals TE7 and TE8 and terminals TE9 and TE10, and power MOSFET 1 corresponds to a MOSFET for the high side, while power MOSFET 4 corresponds to a MOSFET for the low side.

[0074] Terminal TE2 (lead LD2) and terminal TE5 (lead LD5) are electrically coupled to each other outside the semiconductor device PKG. That is, the source (S2) of power MOSFET 2 and the drain (D5) of power MOSFET 5 are electrically coupled to each other via a conductive path provided outside the semiconductor device PKG. Therefore, power MOSFET 2 and power MOSFET 5 are coupled in series between terminals TE7 and TE8 and terminals TE9 and TE10, and power MOSFET 2 corresponds to a MOSFET for the high side, while power MOSFET 5 corresponds to a MOSFET for the low side.

[0075] Terminal TE3 (lead LD3) and terminal TE6 (lead LD6) are electrically coupled to each other outside the semiconductor device PKG. That is, the source (S3) of power MOSFET 3 and the drain (D6) of power MOSFET 6 are electrically coupled to each other via a conductive path provided outside the semiconductor device PKG. To this end, power MOSFET 3 and power MOSFET 6 are coupled in series between terminals TE7 and TE8 and terminals TE9 and TE10, with power MOSFET 3 corresponding to a MOSFET for the high side and power MOSFET 6 corresponding to a MOSFET for the low side.

[0076] Each of power MOSFETs 1, 2, and 3 is a power transistor for high-side (high-potential) switching, and each of power MOSFETs 4, 5, and 6 is a power transistor for low-side (low-potential) switching. Therefore, power MOSFETs 1, 2, 3, 4, 5, and 6 can all be considered switching power transistors.

[0077] However, the conductive paths of the electrical coupling terminals TE1 and TE4, the conductive paths of the electrical coupling terminals TE2 and TE5, and the conductive paths of the electrical coupling terminals TE3 and TE6 are not provided within the semiconductor device PKG. Instead, these conductive paths are provided outside the semiconductor device PKG, for example, within the circuit board PB1 (described later) on which the semiconductor device PKG is mounted. Therefore, the node TE13 between the power MOSFET 1 (source S1) and the power MOSFET 4 (drain D4), the node TE14 between the power MOSFET 2 (source S2) and the power MOSFET 5 (drain D5), and the node TE15 between the power MOSFET 3 (source S3) and the power MOSFET 6 (drain D6) are provided outside the semiconductor device PKG (within the circuit board PB1). Each of the nodes TE13, TE14, and TE15 is coupled to the coil (load) CL of the motor MOT. For example, the coil CL coupled to the node TE13 is the coil CL3 for the W phase, the coil CL coupled to the node TE14 is the coil CL2 for the V phase, and the coil CL coupled to the node TE15 is the coil CL1 for the U phase.

[0078] The direct current supplied to the inverter circuit (INV) formed by power MOSFETs 1 and 4 and the control circuit CLC is converted into alternating current and supplied to the coil CL (CL3) of the motor MOT. The direct current supplied to the inverter circuit (INV) formed by power MOSFETs 2 and 5 and the control circuit CLC is converted into alternating current and supplied to the coil CL (CL2) of the motor MOT. The direct current supplied to the inverter circuit (INV) formed by power MOSFETs 3 and 6 and the control circuit CLC is converted into alternating current and supplied to the coil CL (CL1) of the motor MOT. The motor MOT is driven by the alternating current supplied from each inverter circuit.

[0079] The lead LD11 described later corresponds to the terminal TE11, and the lead LD12 described later corresponds to the terminal TE12. The control circuit CLC is coupled to the terminals TE11 and TE12 (leads LD11 and LD12), and the terminals TE11 and TE12 (leads LD11 and LD12) are coupled to the above-mentioned control circuit CT provided outside the semiconductor device PKG.

[0080] Each semiconductor chip CP1 to CP6 includes not only a power MOSFET (1 to 6) but also a current detection sensing MOSFET (not shown) and a temperature detection diode (not shown). As a result, the current, voltage and temperature of each semiconductor chip CP1 to CP6 can be detected using the above-mentioned control circuit (digital and analog hybrid circuit) CLC. The thermal resistance between the semiconductor chips CP1 to CP6 and the heat sink HS described later is sufficiently smaller than the thermal resistance between the semiconductor chips CP1 to CP6 and the control semiconductor chip CPC. Therefore, even when the temperature of the semiconductor chips CP1 to CP6 reaches, for example, 175°C, the possibility that the temperature of the control semiconductor chip CPC will reach 175°C is small. Therefore, when the control circuit CLC in the control semiconductor chip CPC is used to detect the temperature of each power (switching) semiconductor chip CP1 to CP6, an advantage is brought. When the temperature reaches a predetermined limit temperature (for example, 175°C), the operation of the power semiconductor chips CP1 to CP6 can be stopped by using a thermal shutdown circuit provided in the control circuit CLC to prevent thermal damage to the entire semiconductor device PKG. Therefore, even when the semiconductor device PKG adopts a structure in which the control semiconductor chip CPC is surrounded by the power semiconductor chips CP1 to CP6 when viewed in a plane, as described later, malfunction of the control semiconductor chip CPC caused by heat generated in the power semiconductor chips CP1 to CP6 can be prevented.

[0081] The thermal shutdown circuit referred to here refers to a circuit that cuts off the output voltage to reduce the temperature of the semiconductor chip (power semiconductor chip) to a safe level when the junction temperature of the semiconductor chip of interest (power semiconductor chip) rises abnormally (for example, to 150 to 200°C). The operating principle of the thermal shutdown circuit is as follows: the forward voltage (Vf) of the temperature detection diode built into the power semiconductor chip and a reference voltage (Vk) are input to a comparator in the thermal shutdown circuit; when the temperature of the temperature detection diode rises to a predetermined temperature, the magnitude relationship between the forward voltage (Vf) of the diode and the reference voltage (Vk) is reversed, and the output of the comparator is switched; and the gate of the power MOSFET in the power semiconductor chip can be controlled to stop the operation of the power MOSFET by feeding it on / off to the pre-driver in the control circuit CLC. A comparator is an element that compares two input voltages or currents and switches its output depending on which is greater.

[0082] Structure of semiconductor devices

[0083] Figure 5 is a top view of the semiconductor device PKG in this embodiment; Figure 6 It is a bottom view of the semiconductor device PKG; Figures 7 to 9 is a plan perspective view of the semiconductor device PKG; and Figures 10 to 15It is a cross-sectional view of the semiconductor device PKG. Figure 7 1 is a plan perspective view of the semiconductor device PKG with the sealing portion MR seen through, when viewed from the lower surface side. Figure 8 The wire BW and the metal plates MP1, MP2, MP3, MP4 are further seen (omitted). Figure 7 semiconductor devices in. Figure 9 The semiconductor chips CPC, CP1 to CP6 are further seen (omitted). Figure 8 The semiconductor device in Figures 6 to 9 In the embodiment, the orientation of the semiconductor device PKG is the same, so the position of each side MRc1, MRc2, MRc3, MRc4 (side MRd1, MRd2, MRd3, MRd4) of the sealing portion MR is Figures 6 to 9 Same as in Figures 7 to 9 , the position of the periphery of the sealing portion MR is indicated by a dotted line. Figure 7 The cross section taken along line A1-A1 corresponds substantially to Figure 10 ; Along Figure 7 The cross section taken along line A2-A2 corresponds substantially to Figure 11 ; Along Figure 7 The cross section taken along line A3-A3 substantially corresponds to Figure 12 Along Figure 7 The cross section taken along line A4-A4 substantially corresponds to Figure 13 ; Along Figure 7 The cross section taken along line A5-A5 substantially corresponds to Figure 14 ; Along Figure 7 The cross section taken along line A6-A6 substantially corresponds to Figure 15 In each plan view, the symbol X indicates a first direction, and the symbol Y indicates a second direction intersecting (more specifically, orthogonal to) the first direction. Hereinafter, the first direction will be referred to as the X direction, and the second direction intersecting (more specifically, orthogonal to) the X direction will be referred to as the Y direction. That is, the X direction and the Y direction are directions intersecting each other, and more specifically, directions orthogonal to each other.

[0084] In this embodiment, a semiconductor chip (control semiconductor chip) CPC having the control circuit CLC formed therein and semiconductor chips (power semiconductor chips) CP1, CP2, CP3, CP4, CP5, CP6 having the power MOSFETs 1, 2, 3, 4, 5, 6 formed therein, respectively, are integrated (packaged) into a single semiconductor package to construct a semiconductor device PKG. This makes it possible to reduce the size and profile of the electronic device (for example, the control board PB) and reduce wiring parasitic inductance, resulting in higher frequencies and higher efficiency.

[0085] Figures 5 to 15 The semiconductor device (semiconductor package, semiconductor module, electronic device, SiP) PKG in this embodiment shown in FIG is a semiconductor device in a resin-sealed semiconductor package, and in this example is a QFP (quad flat package) semiconductor device. Figures 5 to 15 A description is given of the configuration of the semiconductor device PKG.

[0086] Figures 5 to 15 The semiconductor device PKG in this embodiment shown in includes: tube core pads (chip mounting parts) DPC, DPH, DP1, DP2, DP3; semiconductor chips CPC, CP1, CP2, CP3, CP4, CP5, CP6; metal plates MP1, MP2, MP3, MP4; multiple wires (bonding wires) BW; multiple leads LD; and a sealing part (sealing body) MR that seals these items.

[0087] Hereinafter, the semiconductor chips CP1, CP2, CP3, CP4, CP5, and CP6 may be referred to as semiconductor chips CP1 to CP6, the metal plates MP1, MP2, MP3, and MP4 may be referred to as metal plates MP1 to MP4, and the die pads DP1, DP2, and DP3 may be referred to as die pads DP1 to DP3. This is similar to other components.

[0088] The sealing portion MR, which is a resin sealing portion (resin sealing body), is formed of a resin material such as a thermosetting resin material and may contain a filler, etc. The sealing portion MR can be formed using an epoxy resin containing a filler, etc. In addition to epoxy-based resins, for example, biphenyl thermosetting resins to which a phenol-based curing agent, silicone rubber, fillers, etc. are added can be used as the material of the sealing portion MR for the purpose of reducing stress, etc.

[0089] The sealing portion MR includes a main surface (top surface) MRa, a back surface (lower surface, bottom surface) MRb located opposite to the main surface MRa, and side surfaces MRc1, MRc2, MRc3, MRc4 intersecting the main surface MRa and the back surface MRb.

[0090] That is, the seal portion MR has an outer appearance of a thin plate surrounded by the main surface MRa, the back surface MRb, and the side surfaces MRc1 to MRc4. Of the side surfaces MRc1 to MRc4 of the seal portion MR, side surface MRc1 and side surface MRc3 are located on opposite sides of each other; side surface MRc2 and side surface MRc4 are located on opposite sides of each other; side surface MRc1 intersects with side surfaces MRc2 and MRc4; and side surface MRc3 intersects with side surfaces MRc2 and MRc4. Side surfaces MRc1 and MRc3 are substantially parallel to the X direction, and side surfaces MRc2 and MRc4 are substantially parallel to the Y direction. Each of the main surface MRa and the back surface MRb is parallel to both the X and Y directions.

[0091] When viewed in a plane, the sealing portion MR includes: a side MRd1 extending along the X direction; a side MRd3 extending along the X direction and located on the opposite side of the side MRd1; a side MRd2 extending along the Y direction; and a side MRd4 extending along the Y direction and located on the opposite side of the side MRd2. When viewed in a plane, each of the sides MRd2 and MRd4 intersects with the sides MRd1 and MRd3. In the sealing portion MR, the side MRd1 corresponds to the side MRc1, the side MRd2 corresponds to the side MRc2, the side MRd3 corresponds to the side MRc3, and the side MRd4 corresponds to the side MRc4. That is, when viewed in a plane, each of the side surfaces MRc1 to MRc4 of the sealing portion MR can be considered to be each of the sides MRd1 to MRd4 of the sealing portion MR.

[0092] The planar shape of the sealing portion MR, that is, the planar shape of each of the main surface MRa and the back surface MRb of the sealing portion MR is, for example, a rectangle (ellipse). The rectangle constituting the planar shape of the sealing portion MR is a rectangle having sides parallel to the X direction and sides parallel to the Y direction.

[0093] A portion of each lead LD is sealed within the seal portion MR, while another portion protrudes from the side of the seal portion MR to the outside of the seal portion MR. Hereinafter, the portion of the lead LD located within the seal portion MR is referred to as the inner lead portion, and the portion of the lead LD located outside the seal portion MR is referred to as the outer lead portion. A plating layer (not shown), such as a solder plating layer, may be formed on the outer lead portion of the lead LD. This facilitates mounting the semiconductor device PKG on a circuit board, etc.

[0094] The semiconductor device PKG in this embodiment has a structure in which a portion of each lead LD (outer lead portion) protrudes from the side of the sealing portion MR. The following description is given based on this structure, but the present invention is not limited to this structure. For example, a QFN (quad flat no-lead package) structure can be adopted in which each lead LD hardly protrudes from the side of the sealing portion MR and a portion of each lead LD is exposed at the back surface MRb of the sealing portion MR. However, compared to the QFN, the QFP has the advantage of enhancing solder wettability during mounting on a circuit board, etc.

[0095] The leads LD provided in the semiconductor device PKG include a plurality of leads LD provided on the side MRc1 of the sealing portion MR, a plurality of leads LD provided on the side MRc2 of the sealing portion MR, a plurality of leads LD provided on the side MRc3 of the sealing portion MR, and a plurality of leads LD provided on the side MRc4 of the sealing portion MR.

[0096] When viewed in a plane, the lead LD provided on the side surface MRc1 of the sealing portion MR can be considered as the lead LD intersecting with the side MRd1 of the sealing portion MR. When viewed in a plane, the lead LD provided on the side surface MRc2 of the sealing portion MR can be considered as the lead LD intersecting with the side MRd2 of the sealing portion MR. When viewed in a plane, the lead LD provided on the side surface MRc3 of the sealing portion MR can be considered as the lead LD intersecting with the side MRd3 of the sealing portion MR. When viewed in a plane, the lead LD provided on the side surface MRc4 of the sealing portion MR can be considered as the lead LD intersecting with the side MRd4 of the sealing portion MR.

[0097] When viewed in a plane, the leads LD (i.e., leads LD4, LD5, LD6) disposed on the side MRc1 side of the seal portion MR extend in the Y direction and are arranged at predetermined intervals in the X direction; and the outer lead portion of each lead LD (LD4, LD5, LD6) protrudes from the side MRc1 of the seal portion MR to the outside of the seal portion MR. When viewed in a plane, the leads LD (i.e., leads LD8, LD10, LD12, LD13) disposed on the side MRc2 side of the seal portion MR extend in the X direction and are arranged at predetermined intervals in the Y direction; and the outer lead portion of each lead LD (LD8, LD10, LD12, LD13) protrudes from the side MRc2 of the seal portion MR to the outside of the seal portion MR. When viewed in a plane, the leads LD (i.e., leads LD1, LD2, LD3) disposed on the side MRc3 of the seal portion MR extend in the Y direction and are arranged at predetermined intervals in the X direction; and the outer lead portion of each lead LD (LD1, LD2, LD3) protrudes from the side MRc3 of the seal portion MR to the outside of the seal portion MR. When viewed in a plane, the leads LD (i.e., leads LD7, LD9, LD11, LD13) disposed on the side MRc4 of the seal portion MR extend in the X direction and are arranged at predetermined intervals in the Y direction; and the outer lead portion of each lead LD (LD7, LD9, LD11, LD13) protrudes from the side MRc4 of the seal portion MR to the outside of the seal portion MR. The outer lead portion of each lead LD is folded so that the lower surface near the end of the outer lead portion is substantially flush with the back surface MRb of the seal portion MR. The outer lead portion of each lead LD serves as an external terminal of the semiconductor device PKG.

[0098] The die pad DPC is a chip mounting portion for mounting the semiconductor chip CPC. The die pad DPH is a chip mounting portion for mounting the semiconductor chips CP1, CP2, and CP3. The die pad DP1 is a chip mounting portion for mounting the semiconductor chip CP4. The die pad DP2 is a chip mounting portion for mounting the semiconductor chip CP5. The die pad DP3 is a chip mounting portion for mounting the semiconductor chip CP6. The planar shape of each of the die pads DPC, DPH, DP1 to DP3 is, for example, a rectangle having sides parallel to the X direction and sides parallel to the Y direction. The three semiconductor chips CP1, CP2, and CP3 are arranged in a row in the X direction and arranged above the die pad DPH, and this arrangement is reflected in the size of the die pad DPH in the X direction being larger than the size in the Y direction. The size of the semiconductor chip CPC in the X direction is larger than the size in the Y direction, and this arrangement is reflected in the size of the die pad DPC in the X direction being larger than the size in the Y direction. Therefore, the length direction of each of the die pad DPH, the die pad DPC, and the semiconductor chip CPC is the X direction.

[0099] In the semiconductor device PKG, the die pad DP1, die pad DP2, and die pad DP3 are arranged in this order in the X direction, and the sleeve die pads DP1, DP2, DP3, one die pad DPC, and one die pad DPH are arranged in this order in the Y direction. In the Y direction, the die pads DP1, DP2, DP3 are located on the side surface MRc1 of the sealing portion MR, and the die pad DPH is located on the side surface MRc3 of the sealing portion MR; and the die pad DPC is provided between the die pad DPH and the sleeve die pads DP1, DP2, DP3.

[0100] Regarding the die pads DP1, DP2, and DP3, in the X direction, die pad DP1 is located on the side MRc4 side of the seal portion MR; die pad DP3 is located on the side MRc2 side of the seal portion MR; and die pad DP2 is located between die pad DP1 and die pad DP3. However, die pad DPH, die pad DPC, die pad DP1, die pad DP2, and die pad DP3 do not contact each other and are spaced apart from each other by a predetermined distance. A portion of the seal portion MR is located between these items.

[0101] The die pads DPC, DPH, DP1, DP2, DP3 and the leads LD are formed of a conductor, and are preferably made of a metal material such as copper (Cu) or a copper alloy. The die pads DPC, DPH, DP1, DP2, DP3 and the leads LD are preferably formed of the same material. This makes it easier to prepare a lead frame in which the die pads DPC, DPH, DP1, DP2, DP3 and the leads LD are coupled to each other, and facilitates the manufacture of a semiconductor device PKG using the lead frame.

[0102] The die pad DPC has a main surface DPCa located on the side where the semiconductor chip CPC is mounted and a back surface DPCb located on the opposite side. The die pad DPH has a main surface DPHa located on the side where the semiconductor chips CP1, CP2, and CP3 are mounted and a back surface DPHb located on the opposite side. The die pad DP1 has a main surface DP1a located on the side where the semiconductor chip CP4 is mounted and a back surface DP1b located on the opposite side. The die pad DP2 has a main surface DP2a located on the side where the semiconductor chip CP5 is mounted and a back surface DP2b located on the opposite side. The die pad DP3 has a main surface DP3a located on the side where the semiconductor chip CP6 is mounted and a back surface DP3b located on the opposite side.

[0103] At least a portion of each of the die pads DPC, DPH, DP1 to DP3 is sealed in the sealing portion MR, but in this embodiment, the backsides DPCb, DPHb, DP1b, DP2b, DP3b of the die pads DPC, DPH, DP1, DP2, DP3 are exposed from the main surface MRa of the sealing portion MR. As a result, heat generated during operation of the semiconductor chips CPC, CP1 to CP6 can be dissipated primarily from the backsides of the semiconductor chips CPC, CP1 to CP6 to the outside of the semiconductor device PKG via the die pads DPC, DPH, DP1 to DP3.

[0104] Each of the semiconductor chips CPC, CP1 to CP6 has a front side (front side of each semiconductor chip) and a back side (back side of each semiconductor chip) as main surfaces located on opposite sides of each other. In the semiconductor chip CPC, the main surface located on the side where the bonding pad (P7) is formed is the front side (front side of the semiconductor chip CPC), and the main surface located on the opposite side is the back side (back side of the back semiconductor chip CPC). In the semiconductor chips CP1 to CP6, the main surface located on the side where the source bonding pad (P1S to P6S) or the gate bonding pad (P1G to P6G) is formed is the front side (front side of each semiconductor chip CP1 to CP6), and the main surface located on the side where the back electrode (BE1 to BE6) is formed is the back side (back side of each semiconductor chip CP1 to CP6).

[0105] In the die pads DPC, DPH, DP1 to DP3, the leads LD, and the lead coupling portions LB1 to LB5, a plating layer (not shown) including silver (Ag) or the like may be formed in the regions where the semiconductor chips CPC, CP1 to CP6 are mounted, the regions where the wires BW are bonded, and the regions where the metal plates MP1 to MP4 are coupled. This makes it possible to more appropriately couple the semiconductor chips CPC, CP1 to CP6, the metal plates MP1 to MP4, and the wires BW to the die pads DPC, DPH, DP1 to DP3, the leads LD, and the lead coupling portions LB1 to LB5.

[0106] Over the main surface DPHa of the die pad DPH, the semiconductor chips CP1, CP2, CP3 are mounted with their back faces toward the die pad DPH. Each of the semiconductor chips CP1, CP2, CP3 is mounted over the main surface DPHa of the die pad DPH via a conductive bonding material (adhesive layer) BD1. In the back side (entire back side) of the semiconductor chip CP1, a back electrode (electrode) BE1 is formed; in the back side (entire back side) of the semiconductor chip CP2, a back electrode (electrode) BE2 is formed; and, in the back side (entire back side) of the semiconductor chip CP3, a back electrode (electrode) BE3 is formed. Each of these back electrodes BE1, BE2, BE3 is bonded and electrically coupled to the die pad DPH via a conductive bonding material BD1. The bonding material BD1 includes a conductive bonding material (adhesive material), and for example, a paste-like conductive adhesive material such as silver paste, solder, etc. can be used for this purpose.

[0107] On the main surface DPHa of the die pad DPH, the semiconductor chip CP1, the semiconductor chip CP2, and the semiconductor chip CP3 are arranged in a row in this order in the X direction. In the X direction, the semiconductor chip CP1 is located on the side surface MRc4 side of the sealing portion MR, the semiconductor chip CP3 is located on the side surface MRc2 side of the sealing portion MR, and the semiconductor chip CP2 is provided between the semiconductor chip CP1 and the semiconductor chip CP3.

[0108] On the main surface DP1a of the die pad DP1, the semiconductor chip CP4 is mounted with its back side facing the die pad DP1. The semiconductor chip CP4 is mounted on the main surface DP1a of the die pad DP1 via the conductive bonding material BD1. On the back side (entire back side) of the semiconductor chip CP4, a back electrode (electrode) BE4 is formed, and this back electrode BE4 is bonded and electrically coupled to the die pad DP1 via the conductive bonding material BD1.

[0109] On the main surface DP2a of the die pad DP2, the semiconductor chip CP5 is mounted with its back side facing the die pad DP2. The semiconductor chip CP5 is mounted on the main surface DP2a of the die pad DP2 via the conductive bonding material BD1. On the back side (entire back side) of the semiconductor chip CP5, a back electrode (electrode) BE5 is formed, and this back electrode BE5 is bonded and electrically coupled to the die pad DP2 via the conductive bonding material BD1.

[0110] On the main surface DP3a of the die pad DP3, the semiconductor chip CP6 is mounted with its back side facing the die pad DP3. The semiconductor chip CP6 is mounted on the main surface DP3a of the die pad DP3 via the conductive bonding material BD1. On the back side (entire back side) of the semiconductor chip CP6, a back electrode (electrode) BE6 is formed, and this back electrode BE6 is bonded and electrically coupled to the die pad DP3 via the conductive bonding material BD1.

[0111] The semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC with its back side facing the die pad DPC. The semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC via a bonding material (adhesive layer) BD2, and the bonding material BD2 can be conductive or insulating.

[0112] The planar shape of each of the semiconductor chips CPC, CP1 to CP6 is, for example, a rectangle, and more specifically, a rectangle having sides parallel to the X direction and sides parallel to the Y direction. The planar size of the semiconductor chip CPC is, for example, approximately 8.4 mm × 2.3 mm, and the planar size of each of the semiconductor chips CP1 to CP6 is, for example, approximately 2.8 mm × 2.8 mm. When viewed in a plane, the semiconductor chips CP1, CP2, CP3 are contained in the main surface DPHa of the die pad DPH, and the semiconductor chip CPC is contained in the main surface DPCa of the die pad DPC. When viewed in a plane, the semiconductor chip CP4 is contained in the main surface DP1a of the die pad DP1, the semiconductor chip CP5 is contained in the main surface DP2a of the die pad DP2, and the semiconductor chip CP6 is contained in the main surface DP3a of the die pad DP3. The semiconductor chips CPC, CP1 to CP6 are sealed in the sealing portion MR, and none of them are exposed from the sealing portion MR.

[0113] Each of the back electrodes BE1 to BE6 of the semiconductor chips CP1 to CP6 is electrically coupled to the drain of the power MOSFET formed in the associated semiconductor chip. Thus, back electrode BE1 serves as the drain electrode of power MOSFET 1, back electrode BE2 serves as the drain electrode of power MOSFET 2, and back electrode BE3 serves as the drain electrode of power MOSFET 3. Back electrode BE4 serves as the drain electrode of power MOSFET 4, back electrode BE5 serves as the drain electrode of power MOSFET 5, and back electrode BE6 serves as the drain electrode of power MOSFET 6.

[0114] In each of the semiconductor chips CPC, CP1 to CP6, the uppermost protective film (uppermost insulating film) has an opening for exposing the bonding pads, and the bonding pads are exposed from the openings in the uppermost protective film. Specifically, in the front face of the semiconductor chip CP1, the gate bonding pad P1G, the source bonding pad P1S, and the other bonding pads P1 are exposed from the uppermost protective film of the semiconductor chip CP1. In the front face of the semiconductor chip CP2, the gate bonding pad P2G, the source bonding pad P2S, and the other bonding pads P2 are exposed from the uppermost protective film of the semiconductor chip CP2. In the front face of the semiconductor chip CP3, the gate pad P3G, the source pad P3S, and the other pads P3 are exposed from the uppermost protective film of the semiconductor chip CP3. In the front face of the semiconductor chip CP4, the gate bonding pad P4G, the source bonding pad P4S, and the other bonding pads P4 are exposed from the uppermost protective film of the semiconductor chip CP4. On the front surface of semiconductor chip CP5, gate bonding pad P5G, source bonding pad P5S, and other bonding pads P5 are exposed from the uppermost protective film of semiconductor chip CP5. On the front surface of semiconductor chip CP6, gate bonding pad P6G, source bonding pad P6S, and other bonding pads P6 are exposed from the uppermost protective film of semiconductor chip CP6. On the front surface of semiconductor chip CPC, multiple bonding pads P7 are exposed from the uppermost protective film of semiconductor chip CPC. Hereinafter, "bonding pad," "bonding pad electrode," "pad electrode," and "electrode" will be simply referred to as "pad."

[0115] The pad P7 of the semiconductor chip CPC is electrically coupled to the control circuit CLC formed in the semiconductor chip CPC via internal wiring of the semiconductor chip CPC. Each of the gate pads P1G, P2G, P3G, P4G, P5G, and P6G of the semiconductor chips CP1, CP2, CP3, CP4, CP5, and CP6 is electrically coupled to the gate electrode of a power MOSFET formed in the associated semiconductor chip. Each of the source pads P1S, P2S, P3S, P4S, P5S, and P6S of the semiconductor chips CP1, CP2, CP3, CP4, CP5, and CP6 is electrically coupled to the source electrode of a power MOSFET formed in the associated semiconductor chip. Therefore, gate pads P1G, P2G, P3G, P4G, P5G, and P6G serve as the respective gate pads of the above-mentioned power MOSFETs 1, 2, 3, 4, 5, and 6, and source pads P1S, P2S, P3S, P4S, P5S, and P6S serve as the respective source pads of power MOSFETs 1, 2, 3, 4, 5, and 6. In each of the semiconductor chips CP1 to CP6, the planar area of each source pad (P1S to P6S) is larger than the planar area of each of the other pads (P1G to P6G, P1 to P6).

[0116] Taking the semiconductor chip CP1 as an example, the specific structure of the semiconductor chips CP1 to CP6 is described. In the semiconductor substrate constituting the semiconductor chip CP1, a plurality of unit transistor cells constituting a power MOSFET (1) are formed. The power MOSFET (1) is formed by coupling these unit transistor cells in parallel. Each unit transistor cell includes, for example, a trench gate MISFET. The source region of the unit transistor cell for the power MOSFET (1) formed in the front surface of the semiconductor substrate constituting the semiconductor chip CP1 is electrically coupled to a common source electrode formed on an interlayer insulating film located above the semiconductor substrate. The source electrode is exposed from an opening in the uppermost protective film, thereby forming a source pad (P1S). The uppermost protective film of the semiconductor chip CP1 is formed on the interlayer insulating film covering the source electrode located above the semiconductor substrate constituting the semiconductor chip CP1, but has an opening that at least partially exposes the source electrode. The semiconductor substrate constituting the semiconductor chip CP1 has the function of sharing a drain region with the unit transistor cells for the power MOSFET (1), and a back electrode (BE1) is formed in the entire back surface of the semiconductor substrate. In the semiconductor chip CP1, the current between the source and drain of the power MOSFET (1) flows in the thickness direction of the semiconductor substrate that constructs the semiconductor chip CP1. That is, the current between the source and drain of the power MOSFET (1) flows between the source pad (P1S) and the back electrode (BE1) of the semiconductor chip CP1. The gate pad (P1G) serves as a control terminal (control electrode) for controlling the continuity between the source pad (P1S) formed on the front side of the semiconductor chip (CP1) and the drain back electrode (BE1) formed on the back side of the semiconductor chip (CP1). The power MOSFET (1) is preferably an n-channel type. The structure of each of the semiconductor chips CP2, CP3, CP4, CP5, CP6 is substantially the same as that of the semiconductor chip CP1; therefore, a repeated description thereof will be omitted here.

[0117] On the front surface of each of the semiconductor chips CP1 to CP6, the other pads (P1G to P6G, P1 to P6) except for the source pads (P1S to P6S) are arranged along the side opposite to the semiconductor chip CPC and are electrically coupled to the pad P7 of the semiconductor chip CPC via the wire BW. That is, one end of the wire BW is coupled to each of the pads P1G to P6G, P1 to P6 of the semiconductor chips CP1 to CP6, and the other end of the wire BW is coupled to the pad P7 of the semiconductor chip CPC. Each of the pads P1G to P6G, P1 to P6 of the semiconductor chips CP1 to CP6 is electrically coupled to the pad P7 of the semiconductor chip CPC via the wire BW, and is further electrically coupled to the above-mentioned control circuit CLC in the semiconductor chip CPC through the internal wiring of the semiconductor chip CPC.

[0118] The wire (bonding wire) BW is a conductive coupling member, and more specifically, a conductive wire. Since the wire BW is formed of metal, the wire can also be considered a metal wire (thin metal wire). For the wire BW, gold (Au) wire, silver (Ag) wire, copper (Cu) wire, aluminum (Al) wire, etc. can be advantageously used. Each wire BW is sealed in the sealing portion MR and does not protrude from the sealing portion MR. In each lead LD, the wire BW bonding point is the inner lead portion located within the sealing portion MR.

[0119] The source pad P1S of the semiconductor chip CP1 is electrically coupled to the lead coupling portion (lead wiring portion) LB1 via the metal plate MP1. That is, the metal plate MP1 is bonded and electrically coupled to the source pad P1S and the lead coupling portion LB1 of the semiconductor chip CP1 via the conductive bonding material BD3.

[0120] The source pad P2S of the semiconductor chip CP2 is electrically coupled to the lead coupling portion (lead wiring portion) LB2 via the metal plate MP2. That is, the metal plate MP2 is bonded and electrically coupled to the source pad P2S and the lead coupling portion LB2 of the semiconductor chip CP2 via the conductive bonding material BD3.

[0121] The source pad P3S of the semiconductor chip CP3 is electrically coupled to the lead coupling portion (lead wiring portion) LB3 via the metal plate MP3. That is, the metal plate MP3 is bonded and electrically coupled to the source pad P3S and the lead coupling portion LB3 of the semiconductor chip CP3 via the conductive bonding material BD3.

[0122] The source pads P4S, P5S, and P6S of the semiconductor chips CP4, CP5, and CP6 are electrically coupled to the lead coupling portions (lead wiring portions) LB4 and LB5 via a common metal plate MP4. That is, the metal plate MP4 is bonded and electrically coupled to the source pad P4S of the semiconductor chip CP4, the source pad P5S of the semiconductor chip CP5, the source pad P6S of the semiconductor chip CP6, the lead coupling portion LB4, and the lead coupling portion LB5, respectively, via a conductive bonding material BD3.

[0123] Electrically coupling the source pads P1S to P6S of the semiconductor chips CP1 to CP6 to the leads LD using metal plates MP1 to MP4 instead of wires can reduce the on-resistance of the power MOSFETs 1 to 6. This makes it possible to reduce package resistance and lower conduction loss.

[0124] The bonding material BD includes a conductive bonding material (adhesive material), and a paste-like conductive adhesive material such as silver paste, solder, etc. can be used for this purpose. In order to couple the metal plates MP1 to MP4 to the source pads P1S to P6S of the semiconductor chips CP1 to CP6, these items can be directly coupled by crimping or the like without using the conductive bonding material BD3.

[0125] The metal plates MP1 to MP4 are conductor plates including a conductor and are preferably formed of a metal (metal material) having high electrical and thermal conductivity, such as copper (Cu), a copper (Cu) alloy, aluminum (Al), or an aluminum (Al) alloy. The dimensions (width) of each metal plate MP1 to MP4 in the X and Y directions are larger than the diameter of the wire BW.

[0126] The heat generated in the semiconductor chips CP1 to CP6 is dissipated from the back side of the semiconductor chips CP1 to CP6 via the die pads DPH, DP1, DP2, and DP3. In addition, the heat can be dissipated from the front side of the semiconductor chips CP1 to CP6 via the metal plates MP1 to MP4. This makes it possible to enhance the dissipation of the heat generated in the semiconductor chips CP1 to CP6.

[0127] Among the plurality of pads P7 of the semiconductor chip CPC, the pads P7 that are not coupled to any pad of the semiconductor chips CP1 to CP6 are electrically coupled to the leads LD11 and LD12 of the plurality of leads LD provided in the semiconductor device PKG. Each of the leads LD11 and LD12 can serve as a signal transmission path between the semiconductor chip CPC in the semiconductor device PKG and the above-mentioned control circuit CT outside the semiconductor device PKG.

[0128] Of the leads LD11 and LD12, lead LD11 is located on the side MRc4 side of the seal portion MR, opposing the die pad DPC (semiconductor chip CPC) in the X direction. Lead LD12 is located on the side MRc2 side of the seal portion MR, opposing the die pad DPC (semiconductor chip CPC) in the X direction. On the front surface of the semiconductor chip CPC, pads P7 located (arranged) along the side MRc4 side of the seal portion MR are electrically coupled to the lead LD11 located on the side MRc4 side of the seal portion MR via wires BW. On the front surface of the semiconductor chip CPC, pads P7 located (arranged) along the side MRc2 side of the seal portion MR are electrically coupled to the lead LD12 located on the side MRc2 side of the seal portion MR via wires BW. Each lead LD11, LD12 is not connected to any of the die pads DPC, DPH, DP1, DP2, DP3, the leads LD1, LD2, LD3, LD4, LD5, LD6, LD7, LD8, LD9, LD10, LD13 and the lead coupling parts LB1, LB2, LB3, LB4, LB5 via a conductor, and is an isolated lead.

[0129] Each of the lead coupling portions LB1, LB2, and LB3 is adjacent to the die pad DPH in the Y direction and extends in the X direction within the sealing portion MR along the side surface MRc3. However, the lead coupling portions LB1, LB2, and LB3 are arranged in a row in the X direction. Of the lead coupling portions LB1, LB2, and LB3, the lead coupling portion LB1 is located on the side surface MRc4 of the sealing portion MR, the lead coupling portion LB3 is located on the side surface MRC2 of the sealing portion MR, and the lead coupling portion LB2 is located between the lead coupling portions LB1 and LB3. Therefore, when viewed in plan, the semiconductor chip CP1 and the lead coupling portion LB1 are opposite each other in the Y direction; the semiconductor chip CP2 and the lead coupling portion LB2 are opposite each other in the Y direction; and the semiconductor chip CP3 and the lead coupling portion LB3 are opposite each other in the Y direction. The lead coupling portion LB1 , the lead coupling portion LB2 , the lead coupling portion LB3 , and the die pad DPH are spaced apart from one another, and a portion of the sealing portion MR is located between these items.

[0130] Lead coupling portion LB4 is adjacent to die pad DP1 in the X direction and extends in the Y direction within the seal portion MR along side MRc4. Lead coupling portion LB5 is adjacent to die pad DP3 in the X direction and extends in the Y direction within the seal portion MR along side MRc2. However, lead coupling portion LB4 and die pad DP1 are separated from each other, with a portion of the seal portion MR located between these two items. Lead coupling portion LB5 and die pad DP3 are separated from each other, with another portion of the seal portion MR located between these two items. Lead coupling portions LB1 to LB5 are sealed within the seal portion MR, and none of them are exposed from the seal portion MR.

[0131] Among the leads LD provided in the semiconductor device PKG, the lead LD1 is integrally coupled to the lead coupling portion LB1. That is, the lead coupling portion LB1 and the lead LD1 are integrally formed. Each lead LD1 is provided on the side surface MRc3 side of the sealing portion MR and extends in the Y direction when viewed in a plane. The leads LD1 are adjacent to each other in the X direction, and the inner lead portions of the leads LD1 are coupled together by the lead coupling portion LB1. Therefore, the lead coupling portion LB1 can be considered as a coupling portion that couples the inner lead portions of the leads LD1 together. The lead LD1 and the lead coupling portion LB1 are electrically coupled to the source pad P1S of the semiconductor chip CP1 via the metal plate MP1. The lead LD1 corresponds to the terminal TE1 described above.

[0132] Among the leads LD provided in the semiconductor device PKG, the lead LD2 is integrally coupled to the lead coupling portion LB2. That is, the lead coupling portion LB2 and the lead LD2 are integrally formed. Each lead LD2 is provided on the side surface MRc3 side of the sealing portion MR and extends in the Y direction when viewed in a plane. The leads LD2 are adjacent to each other in the X direction, and the inner lead portions of the leads LD2 are coupled together by the lead coupling portion LB2. Therefore, the lead coupling portion LB2 can be considered as a coupling portion that couples the inner lead portions of the leads LD2 together. The lead LD2 and the lead coupling portion LB2 are electrically coupled to the source pad P2S of the semiconductor chip CP2 via the metal plate MP2. The lead LD2 corresponds to the above-mentioned terminal TE2.

[0133] Among the leads LD provided in the semiconductor device PKG, the lead LD3 is integrally coupled to the lead coupling portion LB3. That is, the lead coupling portion LB3 and the lead LD3 are integrally formed. Each lead LD3 is provided on the side surface MRc3 side of the sealing portion MR and extends in the Y direction when viewed in a plane. The leads LD3 are adjacent to each other in the X direction, and the inner lead portions of the leads LD3 are coupled together by the lead coupling portion LB3. Therefore, the lead coupling portion LB3 can be considered as a coupling portion that couples the inner lead portions of the leads LD3 together. The lead LD3 and the lead coupling portion LB3 are electrically coupled to the source pad P3S of the semiconductor chip CP3 via the metal plate MP3. The lead LD3 corresponds to the above-mentioned terminal TE3.

[0134] Among the leads LD provided in the semiconductor device PKG, the lead LD9 is integrally coupled to the lead coupling portion LB4. That is, the lead coupling portion LB4 and the lead LD9 are integrally formed. Each lead LD9 is provided on the side surface MRc4 side of the sealing portion MR and extends in the X direction when viewed in a plane. The leads LD9 are adjacent to each other in the Y direction, and the inner lead portions of the leads LD9 are coupled together by the lead coupling portion LB4. Therefore, the lead coupling portion LB4 can be regarded as a coupling portion that couples the inner lead portions of the leads LD9 together. The lead LD9 and the lead coupling portion LB4 are electrically coupled to the source pads P4S, P5S, P6S of the semiconductor chips CP4, CP5, CP6 via the metal plate MP4. The lead LD9 corresponds to the above-mentioned terminal TE9.

[0135] Among the leads LD provided in the semiconductor device PKG, the lead LD10 is integrally coupled to the lead coupling portion LB5. That is, the lead coupling portion LB5 and the lead LD10 are integrally formed. Each lead LD10 is provided on the side surface MRc2 side of the sealing portion MR and extends in the X direction when viewed in a plane. The leads LD10 are adjacent to each other in the Y direction, and the inner lead portions of the leads LD10 are coupled together by the lead coupling portion LB5. Therefore, the lead coupling portion LB5 can be regarded as a coupling portion that couples the inner lead portions of the leads LD10 together. The lead LD10 and the lead coupling portion LB5 are electrically coupled to the source pads P4S, P5S, P6S of the semiconductor chips CP4, CP5, CP6 via the metal plate MP4. The lead LD10 corresponds to the above-mentioned terminal TE10.

[0136] Lead LD1 is coupled together (in a lump) to lead coupling portion LB1; lead LD2 is coupled together to lead coupling portion LB2; lead LD3 is coupled together to lead coupling portion LB3; lead LD9 is coupled together to lead coupling portion LB4; and lead LD10 is coupled together to lead coupling portion LB5. This reduces resistance and conduction loss in power MOSFETs 1, 2, 3, 4, 5, and 6.

[0137] The lead coupling portion LB1 and the lead LD1 coupled thereto, the lead coupling portion LB2 and the lead LD2 coupled thereto, and the lead coupling portion LB3 and the lead LD3 coupled thereto are arranged on the side surface MRc3 side of the seal portion MR and are therefore adjacent to the die pad DPH in the Y direction. The lead coupling portion LB4 and the lead LD9 coupled thereto are arranged on the side surface MRc4 side of the seal portion MR and are therefore adjacent to the die pad DP1 in the X direction; and the lead coupling portion LB5 and the lead LD10 coupled thereto are arranged on the side surface MRc2 side of the seal portion MR and are therefore adjacent to the die pad DP3 in the X direction.

[0138] Among the leads LD provided in the semiconductor device PKG, the lead LD4 is formed integrally with the die pad DP1. Therefore, the lead LD4 is electrically coupled to the die pad DP1 and is electrically coupled to the back electrode BE4 of the semiconductor chip CP4 via the die pad DP1 and the conductive bonding material BD1. The lead LD4 corresponds to the above-mentioned terminal TE4. When viewed in a plane, the lead LD4 is provided on the side surface MRc1 side of the sealing portion MR so as to be opposite to the die pad DP1 (semiconductor chip CP4) in the Y direction. Each lead LD4 extends in the Y direction when viewed in a plane, and the leads LD4 are adjacent to each other in the X direction.

[0139] Among the leads LD provided in the semiconductor device PKG, the lead LD5 is formed integrally with the die pad DP2. Therefore, the lead LD5 is electrically coupled to the die pad DP2 and is electrically coupled to the back electrode BE5 of the semiconductor chip CP5 via the die pad DP2 and the conductive bonding material BD1. The lead LD5 corresponds to the above-mentioned terminal TE5. When viewed in a plane, the lead LD5 is provided on the side surface MRc1 side of the sealing portion MR so as to be opposite to the die pad DP2 (semiconductor chip CP5) in the Y direction. Each lead LD5 extends in the Y direction when viewed in a plane, and the leads LD5 are adjacent to each other in the X direction.

[0140] Among the leads LD provided in the semiconductor device PKG, the lead LD6 is formed integrally with the die pad DP3. Therefore, the lead LD6 is electrically coupled to the die pad DP3 and is electrically coupled to the back electrode BE6 of the semiconductor chip CP6 via the die pad DP3 and the conductive bonding material BD1. The lead LD6 corresponds to the above-mentioned terminal TE6. When viewed in a plane, the lead LD6 is provided on the side surface MRc1 side of the sealing portion MR so as to be opposite to the die pad DP3 (semiconductor chip CP6) in the Y direction. Each lead LD6 extends in the Y direction when viewed in a plane, and the leads LD6 are adjacent to each other in the X direction.

[0141] When focusing only on the semiconductor device PKG, leads LD1 and LD4 are not connected to each other by a conductor and are therefore not electrically coupled to each other; leads LD2 and LD5 are not connected to each other by a conductor and are therefore not electrically coupled to each other; and leads LD3 and LD6 are not connected to each other by a conductor and are therefore not electrically coupled to each other. However, when the semiconductor device PKG is mounted on a circuit board or the like to form an inverter circuit of the semiconductor device PKG, leads LD1 and LD4 of the semiconductor device PKG are electrically coupled to each other; leads LD2 and LD5 are electrically coupled to each other; and leads LD3 and LD6 are electrically coupled to each other through the wiring of the circuit board or the like.

[0142] Among the leads LD provided in the semiconductor device PKG, leads LD7 and LD8 are integrally formed with the die pad DPH. Therefore, leads LD7 and LD8 are electrically coupled to the die pad DPH and, via the die pad DPH and the conductive bonding material BD1, to the back electrodes BE1, BE2, and BE3 of the semiconductor chips CP1, CP2, and CP3. Lead LD7 corresponds to the aforementioned terminal TE7, and lead LD8 corresponds to the aforementioned terminal TE8. When viewed in plan, lead LD7 is positioned on the side MRc4 side of the sealing portion MR so as to oppose the die pad DPH (semiconductor chip CP1) in the X direction, and lead LD8 is positioned on the side MRc2 side of the sealing portion MR so as to oppose the die pad DPH (semiconductor chip CP3) in the X direction. Each lead LD7 extends in the X direction when viewed in plan, and the leads LD7 are adjacent to one another in the Y direction. Each lead LD8 extends in the X direction when viewed in plan, and the leads LD8 are adjacent to one another in the Y direction.

[0143] In the semiconductor device PKG of this embodiment, leads LD1, LD2, and LD3 are arranged on the side MRc3 side of the sealing portion MR. Leads LD4, LD5, and LD6 are arranged on the side MRc1 side of the sealing portion MR. Leads LD9, LD11, and LD7 are arranged on the side MRc4 side of the sealing portion MR. Leads LD10, LD12, and LD8 are arranged on the side MRc2 side of the sealing portion MR. Leads LD1 and LD4 are located on opposite sides of each other in the Y direction; leads LD2 and LD5 are located on opposite sides of each other in the Y direction; and leads LD3 and LD6 are located on opposite sides of each other in the Y direction. Leads LD9 and LD10 are located on opposite sides of each other in the X direction; leads LD11 and LD12 are located on opposite sides of each other in the X direction; and leads LD7 and LD8 are located on opposite sides of each other in the X direction.

[0144] Therefore, the lead group including the lead LD1, the lead group including the lead LD2, and the lead group including the lead LD3 are similarly arranged on the side surface MRc3 side of the seal portion MR. However, when viewed in the X direction, the lead group including the lead LD1 is located closer to the side surface MRc4 of the seal portion MR; the lead group including the lead LD3 is located closer to the side surface MRc2 of the seal portion MR; and the lead group including the lead LD2 is located between the lead group including the lead LD1 and the lead group including the lead LD3.

[0145] The lead group including the lead LD4, the lead group including the lead LD5, and the lead group including the lead LD6 are similarly arranged on the side surface MRc1 side of the seal portion MR. However, when viewed in the X direction, the lead group including the lead LD4 is located closer to the side surface MRc4 of the seal portion MR; the lead group including the lead LD6 is located closer to the side surface MRc2 of the seal portion MR; and the lead group including the lead LD5 is located between the lead group including the lead LD4 and the lead group including the lead LD6.

[0146] The lead group including the lead LD9, the lead group including the lead LD11, and the lead group including the lead LD7 are similarly arranged on the side surface MRc4 side of the seal portion MR. However, when viewed in the Y direction, the lead group including the lead LD9 is located closer to the side surface MRc1 of the seal portion MR; the lead group including the lead LD7 is located closer to the side surface MRc3 of the seal portion MR; and the lead group including the lead LD11 is located between the lead group including the lead LD9 and the lead group including the lead LD7.

[0147] The lead group including the lead LD10, the lead group including the lead LD12, and the lead group including the lead LD8 are similarly arranged on the side surface MRc2 of the seal portion MR. However, when viewed in the Y direction, the lead group including the lead LD10 is located closer to the side surface MRc1 of the seal portion MR; the lead group including the lead LD8 is located closer to the side surface MRc3 of the seal portion MR; and the lead group including the lead LD12 is located between the lead group including the lead LD10 and the lead group including the lead LD8.

[0148] Therefore, on the side MRc3 side of the seal portion MR, the lead group including lead LD1, the lead group including lead LD2, and the lead group including lead LD3 are arranged in this order in the direction from side MRc4 toward side MRc2. On the side MRc1 side of the seal portion MR, the lead group including lead LD4, the lead group including lead LD5, and the lead group including lead LD6 are arranged in this order in the direction from side MRc4 toward side MRc2. On the side MRc4 side of the seal portion MR, the lead group including lead LD9, the lead group including lead LD11, and the lead group including lead LD7 are arranged in this order in the direction from side MRc1 toward side MRc3. On the side MRc2 side of the seal portion MR, the lead group including lead LD10, the lead group including lead LD12, and the lead group including lead LD8 are arranged in this order in the direction from side MRc1 toward side MRc3.

[0149] In the semiconductor device PKG, as described above, the source leads LD1, LD2, and LD3 of the power MOSFETs 1, 2, and 3 for the high side are arranged on the side MRc3 side of the seal portion MR, and the drain leads LD7 and LD8 of the power MOSFETs 1, 2, and 3 for the high side are arranged on the side MRc2 and MRc4 sides of the seal portion MR. The drain leads LD4, LD5, and LD6 of the power MOSFETs 4, 5, and 6 for the low side are arranged on the side MRc1 side of the seal portion MR, and the source leads LD9 and LD10 of the power MOSFETs 4, 5, and 6 for the low side are arranged on the side MRc2 and MRc4 sides of the seal portion MR.

[0150] The die pad DPC has a plurality of leads LD13 integrally coupled thereto. When the semiconductor device PKG is manufactured, these leads LD13 are used to support the die pad DPC on the frame of the lead frame LF described later. Therefore, none of the leads LD13 is electrically coupled to any pad on the semiconductor chips CPC, CP1 to CP6 or any back electrodes BE1, BE2, BE3, BE4, BE5, BE6 of the semiconductor chips CP1 to CP6. Therefore, none of the leads LD13 is used as a signal transmission path between the semiconductor chip CPC in the semiconductor device PKG and the above-mentioned control circuit CT, or as a current path between the semiconductor chips CP1 to CP6 in the semiconductor device PKG and the above-mentioned motor MOT. The leads LD13 are provided on the side MRc4 side and the side MRc2 side of the sealing portion MR.

[0151] Specifically, on the side surface MRc4 of the seal portion MR, one or more leads LD13 are provided between the lead group including the lead LD9 and the lead group including the lead LD11, and one or more leads LD13 are provided between the lead group including the lead LD7 and the lead group including the lead LD11. On the side surface MRc2 of the seal portion MR, one or more leads LD13 are provided between the lead group including the lead LD10 and the lead group including the lead LD12, and one or more leads LD13 are provided between the lead group including the lead LD8 and the lead group including the lead LD12. As long as the semiconductor device PKG can be manufactured, some or all of the leads LD13 may be omitted.

[0152] In semiconductor device PKG, when power MOSFET 1 is on, current flows from leads LD7 and LD8 to lead LD1 through power MOSFET 1 in semiconductor chip CP1. When power MOSFET 2 is on, current flows from leads LD7 and LD8 to lead LD2 through power MOSFET 2 in semiconductor chip CP2. When power MOSFET 3 is on, current flows from leads LD7 and LD8 to lead LD3 through power MOSFET 3 in semiconductor chip CP3. When power MOSFET 4 is on, current flows from lead LD4 to leads LD9 and LD10 through power MOSFET 4 in semiconductor chip CP4. When power MOSFET 5 is on, current flows from lead LD5 to leads LD9 and LD10 through power MOSFET 5 in semiconductor chip CP5. When power MOSFET 6 is on, current flows from lead LD6 to leads LD9 and LD10 through power MOSFET 6 in semiconductor chip CP6.

[0153] Semiconductor device manufacturing process

[0154] Will describe Figures 5 to 15 The manufacturing process (assembly process) of the semiconductor device PKG shown in FIG. Figures 16 to 22 is a plan view of the semiconductor device PKG in this embodiment during the manufacturing process ( Figures 16 to 21 ) or cross-sectional view ( Figure 22 ).

[0155] In order to manufacture the semiconductor device PKG, a lead frame LF is provided and semiconductor chips CPC, CP1 to CP6 are provided. The lead frame LF may be provided first, the semiconductor chips CPC, CP1 to CP6 may be provided first, or both items may be provided at the same time.

[0156] like Figure 16 As shown in FIG, the lead frame LF integrally includes a frame (not shown), die pads DPC, DPH, DP1, DP2, DP3, leads LD, and lead coupling portions LB1 to LB5. One end of each lead LD is coupled to the frame. Each die pad DPC, DPH, DP1, DP2, DP3 is coupled to the frame via a lead LD integrally formed with the die pad. The lead frame LF is formed of a metal material containing, for example, copper (Cu) as a main component, specifically, copper (Cu) or a copper (Cu) alloy. Figure 16 An area of the lead frame LF where one semiconductor device PKG is to be manufactured is shown.

[0157] The lead frame LF is arranged with the main surfaces DPCa, DPHa, DP1a, DP2a, DP3a of the die pads DPC, DPH, DP1, DP2, DP3 facing upward during the subsequent manufacturing process (assembly process) until a molding step is performed to form the sealing portion MR.

[0158] Then, if Figure 17As shown in , a die bonding step is performed on the semiconductor chips CP1 to CP6. First, the semiconductor chips CP1, CP2, and CP3 are mounted on the main surface DPHa of the die pad DPH of the lead frame LF; the semiconductor chip CP4 is mounted on the main surface DP1a of the die pad DP1; the semiconductor chip CP5 is mounted on the main surface DP2a of the die pad DP2; and the semiconductor chip CP6 is mounted on the main surface DP3a of the die pad DP3. These chips are mounted on the relevant die pads via the conductive bonding material BD1 (face-up bonding). For example, silver paste can be used for the bonding material BD1. Afterwards, a treatment (heat treatment) for curing the conductive bonding material BD1 is performed. As a result, the semiconductor chips CP1 to CP6 are bonded and fixed to the die pads DPH, DP1, DP2, and DP3 by the cured conductive bonding material BD1. Thereafter, a cleaning step by plasma (plasma cleaning step) can be performed. This plasma cleaning step cleans the pads P1S to P6S on the semiconductor chips CP1 to CP6 to make it easier to bond the metal plates MP1 to MP4 later.

[0159] Then, if Figure 18 As shown in FIG, the source pad P1S of semiconductor chip CP1 and the lead coupling portion LB1 of lead frame LF are coupled to each other via metal plate MP1. Furthermore, the source pad P2S of semiconductor chip CP2 and the lead coupling portion LB2 of lead frame LF are coupled to each other via metal plate MP2. Furthermore, the source pad P3S of semiconductor chip CP3 and the lead coupling portion LB3 of lead frame LF are coupled to each other via metal plate MP3. Furthermore, the source pads P4S, P5S, and P6S of semiconductor chips CP4, CP5, and CP6 are coupled to the lead coupling portions LB4 and LB5 of lead frame LF via a common metal plate MP4.

[0160] The metal plate MP1 is respectively bonded to the source pad P1S and the lead coupling portion LB1 of the semiconductor chip CP1 via a conductive bonding material BD3. The metal plate MP2 is respectively bonded to the source pad P2S and the lead coupling portion LB2 of the semiconductor chip CP2 via a conductive bonding material BD3. The metal plate MP3 is respectively bonded to the source pad P3S and the lead coupling portion LB3 of the semiconductor chip CP3 via a conductive bonding material BD3. The metal plate MP4 is respectively bonded to the source pads P4S, P5S, P6S and the lead coupling portions LB4, LB5 of the semiconductor chips CP4, CP5, CP6 via a conductive bonding material BD3. For example, silver paste or solder can be used for the bonding material BD3.

[0161] In the case described here, the step of bonding the metal plates MP1 to MP4 is performed before the semiconductor chip CPC is mounted on the die pad DPC. The reason for performing the step of bonding the metal plates MP1 to MP4 before the semiconductor chip CPC is mounted on the die pad DPC is to prevent the semiconductor chip CPC from being exposed to the heat treatment involved in the step of bonding the metal plates MP1 to MP4 (the step of curing the bonding material BD3, etc.). This makes it possible to further enhance the reliability of the semiconductor chip CPC.

[0162] Then, if Figure 19 As shown in , a die bonding step of the semiconductor chip CPC is performed to mount the semiconductor chip CPC on the main surface DPCa of the die pad DPC of the lead frame LF via the bonding material BD2 (face-up bonding). For example, silver paste or insulating paste can be used for the bonding material BD2. Afterwards, a treatment (heat treatment) for curing the bonding material BD2 is performed. As a result, the semiconductor chip CPC is bonded and fixed to the die pad DPC by the cured conductive bonding material BD2. Thereafter, a plasma cleaning step can be performed. This plasma cleaning step cleans the pads of the semiconductor chips CPC, CP1 to CP6 and makes it easier to bond the wires BW.

[0163] Then, if Figure 20 As shown in FIG, a wire bonding step is performed. Specifically, the pads (P1G to P6G, P1 to P6) of the semiconductor chips CP1 to CP6 and the pad (P7) of the semiconductor chip CPC are electrically coupled to each other via the wires BW. Furthermore, the pad (P7) of the semiconductor chip CPC and the leads (LD11, LD12) of the lead frame LF are electrically coupled to each other via the wires BW.

[0164] Various types of wires made of different materials can be used for the wires BW. For example, the pads (P7) of the semiconductor chip CPC and the leads (LD11, LD12) of the lead frame LF are electrically coupled to each other via wires BW made of copper (Cu). The pads (P1G to P6G, P1 to P6) of the semiconductor chips CP1 to CP6 and the pad (P7) of the semiconductor chip CPC are electrically coupled to each other via wires BW made of gold (Au).

[0165] Subsequently, resin molding is performed by a molding step (resin molding step) to seal the semiconductor chips CPC, CP1 to CP6 and the plurality of wires BW and metal plates MP1 to MP4 bonded to the semiconductor chips CPC, CP1 to CP6 with the sealing portion MR, as shown in FIG. Figure 21 and Figure 22 As shown in . Figure 22 shows the equivalent of Figure 10This molding step forms a sealing portion MR that seals the semiconductor chips CPC, CP1 to CP6, the die pads DPC, DPH, DP1 to DP3, the wires BW, the metal plates MP1 to MP4, the lead coupling portions LB1 to LB5, and the inner lead portions of the leads LD. Figure 22 As shown in , in the molding step, the sealing portion MR is formed so that the respective back sides DPCb, DPHb, DP1b, DP2b, DP3b of the die pads DPC, DPH, DP1, DP2, DP3 are exposed from the main surface MRa of the sealing portion MR.

[0166] Each step up to this molding step is performed with the main surfaces DPCa, DPHa, DP1a, DP2a, and DP3a of the die pads DPC, DPH, DP1, DP2, and DP3 facing upward. Therefore, when the sealing portion MR is formed by the molding step, the back surface MRb of the sealing portion MR faces upward. However, when the manufactured semiconductor device PKG is mounted on a circuit board or the like, the back surface MRb of the sealing portion MR faces the circuit board or the like.

[0167] Then, as needed, a plating layer (not shown) is formed on the outer lead portion of the lead LD exposed from the seal portion MR. Thereafter, the lead frame LF is turned upside down (with the back side turned over to the front side) together with the seal portion MR, and then the lead LD is cut at a position outside the seal portion MR to separate the lead LD from the frame of the lead frame LF.

[0168] Subsequently, the outer lead portion of the lead LD protruding from the sealing portion MR is subjected to folding (lead processing, lead forming).

[0169] This produced Figures 5 to 15 The semiconductor device PKG shown in FIG.

[0170] Implementation of semiconductor device PKG

[0171] Figures 23 to 29 is a plan view illustrating the implementation of the semiconductor device PKG ( Figure 23 ) or cross-sectional view ( Figures 24 to 29 ).

[0172] The semiconductor device PKG in this embodiment is a semiconductor device that constructs an inverter circuit, and three inverter circuits INV can be formed by one semiconductor device PKG. In order to control the above-mentioned motor MOT as a 12-phase BLDC motor, 12 inverter circuits INV are required, and thus four semiconductor devices PKG are required. Figure 23 As shown in FIG, four semiconductor devices PKG are mounted on a common circuit board (mounting board, PCB (Printed Circuit Board) board) PB1.

[0173] The circuit board PB1 and the four semiconductor devices PKG implemented (mounted) on the circuit board PB1 constitute the aforementioned control board PB. Therefore, the planar shape of the circuit board PB1 becomes the planar shape of the control board PB. Since the planar shape of the control board PB is circular, the planar shape of the circuit board PB1 is also circular.

[0174] exist Figure 23 In the case shown in , a plurality of (four in this example) semiconductor devices PKG are arranged annularly and provided on the main surface (top surface) PB1a of the circular circuit board PB1 along the edge (edge, periphery) of the circuit board PB1. Figure 23 In the case shown in FIG, when viewed in plan, the distance between each of the (four) semiconductor devices PKG arranged on the circular circuit board PB1 and the center of the circular circuit board PB1 is the same. The four semiconductor devices PKG are symmetrically arranged on the main surface PB1a of the circular circuit board PB1. If the circular circuit board PB1 is rotated 90 degrees, the four semiconductor devices PKG will overlap each other before and after the rotation.

[0175] The circuit board PB1 is provided with a hole (through hole, opening) HL for allowing the above-mentioned steering shaft SF to penetrate. When viewed in a plane, the hole HL is basically formed in the center of the circular circuit board PB1 and penetrates the circuit board PB1. The planar shape of the hole HL is basically the same as the cross-sectional shape of the above-mentioned steering shaft SF (the shape of the cross section basically perpendicular to the axial direction of the steering shaft SF), and is, for example, basically circular. Providing the hole HL in the circuit board PB1 makes it possible to set up a circuit board PB1 (i.e., the above-mentioned control board PB) on which four semiconductor devices PKG are installed, so that the above-mentioned steering shaft SF penetrates the hole HL in the circuit board PB1. (Refer to Figure 2 )

[0176] In the case described here, a plurality of (more specifically, four) semiconductor devices PKG are mounted on a circuit board PB1 having a circular planar shape and provided with a hole HL. In another embodiment, a plurality of (more specifically, four) semiconductor devices PKG may be mounted on a circuit board PB1 having a circular planar shape but not provided with a hole HL.

[0177] Figures 24 to 29 Corresponding to Figure 23 Cross-sectional view of the main parts. Figure 24 is corresponding to Figure 10 The position (i.e., corresponding to Figure 7 A cross-sectional view taken along the line A1-A1 of FIG. Figure 25 is corresponding to Figure 11 The position (i.e., corresponding to Figure 7 A cross-sectional view taken along line A2-A2). Figure 26is corresponding to Figure 12 The position (i.e., corresponding to Figure 7 A cross-sectional view taken along line A3-A3 of FIG. Figure 27 is corresponding to Figure 13 The position (i.e., corresponding to Figure 7 A cross-sectional view taken along line A4-A4). Figure 28 is corresponding to Figure 14 The position (i.e., corresponding to Figure 7 A cross-sectional view taken along line A5-A5) and Figure 29 is corresponding to Figure 15 The position (i.e., corresponding to Figure 7 A cross-sectional view taken along line A6-A6).

[0178] Also like Figures 24 to 29 As shown in FIG, each semiconductor device PKG is mounted on the main surface (top surface) PB1a of the circuit board PB1 so that the back surface MRb of the sealing portion MR thereof faces the main surface PB1a of the circuit board PB1. Each of the leads LD of each semiconductor device PKG is joined and electrically coupled to a terminal (electrode) TM formed in the main surface PB1a of the circuit board PB1 via a conductive bonding material (solder) SD such as solder.

[0179] The terminals TM provided in the circuit board PB1 include: a plurality of terminals TM1 for coupling with the lead LD1; a plurality of terminals TM2 for coupling with the lead LD2; a plurality of terminals TM3 for coupling with the lead LD3; a plurality of terminals TM4 for coupling with the lead LD4; a plurality of terminals TM5 for coupling with the lead LD5; and a plurality of terminals TM6 for coupling with the lead LD6. The terminals TM provided in the circuit board PB1 also include: a plurality of terminals TM7 for coupling with the lead LD7; a plurality of terminals TM8 for coupling with the lead LD8; a plurality of terminals TM9 for coupling with the lead LD9; a plurality of terminals TM10 for coupling with the lead LD10; a plurality of terminals TM11 for coupling with the lead LD11; a plurality of terminals TM12 for coupling with the lead LD12; and a plurality of terminals (not shown) for coupling with the lead LD13.

[0180] The circuit board PB1 has a plurality of wiring layers, and the wiring layers are formed in both main surfaces of the circuit board and inside the circuit board. A so-called multilayer circuit board can be advantageously used for the circuit board PB1. Each terminal TM (TM1 to TM12) is provided in the uppermost wiring layer (the wiring layer on the main surface PB1a side of the circuit board PB1) among the wiring layers provided in the circuit board PB1, but is exposed from an opening in the solder resist layer SR provided in the uppermost layer that constructs the circuit board PB1. Each terminal TM is electrically coupled to the wiring WR of the circuit board PB1. The wiring WR provided in the circuit board PB1 includes the wiring WR1, WR2, WR3, WR4, WR5 described later.

[0181] Each lead LD1 of each semiconductor device PKG is bonded and electrically coupled to terminal TM1; each lead LD2 is bonded and electrically coupled to terminal TM2; each lead LD3 is bonded and electrically coupled to terminal TM3; each lead LD4 is bonded and electrically coupled to terminal TM4; each lead LD5 is bonded and electrically coupled to terminal TM5; and each lead LD6 is bonded and electrically coupled to terminal TM6. These leads are bonded and electrically coupled via a conductive bonding material SD. Each lead LD7 is bonded and electrically coupled to terminal TM7; each lead LD8 is bonded and electrically coupled to terminal TM8; each lead LD9 is bonded and electrically coupled to terminal TM9; each lead LD10 is bonded and electrically coupled to terminal TM10; each lead LD11 is bonded and electrically coupled to terminal TM11; and each lead LD12 is bonded and electrically coupled to terminal TM12. These leads are bonded and electrically coupled via a conductive bonding material SD.

[0182] Terminals TM7 and TM8 are terminals to which the potential VIN is supplied via wiring WR of the circuit board PB1 or the like. Consequently, the potential VIN is supplied from the terminals TM7 and TM8 of the circuit board PB1 to the leads LD7 and LD8 of each semiconductor device PKG, and this potential VIN is further supplied to the back electrodes BE1, BE2, and BE3 of the semiconductor chips CP1, CP2, and CP3 via the die pad DPH within the semiconductor device PKG.

[0183] Terminals TM9 and TM10 are terminals to which a ground potential GND is supplied via wiring WR of the circuit board PB1 or the like. Consequently, the ground potential GND is supplied from the terminals TM9 and TM10 of the circuit board PB1 to the leads LD9 and LD10 of each semiconductor device PKG. Furthermore, this ground potential GND is supplied to the source pads P4S, P5S, and P6S of the semiconductor chips CP4, CP5, and CP6 via the metal plate MP4 within the semiconductor device PKG.

[0184] Terminals TM11 and TM12 are electrically coupled to the control circuit CT via wiring WR and the like on the circuit board PB1. As a result, the control circuit CLC in each semiconductor chip CPC can transmit signals to and from the control circuit CT via pads P7, wires BW, leads LD11 and LD12 of the semiconductor chip CPC, and terminals TM11 and TM12 and wiring WR and the like on the circuit board PB1. On the circuit board PB1, wiring coupled to each terminal TM11 and TM12 does not need to be provided beneath each semiconductor device PKG.

[0185] Terminals TM1, TM2, TM3, TM4, TM5, and TM6 are connected to the motor MOT (coil CL) via wiring WR on the circuit board PB1. On the circuit board PB1, terminals TM1 and TM4 are electrically coupled via wiring WR1; terminals TM2 and TM5 are electrically coupled via wiring WR2; and terminals TM3 and TM6 are electrically coupled via wiring WR3. These wirings WR1, WR2, and WR3 are located on the same layer as the terminals TM and are positioned beneath each semiconductor device PKG mounted on the circuit board PB1. Wiring WR1 extends in the Y direction beneath each semiconductor device PKG to connect terminals TM1 and TM4; wiring WR2 extends in the Y direction beneath each semiconductor device PKG to connect terminals TM2 and TM5; and wiring WR3 extends in the Y direction beneath each semiconductor device PKG to connect terminals TM3 and TM6. Figure 30 is superimposed on Figure 5 The plan view of the wirings WR1, WR2, and WR3 on the semiconductor device PKG (top view) is used to make the planar positions of the wirings WR1, WR2, and WR3 understandable.

[0186] Therefore, when each semiconductor device PKG is mounted on the circuit board PB1, the leads LD1 and LD4 of the semiconductor device PKG are electrically coupled to each other via the terminals TM1, TM4 and the wiring WR1 of the circuit board PB1, and are further electrically coupled to the above-mentioned motor MOT (coil CL) via the wiring WR of the circuit board PB1, etc. The leads LD2 and LD5 of each semiconductor device PKG are electrically coupled to each other via the terminals TM2, TM5 and the wiring WR2 of the circuit board PB1, and are further electrically coupled to the above-mentioned motor MOT (coil CL) via the wiring WR of the circuit board PB1, etc. The leads LD3 and LD6 of each semiconductor device PKG are electrically coupled to each other via the terminals TM3, TM6 and the wiring WR3 of the circuit board PB1, and are further electrically coupled to the above-mentioned motor MOT (coil CL) via the wiring WR of the circuit board PB1, etc.

[0187] The wirings WR1, WR2, and WR3 are arranged in the topmost wiring layer of the wiring layers within the circuit board PB1. In the topmost wiring layer of the circuit board PB1, the wirings WR1, WR2, and WR3 are arranged below each semiconductor device PKG. As a result, the leads LD1 and LD4 of the semiconductor device PKG can be coupled to each other with low resistance; the leads LD2 and LD5 of the semiconductor device PKG can be coupled to each other with low resistance; and the leads LD3 and LD6 of the semiconductor device PKG can be coupled to each other with low resistance. This reduces conduction losses. In the circuit board PB1, the wirings WR1, WR2, and WR3 are separated from each other, and none of them is electrically coupled to another.

[0188] The terminal TM7 and the terminal TM8 of the circuit board PB1 are electrically coupled to each other through the wiring (power wiring) WR4 of the circuit board PB1. The terminal TM9 and the terminal TM10 of the circuit board PB1 are electrically coupled to each other through the wiring (ground wiring) WR5 of the circuit board PB1. Therefore, when each semiconductor device PKG is mounted on the circuit board PB1, the wiring WR4 can be considered as the wiring that electrically couples the lead LD7 and the lead LD8 of the semiconductor device PKG to each other; and the wiring WR5 can be considered as the wiring that electrically couples the lead LD9 and the lead LD10 of the semiconductor device PKG to each other. In the circuit board PB1, the wirings WR4 and WR5 can be arranged in a wiring layer lower than the wiring layer forming the wirings WR1, WR2, and WR3. That is, the wirings WR4 and WR5 can be arranged below the wirings WR1, WR2, and WR3. From a different point of view, in the circuit board PB1, the wirings WR4 and WR5 can be arranged in a wiring layer different from the wiring layer forming the wirings WR1, WR2, and WR3. As a result, in the circuit board PB1, the terminals TM7 and TM8 can be electrically coupled to each other through the wiring WR4, and the terminals TM9 and TM10 can be electrically coupled to each other through the wiring WR5 without being blocked by the wirings WR1, WR2, and WR3. This makes it possible to reduce conduction loss and impedance.

[0189] Furthermore, for example, the wiring widths of the wirings WR4 and WR5 can be increased and made larger than those of the wirings WR1, WR2, and WR3. That is, the wirings WR4 and WR5 can be formed into patterns having large areas (e.g., patterns having larger areas than those of the wirings WR1, WR2, and WR3). This reduces conduction loss and impedance.

[0190] The lead LD13 of the semiconductor device PKG is electrically unnecessary, but it is desirable to couple the lead LD13 to a ground terminal (a terminal supplied with a ground potential GND) on the circuit board PB1 to enhance noise resistance. In this case, a ground potential can be supplied from the ground terminal of the circuit board PB1 to the die pad DPC of the semiconductor device PKG via the lead LD13.

[0191] exist Figures 24 to 29 In the case shown in FIG, a heat sink (housing) HS is provided (mounted) on the main surface MRa of the sealing portion MR of each semiconductor device PKG mounted on the circuit board PB1 via an insulating adhesive material BD4. For example, insulating thermal grease or the like can be used for the adhesive material BD4. For example, a fin-type heat sink or the like can be used for the heat sink HS.

[0192] In the semiconductor device PKG, the back sides DPCb, DPHb, DP1b, DP2b, DP3b of the die pads DPC, DPH, DP1, DP2, DP3 are exposed from the main surface MRa of the sealing portion MR. These back sides DPCb, DPHb, DP1b, DP2b, DP3b are bonded to the heat sink HS via the insulating adhesive material BD4. That is, the insulating adhesive material BD4 is located between the back sides DPCb, DPHb, DP1b, DP2b, DP3b of the die pads DPC, DPH, DP1, DP2, DP3 of the semiconductor device PKG and the heat sink HS. As a result, the heat generated in the semiconductor chips CPC, CP1 to CP6 within the semiconductor device PKG can be dissipated to the heat sink HS via the die pads DPC, DPH, DP1, DP2, DP3 and the adhesive material BD4 (thermal grease).

[0193] Using insulating adhesive material BD4 instead of conductive material can prevent the die pads DPC, DPH, DP1, DP2, DP3 of the semiconductor device PKG from being electrically coupled to each other through the adhesive material BD4 or the heat sink HS, and attach the heat sink HS with large heat capacity (large volume) to the semiconductor device PKG.

[0194] Research example

[0195] Figures 31 to 35 This is a top view illustrating a semiconductor device PKG101 in a research example studied by the present inventors ( Figure 31 )、Bottom view( Figure 32 ) or plan perspective ( Figures 33 to 35 ). Figure 31 Corresponding to Figure 5 ; Figure 32 Corresponding to Figure 6 ; Figure 33 Corresponding to Figure 7 ; Figure 34 Corresponding to Figure 8 ;and Figure 35 Corresponding to Figure 9 .

[0196] exist Figures 31 to 35 In the semiconductor device PKG101 of the study example shown in , the die pads DPH, DPC, the semiconductor chips CPC, CP1, CP2, CP3, the lead coupling portions LB1, LB2, LB3, the leads LD1, LD2, LD3, LD7, LD8, LD11, LD12, and the metal plates MP1, MP2, MP3 are basically the same as those of the semiconductor device PKG. However, Figures 31 to 35 The semiconductor device PKG101 in the study example shown in FIG1 is different from the above-mentioned semiconductor device PKG in that:

[0197] In the semiconductor device PKG101 of the study example, semiconductor chips CP4, CP5, and CP6 are mounted on die pads DP101, DP102, and DP103, which correspond to die pads DP1, DP2, and DP3, respectively. The source pads P4S, P5S, and P6S of the semiconductor chips CP4, CP5, and CP6 are not coupled to a common metal plate. Specifically, the source pad P4S of the semiconductor chip CP4 is coupled to a lead coupling portion LB104a via the metal plate MP104a, and a plurality of leads LD109a are integrally coupled to the lead coupling portion LB104a. The source pad P5S of the semiconductor chip CP5 is coupled to a lead coupling portion LB104b via the metal plate MP104b, and a plurality of leads LD109b are integrally coupled to the lead coupling portion LB104b. The source pad P6S of the semiconductor chip CP6 is coupled to the lead coupling portion LB104c via the metal plate MP104c, and a plurality of leads LD109c are integrally coupled to the lead coupling portion LB104c. Leads LD109a, LD109b, and LD109c for the sources of the low-side power MOSFETs (4, 5, 6) are provided on the side surface MRc1 of the sealing portion MR.

[0198] In the semiconductor device PKG101 of the study example, multiple leads LD104 formed integrally with the die pad DP101 are arranged on the side MRc4 and side MRc1 sides of the seal portion MR. Multiple leads LD105 formed integrally with the die pad DP102 are arranged on the side MRc1 side of the seal portion MR. Multiple leads LD106 formed integrally with the die pad DP103 are arranged on the side MRc2 and side MRc1 sides of the seal portion MR. Therefore, of these leads LD104, LD105, and LD106 serving as the drains of the low-side power MOSFETs (4, 5, and 6), lead LD104 is arranged on the side MRc4 and side MRc1 sides of the seal portion MR; lead LD106 is arranged on the side MRc2 and side MRc1 sides of the seal portion MR; and lead LD105 is arranged only on the side MRc1 side of the seal portion MR.

[0199] The inventors' research has revealed that the following problems may occur in the semiconductor device PKG101 used in the research example:

[0200] Because the die pad DP102 is sandwiched between the die pad DP101 and the die pad DP103, the lead LD105 integrally formed with the die pad DP102 must inevitably be positioned on the side MRc1 side of the seal portion MR, opposite the die pad DP102 (semiconductor chip CP5). Simultaneously, the lead LD109b electrically coupled to the source pad P5S of the semiconductor chip CP5 via the metal plate MP104b must also inevitably be positioned on the side MRc1 side of the seal portion MR, opposite the die pad DP102 (semiconductor chip CP5). This is because the metal plate MP104b is coupled to the source pad P5S of the semiconductor chip CP5, but not to the source pads P4S and P6S of the semiconductor chips CP4 and CP6; therefore, the metal plate MP104b must be positioned so as not to overlap with the die pads DP101 and DP103 and the semiconductor chips CP4 and CP6 when viewed in plan. Therefore, it can be seen that the lead LD109b is set on the side MRc1 side of the sealing part MR, opposite to the tube core pad DP102 (semiconductor chip CP5), and further the lead LD109b and the source pad P5S of the semiconductor chip CP5 are electrically coupled to each other via the metal plate MP104b extending in the Y direction.

[0201] Therefore, in the semiconductor device PKG101 of the study example, the lead LD109b for the source of the semiconductor chip CP5 (power MOSFET 5) and the lead LD105 for the drain must both be arranged in a narrow area on the side MRc1 side of the seal portion MR, opposite the die pad DP102 (semiconductor chip CP5). In other words, the area where the lead LD109b for the source of the semiconductor chip CP5 (power MOSFET 5) can be arranged and the area where the lead LD105 for the drain can be arranged are limited to the narrow area on the side MRc1 side of the seal portion MR, opposite the die pad DP102 (semiconductor chip CP1). This results in an increase in the resistance of the current path through the source pad P5S of the semiconductor chip CP5, the metal plate MP104b, and the lead LD109b, or in an increase in the resistance of the current path through the back electrode BE5 of the semiconductor chip CP5, the die pad DP102, and the lead LD105. This results in an increase in the on-resistance (resistance during conduction) of the semiconductor chip CP5 (power MOSFET 5), which degrades the performance of the semiconductor device PKG101.

[0202] For example, in Figures 31 to 35In the case shown in FIG, the die pad DP102 and the lead LD105 are integrally coupled to each other via a narrow conductor; thus, the resistance of the current path through the back electrode BE5 of semiconductor chip CP5, the die pad DP102, and the lead LD105 increases. In this case, the resistance of the current path through the back electrode BE5 of semiconductor chip CP5 and the lead LD105 becomes greater than the resistance of the current path through the back electrode BE4 of semiconductor chip CP4 and the lead LD104, and the resistance of the current path through the back electrode BE6 of semiconductor chip CP6 and the lead LD106. As a result, the components constituting the inverter circuit formed by semiconductor device PKG101 may become unbalanced. For example, in the above-described motor MOT, there is a possibility that torque increases only when current flows through the back electrode BE5 of semiconductor chip CP5, the die pad DP102, and the lead LD105 to the coil CL of the motor MOT (e.g., V-phase coil CL2). At the same time, in order to increase the width (width in the X direction) of the conductor coupling the die pad DP102 and the lead LD105 to each other, the width (width in the X direction) of the lead coupling portion LB104b must be reduced. This results in an increase in the resistance of the current path passing through the source pad P5S of the semiconductor chip CP5, the metal plate MP104b, and the lead LD109b.

[0203] In order to increase both the width (width in the X direction) of the conductor coupling the die pad DP102 and the lead LD105 to each other and the width (width in the X direction) of the lead coupling portion LB104b, the intervals between the die pads DP101 and DP102 and the intervals between the die pads DP103 and DP102 must be increased, but this results in an increase in the size of the sealing portion MR in the X direction. Consequently, this causes an increase in the size of the semiconductor device PKG101.

[0204] Therefore, in the semiconductor device PKG101 of the study example, the resistance of the current path through the source pad P5S of the semiconductor chip CP5 and the source lead LD109b increases; the resistance of the current path through the drain back electrode BE5 of the semiconductor chip CP5 and the drain lead LD105 increases; or the size of the semiconductor device PKG101 increases. Furthermore, due to the increased thermal resistance between the die pad DP102 and the lead LD105, the semiconductor chip CP5 is more likely to heat up than the semiconductor chips CP4 and CP6.

[0205] The present inventors have considered a semiconductor device obtained by packaging semiconductor chips CP1, CP2, and CP3 including power transistors for high-side switching, semiconductor chips CP4, CP5, and CP6 including power transistors for low-side switching, and a semiconductor chip CPC including a control circuit for controlling these chips. In such a semiconductor device, without adding some design considerations such as how to couple each semiconductor chip and each lead to each other and how to arrange the leads, the performance of the semiconductor device would deteriorate or the size of the semiconductor device would increase.

[0206] Main features and effects

[0207] The semiconductor device PKG in this embodiment is a semiconductor device obtained by sealing semiconductor chips CP1, CP2, CP3, each including a power transistor for high-side switching, semiconductor chips CP4, CP5, CP6, each including a power transistor for low-side switching, and a semiconductor chip CPC including a control circuit for controlling these chips in a sealing portion MR (sealing body). The semiconductor chips CP1, CP2, CP3 (first, second, and third semiconductor chips) are mounted on a common die pad DPH (first chip mounting portion), and the semiconductor chips CP4, CP5, CP6, CPC (fourth, fifth, sixth, and seventh semiconductor chips) are mounted on die pads DP1, DP2, DP3, DPC (second, third, fourth, and fifth chip mounting portions), respectively.

[0208] One of the main features of the semiconductor device PKG in this embodiment is that the control semiconductor chip CPC is arranged in the Y direction (second direction) between a first chip group including semiconductor chips CP1, CP2, CP3 for the high side and a second chip group including semiconductor chips CP4, CP5, CP6 for the low side.

[0209] The semiconductor chips CP1, CP2, CP3 for the high side and the semiconductor chips CP4, CP5, CP6 for the low side are controlled by one semiconductor chip CPC. Therefore, providing the semiconductor chip CPC between the semiconductor chips CP1, CP2, CP3 (first chip group) and the semiconductor chips CP4, CP5, CP6 (second chip group) makes it easier to control the semiconductor chips CP1 to CP6 by the semiconductor chip CPC, and can enhance the performance of the semiconductor device PKG. For example, since the distance from each semiconductor chip CP1 to CP6 to the semiconductor chip CPC can be made substantially the same, the pads of each semiconductor chip CP1 to CP6 and the pads of the semiconductor chip CPC can be easily coupled to each other through the wire BW, and further the coupling resistance can be easily uniformized. As a result, the semiconductor chips CP1 to CP6 can be controlled by the semiconductor chip CPC with a good balance.

[0210] The power transistors for high-side switching and low-side switching must be coupled in series. Therefore, the source pad P1S of semiconductor chip CP1 and the back electrode BE4 of semiconductor chip CP4 need to be electrically coupled to each other. This also applies to semiconductor chips CP2, CP5, and semiconductor chips CP3, CP6.

[0211] In this embodiment, as described above, the semiconductor chip CPC is disposed between the semiconductor chips CP1, CP2, and CP3 (the first chip group) and the semiconductor chips CP4, CP5, and CP6 (the second chip group). Consequently, the semiconductor chip CPC hinders the coupling of the source pad P1S of the semiconductor chip CP1 and the back electrode BE4 of the semiconductor chip CP4 via the conductor within the seal portion MR, making it difficult to couple these items. This also applies to the semiconductor chips CP2, CP5, and the semiconductor chips CP3 and CP6.

[0212] Therefore, in this embodiment, a lead LD1 (first lead) electrically coupled to the pad P1S of the semiconductor chip CP1 (via the metal plate MP1) and a lead LD2 (second lead) electrically coupled to the pad P2S of the semiconductor chip CP2 (via the metal plate MP2) are provided in the semiconductor device PKG. In addition, a lead LD3 (third lead) electrically coupled to the pad P3S of the semiconductor chip CP3 (via the metal plate MP3) and a lead LD4 (fourth lead) integrally formed with the die pad DP1 and electrically coupled to the back electrode BE4 of the semiconductor chip CP4 are provided in the semiconductor device PKG. In addition, a lead LD5 (fifth lead) integrally formed with the die pad DP2 and electrically coupled to the back electrode BE5 of the semiconductor chip CP5 and a lead LD6 (sixth lead) integrally formed with the die pad DP3 and electrically coupled to the back electrode BE6 of the semiconductor chip CP6 are provided in the semiconductor device PKG. In addition, the semiconductor device PKG includes leads LD7 and LD8 (a seventh lead and an eighth lead) formed integrally with the die pad DPH and electrically coupled to the back electrodes BE1, BE2, and BE3 of the semiconductor chips CP1, CP2, and CP3. Furthermore, the semiconductor device PKG includes leads LD9 and LD10 (a ninth lead and a tenth lead) electrically coupled to the source pads P4S, P5S, and P6S of the semiconductor chips CP4, CP5, and CP6 via the metal plate MP4 (first metal plate).

[0213] As a result, when the semiconductor device PKG is mounted on the circuit board PB1, the potential (power supply potential) VIN can be supplied to the leads LD7 and LD8, and the reference potential (ground potential GND) lower than the power supply potential can be supplied to the leads LD9 and LD10. The power transistor included in the semiconductor chip CP1 and the power transistor included in the semiconductor chip CP4 can be coupled in series between the potential VIN and the reference potential (GND). The power transistor included in the semiconductor chip CP2 and the power transistor included in the semiconductor chip CP5 can be coupled in series between the potential VIN and the reference potential (GND). The power transistor included in the semiconductor chip CP3 and the power transistor included in the semiconductor chip CP6 can be coupled in series between the potential VIN and the reference potential (GND). This makes it possible to use the power transistors included in the semiconductor chips CP1, CP2, and CP3 as high-side switches, and to use the power transistors included in the semiconductor chips CP4, CP5, and CP6 as low-side switches.

[0214] In this embodiment, in addition to providing the semiconductor device PKG with these leads LD, some designs on how to arrange and couple these leads LD are added.

[0215] A more specific description will be given. In this embodiment, when viewed in a plane, the leads LD1, LD2, and LD3 are arranged on the side MRd3 (side MRc3) of the sealing portion MR, and the leads LD4, LD5, and LD6 are arranged on the side MRd1 (side MRc1) of the sealing portion MR. That is, when viewed in a plane, the leads LD1, LD2, and LD3 intersect with the side MRd3 (third side) of the sealing portion MR, and the leads LD4, LD5, and LD6 intersect with the side MRd1 (first side) of the sealing portion MR. In this embodiment, when viewed in a plane, the leads LD8 and LD10 are arranged on the side MRd2 (side MRc2) of the sealing portion MR, and the leads LD7 and LD9 are arranged on the side MRd4 (side MRc4). That is, when viewed in plane, the leads LD8 and LD10 intersect with the side MRd2 (second side) of the sealing portion MR, and the leads LD7 and LD9 intersect with the side MRd4 (fourth side).

[0216] Another main feature of this embodiment is that the source pads P4S, P5S, P6S of the semiconductor chips CP4, CP5, CP6 are coupled to a common metal plate MP4, and the metal plate MP4 is coupled to the lead LD10 arranged on the side MRc2 side of the sealing part MR and the lead LD9 arranged on the side MRc4 side of the sealing part MR.

[0217] exist Figures 31 to 35In the semiconductor device PKG101 of the study example shown in FIG, unlike the embodiment, the source pads P4S, P5S, and P6S of the semiconductor chips CP4, CP5, and CP6 are coupled to different metal plates MP104a, MP104b, and MP104c, respectively. Therefore, a source lead must be provided for each of the semiconductor chips CP4, CP5, and CP6. Therefore, as described above, the source lead LD109b and drain lead LD105 of the semiconductor chip CP5 must both be provided in a narrow area on the side surface MRc1 of the seal portion MR, facing the semiconductor chip CP1 (die pad DP102).

[0218] At the same time, in this embodiment, the source pads P4S, P5S, and P6S of semiconductor chips CP4, CP5, and CP6 are coupled to a common metal plate MP4. Therefore, the source lead of semiconductor chip CP4 or the source lead of semiconductor chip CP6 can also be used as the source lead of semiconductor chip CP5, without having to separately provide a source lead for semiconductor chip CP5. That is, while lead LD10 disposed on the side surface MRc2 side of seal portion MR is located close to semiconductor chip CP6, and lead LD9 disposed on the side surface MRc4 side of seal portion MR is located close to semiconductor chip CP4, not only the source pads P4S and P6S of semiconductor chips CP4 and CP6, but also the source pad P5S of semiconductor chip CP5 can be electrically coupled to leads LD9 and LD10 via metal plate MP4. In other words, leads LD9 and LD10 serve as a common source lead for semiconductor chips CP4, CP5, and CP6 (power MOSFETs 1, 2, and 3).

[0219] Therefore, in this embodiment, the lead LD5 only needs to be provided on the side MRd1 of the sealing portion MR, between the lead LD4 and the lead LD6 (between the lead group including the lead LD4 and the lead group including the lead LD6); and there is no need to provide the lead LD electrically coupled to the source pad P5S of the semiconductor chip CP5. From a different point of view, the lead LD5 can be provided on the side MRd1 of the sealing portion MR, at a position opposite to the semiconductor chip CP5 (die pad DP2), and there is no need to provide the lead LD electrically coupled to the source pad P5S of the semiconductor chip CP5. That is, the position between the lead LD4 and the lead LD6 on the side MRd1 of the sealing portion MR, or, from a different point of view, the position opposite to the semiconductor chip CP5 (die pad DP2), can be used as an area dedicated to providing the drain lead LD5 of the semiconductor chip CP5 without providing the source lead of the semiconductor chip CP5.

[0220] Therefore, in the present embodiment, on the side MRd1 of the seal portion MR, the lead LD5 is provided between the lead LD4 and the lead LD6, that is, between the lead group including the lead LD4 and the lead group including the lead LD6, and no lead electrically coupled to the source pad P5S of the semiconductor chip CP5 is provided. From a different point of view, the lead LD5 is provided in a position opposite to the semiconductor chip CP5 (die pad DP2) on the side MRd1 of the seal portion MR, but no lead electrically coupled to the source pad P5S of the semiconductor chip CP5 is provided.

[0221] Therefore, the resistance of the current path through the back electrode BE5 of the semiconductor chip CP5, the die pad DP2, and the lead LD5 can be suppressed, and the on-resistance (resistance during conduction) of the semiconductor chip CP5 (power MOSFET 5) can be suppressed. Figures 31 to 35 The situation is different from the research example shown in Figures 5 to 15 In the case of the present embodiment shown in , the die pad DP2 and the lead LD5 can be integrally coupled to each other via a wide conductor (e.g., a conductor having a width wider than the width of the metal plate MP4 in the Y direction); therefore, the resistance of the current path through the back electrode BE5 of the semiconductor chip CP5, the die pad DP2, and the lead LD5 can be reduced. Furthermore, the number of drain leads LD5 of the semiconductor chip CP5 can be increased, which can also help suppress the on-resistance of the semiconductor chip CP5 (power MOSFET 5). Since the thermal resistance between the die pad DP2 and the lead LD5 can be suppressed, the temperature of the semiconductor chip CP5 can be suppressed or prevented compared to the semiconductor chips CP4 and CP6.

[0222] In this embodiment, the lead LD9 provided at a position opposite to the semiconductor chip CP4 (die pad DP1) and the lead LD10 provided at a position opposite to the semiconductor chip CP6 (die pad DP3) are used not only as source leads of the semiconductor chips CP4 and CP6, but also as source leads of the semiconductor chip CP5. Therefore, a sufficient number of source leads of the semiconductor chip CP5 can be ensured. The leads LD9 and LD10 are electrically coupled to the source pad P5S of the semiconductor chip CP5 via the low-resistance metal plate MP4. Therefore, the resistance of the current path through the source pad P5S of the semiconductor chip CP5, the metal plate MP4 and the leads LD9 and LD10 can be suppressed, and the on-resistance of the semiconductor chip CP5 (power MOSFET 5) can be suppressed. Figures 31 to 35 Compared with the case shown in the study Figures 5 to 15 In the case of the present embodiment shown in , the number of leads LD electrically coupled to the source pad P5S of the semiconductor chip CP5 can be increased, which can also contribute to suppressing the on-resistance of the semiconductor chip CP5 (power MOSFET5).

[0223] As described above, according to this embodiment, it is possible to achieve both resistance suppression in the current path through the source pad P5S and the source lead LD (LD9, LD10) of the semiconductor chip CP5 and resistance suppression in the current path through the drain back electrode BE5 and the drain lead LD (LD5) of the semiconductor chip CP5. Therefore, the on-resistance of the semiconductor chip CP5 (power MOSFET 5) can be appropriately suppressed, thereby enhancing the performance of the semiconductor device PKG.

[0224] In this embodiment, it is not necessary to arrange the source lead of the semiconductor chip CP5 between the lead LD4 and the lead LD6, or, from a different perspective, at a position on the side MRd1 (side surface MRc1) of the seal portion MR that faces the semiconductor chip CP5 (die pad DP2). Therefore, the size of the seal portion MR in the X direction can be suppressed. Therefore, the flat size of the semiconductor device PKG can be reduced, thereby achieving size reduction of the semiconductor device PKG.

[0225] In this embodiment, the leads LD electrically coupled to the source pad P5S of the semiconductor chip CP5 do not need to be provided on the side MRd1 (side MRc1) of the seal portion MR. Therefore, the source leads LD (LD9, LD10) of the semiconductor chips CP4, CP5, and CP6 are provided only on the sides MRd4 and MRd2 of the seal portion MR, and no source leads are provided on the side MRd1 of the seal portion MR. As a result, only the drain leads LD4, LD5, and LD6 of the semiconductor chips CP4, CP5, and CP6 need to be led out from the side MRd1 (side MRc1) of the seal portion MR. This facilitates the routing of the wiring of the circuit board PB1 on which the semiconductor device PKG is mounted.

[0226] Assume that, unlike the present embodiment, lead LD9 is omitted from the source lead LD9 and lead LD10 of semiconductor chips CP4, CP5, and CP6. In this case, when semiconductor chip CP4 (power MOSFET 4) is turned on, current flows from source pad P4S of semiconductor chip CP4 to lead LD10 through metal plate MP4. However, since the current path is extended, there is a concern that conduction loss may increase. Assume that lead LD10 is omitted from the lead LD9 and lead LD10. In this case, when semiconductor chip CP6 (power MOSFET 6) is turned on, current flows from source pad P6S of semiconductor chip CP6 to lead LD9 through metal plate MP4. However, since the current path is extended, there is a concern that conduction loss may increase.

[0227] At the same time, in this embodiment, the leads LD (in this example, the leads LD9 and LD10) electrically coupled to the source pads P4S, P5S, and P6S of the semiconductor chips CP4, CP5, and CP6 are arranged on the side MRd4 and side MRd2 of the seal portion MR. Therefore, when the semiconductor chip CP4 (power MOSFET 4) is turned on, current can flow mainly from the source pad P4S of the semiconductor chip CP4 to the lead LD9 near the semiconductor chip CP4 through the metal plate MP4. When the semiconductor chip CP6 (power MOSFET 6) is turned on, current can flow mainly from the source pad P6S of the semiconductor chip CP6 to the lead LD10 near the semiconductor chip CP6 through the metal plate MP4. When the semiconductor chip CP5 (power MOSFET 5) is turned on, current can flow from the source pad P5S of the semiconductor chip CP5 to both the lead LD9 and the lead LD10 through the metal plate MP4. As a result, no matter which of the semiconductor chips CP4, CP5, and CP6 is turned on, resistance and conduction loss can be suppressed. In addition, impedance can be reduced.

[0228] When controlling the semiconductor device PKG, two of the semiconductor chips CP4, CP5, and CP6 (power MOSFETs 4, 5, and 6) can be turned on simultaneously, but all three of them cannot be turned on simultaneously. Therefore, when the semiconductor chips CP4 and CP5 of the semiconductor chips CP4, CP5, and CP6 are turned on, the temperature of the semiconductor chips CP4 and CP5 in the on state rises, and the temperature of the semiconductor chip CP6 that is not in the on state is lower than that of the semiconductor chips CP4 and CP5. Therefore, the heat generated in the semiconductor chips CP4 and CP5 can be dissipated through the metal plate MP4 toward the lead LD10 that is closer to the semiconductor chip CP6 that is not in the on state and has a lower temperature. When the semiconductor chips CP5 and CP6 of the semiconductor chips CP4, CP5, and CP6 are turned on simultaneously, the heat generated in the semiconductor chips CP5 and CP6 can be dissipated through the metal plate MP4 toward the lead LD9 that is closer to the semiconductor chip CP4 that is not in the on state and has a lower temperature. Therefore, even when two of the semiconductor chips CP4, CP5, and CP6 are connected, the provision of both the lead LD9 and the lead LD10 can enhance the efficiency of heat dissipation from the semiconductor chips CP4, CP5, and CP6 to the lead LD through the metal plate MP4. As a result, the temperature rise of the semiconductor chips CP4, CP5, and CP6 when they are connected can be suppressed, and the reliability of the semiconductor device PKG can be enhanced. The ability to suppress the temperature rise of the semiconductor chips CP4, CP5, and CP6 when they are connected can also help suppress the resistance of the semiconductor chips in the on state (on-resistance).

[0229] Next, still another feature of the semiconductor device PKG in this embodiment will be described.

[0230] Leads LD (in this example, leads LD7 and LD8) integrally coupled to the die pad DPH on which the high-side semiconductor chips CP1, CP2, and CP3 are mounted are provided on both the side MRd2 and the side MRd4 of the seal portion MR. Therefore, when semiconductor chips CP1 and CP2 of the semiconductor chips CP1, CP2, and CP3 are simultaneously turned on, heat generated in the semiconductor chips CP1 and CP2 can be dissipated through the lead LD8, which is closer to the side of the semiconductor chip CP3, which is not in the conducting state and has a lower temperature, through the die pad DPH. When semiconductor chips CP2 and CP3 of the semiconductor chips CP1, CP2, and CP3 are simultaneously turned on, heat generated in the semiconductor chips CP2 and CP3 can be dissipated through the lead LD7, which is closer to the side of the semiconductor chip CP1, which is not in the conducting state and has a lower temperature, through the die pad DPH. Therefore, even when two of the semiconductor chips CP1, CP2, and CP3 are connected, the provision of both leads LD7 and LD8 can enhance the efficiency of heat dissipation from the semiconductor chips CP1, CP2, and CP3 to the leads LD through the die pad DPH. As a result, the temperature rise of the semiconductor chips CP1, CP2, and CP3 when they are connected can be suppressed, and the reliability of the semiconductor device PKG can be enhanced. The ability to suppress the temperature rise of the semiconductor chips CP1, CP2, and CP3 when they are connected can also help suppress the resistance of the semiconductor chips in the on state (on-resistance).

[0231] When viewed in a plane, semiconductor chips CP1, CP2, and CP3 are arranged along the X direction, and semiconductor chips CP4, CP5, and CP6 are arranged along the X direction. As a result, the flat size of the semiconductor device PKG can be reduced, thereby enabling size reduction of the semiconductor device PKG.

[0232] In this embodiment, when viewed in plan, the lead LD12 is arranged on the side MRd2 (side MRc2) of the seal portion MR, and the lead LD11 is arranged on the side MRd4 (side MRc4). That is, when viewed in plan, the lead LD12 intersects with the side MRd2 of the seal portion MR, and the lead LD11 intersects with the side MRd4. This makes it possible to electrically couple the leads LD11 and LD12 to the pad P7 of the semiconductor chip CPC via the conductive coupling member (wire BW in this example) without being hindered by the semiconductor chips CP1 to CP6.

[0233] In this embodiment, on the side MRd4 (side MRc4) of the sealing portion MR, the lead LD11 is arranged between the lead LD7 and the lead LD9 (between the lead group including the lead LD7 and the lead group including the lead LD9). On the side MRd2 (side MRc2) of the sealing portion MR, the lead LD12 is arranged between the lead LD8 and the lead LD10 (between the lead group including the lead LD8 and the lead group including the lead LD10). This makes it possible to electrically couple the leads LD11, LD12 to the pad P7 of the semiconductor chip CPC via a conductive coupling member (in this example, the wire BW) without being hindered by the metal plates MP1 to MP4.

[0234] When the placement positions of leads LD9 and LD4 are interchanged, and leads LD10 and LD6 are interchanged, leads LD11 and LD12 for semiconductor chip CPC are closer to the drain leads LD4 and LD6 of semiconductor chips CP4 and CP6 on the sides MRd2 and MRd4 of the seal portion MR. However, in this case, a large current with a frequency component flows through leads LD4 and LD6 due to switching operations. As a result, there is a possibility that this large current will become a noise source, and noise will be introduced into semiconductor chip CPC from leads LD11 and LD12. When the placement positions of leads LD7 and LD1 are interchanged, and leads LD8 and LD3 are interchanged, leads LD11 and LD12 for semiconductor chip CPC are closer to the source leads LD1 and LD3 of semiconductor chips CP1 and CP3 on the sides MRd2 and MRd4 of the seal portion MR. However, in this case, a large current with a frequency component flows through leads LD1 and LD3 due to switching operations. As a result, there is a possibility that the large current becomes a noise source and the noise is introduced into the semiconductor chip CPC from the leads LD11 , LD12 .

[0235] Furthermore, in this embodiment, on the side MRd4 of the seal portion MR, the lead LD11 for the semiconductor chip CPC is located closer to the leads LD7 and LD9 than to the leads LD1 to LD6. Furthermore, on the side MRd2 of the seal portion MR, the lead LD12 for the semiconductor chip CPC is located closer to the leads LD8 and LD10 than to the leads LD1 to LD6. Since the leads LD7 and LD8 are supplied with the power supply potential VIN (a fixed potential) and the leads LD9 and LD10 are supplied with a reference potential (a fixed potential) lower than the power supply potential, all of these leads are less likely to become noise sources. Therefore, in this embodiment, the leads LD1 to LD6 can be prevented from becoming noise sources, and noise can be prevented from being introduced into the semiconductor chip CPC via the leads LD11 and LD12. This further enhances the performance and reliability of the semiconductor device PKG. In the PWM (pulse width modulation) control of the motor MOT, placing a capacitor or inductor on the power supply side facilitates stabilizing the power supply potential VIN supplied to the leads LD7 and LD8 and the reference potential (ground potential GND) supplied to the leads LD9 and LD10. In this respect as well, the leads LD7, LD8, LD9, and LD10 are less likely to become noise sources. In contrast, the leads LD1 to LD6, which pass large currents having frequency components through switching operations, are more likely to become noise sources.

[0236] The semiconductor device PKG also includes a lead LD13 (thirteenth lead) formed integrally with the die pad DPC on which the semiconductor chip CPC is mounted. It is desirable that one or more of the leads LD13 should be provided at each of the positions between the lead LD7 and the lead LD11 on the side MRd4 (side MRc4) of the sealing portion MR, and at each of the positions between the lead LD9 and the lead LD11. Furthermore, it is desirable that one or more of the leads LD13 should be provided at each of the positions between the lead LD8 and the lead LD12 on the side MRd2 (side MRc2) of the sealing portion MR, and at each of the positions between the lead LD10 and the lead LD12. Therefore, the lead LD adjacent to the lead group including the lead LD11 or the lead group including the lead LD12 is the lead LD13 formed integrally with the die pad DPC on which the semiconductor chip CPC is mounted; therefore, it is possible to more effectively prevent noise from being introduced from the leads LD11 and LD12 into the semiconductor chip CPC.

[0237] So far, the present invention made by the present inventors has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the subject matter thereof.

[0238] An example will be given. With respect to the above-mentioned embodiment, a case has been described in which the power transistors respectively formed in the semiconductor chips CP1 to CP6 are power MOSFETs (1 to 6). Alternatively, IGBTs (insulated gate bipolar transistors) may also be used as the power transistors respectively formed in the semiconductor chips CP1 to CP6. In this case, the pads P1S to P6S formed in the semiconductor chips CP1 to CP6 are emitter pads and are respectively electrically coupled to the emitter regions of the IGBTs formed in the semiconductor chips CP1 to CP6. The back electrodes BE1 to BE6 formed in the semiconductor chips CP1 to CP6 are collector back electrodes and are respectively electrically coupled to the collector regions of the IGBTs formed in the semiconductor chips CP1 to CP6. The pads P1G to P6G formed in the semiconductor chips CP1 to CP6 are gate pads and are respectively electrically coupled to the gates (gate electrodes) of the IGBTs formed in the semiconductor chips CP1 to CP6. The gate pads (P1G to P6G) serve as control terminals (control electrodes) for controlling continuity between the emitter pads (P1S to P6S) formed on the front side of the semiconductor chips (CP1 to CP6) and the collector back electrodes (BE1 to BE6) formed on the back side of the semiconductor chips (CP1 to CP6). Therefore, when using IGBTs instead of the power MOSFETs 1 to 6, in the description of the above embodiment, the "source" only needs to be replaced with the "emitter," and the "drain" only needs to be replaced with the "collector."

Claims

1. A semiconductor device, comprising: a first semiconductor chip including a first power transistor for high-side switching and having a first main surface and a first back surface located on an opposite side of the first main surface, wherein the first semiconductor chip includes a first back electrode formed in the first back surface and coupled to the first power transistor, a first electrode formed in the first main surface and coupled to the first power transistor, and a first gate electrode formed in the first main surface and controlling continuity between the first electrode and the first back electrode; a second semiconductor chip including a second power transistor for high-side switching and having a second main surface and a second back surface located on an opposite side of the second main surface, wherein the second semiconductor chip includes a second back electrode formed in the second back surface and coupled to the second power transistor, a second electrode formed in the second main surface and coupled to the second power transistor, and a second gate electrode formed in the second main surface and controlling continuity between the second electrode and the second back electrode; a third semiconductor chip including a third power transistor for high-side switching and having a third main surface and a third back surface located on an opposite side of the third main surface, wherein the third semiconductor chip includes a third back electrode formed in the third back surface and coupled to the third power transistor, a third electrode formed in the third main surface and coupled to the third power transistor, and a third gate electrode formed in the third main surface and controlling continuity between the third electrode and the third back electrode; a fourth semiconductor chip including a fourth power transistor for low-side switching and having a fourth main surface and a fourth back surface located on an opposite side of the fourth main surface, wherein the fourth semiconductor chip includes a fourth back electrode formed in the fourth back surface and coupled to the fourth power transistor, a fourth electrode formed in the fourth main surface and coupled to the fourth power transistor, and a fourth gate electrode formed in the fourth main surface and controlling continuity between the fourth electrode and the fourth back electrode; a fifth semiconductor chip including a fifth power transistor for low-side switching and having a fifth main surface and a fifth back surface located on an opposite side of the fifth main surface, wherein the fifth semiconductor chip includes a fifth back electrode formed in the fifth back surface and coupled to the fifth power transistor, a fifth electrode formed in the fifth main surface and coupled to the fifth power transistor, and a fifth gate electrode formed in the fifth main surface and controlling continuity between the fifth electrode and the fifth back electrode; a sixth semiconductor chip including a sixth power transistor for low-side switching and having a sixth main surface and a sixth back surface located on an opposite side of the sixth main surface, wherein the sixth semiconductor chip includes a sixth back electrode formed in the sixth back surface and coupled to the sixth power transistor, a sixth electrode formed in the sixth main surface and coupled to the sixth power transistor, and a sixth gate electrode formed in the sixth main surface and controlling continuity between the sixth electrode and the sixth back electrode; a seventh semiconductor chip including a circuit for controlling each of the first, second, third, fourth, fifth, and sixth semiconductor chips and having a seventh main surface and a seventh back surface located on an opposite side of the seventh main surface; wherein the seventh semiconductor chip includes a plurality of seventh electrodes formed in the seventh main surface, and wherein the first gate electrode of the first semiconductor chip, the second gate electrode of the second semiconductor chip, the third gate electrode of the third semiconductor chip, the fourth gate electrode of the fourth semiconductor chip, the fifth gate electrode of the fifth semiconductor chip, and the sixth gate electrode of the sixth semiconductor chip are electrically coupled to the seventh electrode of the seventh semiconductor chip via a plurality of first wires; a first chip mounting portion on which the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are mounted and which is electrically coupled to the first back electrode, the second back electrode, and the third back electrode; a second chip mounting portion, on which the fourth semiconductor chip is mounted and electrically coupled to the fourth back electrode; a third chip mounting portion, on which the fifth semiconductor chip is mounted and electrically coupled to the fifth back electrode; a fourth chip mounting portion, on which the sixth semiconductor chip is mounted and electrically coupled to the sixth back electrode; a fifth chip mounting portion on which the seventh semiconductor chip is mounted; a plurality of first leads electrically coupled to the first electrode of the first semiconductor chip; a plurality of second leads electrically coupled to the second electrode of the second semiconductor chip; a plurality of third leads electrically coupled to the third electrode of the third semiconductor chip; a plurality of fourth leads formed integrally with the second chip mounting portion and electrically coupled to the fourth back electrode of the fourth semiconductor chip; a plurality of fifth leads formed integrally with the third chip mounting portion and electrically coupled to the fifth back electrode of the fifth semiconductor chip; a plurality of sixth leads formed integrally with the fourth chip mounting portion and electrically coupled to the sixth back electrode of the sixth semiconductor chip; a plurality of seventh leads and a plurality of eighth leads formed integrally with the first chip mounting portion and electrically coupled to the first back electrode, the second back electrode, and the third back electrode of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip; a plurality of ninth leads and a plurality of tenth leads electrically coupled to the fourth electrode, the fifth electrode, and the sixth electrode of the fourth semiconductor chip, the fifth semiconductor chip, and the sixth semiconductor chip via a first metal plate; and a sealing body that seals the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the fifth semiconductor chip, the sixth semiconductor chip, the seventh semiconductor chip, at least a portion of the first chip mounting portion, at least a portion of the second chip mounting portion, at least a portion of the third chip mounting portion, at least a portion of the fourth chip mounting portion, at least a portion of the fifth chip mounting portion, the first metal plate, a portion of the first lead, a portion of the second lead, a portion of the third lead, a portion of the fourth lead, a portion of the fifth lead, a portion of the sixth lead, a portion of the seventh lead, a portion of the eighth lead, a portion of the ninth lead, and a portion of the tenth lead, Wherein, when viewed in a plane, the sealing body includes a first side extending along a first direction, a second side extending along a second direction intersecting the first direction, a third side extending along the first direction and located on an opposite side of the first side, and a fourth side extending along the second direction and located on an opposite side of the second side. In the second direction, the seventh semiconductor chip is located between the first chipset and the second chipset, the first chipset includes the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, the second chipset includes the fourth semiconductor chip, the fifth semiconductor chip, and the sixth semiconductor chip, and the first chipset is located on the third side, and the second chipset is located on the first side. Wherein, in the first direction, the second semiconductor chip is located between the first semiconductor chip and the third semiconductor chip, the first semiconductor chip is located on the fourth side, and the third semiconductor chip is located on the second side. Wherein, in the first direction, the fifth semiconductor chip is located between the fourth semiconductor chip and the sixth semiconductor chip, the fourth semiconductor chip is located on the fourth side, and the sixth semiconductor chip is located on the second side. Wherein, when viewed in a plane, the first lead, the second lead and the third lead intersect with the third side of the sealing body, When viewed in a plane, the fourth lead, the fifth lead, and the sixth lead intersect with the first side of the sealing body. wherein, when viewed in a plane, the eighth lead and the tenth lead intersect with the second side of the sealing body, and When viewed in a plane, the seventh lead and the ninth lead intersect with the fourth side of the sealing body.

2. The semiconductor device according to claim 1, in, On the first side of the sealing body, a fifth lead is provided between a fourth lead and a sixth lead, and no lead electrically coupled to the fifth electrode of the fifth semiconductor chip is provided.

3. The semiconductor device according to claim 1, in, On the first side of the sealing body, a fifth lead is provided at a position opposite to the fifth semiconductor chip, and no lead electrically coupled to the fifth electrode of the fifth semiconductor chip is provided.

4. The semiconductor device according to claim 1, in, No wire electrically coupled to the fifth electrode of the fifth semiconductor chip is provided on the first side of the sealing body.

5. The semiconductor device according to claim 1, in, a first lead is electrically coupled to the first electrode of the first semiconductor chip via a second metal plate, wherein the second lead is electrically coupled to the second electrode of the second semiconductor chip via a third metal plate, and The third lead is electrically coupled to the third electrode of the third semiconductor chip via a fourth metal plate.

6. The semiconductor device according to claim 1, in, When viewed in a plane, the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are arranged along the first direction, and When viewed in a plane, the fourth semiconductor chip, the fifth semiconductor chip, and the sixth semiconductor chip are arranged along the first direction.

7. The semiconductor device according to claim 1, in, The seventh semiconductor chip includes a plurality of eighth electrodes and a plurality of ninth electrodes formed in the seventh main surface, and the semiconductor device further includes: a plurality of eleventh leads electrically coupled to the eighth electrode of the seventh semiconductor chip, respectively; and a plurality of twelfth leads, respectively electrically coupled to the ninth electrode of the seventh semiconductor chip, When viewed in a plane, the eleventh lead intersects the fourth side of the sealing body, and the twelfth lead intersects the second side of the sealing body.

8. The semiconductor device according to claim 7, in, On the fourth side, the eleventh lead is disposed between the seventh lead and the ninth lead, and Wherein, on the second side, the twelfth lead is arranged between the eighth lead and the tenth lead.

9. The semiconductor device according to claim 8, in, an eleventh lead is electrically coupled to the eighth electrode of the seventh semiconductor chip via a plurality of second wires, respectively; and The twelfth lead is electrically coupled to the ninth electrode of the seventh semiconductor chip via a plurality of third wires.

10. The semiconductor device according to claim 8, further comprising: a plurality of thirteenth leads formed integrally with the fifth chip mounting portion, Among them, one or more of the thirteenth leads are arranged in each of the positions between the seventh lead and the eleventh lead on the fourth side, between the ninth lead and the eleventh lead on the fourth side, between the eighth lead and the twelfth lead on the second side, and between the tenth lead and the twelfth lead on the second side.

11. The semiconductor device according to claim 1, wherein the seventh lead and the eighth lead are leads to which a power supply potential is supplied, and The ninth lead and the tenth lead are leads to which a reference potential lower than the power supply potential is supplied.

12. The semiconductor device according to claim 11, in, In the semiconductor device, the first lead and the fourth lead are not connected to each other via a conductor, the second lead and the fifth lead are not connected to each other via a conductor, and the third lead and the sixth lead are not connected to each other via a conductor, and Wherein, outside the semiconductor device, the first lead and the fourth lead are electrically coupled to each other, the second lead and the fifth lead are electrically coupled to each other, and the third lead and the sixth lead are electrically coupled to each other.

13. The semiconductor device according to claim 11, wherein the semiconductor device is mounted on a circuit board, wherein the first lead and the fourth lead are electrically coupled to each other through a first wiring of the circuit board, wherein the second lead and the fifth lead are electrically coupled to each other through a second wiring of the circuit board, and The third lead and the sixth lead are electrically coupled to each other through a third wiring of the circuit board.

14. The semiconductor device according to claim 13, in, The first wiring, the second wiring, and the third wiring of the circuit board are provided below the semiconductor device.

15. The semiconductor device according to claim 14, in, The circuit board further includes a fourth wiring electrically coupling the seventh lead and the eighth lead to each other, and a fifth wiring electrically coupling the ninth lead and the tenth lead to each other.

16. The semiconductor device according to claim 15, in, In the circuit board, the fourth wiring and the fifth wiring are formed in a layer below the first wiring, the second wiring, and the third wiring.

17. The semiconductor device according to claim 1, in, The first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the fifth semiconductor chip, the sixth semiconductor chip, and the seventh semiconductor chip are used to form an inverter circuit.

18. The semiconductor device according to claim 1, in, The sealing body has an eighth main surface and an eighth rear surface located on an opposite side of the eighth main surface, and wherein a portion of each of the first chip mounting portion, the second chip mounting portion, the third chip mounting portion, the fourth chip mounting portion, and the fifth chip mounting portion is exposed from the eighth main surface.

19. The semiconductor device according to claim 1, The first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor and the sixth power transistor are all power MOSFETs.

Images