Package-on-package method and apparatus with integrated passive electronic devices

Abstract

This application relates to apparatus and techniques for encapsulating a package-on-package multi-package integrated circuit. Components of an integrated circuit can be located in apertures formed in a circuit package of a multi-package integrated circuit. The apertures can be formed by fabricating an aperture structure having internal apertures corresponding to the components. The aperture structure can be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and the aperture structure can be encapsulated in a molding compound. Sacrificial layers can be removed, exposing the apertures in the aperture structure. The components can be, for example, through-mold vias. The first package can be coupled to a second package. Multi-package integrated circuit assemblies made in accordance with the disclosure herein can include higher densities of electronic components, including passive electronic components.

Description

TECHNICAL FIELD

[0001] This document relates generally to, but is not limited to, electronic circuits, such as electronic circuits that include multiple electronic packages. BACKGROUND

[0002] Electronic circuits, such as electronic circuits that include two or more circuit packages, can be used for logic processing, memory storage, or both. Circuit packages can include one or more chips, such as silicon chips, that include multiple electronic circuits and can also be referred to as "integrated circuits." For example, integrated circuits can be used in personal computers, servers, game consoles, Internet of Things devices, and other electronic devices. Data center, server, and client device markets seek integrated circuits with higher performance, compact size, and reduced power consumption.

[0003] As computing demands increase, electronic circuits tend to include multiple chips. For example, multiple chips within a circuit package can be stacked on top of one another to provide higher processing and storage capabilities, sometimes referred to as "stacked die products." However, when combined in this way, manufacturing flexibility is reduced because processors and memory are combined and because it can be difficult to test memory independently of processors, meaning that testing can only occur after the chips are stacked.

[0004] As an alternative to stacked die products, separate circuit packages can be stacked (e.g., package on package or "PoP") to reduce the amount of board space needed to couple the electronic circuit to a printed circuit board (PCB) or substrate of a larger circuit package. However, there is often unused space within the stacked circuit packages and additional space must be left to establish electrical connections between the packages.

[0005] Electrical connections (also referred to herein as "electrical contacts") between stacked circuit packages are often located next to the chips, such as around the perimeter of the chips. Electrical pads of an upper circuit package (also referred to herein as an "upper package") and a lower circuit package (also referred to herein as a "bottom package" or "bottom circuit package") are specially configured for the stacked arrangement. For example, contacts of the upper circuit package can be arranged in an area that corresponds to a location around an outer perimeter of the bottom circuit package. The substrate of the upper circuit package or the lower circuit package can include a size that is large enough to accommodate the footprint of the chips and the electrical connections.

[0006] Passive electrical components are also typically included in the circuit package. As used herein, "passive electrical components" refer to, for example, through mold vias (TMVs), resistors, capacitors, magnetic (inductive) devices, transducers, detectors, antennas, and other electrical power delivery, management, or transmission components that are generally capable of controlling current with another electrical signal. Among passive electrical components, a legacy TMV formed by, for example, laser drilling typically has a tapered cross-section when viewed from an elevation angle.

[0007] Electrical connections between two circuit packages and from a circuit package to a PCB or motherboard can be provided by, for example, ball grid arrays, pin grid arrays, TMVs, etc.

[0008] In some instances, techniques for forming apertures in a circuit package (e.g., laser drilling, mechanical drilling, chemical or vapor etching, etc.) can cause defects and increase fabrication costs. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0010] Figure 1 An example of an aperture structure according to an embodiment is shown.

[0011] Figure 2 An example of an aperture structure of Figure 1 mounted to a substrate according to an embodiment is shown.

[0012] Figure 3 An example of an aperture structure of Figure 2 , a substrate, and other components encapsulated in a partially formed package according to an embodiment is shown.

[0013] Figure 4 A partially formed package of Figure 3 and a sacrificial layer according to an embodiment is shown.

[0014] Figure 5 A partially formed package of Figure 3 with the sacrificial layer of Figure 4 removed, exposing an aperture and creating another partially formed package is shown.

[0015] Figure 6 Formation of an additional aperture in another partially formed package according to an embodiment is shown.

[0016] Figure 7 Assembly of a through mold via in a partially formed package according to an embodiment is shown.

[0017] Figure 8 is an assembly of passive electrical components on a package in a flipped position according to embodiments.

[0018] Figure 9 shows a package to be assembled with Figure 7 a package according to embodiments.

[0019] Figure 10 shows a package on package assembly of Figure 9 a package and Figure 7 a package according to embodiments.

[0020] Figure 11 shows a system level diagram according to embodiments. DETAILED DESCRIPTION

[0021] The following detailed description and examples are illustrative only; however, the disclosed subject matter is not limited to the provided descriptions and examples. Particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. The embodiments set forth in the claims are not limited to the particular embodiments disclosed in the specification.

[0022] This application relates to apparatus and techniques for multi-package integrated circuits, such as multi-package integrated circuit assemblies comprising multiple circuit packages. A first circuit package can be electrically coupled to a second circuit package, with a passive electronic component located in an aperture or bore formed in one of the electronic packages. The aperture can be formed by fabricating an aperture structure having an internal aperture corresponding to the passive electronic component. The aperture structure can be bonded to a first substrate. The first substrate can include a first integrated circuit on a die side of the first substrate. The first substrate, aperture structure, and first integrated circuit can be encapsulated in a molding compound in a partially formed die side layer of the first circuit package. The aperture structure can be made of the molding compound.

[0023] A sacrificial layer of the partially formed first circuit package can be removed from the die side layer of the first circuit package, thereby exposing the aperture in the aperture structure. Additional apertures can optionally be formed in the first circuit package, for example, by mechanical drilling, laser drilling, chemical etching, etc. The passive electronic component can be communicatively coupled or bonded (e.g., electrically or physically coupled) to an interface side of a second substrate of the second circuit package; the coupling can include one or more of mechanical, electrical, or optical coupling. After the sacrificial layer is removed, the passive electronic component, such as a TMV, can be partially formed in the aperture. The first circuit package and the second package can be communicatively coupled together with the passive electronic component in the aperture.

[0024] A multi-package integrated circuit assembly made in accordance with the disclosure herein can include a higher density of electronic components (including passive electronic components) than older multi-package integrated circuit assemblies. A multi-package integrated circuit assembly made in accordance with the disclosure herein can be more compact than older multi-package integrated circuit assemblies. A multi-package integrated circuit assembly made in accordance with the disclosure herein can have a more complex structure than older multi-package integrated circuit assemblies.

[0025] A TMV formed in a circuit package in accordance with the disclosure herein can have a non-conical or non-tapered sidewall, in contrast to older TMVs that have conical or tapered sidewalls due to limitations of, for example, a laser drilling process. Limitations of a laser drilling process include, for example, a minimum value of a depth-to-diameter aspect ratio. This can establish, for example, a minimum width of a TMV given a depth of a molding compound. Other limitations include plasma effects, focal point effects, recasting of the drilled material, and tumbling of the drilled material, among others, which result in a laser-drilled aperture that has a taper. A TMV having a conical or tapered sidewall occupies more space in a circuit package than a TMV formed in accordance with the disclosure herein that can have a vertical sidewall.

[0026] A sidewall of a via formed in accordance with the disclosure herein can be vertical, curvilinear, can have an inverse taper, or can have a stepped structure.

[0027] A clearance or top of a package made in accordance with the disclosure herein can be lower than a clearance of a package made in accordance with older technology. For example, older technology can require passive electronic components to be less than a thickness of a molding compound, and they leave a mold cap void, 100 μιη being one example of a mold cap void.

[0028] Older approaches to PoP assemblies can also place all passive and power components on a substrate, with a significant clearance left above such components.

[0029] In the case of stacked circuit packages, one of the multiple circuit packages in a stack can be placed at the bottom when it has more input-output (I / O) electrical connections. For example, in a PoP arrangement that includes a logic circuit package and a memory circuit package, the logic circuit package can have more I / O electrical connections (or can have a more complex plurality of electrical connections) than the memory circuit package. In this example, the memory circuit package can also provide memory for the logic circuit package, while the logic circuit package can provide output to a larger device of which the stacked circuit package is a component. In this example, the logic circuit package can be placed at the bottom of the stacked circuit package, with less dense or less complex ball grid array connections to the top circuit package that includes the memory circuit package. The bottom circuit package can have more dense or more complex ball grid array connections to a motherboard.

[0030] To couple the upper package to the lower package, the pin outputs (e.g., ball grid array) of the upper package can be aligned with the TMVs from the bottom package. As previously discussed, the TMVs tend to be located around the perimeter of the die of the lower package. In other words, the signal contacts of the second package are not located in a central portion of the second package. Accordingly, the size of the bottom package can be increased due to the location of the TMVs around the perimeter of the die. Accordingly, the upper package or the lower package can be less desirable for sale as a standalone package due to the non-standard arrangement of the signal contacts (e.g., located around the perimeter of the die) and the larger size. Further, in cases where the package size is limited, the number of die-to-die interconnections can be reduced due to the limited space for the TMVs around the perimeter of the package.

[0031] A package that includes stacked silicon dies can have an increased thickness compared to a single die package. For example, the package thickness can increase with each additional die. As previously discussed, due to the tapering of the TMVs, the size (e.g., diameter or width) of the TMVs can increase as the length of the TMVs corresponds to the thickness of the package. As previously discussed, larger TMVs can result in a larger size of the electronic package or PoP module. Further, a package with 16 or more dies can include a thickness that is greater than 1 mm. From a manufacturing perspective, forming TMVs through an electronic package with a thickness of 1 mm or greater can be problematic.

[0032] The problems addressed by the present disclosure can include packing electronic components, including passive electronic components, more densely into a circuit package with more complex designs.

[0033] The subject matter can provide a solution to the problem by, for example, causing the TMV to have vertical sidewalls and embedding a passive electrical component into a die side layer of one package (e.g., a bottom package), where the passive electrical component is electrically coupled to an interface layer of a second package (e.g., a top package).

[0034] Figures 1 to 11 Techniques for fabricating PoP multi-package integrated circuits are shown in accordance with the disclosure herein.

[0035] Figure 1 Examples of a void structure 100 of the present disclosure in accordance with embodiments are shown. In Figure 1 the void structure can be made in various shapes and sizes. For example, void structure 105 is box-shaped, while other void structures can be "U"-shaped. Other void structure shapes can be made, such as curved structures, tapered structures (including structures with tapered shapes that are flipped versions of tapered shapes formed in legacy TMVs), and stepped structures. Such void structure shapes are not possible in legacy processes that use removal of molding material.

[0036] When a void structure encloses an interior space (e.g., void 106), a gap (not shown in void 106) can be left in the void structure to empty or clean the interior of the void structure after or during fabrication of the void structure.

[0037] A void in a void structure can be sized to accommodate a component to be inserted into the void. Figure 10 Examples of components to be inserted into a void in Figure 1 are shown.

[0038] For example, a void structure can be made of a substance such as a molding compound. For example, a molding compound can be an epoxy, a polymer, a plastic, a liquid crystal polymer, a nylon, an epoxy, a silica, etc. A void structure substance can be selected to withstand heat that can be generated during a reflow process. An outer surface of a void structure can be textured and / or chemically treated to promote bonding with a molding compound, a substrate, a die, etc. A void structure substance can be selected to bond with a molding compound or another component. A void structure substance or a molding compound can be an insulating covering. An insulating covering can electrically or physically isolate a component.

[0039] Figure 1 The void structures shown are shown with physical arrangements to accommodate components to be inserted into the void structures. A carrier can be made between the void structures to facilitate maintaining such physical arrangements during manufacturing. Such a carrier can be made independently of or in conjunction with the void structures. For example, an optional carrier 107 is shown in dashed lines in Figure 1 .

[0040] Figure 2 An example of a porous structure of a substrate 210 is shown mounted to a die 211, other components of a stacked die 212, and electrical contacts 213, in accordance with an embodiment. Figure 1 The porous structure of the substrate can be mounted to the substrate by, for example, chemical bonding, physical attachment, etc. The substrate 210 is shown to include an electrical routing layer for electrical communication, e.g., electrical interconnects 214. Figure 2 The locations of the electrical interconnects 214 (and other electrical connections in other figures) are examples only.

[0041] The die 211 or stacked die 212 can include a semiconductor material, e.g., single crystal silicon or gallium arsenide, etc. In various examples, the die can be configured as a processor (e.g., a graphics processing unit (GPU) or central processing unit (CPU)), a memory package (e.g., random access memory (RAM), flash memory, read only memory (ROM)), or other logic or memory package. The die can include at least one electrical contact (die interconnect). For example, the die interconnect can include, but is not limited to, a solder pad, a ball grid array (BGA), a land grid array (LGA), a wire bond pad, a chip carrier contact, or other electrical contact for electrically coupling the die to a substrate, e.g., the substrate 210.

[0042] The substrate 210 can provide mechanical support to the die and can provide one or more electrical routing layers for electrical communication between the die and an electronic device. The substrate can include a die side and an interface side. The substrates discussed herein can include insulating dielectric materials and conductive materials (e.g., electrical routing layers, metal foils, copper clad laminates, etc.). The dielectric materials can include at least one dielectric layer made of a material including, but not limited to, FR-4, prepreg, ceramic, epoxy, other glass or fiber filled resins, polyimide, polyester fiber, polyether ether ketone (PEEK), etc. The conductive materials and dielectric materials can be printed, e.g., with inkjet printing agents, etc., and can be etched. The conductive materials can be electro-deposited (plated) and can be formed into one or more electronic circuits. The conductive materials of the substrate can provide circuit routing, ground, thermal energy distribution, electromagnetic shielding, etc.

[0043] The substrate can include multiple layers. The substrate can include contacts on either or both of the interface side and the die side. The contacts can be exposed for coupling to another contact or electronic or other electrical component. The contacts can be arranged to be interchangeable with a die, electronic package, or electronic device, including according to industry standard formats.

[0044] Figure 3A partial formation of a package 300 is shown according to an embodiment. The partial formation of the package 300 includes a mold compound 315 that encapsulates a Figure 2 porous structure, a substrate, and other components. The encapsulation of such components can be by injection molding, deposition, 3D printing, by joining a form around the components, etc. To help understand the encapsulation of such structures in the mold compound, an outer perimeter of a porous structure, such as the porous structure 105, is shown in Figure 2 However, in some embodiments, such as when the porous structure is made of the same material as the mold compound 315, such an outer perimeter can be difficult to distinguish from and / or can be merged with the mold compound 315. For example, in subsequent figures, an outer perimeter of a porous structure is not shown. The package 300 can be a bottom package. Figure 3

[0045] A partial formation of a package 300 is shown according to an embodiment. The partial formation of the package 300 includes a mold compound 315 that encapsulates a Figure 4 sacrificial layer 420. The sacrificial layer 420 can be removed by, for example, mechanical grinding, laser etching, liquid or vapor phase chemical etching, etc. In Figure 3 the sacrificial layer 420 has not yet been removed, but is indicated to show where the sacrificial layer 420 is to be removed. Figure 4

[0046] A further partial formation of a package is shown according to an embodiment. The further partial formation of the package includes a mold compound 515 that encapsulates a Figure 5 sacrificial layer 420 has been removed, exposing pores and creating a further partial formation of a package 500. A top die side layer 521 of the further partial formation of the package 500 is labeled. As noted, the partial formation of the package 500 can be a bottom package. Figure 3 Figure 4 A formation of optional additional pores 625a-625c in the top die side layer 521 of the further partial formation of the package 500 is shown according to an embodiment. The additional pores 625a-625c can be formed by a legacy pore formation process, such as mechanical drilling, laser drilling, chemical etching, etc. As exemplified above, it is possible to form the additional pores 625a-625c by using a porous structure. The discussion of forming the additional pores 625a-625c by a legacy pore formation process is to demonstrate that the use of a porous structure as described herein can coexist with a legacy pore formation process. The additional pores 625a-625c can have been formed by a legacy pore formation process prior to the removal of the sacrificial layer 420. As shown, the additional pores 625a-625c can have a non-vertical cross-section, for example, due to limitations of the legacy pore formation process.

[0047] Figure 6

[0048] Figure 7 ​​Assembly of a TMV in a partially formed package according to an embodiment is shown. The TMV can be formed by filling the aperture with conductors 732a and 732b and capping such conductors with, for example, solder paste 730a and 730b. Filling the aperture with conductors 732a and 732b can be by electroless (electroplating) Cu plating or solder paste plating, etc. The result can be package 700, which is ready to be assembled with another package. As noted, package 700 can be a bottom package.

[0049] Figure 8 Assembly of a passive electrical component (e.g., passive electrical component 835) on package 840 according to an embodiment is shown. Assembly of the passive electrical component on package 840 can be by reflow soldering, chemical bonding, and other techniques that can electrically and / or physically bond or couple such a passive electrical component to the interface side of package 840 and to electrical interconnects within the substrate of package 840 (as noted above, the location of the electrical interconnects within the substrate is merely an example). Package 840 can be in an upside down position to facilitate assembly. Package 840 can be a top package. As shown, package 840 can contain a die, such as a memory die, a stacked memory die. Package 840 can contain a die such as a processor or other circuit or integrated circuit.

[0050] Figure 9 Assembly of package 900, which is to be assembled with package 700 of Figure 7 is shown. Package 900 includes a passive electrical component coupled to Figure 8 the interface side of package 840. Package 900 can be a top package. As shown, package 900 can be in an orientation for insertion into the aperture of package 700.

[0051] Figure 10 Package 900 of Figure 9 and package 700 of Figure 7 assembled into PoP 1000 is shown. In an embodiment, for example, the assembly occurs after electrically or physically coupling package 900 and package 700. The electrical or physical coupling can be by reflow soldering of solder balls 730a and 730b to electrical contacts on the interface side of the substrate of package 900, thereby completing the TMV connection between the packages. Other techniques can be used to electrically or physically couple package 900 and package 700, such as with an adhesive (e.g., epoxy), die attach film, thermal bonding, or ultrasonic welding, etc.

[0052] The voids between the packages of PoP 1000 can be reduced relative to legacy multi-package integrated circuits. For example, PoP 1000 can include TMVs having vertical sidewalls. As discussed herein, TMVs having vertical sidewalls can allow the packages of PoP 1000 to become smaller along one or more axes (in an x, y, z axis coordinate system). In addition, PoP 1000 can include passive components or other components in the clearance above other passive components (or other components) on a package (e.g., a bottom package).

[0053] The electrical or physical coupling of package 900 and package 700 can also include electrical or physical coupling of a component of package 900 to a surface or a component of package 700. For example, Figure 10 The dashed circle 1041 in FIG. 10B illustrates where a component of package 900 can be electrically or physically coupled to a surface of package 700 within an aperture formed in package 700.

[0054] PoP 1000 can be prepared for assembly with another component, such as motherboard 1040. For example, as shown in FIG. 10B, PoP 1000 can include solder balls 1045 to be reflow soldered to motherboard 1040. Figure 10

[0055] Figure 11 A system level diagram is shown in accordance with an embodiment. For example, Figure 11 An example of an electronic device (e.g., a system) including a multi-package integrated circuit, such as a PoP prepared as described in this disclosure, is depicted. The example includes Figure 11 An example is shown to illustrate a higher level device application of a PoP. In one embodiment, system 1100 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook, a personal digital assistant (PDA), a server, a workstation, a cellular phone, a mobile computing device, a smart phone, an Internet appliance, or any other type of computing device. In some embodiments, system 1100 is a system on a chip ("SoC") system.

[0056] ​In one embodiment, the processor 1110 has one or more processing cores 1112 and 1112n, where 1112n represents the nth processor core within processor 1110, where n is a positive integer. For example, processing core 1112 or processing core 1112n can include a die as described herein. In one embodiment, system 1100 includes multiple processors including 1110 and 1105, where processor 1105 has logic similar or identical to that of processor 1110. In an example, processor 1110 can include die 211 or stacked die 212. In some embodiments, processing core 1112 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, etc. In some embodiments, processor 1110 has cache memory 1116 to cache instructions and / or data for system 1100. Cache memory 1116 can be organized into a hierarchy including one or more levels of cache memory.

[0057] In some embodiments, processor 1110 includes a memory controller 1114 operable to perform functions enabling processor 1110 to access and communicate with memory 1130 including volatile memory 1132 and / or non-volatile memory 1134. In some embodiments, processor 1110 is coupled with memory 1130 and chipset 1120. In an example, processor 1130 can include or be part of package 900 or package 700. Processor 1110 can also be coupled to wireless antenna 1178 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, wireless antenna 1178 can include an interface to operate according to, but not limited to, IEEE 802.11 standards and their related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMAX, Long Term Evolution, or any form of wireless communication protocol.

[0058] In some embodiments, volatile memory 1132 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. Non-volatile memory 1134 includes, but is not limited to, flash memory, phase change memory (PCM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), or any other type of non-volatile memory device.

[0059] Memory 1130 stores information and instructions that can be executed by processor 1110. In one implementation, memory 1130 can also store temporary variables or other intermediate information during execution of instructions by processor 1110. In the illustrated embodiment, chipset 1120 is connected to processor 1110 via point-to-point (PtP or P-P) interfaces 1117 and 1122. Chipset 1120 provides a connection between processor 1110 and other components in system 1100. In some embodiments, interfaces 1117 and 1122 operate in accordance with a PtP communication protocol (e.g., Quick Path Interconnect (QPT), etc.). In other embodiments, different interconnects can be used.

[0060] In some embodiments, chipset 1120 is operable to communicate with processor 1110, 1105, display 1140, and other devices 1172, 1176, 1174, 1160, 1162, 1164, 1166, 1177, etc. In an example, chipset 1120 can include die 211 or stacked die 212. Chipset 1120 can also be coupled to wireless antenna 1178 to communicate with any device configured to transmit and / or receive wireless signals.

[0061] Chipset 1120 is connected to display 1140 via interface 1126. Display 1140 can be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments, processor 1110 and chipset 1120 are fused into a single SOC. Furthermore, chipset 1120 is connected to one or more buses 1150 and 1155, which interconnect various elements 1174, 1160, 1162, 1164, and 1166. Buses 1150 and 1155 can be interconnected together via bus bridge 1172. In one embodiment, chipset 1120 is coupled with non-volatile memory 1160, mass storage device 1162, keyboard / mouse 1164, network interface 1166, smart television 1176, consumer electronic device 1177, etc. via interface 1124. In various examples, an integrated circuit can be included in at least one or more of display 1140, smart television 1176, I / O device 1174, non-volatile memory 1160, storage media 1162, network interface 1166, processor 1105, or consumer electronic device 1177.

[0062] In one embodiment, mass storage device 1162 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash drive, or any other form of computer data storage media. In one embodiment, network interface 1166 is implemented by any type of known network interface standard, including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other appropriate type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standards and related series, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMAX, Long Term Evolution, or any form of wireless communication protocol.

[0063] Although Figure 11 The illustrated modules are depicted as separate blocks within system 1100, but the functions performed by some of these blocks can be integrated within a single semiconductor circuit, or can be implemented using two or more separate integrated circuits. For example, although cache 1116 is depicted as a separate block within processor 1110, cache 1116 (or selected aspects of 1116) can be incorporated into processor core 1112.

[0064] Various notes and examples

[0065] Each of these non-limiting examples can stand on its own, or can be combined in various permutations or combinations with one or more of the other examples. To better illustrate the methods and apparatus disclosed herein, a non-limiting list of embodiments is provided.

[0066] Example 1. A method of fabricating a multi-package integrated circuit, comprising: preparing an aperture structure comprising apertures, wherein the apertures are sized to accommodate a passive electrical component; preparing a bottom circuit package comprising a bottom circuit package substrate and comprising a first integrated circuit and the aperture structure in a die-side layer of the bottom circuit package; removing a sacrificial layer from the die-side layer of the bottom circuit package to expose the apertures in the aperture structure; preparing a top circuit package comprising a top circuit package substrate and a second integrated circuit in a die-side layer of the top circuit package substrate; placing or forming a passive electrical component into the apertures; electrically coupling the passive electrical component to an interface side of the top circuit package substrate; and mounting the top circuit package substrate to the bottom circuit package substrate with the passive electrical component in the apertures.

[0067] Example 2. The method of example 1, further comprising electrically coupling the passive electrical component to the interface side of the top circuit package substrate prior to mounting the top circuit package substrate to the bottom circuit package having the passive electrical component in the aperture.

[0068] Example 3. The method of example 2, wherein the passive electrical component is taller than a height of the bottom circuit package.

[0069] Example 4. The method of example 1, wherein the passive electrical component comprises at least one of a resistor, a capacitor, a power component, or a through- mold-via (TMV).

[0070] Example 5. The method of example 4, further comprising forming the TMV in the aperture, and wherein at least one of electrically coupling the TMV to the interface side of the top circuit package substrate or mounting the top circuit package substrate to the bottom circuit package having the passive electrical component in the aperture is performed by reflow soldering.

[0071] Example 6. The method of example 4, further comprising preparing the aperture structure such that a vertical wall of an aperture in the aperture structure is perpendicular to a horizontal floor of the aperture in the aperture structure.

[0072] Example 7. The method of example 4, further comprising preparing the aperture structure such that an aperture in the aperture structure has a stepped wall.

[0073] Example 8. The method of example 4, wherein forming the TMV in the aperture comprises filling the aperture with a conductor, capping the conductor with a solder paste, and wherein the reflow soldering melts the solder paste.

[0074] Example 9. The method of example 1, wherein preparing the aperture structure comprises preparing the aperture structure from a material of the bottom circuit package.

[0075] Example 10. The method of example 8, wherein the material of the bottom circuit package is a polymer-based molding compound.

[0076] Example 11. The method of example 1, wherein removing the sacrificial layer from a die side layer of the bottom circuit package to expose an aperture in the aperture structure comprises removing the sacrificial layer by lapping.

[0077] Example 12. The method of example 1, wherein the aperture is a first aperture, the passive electrical component is a first passive electrical component, and the method further comprises: forming a second aperture in the bottom circuit package by an aperture forming process; and inserting or forming a second passive electrical component in the second aperture.

[0078] Example 13. The method of example 11, wherein the via formation process includes at least one of mechanical drilling, mechanical drilling, or chemical etching.

[0079] Example 14. The method of example 1, wherein mounting the top circuit package substrate to the bottom circuit package substrate utilizes a first ball grid array, and wherein mounting the top circuit package substrate to the bottom circuit package having passive electrical components in the via with the first ball grid array includes: electrically coupling the top circuit package and the bottom circuit package with the first ball grid array, wherein the bottom circuit package includes an interface side of the bottom circuit package substrate; and electrically coupling the interface side of the bottom circuit package substrate to a motherboard with a second ball grid array.

[0080] Example 15. The method of example 13, wherein the second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms between the interface side of the top circuit package substrate and the bottom circuit package.

[0081] Example 16. The method of example 1, wherein the second integrated circuit includes a stacked memory die, and wherein the first integrated circuit includes a computer processor.

[0082] Example 17. A multi-package integrated circuit, comprising a top circuit package and a bottom circuit package, wherein the top circuit package includes a first integrated circuit, a top circuit package substrate, and a passive electrical component electrically coupled to an interface side of the top circuit package substrate, wherein the bottom circuit package includes a second integrated circuit and a via, and wherein the top circuit package and the bottom circuit package are electrically coupled, and wherein the passive electrical component is disposed in or formed in the via.

[0083] Example 18. The multi-package integrated circuit of example 16, wherein the via is a hollow core of a via structure molded into the bottom circuit package.

[0084] Example 19. The multi-package integrated circuit of example 17, wherein the via structure is made of a material of the bottom circuit package.

[0085] Example 20. The multi-package integrated circuit of example 18, wherein the material of the bottom circuit package is a polymer-based molding compound.

[0086] Example 21. A multi-package integrated circuit according to Example 16, wherein the aperture is a first aperture, the passive electrical component is a first passive electrical component, and the multi-package integrated circuit further includes a second aperture in the bottom circuit package and a second passive electrical component in the second aperture.

[0087] Example 22. A multi-package integrated circuit according to Example 16, wherein the passive electrical component is higher than the height of the bottom circuit package.

[0088] Example 23. The multi-package integrated circuit according to Example 16, wherein the passive electrical component includes at least one of a resistor, a capacitor, a power component, or a through-hole (TMV).

[0089] Example 24. A multi-package integrated circuit according to Example 22, wherein the passive electrical component is electrically coupled to the bottom circuit package.

[0090] Example 25. A multi-package integrated circuit according to Example 22, wherein the bottom circuit package includes a bottom circuit package substrate, and wherein the TMV includes a vertical wall perpendicular to the top circuit package substrate and the bottom circuit package substrate.

[0091] Example 26. A multi-package integrated circuit according to Example 16, wherein the top circuit package and the bottom circuit package are electrically coupled via a first ball grid array, and wherein the interface side of the bottom circuit package substrate of the bottom circuit package is mounted to a motherboard via a second ball grid array.

[0092] Example 27. A multi-package integrated circuit according to Example 25, wherein the second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms electrical contacts between the interface side of the top circuit package substrate and the bottom circuit package.

[0093] Example 28. A multi-package integrated circuit according to Example 16, wherein the first integrated circuit includes a stacked memory die, and the second integrated circuit includes a computer processor.

[0094] Example 29. A computer device comprising: a top circuit package, a bottom circuit package, and a motherboard, wherein the top circuit package includes a first integrated circuit, a top circuit package substrate, and a passive electrical component electrically coupled to an interface side of the top circuit package substrate, wherein the bottom circuit package includes a second integrated circuit and an aperture, wherein the top circuit package and the bottom circuit package are electrically coupled via a first ball grid array, wherein the passive electrical component is disposed in or formed in the aperture, and wherein the interface side of the bottom circuit package substrate of the bottom circuit package is mounted to the motherboard via a second ball grid array.

[0095] Example 30. A computer device according to Example 28, wherein the aperture is a hollow core of an aperture structure molded into the bottom circuit package.

[0096] Example 31. A computer device according to Example 29, wherein the aperture structure is made of the material of the bottom circuit encapsulation.

[0097] Example 32. The computer device according to Example 30, wherein the material of the bottom circuit package is a polymer-based molding compound.

[0098] Example 33. A computer device according to Example 28, wherein the aperture is a first aperture, the passive electrical component is a first passive electrical component, and the computer device further includes a second aperture in the bottom circuit package and a second passive electrical component in the second aperture.

[0099] Example 34. A computer device according to Example 28, wherein the passive electrical component is higher than the height of the bottom circuit package.

[0100] Example 35. A multi-package integrated circuit according to Example 28, wherein the passive electrical component includes at least one of a resistor, a capacitor, a power component, or a through-hole via (TMV).

[0101] Example 36. A computer device according to Example 34, wherein the passive electrical component is electrically coupled to the bottom circuit package.

[0102] Example 37. A computer device according to Example 34, wherein the bottom circuit package includes a bottom circuit package substrate, and wherein the TMV includes a vertical wall perpendicular to the top circuit package substrate and the bottom circuit package substrate.

[0103] Example 38. The computer device according to Example 28, wherein the ball grid array is a first ball grid array, and wherein the interface side of the bottom circuit package substrate of the bottom circuit package is mounted to the motherboard via a second ball grid array.

[0104] Example 39. The computer device of example 37, wherein the second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms between the interface side of the top circuit package substrate and the bottom circuit package.

[0105] Example 40. The computer device of example 28, wherein the first integrated circuit comprises a stacked memory die and the second integrated circuit comprises a computer processor.

[0106] Each of these non-limiting examples can stand on its own or can be combined in various permutations or combinations with one or more of the other examples.

[0107] The above DETAILED DESCRIPTION section includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate examples of embodiments. In the drawings, like reference numerals refer to like parts throughout the various drawings. In the drawings:

[0108] To the extent that there is a contradiction between what is herein and what is in any document incorporated by reference, what is herein prevails.

[0109] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In this document, the terms "including" and "comprising" are used as the plain-English equivalents of the respective terms "including," "comprising," and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on the objects to which they refer.

[0110] Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, in an example, the code can be tangibly embodied in one or more volatile or non-volatile, transitory or non-transitory computer-readable media, such as during execution by a processing device. Examples of such computer-readable media can include, but are not limited to, volatile media, non-volatile media, storage media, and / or memory media, including, but not limited to, magnetic storage media, optical storage media, solid-state storage media, and / or hybrid storage media that utilize two or more of the above technologies in combination. Specific examples of volatile media can include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and / or the like, and specific examples of non-volatile media can include, but are not limited to, read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, compact disc read only memory (CD-ROM), digital video disc read only memory (DVD-ROM), blu-ray disc read only memory (BD-ROM), and / or the like.

[0111] The above specification is intended to be illustrative, and not restrictive. For example, the examples described above (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used in addition to, or in place of, the examples described above. While the abstract is filed to comply with 37 C.F.R. § 1.72(b) to allow the reader to quickly ascertain the nature of the technical disclosure, it is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This should not be interpreted as implying that the claimed subject matter requires more features than are expressly identified in the claims. Rather, the subject matter described herein below extends to various combinations or permutations of the features described herein. In addition, the description above is intended by way of example only and is not intended to limit the scope of the application in any way. Examples, as described herein, can include electronic components, input / output circuitry, and various forms of memory in the examples provided. However, one of ordinary skill in the art will recognize that the examples described herein can be implemented with a variety of components and circuitry and that the chosen components need not necessarily be in the physical order described, but can be in other orders.

Claims

1. A method of fabricating a multi-package integrated circuit, comprising: preparing a void structure comprising a void, wherein a size of the void is set to accommodate a passive electrical component; preparing a bottom circuit package comprising a bottom circuit package substrate and comprising a first integrated circuit in a die-side layer of the bottom circuit package and the void structure; thinning from the die-side layer of the bottom circuit package to expose the void in the void structure; preparing a top circuit package comprising a top circuit package substrate and a second integrated circuit in a die-side layer of the top circuit package substrate; placing or forming the passive electrical component into the void; electrically coupling the passive electrical component to an interface side of the top circuit package substrate opposite the die-side layer of the top circuit package substrate; and mounting the top circuit package substrate to the bottom circuit package substrate with the passive electrical component in the void; wherein the void is a hollow core of a void structure molded into the bottom circuit package, and wherein the void structure is made of a material of the bottom circuit package.

2. The method of claim 1, further comprising: electrically coupling the passive electrical component to the interface side of the top circuit package substrate is performed prior to mounting the top circuit package substrate to the bottom circuit package substrate with the passive electrical component in the void.

3. The method of claim 1, further comprising preparing the void structure to have vertical walls of the void in the void structure perpendicular to a horizontal floor of the void in the void structure.

4. The method of claim 1, wherein, thinning from the die-side layer of the bottom circuit package to expose the void in the void structure comprises thinning by lapping.

5. The method of any one of claims 1 to 4, wherein, the passive electrical component comprises at least one of a resistor, a capacitor, a power component, or a through mold via (TMV).

6. The method of claim 5, further comprising forming the TMV in the void, and wherein, at least one of electrically coupling the TMV to the interface side of the top circuit package substrate or mounting the top circuit package substrate to the bottom circuit package substrate with the passive electrical component in the void is performed by reflow soldering.

7. The method of claim 6, wherein, forming the TMV in the void comprises filling the void with a conductor, capping the conductor with a solder paste, and wherein reflow soldering melts the solder paste.

8. The method of any one of claims 1 to 4, wherein, the void is a first void, the passive electrical component is a first passive electrical component, and the method further comprises forming a second void in the bottom circuit package by a void formation process and inserting or forming a second passive electrical component in the second void.

9. The method of claim 8, wherein, the void formation process comprises at least one of mechanical drilling, laser drilling, or chemical etching.

10. The method of any one of claims 1 to 4, wherein, mounting the top circuit package substrate to the bottom circuit package substrate utilizes a first ball grid array, and wherein mounting the top circuit package substrate to the bottom circuit package having the passive electrical component in the aperture utilizing the first ball grid array comprises: electrically coupling the top circuit package and the bottom circuit package utilizing the first ball grid array, wherein the bottom circuit package includes an interface side of the bottom circuit package substrate opposite the die side of the bottom circuit package substrate; and electrically coupling the interface side of the bottom circuit package substrate to a motherboard utilizing a second ball grid array.

11. The method of claim 10, wherein, The second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms between the interface side of the top circuit package substrate and the bottom circuit package.

12. A multi-package integrated circuit comprising a top circuit package and a bottom circuit package, wherein, The top circuit package includes a first integrated circuit, a top circuit package substrate, and a passive electrical component electrically coupled to a side of the top circuit package substrate opposite the first integrated circuit, wherein the bottom circuit package includes a bottom circuit package substrate, a second integrated circuit on the bottom circuit package substrate, and an aperture, and wherein the top circuit package and the bottom circuit package are electrically coupled, and wherein the passive electrical component is disposed in or formed in the aperture, wherein the aperture is a hollow core of an aperture structure molded into the bottom circuit package, and wherein the aperture structure is made of a material of the bottom circuit package.

13. The multi-package integrated circuit of claim 12, wherein, The aperture is a hollow core of an aperture structure molded into the bottom circuit package, and wherein the aperture structure is made of a material of the bottom circuit package.

14. The multi-package integrated circuit of claim 12, wherein, The passive electrical component is electrically coupled to the bottom circuit package.

15. The multi-package integrated circuit of any of claims 12 to 14, wherein, The passive electrical component includes at least one of a resistor, a capacitor, a power component, or a through mold via (TMV).

16. The multi-package integrated circuit of claim 15, wherein, The bottom circuit package includes a bottom circuit package substrate, and wherein the TMV includes a vertical wall perpendicular to the top circuit package substrate and the bottom circuit package substrate.

17. The multi-package integrated circuit of any one of claims 12-14, wherein, The aperture is a first aperture, the passive electrical component is a first passive electrical component, and the multi-package integrated circuit further includes a second aperture in the bottom circuit package and a second passive electrical component in the second aperture.

18. The multi-package integrated circuit of any one of claims 12-14, wherein, The top circuit package and the bottom circuit package are electrically coupled by a first ball grid array, and wherein a side of a bottom circuit package substrate of the bottom circuit package opposite the second integrated circuit is mounted to a motherboard by a second ball grid array.

19. A computer apparatus comprising: A top circuit package, a bottom circuit package, and a motherboard, wherein the top circuit package includes a first integrated circuit, a top circuit package substrate, and a passive electrical component electrically coupled to a side of the top circuit package substrate opposite the first integrated circuit, wherein the bottom circuit package includes a bottom circuit package substrate, a second integrated circuit on the bottom circuit package substrate, and an aperture, wherein the top circuit package and the bottom circuit package are electrically coupled by a first ball grid array, wherein the passive electrical component is disposed in or formed in the aperture, and wherein a side of the bottom circuit package substrate opposite the second integrated circuit is mounted to the motherboard by a second ball grid array, wherein the aperture is a hollow core of an aperture structure molded into the bottom circuit package, and wherein the aperture structure is made of a material of the bottom circuit package.

20. The computer arrangement according to claim 19, wherein, The second ball grid array forms more electrical contacts between the side of the bottom circuit package substrate and the motherboard than the first ball grid array forms between the side of the top circuit package substrate and the bottom circuit package.

21. The computer apparatus according to claim 19 or claim 20, wherein, The passive electrical component includes at least one of a resistor, a capacitor, a power component, or a through mold via (TMV).

22. The computer device of claim 21, wherein, The passive electrical component is electrically coupled to the bottom circuit package.

23. The computer device of claim 21, wherein, The bottom circuit package includes a bottom circuit package substrate, and wherein the TMV includes a vertical wall perpendicular to the top circuit package substrate and the bottom circuit package substrate. The passive electrical component is electrically coupled to the bottom circuit package. The bottom circuit package includes a bottom circuit package substrate, and wherein the TMV includes a vertical wall perpendicular to the top circuit package substrate and the bottom circuit package substrate.

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