Floating-point to fixed-point conversion

Abstract

The instructions, their operation, and embodiments of support for execution of the instructions are described. In some embodiments, the processor includes decoding circuitry for decoding an instruction having a field for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry for executing the decoded instructions to convert a single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as a 32-bit integer and a 32-bit integer exponent at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

Description

Background Technology

[0001] There are many different ways to represent numbers in a computer processor. For example, integers can be represented as integer values. Decimals and other non-integer values ​​can be represented as fixed-point numbers, where multiple bits are used for the integer component and multiple bits are used for the fractional part (e.g., INTEGER.FRACTION). Another way to represent decimals is to use floating-point numbers, which include bits for the sign, the string of numbers (mantissa, decimal, or significant digits)—the length of which determines the precision of the number—and an exponent indicating the position of the decimal point. Attached Figure Description

[0002] The invention is illustrated by way of example, not limitation, in the accompanying drawings, wherein similar reference numerals indicate similar elements, and in the drawings:

[0003] Figure 1 An example of a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand is shown;

[0004] Figure 2 An embodiment of a method for processing floating-point to fixed-point conversion instructions executed by a processor is shown;

[0005] Figures 3(A)-(B) show a more detailed description of the method for executing the conversion of an unsigned word from a fixed-point instruction to a floating-point instruction;

[0006] Figure 4 An embodiment of hardware for processing instructions such as those detailed herein is shown;

[0007] Figure 5A An exemplary instruction format is shown;

[0008] Figure 5B Showing from Figure 5A Which fields constitute the complete opcode field and the basic operation field?

[0009] Figure 5C Showing from Figure 5A Which fields constitute the register index fields;

[0010] Figure 6 This is a block diagram of a register architecture according to an embodiment of the present invention;

[0011] Figure 7A This is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming, out-of-order release / execution pipeline according to embodiments of the present invention;

[0012] Figure 7BThis is a block diagram illustrating an exemplary embodiment of an ordered architecture core to be included in a processor according to an embodiment of the present invention, and an exemplary register renaming, out-of-order release / execution architecture core;

[0013] Figure 8A -B shows a more specific block diagram of an exemplary ordered core architecture, which will be one of several logic blocks in the chip (including other cores of the same type and / or different types); Figure 9 This is a block diagram of a processor according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0014] Figure 10-13 It is a block diagram of an exemplary computer architecture;

[0015] Figure 14 This is a block diagram illustrating the use of a software instruction converter according to an embodiment of the invention to convert binary instructions in a source instruction set into binary instructions in a target instruction set; and

[0016] Figure 15 This is an example of pseudocode representing the operation of the described instructions. Detailed Implementation

[0017] In the following description, many specific details are set forth. However, it should be understood that the invention can be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0018] References to "an embodiment," "an example embodiment," "an exemplary embodiment," etc., in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include this specific feature, structure, or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, it is assumed that the influence of other embodiments on such feature, structure, or characteristic is within the knowledge of those skilled in the art, whether explicitly described or not.

[0019] Sometimes, it is beneficial to move from one data type (e.g., fixed-point) to another (e.g., floating-point). This article details instructions for converting a single-precision floating-point value from a packed data operand (e.g., a Single Instruction Multiple Data (SIMD) or vector register) to a fixed-point value and storing that value in the packed data operand. Depending on the implementation, the instructions detailed herein may use packed data register operands of different sizes (e.g., 128-bit, 256-bit, 512-bit registers, etc.) and / or at least use memory locations as the source of the instructions. This instruction is an improvement to the computer itself because it provides support for the conversion of specific data elements that were not previously performed. Specifically, the execution of the floating-point to fixed-point conversion instruction causes: the single-precision floating-point data element at the least significant packed data element location of the identified packed data source operand to be converted to a fixed-point representation; the fixed-point representation to be stored as a 32-bit integer and a 32-bit integer exponent at the two least significant packed data element locations of the identified packed data destination operand; and all remaining packed data elements of the identified packed data destination operand to be zeroed.

[0020] Figure 1 An example of a selected portion of the execution of a fixed-point to floating-point conversion instruction with a source operand (register or memory) and a destination operand is shown. The instruction format includes fields for the opcode (“VCTFSS2D” is the opcode mnemonic in this illustration), the packet data source operand identifier (displayed as “SOURCE / MEM”), and the packet data destination operand identifier (displayed as “Destination”).

[0021] The packaged data source operand field indicates the register location or memory location of the packaged data, where a single-precision floating-point value of the packaged data will be converted from floating-point to fixed-point (two 32-bit values).

[0022] The destination operand field of the packaged data indicates the register location of the packaged data, where the result of the transformation (fixed-point value) will be stored.

[0023] In the example shown, the identified source operand 101 has multiple single-precision floating-point elements. The single-precision floating-point element in the least significant position is single-precision floating-point element 0, and the single-precision floating-point element in the most significant position is single-precision floating-point element N. The number of single-precision floating-point elements depends on the size of the identified source operand 101 (e.g., 128-bit, 256-bit, 512-bit, etc.).

[0024] The execution circuit 111 obtains a single-precision floating-point value from the least significant packed data element position of the identified source operand 101 and converts this value into a fixed-point value. The fixed-point value includes a 32-bit integer component and a 32-bit exponent component. A more detailed execution process will be described later.

[0025] Then, in the identified destination operand 121, the fixed-point value is stored in the consecutive least significant data element positions, and all other data element positions are set to 0. Although the integer components are shown to be stored in the least significant positions, in some embodiments, the order is reversed when the exponent is stored in the least significant position.

[0026] Figure 2 An embodiment of a method for processing floating-point to fixed-point conversion instructions executed by a processor is shown.

[0027] At position 201, retrieve the instruction. For example, retrieve the floating-point to fixed-point conversion instruction. The floating-point to fixed-point conversion instruction includes fields for the opcode, the packaged data source operand identifier, and the packaged data destination operand identifier. In some embodiments, the instruction is retrieved from an instruction cache.

[0028] The acquired instruction is decoded at position 203. For example, the acquired floating-point to fixed-point conversion instruction is decoded by a decoding circuit such as the one detailed herein.

[0029] At position 205, retrieve the data value associated with the identified source operand of the decoded instruction and schedule the decoded instruction (as needed). For example, when the identified source operand is a memory operand, retrieve the data from the indicated memory location.

[0030] At position 207, the decoded instruction is executed by execution circuitry (hardware), as detailed herein. For a floating-point to fixed-point conversion instruction, execution causes the execution circuitry to convert the single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as a 32-bit integer and a 32-bit integer exponent at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

[0031] In some embodiments, a submit or retire instruction is given at 209.

[0032] Figures 3(A)-(B) illustrate a more detailed description of the method for executing the conversion of an unsigned word from fixed-point to floating-point instructions. Typically, this is performed by execution circuitry such as those detailed above. In some embodiments, the circuitry executes the method as a state machine.

[0033] At 301, the floating-point value is decomposed into sign, exponent and fractional components. For example, sign←SRC1

[31] , exponent[7:0]←SRC1[30:23], fractional[22:0]←SRC1[22:0].

[0034] At position 303, it is determined whether the exponent component is 0. For example, exponent[7:0] == 8'b00000000? When the exponent component is 0, the fixed-point integer and exponent component are set to zero at position 305. For example, integer32Val[31:0] ← 32'h00000000 and intExponent[31:0] ← 32'h00000000.

[0035] When the exponential component is not 0, determine whether all exponential components are 1 at position 307.

[0036] When all exponent components are 1, the determination of whether the most significant bit of the fractional component is 0 is performed at position 309.

[0037] When the most significant bit of the fractional component is 0, the sign is determined at position 311. When the sign is 0, the fixed-point integer component is set to the value corresponding to hexadecimal 7fffffff at position 313, and the exponent component is set to the value corresponding to hexadecimal 7fffffff. For example, integer32Val[31:0]←32'h7fff_ffff and intExponent[31:0]←32'h7fff_ffff.

[0038] When the sign is not 0, the fixed-point integer component at position 315 is set to the value corresponding to hexadecimal 8000000, and the exponent component is set to the value corresponding to hexadecimal 7fffffff. For example, integer32Val[31:0]←32'h800_0000 and intExponent[31:0]←32'h7fff_ffff.

[0039] When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to the value corresponding to h0000000 at position 317, and the exponent component is set to the value corresponding to h7fffffff. For example, integer32Val[31:0]←32'h000_0000 and intExponent[31:0]←32'h7fff_ffff.

[0040] When the exponent component is not all ones or zeros, b000000001 is concatenated with the fractional component at position 319 to generate the absolute value of the integer. For example, absInteger32Val[31:0]←{8'b0,1'b1,fractional[22:0]}. This preserves 24 bits of precision.

[0041] At position 321, it is determined whether the sign is 0. In other words, the sign is applied.

[0042] When the sign is 0, the integer component at position 323 is set to the absolute value of the integer. For example, integer32Val[31:0] ← absInteger32Val[31:0];

[0043] When the sign is not 0, the integer component at position 325 is set to the complement of the absolute value of the integer plus 1. For example, integer32Val[31:0] ← ~ absInteger32Val[31:0] + 1'b1. In some embodiments, the user is allowed to determine the precision loss.

[0044] At 327, a temporary value is generated by concatenating b0 with the exponent added to b101101010 (e.g., temp[8:0] = {1'b0,exponent[7:0]} + 9'b1_0110_1010).

[0045] At 329, the exponential component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value (e.g., intExponent[31:0] ← {23{temp[8]}, temp[8:0]}).

[0046] At position 331, the generated integer and exponential components are stored (and the remaining data elements are set to zero).

[0047] Figure 4 An embodiment of hardware for processing instructions such as those detailed herein is shown. As shown, storage device 403 stores VCVTFSS2D instructions 401 to be executed.

[0048] Instruction 401 is received by decoding circuitry 405. For example, decoding circuitry 405 receives the instruction from acquisition logic / circuit. The instruction includes fields for opcode, source identifier, and destination identifier. In some embodiments, the source and destination are registers, and in other embodiments, one or both are memory locations.

[0049] A more detailed embodiment of at least one instruction format will be described later. Decoding circuitry 405 decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry 409). Decoding circuitry 405 also decodes instruction prefixes.

[0050] In some embodiments, register renaming, register allocation, and / or scheduling circuitry 407 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some embodiments), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool for execution on execution circuitry (e.g., using a reserved station in some embodiments).

[0051] Registers (register file) and / or memory 408 store data as operands for instructions to be operated on by execution circuitry 409. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0052] The execution circuit 409 executes the decoded instruction. The execution of the decoded instruction causes the execution circuit to convert the data element at the least significant packed data element position of the identified packed data source operand from floating-point representation to fixed-point representation, store the fixed-point representation at the consecutive least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

[0053] In some embodiments, the write-back / write-back circuit 411 architecturally commits the destination register to register or memory 408 and writes back the instruction.

[0054] Figure 15 This is an example of pseudocode representing the operation of the described instructions.

[0055] An example of the format used for floating-point to fixed-point conversion instructions is VCVTFSS2D DST, SRC / MEM. VCVTFSS2D is the opcode of the instruction. The exemplary opcode mnemonic has been detailed above. DST is the field that identifies the destination operand. SRC1 is the field used for source operand identifiers, such as register and / or memory locations. In some embodiments, the operand field is encoded using the VVVV field 520, MOD R / M 540, and / or SIB 550.

[0056] In one embodiment, the instruction encoding includes a scale-index-base (SIB) type memory addressing operand that indirectly identifies multiple indexed destination locations (e.g., field 550) in memory. In one embodiment, the SIB type memory operand may include encoding that identifies a base address register. The contents of the base address register may represent a base address in memory from which the address of a specific destination location in memory is calculated. For example, the base address may be the address of a first location in a block of potential destination locations used for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding that identifies an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the block of potential destination locations from the base address. In one embodiment, the SIB type memory operand may include encoding that specifies a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor value of four is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to calculate the destination address.

[0057] In one embodiment, a SIB type memory operand of the form vm32{x,y,z} can identify a vector array of memory operands specified using SIB type memory addressing. In this example, an array of memory addresses is specified using a common base address register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, a SIB type memory operand of the form vm64{x,y,z} can identify a vector array of memory operands specified using SIB type memory addressing. In this example, an array of memory addresses is specified using a common base address register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit (e.g., XMM) register (vm64x), a 256-bit (e.g., YMM) register (vm64y), or a 512-bit (e.g., ZMM) register (vm64z).

[0058] The following details exemplary instruction formats, architectures, and systems that can be used with the instructions detailed above. For example, exemplary pipelines supporting the instructions are detailed, which include circuitry for executing the methods detailed herein.

[0059] An instruction set comprises one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify the operation (opcode) to be performed and the operands (on which the operation is performed) in other things. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, an instruction template for a given instruction format may be defined with different subsets of the fields of the instruction format (the included fields typically follow the same order, but at least some have different bit positions because fewer fields are included) and / or defined with given fields that are interpreted differently. Thus, each instruction in an ISA is represented using a given instruction format (and, if defined, one of the given instruction templates for that instruction format) and includes fields for specifying the operation and operands. For example, the exemplary ADD instruction has a specific opcode and instruction format, which includes an opcode field for specifying which opcode and an operand field (source 1 / destination and source 2) for selecting operands; and the occurrence of this ADD instruction in the instruction stream will have specific content in the operand field for selecting specific operands.

[0060] Exemplary instruction format

[0061] The embodiments of the instructions described herein can be implemented in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions can be executed in such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0062] Instruction format

[0063] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 58 bits. The use of the VEX prefix provides three-operand (or more operand) syntax. For example, the first two operand instructions perform operations such as A = A + B, which overwrites the source operand. The use of the VEX prefix allows operands to perform non-destructive operations such as A = B + C.

[0064] Figure 5A An exemplary AVX instruction format is shown, which includes a VEX prefix 502, a true opcode field 530, a Mod R / M byte 540, a SIB byte 550, a displacement field 562, and an IMM 8572. Figure 5B Shown from Figure 5A Which fields make up the complete opcode field 574 and the basic opcode field 541? Figure 5C Shown from Figure 5A Which fields make up register index field 544?

[0065] The VEX prefix (bytes 0-2) 502 is encoded in three-byte form. The first byte is the format field 590 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (the unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include several bit fields that provide specific capabilities. Specifically, the REX field 505 (VEX byte 1, bits [7-5]) consists of the following: the VEX.R bit field (VEX byte 1, bits [7] - R), the VEX.X bit field (VEX byte 1, bits [6] - X), and the VEX.B bit field (VEX byte 1, bits [5] - B). Other fields of the instruction are encoded as the lower three bits of the register index (rrr, xxx, and bbb) as known in the art, such that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode mapping field 515 (VEX byte 1, bits [4:0] - mmmmmm) includes the contents used to encode the implied leading opcode byte. The W field 564 (VEX byte 2, bits [7] - W) is represented by the symbol VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 520 (VEX byte 2, bits [6:3] - vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. If the VEX.L 568 size field (VEX byte 2, bits [2]-L) = 0, it indicates a 58-byte vector; if VEX.L = 1, it indicates a 256-byte vector. The prefix encoding field 525 (VEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field 541.

[0066] The true opcode field 530 (byte 3) is also known as the opcode byte. The opcode portion is specified in this field.

[0067] The MOD R / M field 540 (byte 4) includes the MOD field 542 (bits [7-6]), the Reg field 544 (bits [5-3]), and the R / M field 546 (bits [2-0]). The role of the Reg field 544 may include: encoding the destination register operand or the source register operand (Rrrr of Rrrr), or being treated as an opcode extension and not used to encode any instruction operand. The role of the R / M field 546 may include: encoding the instruction operand that references a memory address, or encoding the destination register operand or the source register operand.

[0068] Scaling, Indexing, Base Address (SIB) — The contents of scaling field 550 (byte 5) include SS552 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 554 (bits [5-3]) and SIB.bbb 556 (bits [2-0]) have been previously mentioned regarding register indices Xxxx and Bbbb.

[0069] Displacement field 562 and immediate number field (IMM8) 572 contain data.

[0070] Exemplary Register Architecture

[0071] Figure 6 This is a block diagram of a register architecture 600 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 610, each 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower 256 bits of the bottom nine zmm registers are overwritten on registers ymm0-15. The lower 128 bits of the bottom nine zmm registers (the lower 128 bits of the ymm registers) are overwritten on registers xmm0-15.

[0072] General Purpose Register 625 - In the illustrated embodiment, there are sixteen 64-bit general purpose registers used together with the existing x86 addressing modes for addressing memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0073] The scalar floating-point stack register file (x87 stack) 645, on which the MMX packed integer flat register file 650 is aliased - in the illustrated embodiment, the x87 stack is an octal stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; while the MMX register is used to perform operations on 64-bit packed integer data, and also to hold operands for some operations performed between the MMX and XMM registers.

[0074] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0075] Exemplary core architectures, processors, and computer architectures

[0076] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; and 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) CPUs comprising one or more general-purpose ordered cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) coprocessors comprising one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which may include: 1) coprocessors on a separate chip from the CPU; 2) coprocessors on a separate die in the same package as the CPU; 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) on-chip systems that may include the described CPU (sometimes referred to as application cores or application processors), the coprocessors described above, and additional functionality on the same die. The exemplary core architecture is described next, followed by descriptions of exemplary processors and computer architectures. The details in this document include the circuitry (units) of the exemplary core, processor, etc.

[0077] Exemplary nuclear architecture

[0078] Ordered and disordered kernel diagrams

[0079] Figure 7A It is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming, out-of-order release / run pipeline according to embodiments of the present invention. Figure 7B It is a block diagram illustrating exemplary embodiments of ordered architecture cores to be included in a processor according to embodiments of the present invention, and exemplary register renaming, out-of-order release / running architecture cores. Figure 7A The solid boxes in -B represent ordered pipelines and ordered cores, while the optional dashed boxes represent register renaming, out-of-order release / run pipelines, and cores. Given that the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0080] exist Figure 7AIn this process, the processor pipeline 700 includes a fetch stage 702, a length decoding stage 704, a decoding stage 706, an allocation stage 708, a renaming stage 710, a scheduling (also known as dispatch or issue) stage 712, a register read / memory read stage 714, a run stage 716, a write-back / memory write stage 718, an exception handling stage 722, and a commit stage 724.

[0081] Figure 7B A processor core 790 is shown, which includes a front-end unit 730 coupled to a runtime engine unit 750, and both are coupled to a memory unit 770. Core 790 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. As another option, core 790 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0082] Front-end unit 730 includes a branch prediction unit 732 coupled to instruction cache unit 734, which is coupled to instruction translation lookaside buffer (TLB) 736, which is coupled to instruction fetch unit 738, which is coupled to decode unit 740. Decoding unit 740 (or decoder) decodes instructions and generates outputs of one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals, which are decoded from, or otherwise reflected in, or derived from the original instruction. Decoding unit 740 can be implemented using various mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 790 includes a microcode ROM or another medium (e.g., in decoder 740 or otherwise within front-end unit 730) storing microcode for certain macro instructions. The decoding unit 740 is coupled to the rename / assigner unit 752 in the running engine unit 750.

[0083] The execution engine unit 750 includes a rename / allocator unit 752 coupled to a set of retirement units 754 and one or more scheduler units 756. Scheduler units 756 represent any number of different schedulers, including reservation stations, central instruction windows, etc. Scheduler units 756 are coupled to physical register file units 758. Each of the physical register file units 758 represents one or more physical register files, which store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer to the address of the next instruction to be executed), etc. In one embodiment, physical register file unit 758 includes vector register units and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. Physical register file unit 758 is overlapped by retirement unit 754 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and retirement register file; using a future heap, history buffer, and retirement register file; using register mapping and register pools; etc.). Retirement unit 754 and physical register file unit 758 are coupled to run cluster 760. Run cluster 760 includes a set of one or more run units 762 and a set of one or more memory access units 764. Run units 762 can perform various operations (e.g., shift, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integers, packed floating-point, vector integers, vector floating-point). While some embodiments may include multiple run units dedicated to a particular function or set of functions, other embodiments may include multiple run units that all perform all functions or only one run unit. Scheduler unit 756, physical register file unit 758, and run cluster 760 are shown as possibly multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having its own scheduler unit, physical register file unit, and / or run cluster—and in the case of separate memory access pipelines, some embodiments in which only the run cluster of this pipeline has memory access unit 764 are implemented). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order deployments / runs, and the remainder are ordered.

[0084] A set of memory access units 764 is coupled to memory unit 770, which includes a data TLB unit 772 coupled to a data cache unit 774, which is coupled to a Level 2 (L2) cache unit 776. In one exemplary embodiment, memory access unit 764 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 772 in memory unit 770. Instruction cache unit 734 is further coupled to the Level 2 (L2) cache unit 776 in memory unit 770. The L2 cache unit 776 is coupled to one or more other levels of cache and ultimately to main memory.

[0085] By way of example, the exemplary register renaming, out-of-order release / running kernel architecture can implement the following pipeline 700: 1) Instruction fetch 738 executes fetch and length decoding stages 702 and 704; 2) Decoding unit 740 executes decoding stage 706; 3) Rename / allocator unit 752 executes allocation stage 708 and rename stage 710; 4) Scheduler unit 756 executes scheduling stage 712; 5) Physical register file unit 758 and memory unit 770 execute register read / memory read stage 714; running cluster 760 executes running stage 716; 6) Memory unit 770 and physical register file unit 758 execute write-back / memory write stage 718; 7) Various units may be involved in exception handling stage 722; and 8) Retirement unit 754 and physical register file unit 758 execute commit stage 724.

[0086] Core 790 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set of ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, core 790 includes logic for supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thus allowing operations used by many multimedia applications to be performed using packaged data.

[0087] It should be understood that a core can support multithreading (running two or more parallel sets of operations or threads), and can do so in a variety of ways, including time-segmented multithreading, simultaneous multithreading (in the case of a single physical core providing a logical core for each thread, that physical core is performing simultaneous multithreading), or combinations thereof (e.g., such as in...). (Time-segmented fetching and decoding in hyper-threading technology and subsequent simultaneous multithreading).

[0088] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in ordered architectures. While the illustrated embodiment of the processor also includes separate instruction and data cache units 734 / 774 and a shared L2 cache unit 776, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0089] Specific exemplary ordered nuclear architecture

[0090] Figure 8A -B illustrates a block diagram of a more specific, exemplary, ordered core architecture where the core is one of several logic blocks in a chip (including other cores of the same type and / or different types). The logic blocks communicate via a high-bandwidth interconnect network (e.g., a ring network) depending on the application, consisting of some fixed functional logic, memory I / O interfaces, and another necessary I / O logic.

[0091] Figure 8A This is a block diagram of a single processor core according to an embodiment of the invention, along with its connections to an on-die interconnect network 802 and its local subset of a Level 2 (L2) cache 804. In one embodiment, the instruction decoder 800 supports the x86 instruction set with packed data instruction set extensions. The L1 cache 806 allows low-latency access to cache memory into scalar and vector units. While in one embodiment (for design simplification), scalar unit 808 and vector unit 810 use separate register sets (correspondingly, scalar register 812 and vector register 814), and data transferred between them is written to memory and then read back from the L1 cache 806, alternative embodiments of the invention may use different means (e.g., using a single register set or including a communication path that allows data to be transferred between the two register sets without being written and read back).

[0092] The local subsets of L2 cache 804 are part of the global L2 cache, which is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of L2 cache 804. Data read by a processor core is stored in its L2 cache subset 804 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 804 and is dumped and cleared from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logical blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide per direction.

[0093] Figure 8B This is according to an embodiment of the present invention. Figure 8A An expanded view of a portion of the processor cores. Figure 8B This includes the L1 data cache 806A portion of the L1 cache 804, and further details regarding the vector unit 810 and vector register 814. Specifically, the vector unit 810 is a 9-wide vector processing unit (VPU) (see 16-wide ALU 828) that runs one or more integer, single-precision float, and double-precision float instructions. The VPU supports scrambling register inputs at memory inputs via scrambling unit 820, performing value conversions via value conversion units 822A-B, and performing copying via copy unit 824.

[0094] Processor with integrated memory controller and graphics

[0095] Figure 9 This is a block diagram of a processor 900 according to an embodiment of the present invention, which may have more than one core, an integrated memory controller, and an integrated graphics. Figure 9 The solid box in the diagram shows a processor 900 with a single core 902A, a system agent 910, and a collection of one or more bus controller units 916, while the dashed box shows an alternative processor 900 with multiple cores 902A-N, a collection of one or more integrated memory controller units 914 among the system agent units 910, and dedicated logic 908.

[0096] Therefore, different implementations of processor 900 may include: 1) a CPU with dedicated logic 908 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and cores 902A-N that are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or combinations of said two cores); 2) a coprocessor with cores 902A-N that are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor with cores 902A-N that are a large number of general-purpose ordered cores. Thus, processor 900 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput multi-core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor may be implemented on one or more chips. Using any of a number of processing technologies (e.g., BiCMOS, CMOS, or NMOS), processor 900 may be implemented on one or more substrates and / or portions thereof.

[0097] The memory hierarchy includes one or more levels of cache within cores 904A-N, a collection or one or more of shared cache units 906, and external memory (not shown) coupled to a collection of integrated memory controller units 914. The collection of shared cache units 906 may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, Last Level Cache (LLC), and / or combinations thereof. While in one embodiment, ring-based interconnect units 912 interconnect integrated graphics logic 908, the collection of shared cache units 906, and system proxy units 910 / integrated memory controller units 914, alternative embodiments may use any number of known techniques for interconnecting such units. In one embodiment, consistency between one or more cache units 906 and cores 902A-N is maintained.

[0098] In some embodiments, one or more cores of core 902A-N have multi-threading capabilities. System agent 910 includes those components that coordinate and operate core 902A-N. System agent unit 910 may include, for example, a power control unit (PCU) and a display unit. PCU may be or include the logic and components required to regulate the power state of integrated graphics logic 908 and core 902A-N. The display unit is used to drive one or more externally connected displays.

[0099] The 902A-N core can be homogeneous or heterogeneous in terms of its architecture instruction set; that is, two or more cores of the 902A-N core can be capable of running the same instruction set, while other cores can be capable of running different instruction sets or only a subset of those instruction sets.

[0100] Exemplary computer architecture

[0101] Figure 10-13 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the fields of laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, systems or electronic devices capable of incorporating a wide variety of processors and / or other operating logic as disclosed herein are generally suitable.

[0102] Now refer to Figure 10 The diagram illustrates a system 1000 according to an embodiment of the present invention. System 1000 may include one or more processors 1010, 1015 coupled to a controller hub 1020. In one embodiment, the controller hub 1020 includes a graphics memory controller hub (GMCH) 1090 and an input / output hub (IOH) 1050 (which may be on a separate chip); the GMCH 1090 includes a memory 1040 and a coprocessor 1045 coupled to the memory and graphics controller; the IOH 1050 couples an input / output (I / O) device 1060 to the GMCH 1090. Alternatively, one or both of the memory and the graphics controller may be integrated within a processor (as described herein), with the memory 1040 and the coprocessor 1045 directly coupled to the processor 1010 and the controller hub 1020 on a single chip with the IOH 1050.

[0103] The optional nature of the additional processor 1015 is in Figure 10 The term "disconnected line" is used to refer to the processor. Each processor 1010, 1015 may include one or more of the processing cores described herein, and may be a version of processor 900.

[0104] The memory 1040 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of the two memories. In at least one embodiment, the controller hub 1020 communicates with the processors 1010, 1015 via a multipoint bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 1095.

[0105] In one embodiment, the coprocessor 1045 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 1020 may include an integrated graphics accelerator.

[0106] There are several differences in the spectrum of physical resources 1010 and 10155 regarding specifications including architecture, microarchitecture, thermal, power consumption characteristics, and similar metrics.

[0107] In one embodiment, processor 1010 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 1010 recognizes these coprocessor instructions as the type to be executed by an attached coprocessor 1045. Therefore, processor 1010 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1045 on a coprocessor bus or other interconnect. Coprocessor 1045 accepts and executes the received coprocessor instructions.

[0108] Now refer to Figure 11 The diagram shown is a block diagram of a first more specific exemplary system 1100 according to an embodiment of the present invention. Figure 11 The multiprocessor system 1100 shown is a point-to-point interconnect system and includes a first processor 1170 and a second processor 1180 coupled via point-to-point interconnect 1150. Each of processors 1170 and 1180 may be a version of processor 900. In one embodiment of the invention, processors 1170 and 1180 are respectively processors 1010 and 1015, and coprocessor 1138 is coprocessor 1045. In another embodiment, processors 1170 and 1180 are respectively processor 1010 and coprocessor 1045.

[0109] Processors 1170 and 1180 are shown, each including an integrated memory controller (IMC) unit 1172 and 1182 respectively. Processor 1170 also includes point-to-point (PP) interfaces 1176 and 1178 as part of its bus controller unit; similarly, the second processor 1180 includes PP interfaces 1186 and 1188. Using the PP interface circuits 1178 and 1188, processors 1170 and 1180 can exchange information via point-to-point (PP) interface 1150. Figure 11 As shown, IMC 1172 and 1182 couple the processor to the corresponding memory (i.e., memory 1132 and memory 1134), which may be a portion of the main memory locally attached to the corresponding processor.

[0110] Using point-to-point interface circuits 1176, 1194, 1186, and 1198, processors 1170 and 1180 can each exchange information with chipset 1190 via their respective PP interfaces 1152 and 1154. Chipset 1190 can optionally exchange information with coprocessor 1138 via high-performance interface 1192. In one embodiment, coprocessor 1138 is a dedicated processor, such as, for example, a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, etc. A shared cache (not shown) may be included in any one of the processors or outside of both processors and connected to the processors via PP interconnects, such that if the processors are placed in a low-power mode, the local cache information of any one or two processors can be stored in the shared cache.

[0111] Chipset 1190 may be coupled to first bus 1116 via interface 1196. In one embodiment, first bus 1116 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI high-speed bus or another I / O interconnect bus, although the scope of the invention is not so limited.

[0112] like Figure 11 As shown, various I / O devices 1114 may be coupled to a first bus 1116 along with a bus bridge 818, which couples the first bus 1116 to a second bus 1120. In one embodiment, one or more additional processors 1115, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 1116. In one embodiment, the second bus 1120 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 1120, including, for example, a keyboard and / or mouse 1122, a communication device 1127, and a storage unit 1128, such as a hard disk drive or other mass storage device, which may include instructions / code and data 1130 (in one embodiment). Further, audio I / O 1124 may be coupled to the second bus 1120. Note that other architectures are possible. For example, alternatives... Figure 11 The point-to-point architecture allows the system to implement a multi-point bus or another such architecture.

[0113] Now refer to Figure 12 The diagram shown is a block diagram of a second more specific exemplary system 1200 according to an embodiment of the present invention. Figure 11 and 12 Similar elements in the drawings are marked with similar reference numerals, and Figure 11 Some aspects have been from Figure 12The middle part is omitted to avoid making Figure 12 Other aspects are difficult to understand.

[0114] Figure 12 Processors 1170 and 1180 are shown to respectively include integrated memory and I / O control logic (“CL”) 1272 and 1282. Therefore, CL 1272 and 1282 include an integrated memory controller unit and I / O control logic. Figure 12 It is shown that not only are memories 1132 and 1134 coupled to CLs 1272 and 1282, but I / O device 1214 is also coupled to control logic 1172 and 1182. Legacy I / O device 1215 is coupled to chipset 1190.

[0115] Now refer to Figure 13 The diagram shown is a block diagram of a SoC 1300 according to an embodiment of the present invention. Figure 9 Similar components are labeled with similar reference numerals. Similarly, the dashed box is an optional feature on more advanced SoCs. Figure 13 In this configuration, interconnect unit 1302 is coupled to: application processor 1310, which includes a collection of one or more cores 132A-N, cache units 904A-N, and a shared cache unit 906; system agent unit 910; bus controller unit 916; integrated memory controller unit 914; a collection or one or more coprocessors 1320, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; static random access memory (SRAM) unit 1330; direct memory access (DMA) unit 1332; and display unit 1340 for coupling to one or more external displays. In one embodiment, coprocessor 1320 includes a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, and the like.

[0116] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention may be implemented as program code or a computer program running on a programmable system, said programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0117] Such as Figure 11The program code 1130 shown can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0118] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited to any specific programming language. In any case, the language can be a compiled or interpreted language.

[0119] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, the representative instructions representing various logics within a processor that, when read by a machine, cause the machine to make logic for performing the techniques described herein. Such representations (known as “IP cores”) may be stored on tangible, machine-readable media and supplied to various customers or manufacturing facilities for loading onto manufacturing machines that actually make the logic or processor.

[0120] Such machine-readable storage media can include, without limitation, a non-transitory, tangible arrangement of articles made or formed by a machine or apparatus, including storage media such as hard disks, including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact discs (CD-RW), and any other type of disk, magneto-optical disk, semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

[0121] Therefore, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or design data, such as hardware description languages ​​(HDLs), that define the architectures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0122] Simulation (including binary conversion, code transformation, etc.)

[0123] In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the core. Instruction translators are implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on the processor but not entirely off the processor.

[0124] Figure 14 This is a block diagram illustrating the use of a software instruction converter according to an embodiment of the invention to convert binary instructions in a source instruction set into binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 14 The diagram illustrates that, using a first compiler 1404, a program written in a high-level language 1402 can be compiled to generate first binary code (e.g., x86) 1406, which can be natively executed by a processor 1416 having at least one first instruction set core. In some embodiments, a processor 1416 having at least one first instruction set core refers to any processor capable of performing substantially the same functions as an Intel processor having at least one x86 instruction set core, by compatiblely running or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) an object code version of an application or other software running on an Intel processor having at least one x86 instruction set core, to achieve substantially the same results as on an Intel processor having at least one x86 instruction set core. The first compiler 1404 refers to a compiler operable to generate binary code 1406 (e.g., object code) of the first instruction set, which can be executed on a processor 1416 having at least one first instruction set core, with or without additional linking processing. Similarly, Figure 14A program written in a high-level language 1402 is illustrated using an alternative instruction set compiler 1408 to generate alternative instruction set binary code 1410, which can be natively executed by a processor 1414 without at least one first instruction set core (e.g., a processor with a core running the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter 1412 is used to translate the first binary code 1406 into code that can be natively executed by the processor 1414 without a first instruction set core. This translated code cannot be identical to the alternative instruction set binary code 1410, as an instruction converter capable of doing so would be difficult to make; however, the translated code will perform general operations and consist of instructions from the alternative instruction set. Therefore, the instruction converter 1412 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first instruction set processor or core to run the first binary code 1406 through emulation, simulation, or any other process.

[0125] Examples of various embodiments are described in detail below.

[0126] Example 1. A processor comprising: a decoding circuit for decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and an execution circuit for executing the decoded instruction to convert a single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as a 32-bit integer exponent at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

[0127] Example 2. A processor as described in Example 1, wherein the integer component is stored in the least valid packaged data element position of the identified packaged data destination operand.

[0128] Example 3. A processor as described in Example 2, wherein the execution circuitry is configured to: decompose a floating-point value into a sign, an exponent, and a fractional component; determine whether the exponent component is 0; when the exponent component is 0, set the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determine whether the exponent component is all ones; when the exponent component is all ones, determine whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determine whether the sign is 0; when the sign is 0, set the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and set the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, set the fixed-point integer component to a value corresponding to hexadecimal 8000000 and set the exponent component to a value corresponding to ten. The value of hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all 1s or zeros, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; determining whether the sign is 0; and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

[0129] Example 4. The processor as described in Example 1, wherein the exponential component is stored in the least valid packed data element position of the identified packed data destination operand.

[0130] Example 5. A processor as described in Example 4, wherein the execution circuitry is configured to: decompose a floating-point value into a sign, an exponent, and a fractional component; determine whether the exponent component is 0; when the exponent component is 0, set the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determine whether the exponent component is all ones; when the exponent component is all ones, determine whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determine whether the sign is 0; when the sign is 0, set the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and set the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, set the fixed-point integer component to a value corresponding to hexadecimal 8000000 and set the exponent component to a value corresponding to ten. The value of hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all 1s or zeros, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; determining whether the sign is 0; and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

[0131] Example 6. A method comprising: decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and executing the decoded instruction to convert a single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand to a fixed-point representation, storing the fixed-point representation as a 32-bit integer exponent at the two least significant packed data element positions of the identified packed data destination operand, and zeroing out all remaining packed data elements of the identified packed data destination operand.

[0132] Example 7. The method as described in Example 6, wherein the integer component is stored in the least valid packaged data element position of the identified packaged data destination operand.

[0133] Example 8. The method as described in Example 7, wherein the execution further comprises: decomposing the floating-point value into a sign, an exponent, and a fractional component; determining whether the exponent component is 0; when the exponent component is 0, setting the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determining whether the exponent component is all ones; when the exponent component is all ones, determining whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determining whether the sign is 0; when the sign is 0, setting the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and setting the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, setting the fixed-point integer component to a value corresponding to hexadecimal 8000000 and setting the exponent component to a value corresponding to ten. The value of hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all one or zero, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; determining whether the sign is 0 and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

[0134] Example 9. The method as described in Example 6, wherein the exponential component is stored in the least valid packaged data element position of the identified packaged data destination operand.

[0135] Example 10. The method as described in Example 9, wherein the execution further comprises: decomposing the floating-point value into a sign, an exponent, and a fractional component; determining whether the exponent component is 0; when the exponent component is 0, setting the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determining whether the exponent component is all ones; when the exponent component is all ones, determining whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determining whether the sign is 0; when the sign is 0, setting the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and setting the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, setting the fixed-point integer component to a value corresponding to hexadecimal 8000000 and setting the exponent component to a value corresponding to hexadecimal 8000000. The value of hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all one or zero, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; determining whether the sign is 0 and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

[0136] Example 11. A non-transitory machine-readable medium storing instructions, wherein, in response to the instructions, the processor is configured to execute a method comprising: decoding instructions having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and executing the decoded instructions to convert a single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand to a fixed-point representation, storing the fixed-point representation as a 32-bit integer exponent at the two least significant packed data element positions of the identified packed data destination operand, and zeroing out all remaining packed data elements of the identified packed data destination operand.

[0137] Example 12. A non-transitory machine-readable medium as described in Example 11, wherein the integer component is stored in the least significant packed data element location of the identified packed data destination operand.

[0138] Example 13. A non-transitory machine-readable medium as described in Example 12, wherein the execution further comprises: decomposing a floating-point value into a sign, an exponent, and a fractional component; determining whether the exponent component is 0; when the exponent component is 0, setting the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determining whether the exponent component is all ones; when the exponent component is all ones, determining whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determining whether the sign is 0; when the sign is 0, setting the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and setting the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, setting the fixed-point integer component to a value corresponding to hexadecimal 8000000 and setting the exponent component to zero. The value corresponds to hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all one or zero, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; it is determined whether the sign is 0 and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

[0139] Example 16. A processor comprising: a decoding unit for decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and an execution unit for executing the decoded instruction to convert a single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as a 32-bit integer exponent at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

[0140] Example 17. The device as described in Example 16, wherein the integer component is stored in the least valid packaged data element position of the identified packaged data destination operand.

[0141] Example 18. The device of Example 17, wherein the execution unit is configured to: decompose a floating-point value into a sign, an exponent, and a fractional component; determine whether the exponent component is 0; when the exponent component is 0, set the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determine whether the exponent component is all ones; when the exponent component is all ones, determine whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determine whether the sign is 0; when the sign is 0, set the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and set the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, set the fixed-point integer component to a value corresponding to hexadecimal 8000000 and set the exponent component to a value corresponding to hexadecimal 8000000. The value of hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all one or zero, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; determining whether the sign is 0 and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

[0142] Example 19. The device as described in Example 16, wherein the exponential component is stored in the least valid packaged data element position of the identified packaged data destination operand.

[0143] Example 20. The device of Example 19, wherein the execution unit is configured to: decompose a floating-point value into a sign, an exponent, and a fractional component; determine whether the exponent component is 0; when the exponent component is 0, set the fixed-point integer and the exponent component to zero; when the exponent component is not 0, determine whether the exponent component is all ones; when the exponent component is all ones, determine whether the most significant bit of the fractional component is 0; when the most significant bit of the fractional component is 0, determine whether the sign is 0; when the sign is 0, set the fixed-point integer component to a value corresponding to hexadecimal 7fffffff and set the exponent component to a value corresponding to hexadecimal 7fffffff; and when the sign is not 0, set the fixed-point integer component to a value corresponding to hexadecimal 8000000 and set the exponent component to a value corresponding to hexadecimal 8000000. The value of hexadecimal 7fffffff; when the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000 and the exponent component is set to h7fffffff; and when the exponent component is not all one or zero, b000000001 is concatenated with the fractional component to generate the absolute value of the integer; determining whether the sign is 0 and when the sign is 0, the integer component is set to the absolute value of the integer; and when the sign is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; and a temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating 23 copies of the most significant bit of the temporary value with the temporary value; and the integer and exponent components are stored.

Claims

1. A processor, comprising: A decoding circuit for decoding instructions, the instructions having fields for opcode, packaged data source operand identifier, and packaged data destination operand identifier; as well as An execution circuit is configured to execute the decoded instructions to convert the single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand into a fixed-point representation, store the fixed-point representation as a 32-bit integer component and a 32-bit exponent component at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

2. The processor of claim 1, wherein the integer component is stored in the least significant packaged data element position of the identified packaged data destination operand.

3. The processor of claim 2, wherein the execution circuitry is used for: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010. The exponential component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value in parallel. as well as Store the integer and exponential components.

4. The processor of claim 1, wherein the exponential component is stored in the least significant packed data element location of the identified packed data destination operand.

5. The processor of claim 4, wherein the execution circuitry is used to: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

6. A method for converting floating-point to fixed-point values, comprising: Decoding instructions, the instructions having fields for opcode, packaged data source operand identifier, and packaged data destination operand identifier; as well as The decoded instructions are executed to convert the single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand into a fixed-point representation, store the fixed-point representation as a 32-bit integer component and a 32-bit exponent component at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

7. The method of claim 6, wherein the integer component is stored in the least significant packaged data element position of the identified packaged data destination operand.

8. The method of claim 7, wherein the execution further comprises: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

9. The method of claim 6, wherein the exponential component is stored in the least valid packaged data element position of the identified packaged data destination operand.

10. The method of claim 9, wherein the execution further comprises: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

11. A non-transitory machine-readable medium storing instructions, which, when executed by a processor, cause the processor to perform a method comprising the following steps: Decoding instructions, the instructions having fields for opcode, packaged data source operand identifier, and packaged data destination operand identifier; and The decoded instructions are executed to convert the single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand into a fixed-point representation, store the fixed-point representation as a 32-bit integer component and a 32-bit exponent component at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

12. The non-transitory machine-readable medium of claim 11, wherein the integer component is stored in the least significant packed data element location of the identified packed data destination operand.

13. The non-transitory machine-readable medium of claim 12, wherein the execution further comprises: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

14. The non-transitory machine-readable medium of claim 11, wherein the exponential component is stored in the least significant packed data element location of the identified packed data destination operand.

15. The non-transitory machine-readable medium of claim 14, wherein the execution further comprises: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

16. A processor, comprising: A decoding component for decoding instructions, the instructions having fields for opcode, packaged data source operand identifier, and packaged data destination operand identifier; as well as An execution unit is configured to execute the decoded instructions to convert the single-precision floating-point data element at the least significant packed data element position of the identified packed data source operand into a fixed-point representation, store the fixed-point representation as a 32-bit integer component and a 32-bit exponent component at the two least significant packed data element positions of the identified packed data destination operand, and zero out all remaining packed data elements of the identified packed data destination operand.

17. The processor of claim 16, wherein the integer component is stored in the least significant packed data element position of the identified packed data destination operand.

18. The processor of claim 17, wherein the execution unit is configured to: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; When the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

19. The processor of claim 16, wherein the exponential component is stored in the least significant packed data element location of the identified packed data destination operand.

20. The processor of claim 19, wherein the execution unit is configured to: Decompose floating-point values ​​into sign, exponent, and decimal components; Determine whether the exponential component is 0; When the exponential component is 0, the fixed-point integer and the exponential component are set to zero; When the exponential component is not 0, determine whether the exponential component is all one; When all the exponent components are one. Determine whether the most significant bit of the fractional component is 0; When the most significant bit of the fractional component is 0, determine whether the sign is 0; When the sign is 0, the fixed-point integer component is set to a value corresponding to hexadecimal 7fffffff, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; and When the sign is not 0, the fixed-point integer component is set to a value corresponding to hexadecimal 8000000, and the exponent component is set to a value corresponding to hexadecimal 7fffffff; When the most significant bit of the fractional component is not 0, the fixed-point integer component is set to h8000000, and the exponent component is set to h7fffffff; and When the exponential components are not all one or zero Concatenate b000000001 with the decimal to generate the absolute value of the integer; Determine whether the symbol is 0; And when the sign is 0, the integer component is set to the absolute value of the integer; as well as When the symbol is not 0, the integer component is set to the two's complement of the absolute value of the integer plus 1; as well as A temporary value is generated by concatenating b0 with the exponent added to b101101010, and the exponent component is generated by concatenating the 23 most significant bits of the temporary value with the temporary value. as well as Store the integer and exponential components.

21. A computer program product comprising instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 6-10.

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