Storage device, computing system and debugging method thereof

Abstract

A storage device, a computing system and a debugging method thereof are provided. The storage device generates dump data for debugging when an error occurs, and comprises: a storage device, the storage device comprising a dump area for storing the dump data; and a storage controller, the dump controller receiving a dump request from a host through a first host interface, storing the dump data in the dump area in response to the dump request, and transmitting the stored dump data to the host by using the second host interface after resetting a second host interface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed on Korean Patent Application No. 10-2017-0132780 filed on October 12, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concepts described herein relate to semiconductor memory devices, and more particularly, to memory devices, computing systems, and debugging methods thereof. Background Art

[0004] Flash memory devices are widely used as voice and image data storage media for information devices such as computers, smart phones, personal digital assistants (PDAs), digital cameras, recorders, MP3 players, handheld PCs, etc. However, since an erase operation must be performed before data is written to the flash memory, the data unit of the flash memory to be erased may be larger than the data unit to be written to the flash memory. This makes it difficult to use a file system for a normal hard disk even when the flash memory is used as an auxiliary storage device. In addition, due to this characteristic, the sequential input / output processing associated with the flash memory is more efficient than the non-sequential input / output processing.

[0005] A typical example of a high-capacity storage device based on flash memory is a solid-state drive (hereinafter referred to as "SSD"). As the use of SSDs and the types of devices using SSDs become more diverse, the demand for SSDs has increased accordingly. For example, SSDs can be used as storage devices for servers, clients, data centers, etc. The maintenance of SSDs in the above applications can be used to provide high reliability and optimized service quality.

[0006] However, unexpected failures or errors may occur due to hardware or software problems during the operation of the SSD in the above-mentioned application. In this case, the SSD can collect device states when errors or failures occur, and store the collected device states as dump data. The collected dump data can be transmitted to a host to which the SSD is connected. The dump data transmitted to the host can be provided to and used by a debugging tool or a debugging device, and debugging based on the dump data can be performed.

[0007] However, as the capacity and complexity of SSDs increase, the size of dump data also increases. Specifically, it is necessary to collect and extract larger dump data as quickly and efficiently as possible for detailed fault analysis. In this case, the transfer speed of dump data to the debug channel provided for fault analysis of SSDs is limited, making it difficult to perform fast analysis. Therefore, in order to accurately debug the SSD, it is difficult to obtain real-time status information when an error / failure occurs. Summary of the invention

[0008] Embodiments of the inventive concept provide a storage device capable of improving debugging accuracy by minimizing the loss of dump data or log information when a problem occurs, a computing system including the storage device, and a debugging method thereof.

[0009] An embodiment of the present invention provides a storage device, comprising: a storage device, the storage device comprising a dump area for storing dump data; and a storage controller, the storage controller receiving a dump request from a host through a first host interface when an error occurs, generating dump data including status information of the storage device for debugging in response to the dump request, storing the dump data in the dump area, and transmitting the stored dump data to the host using the second host interface after resetting a second host interface.

[0010] An embodiment of the inventive concept also provides a method for debugging a storage device that communicates with a host through a sideband interface and an in-band interface. The debugging method includes: when an error occurs, the storage device receives a dump request from the host through the sideband interface; in response to the dump request, the storage device generates dump data for debugging including state information of the storage device; the storage device stores the dump data in a storage device; the storage device receives a reset request from the host to reset the in-band interface; in response to the reset request, the storage device resets the in-band interface; and after the in-band interface is completely reset, the storage device transmits the stored dump data to the host through the in-band interface.

[0011] Embodiments of the inventive concept also provide a computing system including a storage device and a host. The storage device includes a first host interface and a second host interface. The storage device collects dump data including state information of the storage device for debugging, and stores the dump data in response to a dump request when an error occurs. The host transmits the dump request to the storage device using the first host interface, and reads the stored dump data using the second host interface after resetting the second host interface in response to a reset request for the second host interface.

[0012] Embodiments of the inventive concept also provide a storage device, the storage device comprising a first interface and a second interface, a memory including a dump area, and a storage controller. The storage controller is configured to detect an error in the storage device and transmit an error report to a host through the first interface; after transmitting the error report, generate dump data in response to a dump request received from the host through the first interface, and store the dump data including status information of the storage device in the dump area; after storing the dump data in the dump area, transmit a notification to the host; after transmitting the notification, reset the second interface in response to a reset request received from the host through the second interface; and after resetting the second interface, transmit the stored dump data to the host through the second interface in response to a dump data request received from the host through the second interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects and features of the present inventive concept will become apparent from the following detailed description made with reference to the accompanying drawings.

[0014] Figure 1 A block diagram of a memory device and a computing system including the memory device according to an embodiment of the inventive concept is shown.

[0015] Figure 2 Shows Figure 1 A block diagram of a configuration of a storage device.

[0016] Figure 3 A block diagram illustrating a process of storing dump data of a storage device according to an embodiment of the present inventive concept.

[0017] Figure 4 A block diagram showing an area where dump data is stored.

[0018] Figure 5 A flowchart illustrating an operation of a host according to an embodiment of the inventive concept is shown.

[0019] Figure 6 A flowchart of a dump data management method of a storage device according to an embodiment of the inventive concept is shown.

[0020] Figure 7 Shown is a reference Figure 5 and Figure 6 A view describing the operation of the host and storage device in the event of a failure.

[0021] Figure 8 A flowchart of a dump data management method of a storage device according to another embodiment of the inventive concept is shown.

[0022] Fig. 9 Shows Figure 8 A view of the operations of storage devices and hosts.

[0023] Fig.10 A diagram illustrating a server system according to an embodiment of the inventive concept.

[0024] Fig.11 Shows Figure 1 A block diagram of the configuration of the nonvolatile memory device described in .

[0025] Fig.12 Shown included in Fig.11 A circuit diagram of an example of a first memory block of a memory cell array.

[0026] Fig.13 A block diagram of a solid state drive system to which a debugging method according to the inventive concept is applied is shown.

[0027] Fig.14 A block diagram of a user system including a storage device according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0028] As is conventional in the field of the present invention, the embodiment can be described and illustrated with respect to the block that performs the one or more functions described. These blocks (which may be referred to as units or modules, etc. in this article) are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, storage circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software. For example, the circuit can be embodied in one or more semiconductor chips, or embodied on substrate supports such as printed circuit boards, etc. The circuit constituting the block can be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and related circuits), or by a combination of dedicated hardware for executing some functions of the block and a processor for executing other functions of the block. Without departing from the scope of the present invention, each block of the embodiment can be physically divided into more than two interactive and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of the embodiment can be physically combined into more complex blocks.

[0029] Hereinafter, as an example of a storage device, a solid state drive using a flash storage device will be illustrated to describe the features and functions of the inventive concept. However, those skilled in the art can easily understand other advantages and performances of the inventive concept based on the content disclosed herein. The inventive concept can be implemented or applied through other embodiments. In addition, the detailed description can be changed or modified according to the viewpoint and application without departing from the claims, scope and spirit of the inventive concept and any other purpose.

[0030] Figure 1 FIG. 1 is a block diagram of a computing system including a storage device according to an embodiment of the inventive concept. Figure 1 , a computing system 10 of the inventive concept includes a host 100 and a storage device 200 .

[0031] The host 100 writes data into the storage device 200 or reads data stored in the storage device 200. The host 100 may generate an instruction for writing data into the storage device 200 or reading data stored in the storage device 200. The host 100 may be, for example, a personal computer or a server. For example, the host 100 may search for data stored in the storage device 200 in response to a request from a client, and may provide the found result to the client.

[0032] The host 100 includes an error manager module 150 for detecting a failure or error of the storage device 200 and extracting dump data. The error manager module 150 can monitor error events at the storage device 200. If (when) an error event occurs (when), the error manager module 150 requests the storage device 200 to collect and store dump data for debugging. The request is made through the sideband channel 300. If (when) the dump data is completely stored in the storage device 200 (when), the error manager module 150 can request the storage device 200 to reset the in-band channel 350. For example, as will be described below, the error manager module 150 can request the storage device 200 to reset the in-band interface of the storage device 200, thereby resetting the in-band channel 350. If (when) the in-band channel 350 is completely reset (when), the error manager module 150 can receive the dump data stored in the storage device 200 through the in-band channel 350.

[0033] The storage device 200 can provide data requested by the host 100, or can store data written by the host 100. Specifically, if (when) various errors or problems occur, the storage device 200 generates dump data including state information of the storage device 200 at (i.e., corresponding to) the time point when the error occurs, and stores the dump data in the buffer memory 220 or the non-volatile memory device (NVM) 230. The dump data includes an error or failure background. The storage device 200 can transmit the dump data stored in the buffer memory 220 or the non-volatile memory device 230 to the host 100. Specifically, when an error occurs, the storage device 200 receives a dump request for dump data for debugging (i.e., debug dump data) from the host 100 through the sideband channel 300. The storage device 200 stores dump data for saving the state of the storage device 200 at the time point when the error occurs or corresponding to the time point when the error occurs in response to the dump request. If (when) the dump data is completely stored, the storage device 200 resets the storage controller 210 and transmits information indicating that the dump data is completely stored to the host 100 through the sideband channel 300. After that, the host 100 may perform a reset and initialization of the in-band channel 350. If the reset and initialization of the in-band channel 350 are completed, the storage device 200 transmits the stored dump data through the in-band channel 350 in response to a request of the host 100.

[0034] In order to transfer the dump data, the storage device 200 may include a storage controller 210, a buffer memory 220, and a nonvolatile memory device 230. Data provided according to a write request of the host 100 may be programmed in the nonvolatile memory device 230 through the buffer memory 220. If (when) a read request of the host 100 is generated, data present in the nonvolatile memory device 230 or the buffer memory 220 may be provided to the host 100. The storage controller 210 may control the buffer memory 220 and the nonvolatile memory device 230 in response to a request of the host 100. The buffer memory 220 may be implemented with, for example, a dynamic random access memory (DRAM).

[0035] When an error occurs, the storage controller 210 collects dump data for analyzing the error and stores the collected dump data in the buffer memory 220 or the non-volatile memory device 230. If (when) the dump data is completely stored (when), the storage controller 210 can perform a reset of the storage controller 210. In this case, the reset of the storage controller 210 can proceed to the reset level of the power cycle. For example, the storage controller 210 can be reset to the reset level of the power cycle. Therefore, various errors that may occur in the storage controller 210 can be initialized by resetting. In some embodiments, after the dump data is stored, the reset of the storage controller 210 can be omitted.

[0036] After the reset, the storage controller 210 notifies the host 100 that the dump data is completely stored. If (when) a reset request for the physical layer of the in-band channel 350 is received from the host 100, the storage controller 210 resets the interface using the in-band channel 350. If (when) the host 100 requests the storage controller 210 to transfer the dump data, the storage controller 210 may transfer the dump data stored in the buffer memory 220 or the nonvolatile memory device 230 through the in-band channel 350. The debugging device may analyze an error occurring in the storage device 200 using the dump data transferred to the host 100.

[0037] According to the above configuration and function of the storage device 200 of the present inventive concept, a dump request for dump data for debugging can be provided through the low-speed sideband channel 300. After the dump data is completely stored, after resetting the interface using the in-band channel 350, the dump data can be transmitted to the host 100 at a high speed.

[0038] Figure 2 Shows Figure 1 A block diagram of a configuration of a storage device. Figure 2 , the memory device 200 includes a memory controller 210 , a buffer memory 220 , and a nonvolatile memory device 230 .

[0039] The storage controller 210 includes a sideband interface 211, a central processing unit (CPU) 212, a working memory 213, an inband interface 214, a buffer manager 216, and a flash memory interface 218. The sideband interface 211 and the inband interface 214 may constitute a host interface.

[0040] The sideband interface 211 may provide an interface connection between the storage controller 210 and the host 100. The sideband interface 211 may be, for example, an inter-integrated circuit (IIC) including a serial data line SDA and a serial clock line SCL and supporting bidirectional communication. 2 C) bus interface. 2In the protocol of the I C interface, the communication target can be determined by specifying a unique address of the communication target at the bus master. 2 The sideband interface 211 of the C interface may use bidirectional open collector lines of a serial data line SDA and a serial clock line SCL respectively connected to pull-up resistors.

[0041] However, it is understood that the sideband interface 211 can be replaced or configured according to any of a variety of protocols (such as system management bus (SMBus), universal asynchronous receiver and transmitter (UART), serial peripheral interface (SPI), high-speed chip interconnect (HSIC), etc.). The sideband interface 211 can implement data communication (e.g., transmission and reception) with any device designated by the bus master. In addition, since the mechanism for avoiding bus contention is defined by the protocol of the sideband interface 211, a randomly designated device can act as a master.

[0042] The central processing unit 212 may be characterized as a control circuit, and may provide various control information required to perform read and write operations on the nonvolatile memory device 230 to registers of the sideband interface 211, registers of the in-band interface 214, and registers of the flash memory interface 218. The central processing unit 212 may operate according to firmware provided for various control operations of the storage controller 210. For example, the central processing unit 212 may perform garbage collection to manage the nonvolatile memory device 230 or a flash translation layer (FTL) for performing address management, wear leveling, and the like.

[0043] The central processing unit 212 may execute a dump storage module 215 and a dump transmission module 217 set in a working memory 213 or a read-only memory (ROM). The dump storage module 215 executed by the central processing unit 212 may store dump data (e.g., stored in a buffer memory 220 or a non-volatile memory device 230) in response to a dump request from the host 100, and the dump data is used to save the state of the storage device 200 at a time point when an error or failure occurs or corresponding to a time point when an error or failure occurs. The dump data includes data that will be lost when a reset process is performed, and data that will not be lost when a reset process is performed (i.e., data that will be maintained). The dump storage module 215 may first store data that may be lost due to reset in the buffer memory 220 or the non-volatile memory device 230.

[0044] When the dump transfer module 217 is driven (executed), the central processing unit 212 can reset the in-band interface 214. After the reset, the central processing unit 212 uses the dump transfer module 217 to transfer the dump data stored in the buffer memory 220 or the non-volatile memory device 230 to the host 100 through the in-band interface 214.

[0045] The working memory 213 can be used as a running memory, a cache memory or a buffer memory of the central processing unit 212. The working memory 213 can store the code or command executed by the central processing unit 212. The working memory 213 can store the data processed by the central processing unit 212. In one embodiment, the working memory 213 can be implemented with a static RAM (SRAM). Specifically, the dump storage module 215 used by the central processing unit 212 to extract and store the dump data when an error or failure event occurs and the dump transmission module 217 used by the central processing unit 212 to transmit the stored dump data are loaded onto the working memory 213. The dump storage module 215 and the dump transmission module 217 can be executed by the central processing unit 212, and can control the operation of storing the dump data and transmitting the dump data to the host 100. In addition, the flash translation layer FTL or various storage management modules can be stored in the working memory 213. Herein, a description will be given under the assumption that the dump storage module 215 and / or the dump transmission module 217 are implemented by software. However, it should be understood that in other embodiments of the inventive concept, the dump storage module 215 and / or the dump transmission module 217 may be implemented in hardware such as an intellectual property (IP) block.

[0046] The in-band interface 214 provides a main channel for exchanging data with the host 100. The sideband interface 211 provides a channel for management and error control, and the in-band interface 214 provides a high-speed data transmission channel. The in-band interface 214 can be configured according to any of various communication protocols such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed ​​Inter-Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Host Controller Interface (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Low Load DIMM (LRDIMM), etc.

[0047] The buffer manager 216 controls the read and write operations of the buffer memory 220. For example, the buffer manager 216 temporarily stores the write data or the read data in the buffer memory 220. In addition, the buffer manager 216 may store the dump data in the dump area 225 of the buffer memory 220 under the control of the central processing unit 212.

[0048] The flash interface 218 exchanges data with the nonvolatile memory device 230. The flash interface 218 writes data transferred from the buffer memory 220 into the nonvolatile memory device 230. The flash interface 218 may transfer read data from the nonvolatile memory device 230 to the buffer memory 220 or the host 100. Specifically, the flash interface 218 may store dump data in the dump area 235 of the nonvolatile memory device 230 or read dump data from the dump area 235 of the nonvolatile memory device 230 under the control of the central processing unit 212.

[0049] The buffer memory 220 is used as an input / output buffer of the storage device 200. In addition, the buffer memory 220 may store dump data of the storage device 200. In the event of an error caused by the storage device 200, the storage controller 210 may extract the dump data and may write the dump data in the dump area 225 of the buffer memory 220. In addition, the buffer memory 220 may store an operation state of the storage device 200 or various monitoring information.

[0050] The nonvolatile memory device 230 is a storage medium that finally stores data requested to be written by the host 100. The nonvolatile memory device 230 is connected to the flash memory interface 218 of the storage device 200. The nonvolatile memory device 230 may further include a dump area 235 for storing dump data. For example, in the case where the buffer memory 220 is included as a target to be reset by the dump storage module 215 after extracting the dump data, the dump data may be preferably stored in the nonvolatile memory device 230. However, even if the buffer memory 220 is not included as a target to be reset by the dump storage module 215, the dump area 235 for storing the dump data may be included in the nonvolatile memory device 230.

[0051] The nonvolatile memory device 230 may include, for example, one or more flash memories. In one embodiment, the nonvolatile memory device 230 may be implemented with nonvolatile memory cells such as electrically erasable and programmable ROM (EEPROM) cells, NAND flash memory cells, NOR flash memory cells, phase change RAM (PRAM) cells, resistive RAM (ReRAM) cells, ferroelectric RAM (FRAM) cells, spin torque magnetic RAM (STT-MRAM) cells, etc. For ease of description, it may be assumed that the nonvolatile memory device is a NAND flash memory.

[0052] For example, as an exemplary embodiment of the inventive concept, the nonvolatile memory device 230 may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed in one or more physical layers of a memory cell array having an active region arranged as part of a circuit on a silicon substrate, and the circuit may control the operation of the memory cell. The circuitry associated with the operation of the memory cell may be located in or on the substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array.

[0053] As an exemplary embodiment of the inventive concept, a three-dimensional memory array may have a vertically oriented characteristic and may include a vertical NAND string in which at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. Each vertical NAND string may include at least one selection transistor located above the memory cell. The at least one selection transistor may have the same structure as that of the memory cell and may be monolithically formed with the memory cell.

[0054] The following patent documents, which are incorporated herein by reference, describe suitable configurations for a three-dimensional memory array, wherein the three-dimensional memory array is configured as multiple levels with word lines and / or bit lines shared between levels: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0055] According to the above structure, the storage device 200 receives the dump request through the sideband interface 211 of the low-speed operation, and stores the dump data in the buffer memory 220 or the non-volatile memory device 230. Afterwards, after the in-band interface 214 is reset, the storage device 200 transmits the stored dump data to the host 100 through the in-band interface 214. Therefore, even if an error or fault may be caused by the in-band interface 214 or an error or fault may occur due to the in-band interface 214, the storage device 200 of the present invention is still able to store the dump data to which the fault state is applied. In addition, since the stored dump data is transmitted through the high-speed in-band interface 214, a large amount of dump data can be quickly transmitted to the host 100.

[0056] Figure 3 FIG. 1 is a block diagram showing a process of storing dump data of a storage device according to the present invention. Figure 3 , the storage device 200 extracts dump data in response to a dump request of the host 100 , and stores the extracted dump data in the buffer memory 220 or the nonvolatile memory device 230 .

[0057] The storage controller 210 collects dump data 219 in response to a dump request received through the sideband interface 211. The failure or error that causes the transmission of the request for dump data may be, for example, a hardware problem, a processing error of software, or a response delay error of an interface (e.g., an in-band interface) that occurs or appears at the storage device 200. The host 100 may detect such an error or problem, or the storage device 200 may detect the error or problem and report the error event to the host 100. The host 100 transmits the dump request to the storage controller 210 by using the sideband interface 211.

[0058] The storage controller 210 generates or creates dump data of the overall storage state including the time point when an error or problem occurs (or the time point corresponding to the time point when an error or problem occurs) in response to the dump request. The dump data generated in this way can be written in the dump area 225 of the buffer memory 220. Figure 3 Reference mark ① in indicates the operation of writing dump data into the dump area 225 of the buffer memory 220. It should be understood that dump data can be generated or created in various different ways, so a detailed description of the way of generating or creating dump data at the time point when an error occurs is omitted.

[0059] The dump data 219 stored in the dump area 225 of the buffer memory 220 may be migrated to the dump area 235 of the nonvolatile memory device 230 . Figure 3 Reference mark ② in indicates migration of the dump data 219 to the dump area 235. In the case where the buffer memory 220 is reset after completely storing the dump data 219, the dump data stored in the buffer memory 220 may be lost. Therefore, for the purpose of stably holding the dump data even when the buffer memory 220 is reset, the dump data 219 may also be stored in the dump area 235 of the nonvolatile memory device 230.

[0060] The dump data 219 may be stored without using the buffer memory 220. For example, if the nonvolatile memory device 230 provides high-speed writing performance, the dump data 219 may be written directly from the storage controller 210 to the dump area of ​​the nonvolatile memory device 230. Reference numeral ③ indicates an operation of writing the dump data 219 directly into the nonvolatile memory device 230.

[0061] The manner in which dump data is stored in the storage device 200 in response to a dump request is described above. However, the location where the dump data 219 is stored may vary depending on the reset operation to be performed after the dump data is stored. In the case where the buffer memory 220 is excluded as a reset target of the reset operation, the dump data 219 does not need to be migrated to the nonvolatile memory device 230. However, in the case of including the buffer memory 220 as a reset target, the dump data 219 may be migrated and stored in the nonvolatile memory device 230.

[0062] Figure 4 A diagram showing an area for storing dump data of the inventive concept. Figure 4 , shows a configuration of the dump area 235 of the nonvolatile memory device 230. Here, the dump area 225 of the buffer memory 220 may be divided in the same manner as the dump area 235 of the nonvolatile memory device 230 according to the attributes of the dump data.

[0063] First, the first dump data Dump_data_1 that may be lost during the reset process may be stored in the first dump area 237. Once a dump request is received, the dump storage module 215 executed by the central processing unit 212 may store the first error or fault, or the state information, management data, user data, etc. of the storage device 200 at the time point when the defect is detected or corresponding to the time point when the defect is detected. These data may include data that will change in the reset operation to be performed after the dump data is completely stored. For example, in the case of an error when transmitting data through the in-band interface 214, after the in-band interface 214 is reset, the command or state information loaded on the register of the in-band interface 214 may be lost. The dump storage module 215 regards such data as the first dump data Dump_data_1 and stores such data in the first dump area 237. The first dump data Dump_data_1 may include, for example, the context of the in-band interface 214, the firmware context for data transmission, and the command history. The dump storage module 215 may store snapshot data generated by dumping the first dump area 237 in the first dump data Dump_data_1.

[0064] In contrast, the second dump data Dump_data_2 that is not lost or changed due to a reset operation to be performed after the dump data is stored may be stored in the second dump area 239. For example, metadata (e.g., address mapping information or user data) updated in the storage device 200 may maintain the same value before or after the in-band interface 214 is reset. The second dump data Dump_data_2 may be transmitted to the host 100 after being stored in the second dump area 239. The second dump data Dump_data_2 may be transmitted to the host 100 from the location where the second dump data Dump_data_2 is stored without a separate dump operation.

[0065] When an error or a fault occurs, both the first dump data and the second dump data are substantially needed to analyze the overall state of the storage device 200. However, the size of the dump data required for accurately analyzing an error or a fault cannot be too large. Providing a large amount of dump data to the main frame 100 through the sideband channel 300 can consume a considerable amount of time (e.g., several hours or days). However, according to an embodiment of the inventive concept, due to transmitting a large amount of dump data at high speed, rapid fault analysis can be performed.

[0066] Figure 5 FIG. 1 is a flowchart showing the operation of the host 100 according to an embodiment of the inventive concept. Figure 5 If an error or failure is detected during communication with the storage device 200 , the host 100 sends a dump request to the sideband channel 300 , and the stored dump data is provided to the host 100 through the in-band channel 350 .

[0067] In operation S110, the host 100 detects an error or a fault of the storage device 200. For example, the host 100 may detect an error from data provided by the storage device 200, or may identify an error or a fault through an error report of the storage device 200. The storage device 200 may detect an error or a fault, and may report the detection result to the host 100. Alternatively, the host 100 may provide a status confirmation command such as an asynchronous event request to the storage device 200. The host 100 may determine a problem or a communication problem of the storage device 200 through an error or a fault report or automatic detection of the storage device 200. If no error or a fault is detected in operation S110 (No), the process proceeds to (i.e., remains in) operation S110 to continuously monitor the error or the fault. However, if an error or a fault is detected in operation S110 (Yes), the process proceeds to operation S120.

[0068] In operation S120, the host 100 requests the storage device 200 to extract and store the time point at which an error or fault occurs or the time point corresponding to the time point at which an error or fault occurs, for preserving the dump data or fault background of the state of the storage device 200. That is, the host 100 transmits a dump request (that is, a fault dump) of the dump data to the storage device 200 through the sideband channel 300. In this case, the storage device 200 extracts the state of the storage device 200 at the time point at which an error or fault occurs in each component including the in-band interface 214 or the firmware or corresponding to the time point, and generates or creates dump data based on the extracted state. The dump data thus generated or created is stored in the dump area 225 or the dump area 235. Selectively, the storage device 200 can perform a reset operation on some or all components of the storage device 200. If the reset operation is completed, the storage device 200 notifies the host 100 that the dump data is completely stored.

[0069] In operation S130, the host 100 determines whether it is reported that the dump data is completely stored. If a report indicating that the dump data is completely stored is not received from the storage device 200 (No), the host 100 repeats operation S130 and waits until a completion report is received. On the contrary, if a report indicating that the dump data is completely stored is received from the storage device 200 in operation S130 (Yes), the process proceeds to operation S140.

[0070] In operation S140, the host 100 transmits a reset and initialization request associated with the in-band interface 214 of the storage device 200 to the storage device 200 in response to the dump storage completion report from the storage device 200. In the case of an error or failure in the in-band interface 214, the in-band interface 214 can be reset first to receive dump data at high speed. A reset or initialization command can be provided from the host 100 to return the in-band interface 214 to a usable state (i.e., the in-band interface 214 can be used for transmission). In this case, it should be understood that the reset or initialization command is provided by a control signal such as a reset signal and a command sequence. If (when) the in-band interface 214 is completely reset (when), a reset completion report of the in-band interface 214 from the storage device 200 is provided to the host 100.

[0071] In operation S150, the host 100 recognizes that the in-band interface 214 has returned to an available state based on the reset completion report of the in-band interface 214. In addition, the host 100 requests that the stored dump data be transmitted to the host 100 using the in-band interface 214. In this case, a general read command can be used to request the dump data, and the dump data can be transmitted using the in-band interface 214. Even if the dump data is large, because the dump data is provided through the high-speed in-band interface 214, the dump data can be quickly obtained.

[0072] According to the above description, when an error is caused by the storage device 200, the host 100 transmits a dump request to the storage device 200 using the sideband interface 211. In addition, the host 100 resets the in-band interface 214, and provides the stored dump data to the host 100 through the reset in-band interface 214. Through the above process, even if an error or failure is caused by the in-band interface 214, the dump data including error information can be provided to the host 100 at a high speed.

[0073] Figure 6 FIG. 1 is a flowchart of a dump data management method of a storage device according to an embodiment of the inventive concept. Figure 6 The storage device 200 receives the dump request through the sideband interface 211 and transmits the dump data to the host 100 through the in-band interface 214 .

[0074] In step S210, the storage device 200 detects whether an error or failure has occurred. For example, the storage device 200 may detect an error or failure that occurs in an internal memory management operation or command of the host 100. In addition, the storage device 200 may detect various hardware failures including power failures and software errors. If no error is detected in operation S210 (No), the process returns to operation S210, and the storage device 200 continues to monitor for errors. If an error is detected in operation S210 (Yes), the process proceeds to operation S220.

[0075] In operation S220, the storage device 200 reports the fault event to the host 100 through the sideband interface 211. The storage device 200 may report the occurrence of a fault to the host 100 in response to a fault event report request from the host 100 or in accordance with an internal fault reporting method. The host 100 transmits a dump request to the storage device 200 in response to the fault report.

[0076] In operation S230 , the storage device 200 receives a dump request transmitted through the sideband interface 211 from the host 100 .

[0077] In operation S240, the dump storage module 215 (refer to Figure 2) generates dump data in response to a dump request transmitted through the sideband interface 211. The storage device 200 may collect overall data indicating the operating state of the storage device 200 at a time point at which a failure occurs or corresponding to the time point in response to the dump request. Specifically, the storage device 200 may collect state information of the firmware for processing commands from the host 100 or register information of the interfaces 211, 214, and 218, and may store the collected information as dump data. The register information of the interfaces 211, 214, and 218 refers to data that may be lost in a reset operation performed later. Therefore, such data may be the first data among all data extracted when generating the dump data. In addition, the storage device 200 may include multiple pieces of data that are not lost in the reset process in the dump data. For example, the storage device 200 may include various user data or metadata such as address mapping information in the dump data. The dump data may be stored in the dump area 225 of the buffer memory 220 or in the dump area 235 of the non-volatile memory device 230.

[0078] In operation S250, the storage device 200 receives a reset request for the in-band interface 214 from the host 100. For example, the reset request may be received by the dump transfer module 217 (see Figure 2 ) detects a reset request for the in-band interface 214 provided by the host 100. The reset request for the in-band interface 214 may be transmitted through the in-band interface 214.

[0079] In operation S260, the storage device 200 resets the in-band interface 214 according to the reset request transmitted from the host 100. After performing the reset operation, the setting parameters of the in-band interface 214 can be initialized to default values. Even if the in-band interface 214 was previously in a fault state or in an error state, the in-band interface 214 can be returned to a usable state through the reset operation. If (when) the reset operation is completed, the storage device 200 transmits a reset completion response.

[0080] In operation S270, the storage device 200 waits for receiving a dump data transfer request from the host 100. If the dump data transfer request is not received from the host 100 in operation S270 (No), the process returns to operation S270, and the storage device 200 continues to wait for receiving a dump data transfer request. If the dump data transfer request is received from the host 100 in operation S270 (Yes), the process proceeds to operation S280.

[0081] In operation S280 , the storage device 200 transmits the dump data stored in the dump area 225 or 235 to the host 100 using the in-band interface 214 .

[0082] As described, in the embodiment of the present invention, the dump request is received by the storage device 200 through the sideband interface 211, and the dump data is transmitted from the storage device 200 to the host 100 using the in-band interface 214. Therefore, according to the debugging method of the present invention, even if the capacity of the dump data is large, the dump data can be obtained at high speed. In addition, according to the embodiment of the present invention, a large amount of dump data can be quickly extracted by the storage device 200 without losing fault information, and a large amount of dump data can be transmitted to the remote debugging host. Therefore, the storage device 200 of the present invention can be managed by remote diagnosis or remote debugging.

[0083] Figure 7 Shown is a reference Figure 5 and Figure 6 A diagram describing the fault management operations of a host and a storage device. Figure 7 , the dump request can be transmitted through the sideband interface 211, and the dump data can be transmitted to the host 100 through the in-band interface 214.

[0084] In operation S1, an internal fault or error of the storage device 200 is detected. For example, the host 100 may monitor whether a fault or error event occurs through the sideband interface 211. The host 100 may detect a fault or error in a transaction with the storage device 200 through various fault detection operations.

[0085] In operation S2, the host 100 transmits a dump request according to the detected failure or error to the storage device 200. When a failure occurs, the storage device 200 receives a dump request for dump data for debugging from the host 100 through the sideband channel 300.

[0086] In operation S3, the storage device 200 stores dump data or a fault context for saving the state of the fault occurrence in response to the dump request. The storage device 200 extracts the dump data and stores the extracted dump data in the dump area 225 of the buffer memory 220 or the dump area 235 of the non-volatile memory device 230. Specifically, the storage device 200 may first store data (i.e., first dump data) among a plurality of pieces of state data at a time point when a fault or error occurs or corresponding to a time point when a fault or error occurs, which may be lost when the in-band interface 214 is subsequently reset.

[0087] In operation S4, the storage device 200 notifies the host 100 that the dump data is completely stored. If the dump data is completely stored, the storage device 200 transmits information indicating that the dump data is completely stored to the host 100 through the sideband interface 300.

[0088] In operation S5, the host 100 transmits a reset request for the in-band interface 214 to the storage device 200. In the case where a fault or error is detected caused by the in-band interface 214, a reset operation may be first performed to return the in-band interface 214 to a state where it can be reused. The reset request for the in-band interface 214 may be transmitted by using a control signal provided by a separate pin or by using a lower-level command. Therefore, resetting the in-band interface 214 enables the dump data to be transmitted by utilizing the in-band interface 214.

[0089] In operation S6, the storage device 200 performs a reset operation on the in-band interface 214. The operation state of the in-band interface 214 may be initialized through the reset operation. The register value or setting value of the in-band interface 214 may be initialized to a default value.

[0090] In operation S7, the storage device 200 transmits a reset completion response associated with the in-band interface 214 to the host 100. The above process refers to a process of notifying the host 100 that high-speed data transmission can be performed through the in-band interface 214.

[0091] In operation S8, the host 100 transmits a read request for dump data stored in the dump area 225 or 235 to the storage device 200. In this case, the read request for the dump data may be transmitted using the in-band interface 214.

[0092] In operation S9, the storage device 200 transmits the dump data to the host 100 through the in-band interface 214. Even if the dump data is large, since the in-band interface 214 is used, the dump data can be transmitted at a high speed.

[0093] Here, the communication between the host 100 and the storage device 200 performed in operations S1 to S4 may be performed through the sideband interface 211. The reason is that the detected fault or error comes from the in-band interface 214. The communication between the host 100 and the storage device 200 performed in operations S5 to S9 may be performed through the in-band interface 214. The reason is that since the in-band interface 214 is reset after all dump data is stored, the in-band interface 214 is available again.

[0094] Figure 8 FIG. 2 is a flowchart of a method for managing dump data of a storage device according to another embodiment of the present invention. Figure 8, the storage device 200 receives the dump request through the sideband interface 211, and transmits the dump data to the host 100 through the in-band interface 214. In addition, if the dump data is completely stored, the storage device 200 transmits a dump completion response to the host 100 after resetting part or all of the hardware of the storage device 200. In other words, after the dump data is completely stored by the storage device 200, the storage controller 210 resets at least one of the multiple components of the storage device 200.

[0095] In operation S310, the storage device 200 detects whether an error or fault has occurred in the storage device 200. The storage device 200 can detect hardware faults and operational faults of firmware or software errors such as interface response delays. If no fault is detected in operation S310 (no), the process returns to operation S310, and the storage device 200 continues to monitor the fault. If a fault is detected in operation S310 (yes), the process proceeds to operation S320.

[0096] In operation S320, the storage device 200 reports to the host 100 that a failure or error event has occurred through the sideband interface 211. The host 100 may transmit a dump request to the storage device 200 through the sideband interface 211 in response to the report of the failure event.

[0097] In operation S330, the storage device 200 determines whether a dump request has been received from the host 100 through the sideband interface 211. If a dump request has not been received from the host 100 in operation S330 (No), the process returns to operation S330, and the storage device 200 waits for the transmission of the dump request. On the contrary, if a dump request is received from the host 100 in operation S330 (Yes), the storage device 200 recognizes the dump request. Then, the process proceeds to operation S340.

[0098] In operation S340, the dump storage module 215 (see Figure 2) extracts dump data in response to a dump request transmitted through the sideband interface 211. The dump storage module 215 can collect all data indicating the operating state of the storage device 200 at the time point of a fault or error or corresponding to the time point of a fault or error in response to the dump request. Specifically, the state information of the firmware for processing the command from the host 100 or the register information of the interfaces 211, 214 and 218 can be collected, and the collected information can be stored as dump data. The register information of the interfaces 211, 214 and 218 refers to the state data that may be lost when a part of the hardware of the storage device 200 is reset. Therefore, the state data that may be lost can be the first data of all the data extracted when the dump data is generated. In addition, multiple pieces of data that are not lost during the reset process can also be included in the dump data. For example, the storage device 200 can include various user data in the dump data or metadata such as address mapping information. The dump data can be stored in the dump area 225 of the buffer memory 220 or the dump area 235 of the non-volatile storage device 230.

[0099] In operation S342, the storage device 200 performs a reset operation on some or all components (i.e., at least one of the plurality of components) included in the storage device 200. The detected error or failure may not be an error or failure caused by the in-band interface 214. That is, in order to be able to transmit the dump data to the host 100, the hardware or firmware of the storage device 200 may be reset. In operation S342, the reset of the in-band interface 214 may be skipped.

[0100] In operation S344, the storage device 200 notifies the host 100 that the dump data is completely stored. If the dump data is completely stored, the storage device 200 transmits information indicating that the dump data is completely stored to the host 100.

[0101] In operation S350, the storage device 200 determines whether a reset request for the in-band interface 214 is received from the host 100. For example, the reset request for the in-band interface 214 provided from the host 100 may be detected by the dump transmission module 217. The reset request for the in-band interface 214 may be transmitted through the in-band interface 214. If the reset request for the in-band interface 214 is not received in operation S350 (No), the process returns to operation S350, and the storage device 200 continues to wait for the transmission of the reset request. On the contrary, if the reset request for the in-band interface 214 is received in operation S350 (Yes), the process proceeds to operation S360.

[0102] In operation S360, the storage device 200 resets the in-band interface 214 according to the reset request transmitted from the host 100. After performing the reset operation, the setting parameters of the in-band interface 214 can be initialized to default values. Even if the in-band interface 214 was previously in a fault state or in an error state, the in-band interface 214 can also return to a usable state through the reset operation. If (when) the reset operation is completed (when), the storage device 200 transmits a reset completion response.

[0103] In operation S370, the storage device 200 waits for a dump data transfer request from the host 100. If the dump data transfer request is not received from the host 100 in operation S370 (No), the process returns to operation S370, and the storage device 200 continues to wait for the dump data transfer request. If the dump data transfer request is received from the host 100 in operation S370 (Yes), the process proceeds to operation S380.

[0104] In operation S380 , the storage device 200 transmits the dump data stored in the dump area 225 or 235 to the host 100 using the in-band interface 214 .

[0105] As described, the dump request is received by the storage device 200 through the sideband interface 211, and the dump data is transmitted from the storage device 200 to the host 100 using the in-band interface 214. The storage device 200 may reset some components of the storage device 200 before receiving the reset request for the in-band interface 214 and immediately after the dump data is completely stored. By performing the reset of the components of the storage device 200, the probability of successfully transmitting the dump data may become higher.

[0106] Fig. 9 Shows Figure 8 A view of the interaction between the storage device and the host. Fig. 9 If a dump request is transmitted through the sideband interface 211, the storage device 200 performs a reset operation on part of the hardware after storing the dump data.

[0107] In operation S11, a fault or error is detected by the storage device 200 or the host 100. When a fault of the storage device 200 is detected, the storage device 200 may provide information indicating that a fault or error event has occurred to the host 100 via the sideband interface 211. Alternatively, the host 100 may be monitored to detect whether an error or fault event has occurred.

[0108] In operation S12, the host 100 transmits a dump request in response to a failure or error event to the storage device 200. In this case, the storage device 200 receives the dump request for dump data for debugging through the sideband channel 300.

[0109] In operation S13 , the storage device 200 stores dump data or a failure context for saving a failure state in response to the dump request. The storage device 200 extracts the dump data and stores the extracted dump data in the dump area 225 of the buffer memory 220 or the dump area 235 of the nonvolatile memory device 230 .

[0110] In operation S14, the storage device 200 resets part or all of the components of the storage device 200 after storing the dump data. Through the reset operation, it is possible to recover from a failure or error caused by the storage device 200 to a usable state.

[0111] In operation S15, the storage device 200 notifies the host 100 that the dump data is completely stored. If the dump data is completely stored, the storage device 200 transmits information indicating that the dump data is completely stored to the host 100 through the sideband interface 300.

[0112] In operation S16, the host 100 transmits a reset request for the in-band interface 214 to the storage device 200. In the case of detecting a fault or error caused by the in-band interface 214, a reset operation may be first performed to return the in-band interface 214 to a state where it can be reused. The reset request for the in-band interface 214 may be transmitted using a control signal provided by a separate pin. Therefore, the reset request for the in-band interface 214 may be transmitted through the in-band interface 214.

[0113] In operation S17, the storage device 200 performs a reset operation on the in-band interface 214. The operation state of the in-band interface 214 may be initialized by the reset operation. A register value or a setting value of the in-band interface 214 may be initialized to a default value.

[0114] In operation S18, the storage device 200 transmits a reset completion response associated with the in-band interface 214 to the host 100. The above process refers to a process of notifying the host 100 that high-speed data transmission can be performed through the in-band interface 214.

[0115] In operation S19, the host 100 transmits a read request for the dump data stored in the dump area 225 or 235 to the storage device 200. In this case, the read request for the dump data may be transmitted by using the in-band interface 214.

[0116] In operation S20, the storage device 200 transmits the dump data to the host 100 through the in-band interface 214. Even if the dump data is large, since the in-band interface 214 is used, the dump data can be transmitted at a high speed.

[0117] Here, the communication between the host 100 and the storage device 200 performed in operations S11 to S15 may be performed through the sideband interface 211. The communication between the host 100 and the storage device 200 performed in operations S16 to S20 may be performed through the in-band interface 214.

[0118] Fig.10 FIG. 1 is a block diagram of a server system according to an embodiment of the present invention. Fig.10 , the server system 400 may include a memory 410 and a server host 420 .

[0119] The storage 410 may be connected to the server host 420 to exchange data therewith. The storage 410 may include a plurality of solid state drives 411, 413, 415, 417, and 419. Each of the plurality of solid state drives 411, 413, 415, 417, and 419 may be connected to a server host 420 to exchange data therewith. Figure 1 The storage device 200 of the embodiment of the present invention can report the fault to the server host 420 and transmit the dump data to the server host 420 in the same manner. That is, each of the plurality of solid state drives 411, 413, 415, 417 and 419 can receive the dump request through the sideband interface. After resetting the in-band interface, each of the plurality of solid state drives 411, 413, 415, 417 and 419 can transmit the stored dump data by utilizing the in-band interface.

[0120] In one embodiment, the SSD 419 with an error or failure can receive a dump request from the server host 420 through the sideband interface. The SSD 419 generates dump data by collecting and storing the failure context in response to the dump request. The SSD 419 can transmit the dump data to the server host 420 after resetting the in-band interface.

[0121] When receiving the dump data, the server host 420 transmits the dump data to the debugging host 600 through the network 500. Since the server host 420 receives the dump data of the solid state drive 419, the server host 420 can quickly transmit the dump data to the debugging host 600. In this case, the dump data can be quickly transmitted to the debugging host 600 located remotely through the network 500.

[0122] Fig.11 Shown is a reference Figure 1 A block diagram of a nonvolatile memory device configuration is described. Fig.11 , the nonvolatile memory device 230 includes a memory cell array 231 , an address decoder 232 , a control logic and voltage generation circuit 236 , a page buffer 233 , and an input / output circuit 234 .

[0123] The memory cell array 231 may include a plurality of memory blocks. Each memory block may include a plurality of cell strings. Each cell string may include a plurality of memory cells. These memory cells may be connected to a plurality of word lines WL. Each memory cell may be a single-layer cell (SLC) storing one bit or a multi-layer cell (MLC) storing at least two bits.

[0124] The address decoder 232 is connected to the memory cell array 231 through the word line WL, the string selection line SSL and the ground selection line GSL. The address decoder 232 can receive a physical address ADD from an external device (e.g., the memory controller 210) and decode the physical address ADD, and can drive the word line based on the decoding result. For example, the address decoder 232 can decode the physical address ADD received from the external device, can select at least one word line WL based on the decoded physical address, and can drive the selected word line.

[0125] The control logic and voltage generation circuit 236 may control the address decoder 232, the page buffer 233, and the input / output circuit 234 in response to a storage command CMD and a control signal CTRL from an external device. For example, the control logic and voltage generation circuit 236 may control other components in response to the signals CMD and CTRL so that data is stored in the memory cell array 231. Alternatively, the control logic and voltage generation circuit 236 may control other components in response to the signals CMD and CTRL so that data stored in the memory cell array 231 is transmitted to an external device.

[0126] The page buffer 233 is connected to the memory cell array 231 through a plurality of bit lines BL. Under the control of the control logic and voltage generation circuit 236, the page buffer 233 may control the bit lines BL so that data provided from the input / output circuit 234 is stored in the memory cell array 231. Under the control of the control logic and voltage generation circuit 236, the page buffer 233 may read data stored in the memory cell array 231, and may provide the read data to the input / output circuit 234. For example, data may be provided to the page buffer 233 from the input / output circuit 234 by page, or the page buffer 233 may read data from the memory cell array 231 by page.

[0127] The input / output circuit 234 may receive data DATA from an external device and may provide the received data to the page buffer 233. Alternatively, the input / output circuit 234 may receive data from the page buffer 233 and may transmit the received data as data DATA to the external device. For example, the input / output circuit 234 may exchange data with the external device in synchronization with the control signal CTRL.

[0128] The control logic and voltage generation circuit 236 may generate various voltages Vers required for the operation of the nonvolatile memory device 230. For example, the control logic and voltage generation circuit 236 may generate a plurality of program voltages, a plurality of transfer voltages, a plurality of verification voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, etc. The control logic and voltage generation circuit 236 may provide the generated voltages to the address decoder 232 or the substrate of the memory cell array 231.

[0129] Fig.12 Shown included in Fig.11 A circuit diagram of an example of a first memory block in a memory cell array of FIG. Fig.12 The first memory block BLK1 having a three-dimensional structure is described. However, the inventive concept is not limited thereto, and other memory blocks included in the nonvolatile memory device 230 may have a similar structure to the first memory block BLK1.

[0130] Reference Fig.12 , the first memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. The cell strings CS11, CS12, CS21, and CS22 may be arranged in row and column directions to form rows and columns.

[0131] For example, cell strings CS11 and CS12 may be connected to string selection lines SSL1a and SSL1b to constitute a first row. Cell strings CS21 and CS22 may be connected to string selection lines SSL2a and SSL2b to constitute a second row.

[0132] For example, cell strings CS11 and CS21 may be connected to a first bit line BL1 to constitute a first column. Cell strings CS12 and CS22 may be connected to a second bit line BL2 to constitute a second column.

[0133] Each of the cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. For example, each of the cell strings CS11, CS12, CS21, and CS22 may include string selection transistors SSTa and SSTb, a plurality of memory cells MC1 to MC8, ground selection transistors GSTa and GSTb, and dummy memory cells DMC1 and DMC2.

[0134] In one embodiment, each memory cell included in the cell strings CS11, CS12, CS21, and CS22 may be a charge trap flash (CTF) memory cell.

[0135] The memory cells MC1 to MC8 may be connected in series and may be stacked in a height direction, which is a direction perpendicular to a plane defined by a row direction and a column direction. The string selection transistors SSTa and SSTb may be connected in series and may be disposed between the memory cells MC1 to MC8 and the bit line BL. The ground selection transistors GSTa and GSTb may be connected in series and may be disposed between the memory cells MC1 to MC8 and the common source line CSL.

[0136] In one embodiment, in each cell string, a first dummy memory cell DMC1 may be provided between the memory cells MC1 to MC8 and the ground selection transistors GSTa and GSTb. In one embodiment, in each cell string, a second dummy memory cell DMC2 may be provided between the memory cells MC1 to MC8 and the string selection transistors SSTa and SSTb.

[0137] The ground selection transistors GSTa and GSTb of the cell strings CS11 , CS12 , CS21 , and CS22 may be commonly connected to a ground selection line GSL.

[0138] In one embodiment, the ground selection transistors in the same row can be connected to the same ground selection line, while the ground selection transistors in different rows can be connected to another ground selection line. For example, the first ground selection transistors GSTa of the cell strings CS11 and CS12 in the first row can be connected to the first ground selection line, and the first ground selection transistors GSTa of the cell strings CS21 and CS22 in the second row can be connected to the second ground selection line.

[0139] In one embodiment, even if not in Fig.12 As shown in FIG. 1 , ground selection transistors disposed at the same height from a substrate (not shown) may be connected to the same ground selection line, while ground selection transistors disposed at different heights may be connected to different ground selection lines. For example, the first ground selection transistors GSTa of cell strings CS11, CS12, CS21, and CS22 may be connected to the first ground selection line, and the second ground selection transistors GSTb thereof may be connected to the second ground selection line.

[0140] Memory cells located at the same height from the substrate (or ground selection transistors GSTa and GSTb) can be connected to the same word line, and memory cells located at different heights can be connected to different word lines. For example, the first to eighth memory cells MC1 to MC8 in cell strings CS11, CS12, CS21, and CS22 can be connected to the first to eighth word lines WL1 to WL8, respectively.

[0141] The string selection transistors SSTa of the first string selection transistors SSTa located at the same height and belonging to the same row may be connected to the same string selection line, and the string selection transistors belonging to different rows may be connected to different string selection lines. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 in the first row may be connected to the string selection line SSL1a in common, and the first string selection transistors SSTa of the cell strings CS21 and CS22 in the second row may be connected to the string selection line SSL2a in common.

[0142] Similarly, the string selection transistors belonging to the same row among the second string selection transistors SSTb arranged at the same height may be connected to the same string selection line, and the string selection transistors belonging to different rows among the second string selection transistors SSTb may be connected to different string selection lines. For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 in the first row may be commonly connected to the string selection line SSL1b, and the second string selection transistors SSTb of the cell strings CS21 and CS22 in the second row may be commonly connected to the string selection line SSL2b.

[0143] Although not in Fig.12 , but the string selection transistors of the cell strings in the same row can be connected to the same string selection line in common. For example, the first string selection transistors SSTa and the second string selection transistors SSTb of the cell strings CS11 and CS12 in the first row can be connected to the same string selection line in common. The first string selection transistors SSTa and the second string selection transistors SSTb of the cell strings CS21 and CS22 in the second row can be connected to the same string selection line in common.

[0144] In one embodiment, pseudo memory cells at the same height may be connected to the same pseudo word line, and pseudo memory cells at different heights may be connected to different pseudo word lines. For example, the first pseudo memory cell DMC1 may be connected to the first pseudo word line DWL1, and the second pseudo memory cell DMC2 may be connected to the second pseudo word line DWL2.

[0145] In the first memory block BLK1, read and write operations may be performed in row units. For example, one row in the first memory block BLK1 may be selected by string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

[0146] For example, when a turn-on voltage is provided to string selection lines SSL1a and SSL1b and a turn-off voltage is provided to string selection lines SSL2a and SSL2b, cell strings CS11 and CS12 in the first row are connected to bit lines BL1 and BL2, respectively. When a turn-on voltage is provided to string selection lines SSL2a and SSL2b and a turn-off voltage is provided to string selection lines SSL1a and SSL1b, cell strings CS21 and CS22 in the second row are connected to bit lines BL1 and BL2, respectively. When a word line is driven, memory cells belonging to the same height among memory cells of the cell string in the row corresponding to the driven word line may be selected. A read or write operation may be performed on the selected memory cell. The selected memory cell may constitute a physical page unit.

[0147] In the first memory block BLK1, memory cells may be erased in units of memory blocks or sub-blocks. When an erase operation is performed in units of memory blocks, all memory cells in the memory block BLK1 may be erased simultaneously according to an erase request. When an erase operation is performed in units of sub-blocks, a portion of memory cells in the memory block BLK1 may be erased simultaneously according to an erase request, and erasure of the remaining memory cells may be prohibited. A low voltage (e.g., a ground voltage) may be provided to a word line connected to a memory cell to be erased, and a word line connected to a memory cell for which erasure is prohibited may be floated.

[0148] Fig.12 The first storage block BLK1 shown in is exemplary. The number of cell strings can be increased or decreased, and the number of rows of cell strings and the number of columns of cell strings can be increased or decreased according to the number of cell strings. In the first storage block BLK1, the number of transistors (GST, MC, DMC, SST, etc.) can also be increased or decreased, and the height of the first storage block BLK1 can be increased or decreased according to the number of transistors. In addition, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the transistors can be increased or decreased according to the number of transistors.

[0149] Fig.13 FIG. 1 is a block diagram of a solid state hard disk system to which a storage device according to the present invention is applied. Fig.13 , the SSD system 1000 includes a host 1100 and an SSD 1200. The SSD 1200 exchanges a signal SIG with the host 1100 through a signal connector 1001, and is supplied with power PWR through a power connector 1002. The SSD 1200 may include an SSD controller 1210, a plurality of nonvolatile memories 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240.

[0150] The SSD controller 1210 may control the flash memories 1221 to 122n through corresponding channels CH1 to CHn in response to a signal SIG from the host 1100. In one embodiment, the SSD controller 1210 may control the flash memories 1221 to 122n based on the reference signal SIG. Figure 2 The components described above generate dump data and transmit the dump data to the host 1100. When a fault or error occurs, the SSD controller 1210 can report the fault event to the host 1100 using the sideband interface, and can receive a dump request using the sideband interface. If the dump data is completely stored, the SSD controller 1210 resets the in-band interface and transmits the dump data to the host 1100 using the reset in-band interface.

[0151] The auxiliary power supply 1230 is connected to the host 1100 through the power connector 1002. The auxiliary power supply 1230 can be charged by the power PWR from the host 1100. When power cannot be supplied smoothly from the host 1100, the auxiliary power supply 1230 can supply power to the SSD system 1000. The auxiliary power supply 1230 can be placed inside or outside the SSD 1200. For example, the auxiliary power supply 1230 can be located on the mainboard to provide auxiliary power to the SSD 1200.

[0152] The buffer memory 1240 acts as a buffer memory of the SSD 1200. For example, the buffer memory 1240 may temporarily store data received from the host 1100 or from the flash memories 1221 to 122n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 1221 to 122n. The buffer memory 1240 may include a volatile memory such as a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, a low power double data rate (LPDDR) SDRAM, a static RAM (SRAM), etc., or a non-volatile memory such as a ferroelectric RAM (FRAM), a resistive RAM (ReRAM), a spin transfer torque magnetoresistive RAM (STT-MRAM), a phase change RAM (PRAM), etc.

[0153] Fig.14 1 is a block diagram of a user system including a storage device according to an embodiment of the inventive concept. Fig.14 , the user system 2000 may include an application processor 2100 , a memory module 2200 , a network module 2300 , a storage module 2400 , and a user interface 2500 .

[0154] The application processor 2100 may drive components and an operating system included in the user system 2000. In one embodiment, the application processor 2100 may include a controller for controlling components of the user system 2000, a graphic engine, various interfaces, etc. The application processor 2100 may be implemented with a system on chip (SoC).

[0155] The memory module 2200 may operate as a main memory, a working memory, a buffer memory, or a cache memory of the user system 2000. The memory module 2200 may include a volatile random access memory such as DRAM, SDRAM, double data rate (DDR) SDRAM, DDR2SDRAM, DDR3SDRAM, LPDDR SDRAM, LPDDR3SDRAM, etc., or a nonvolatile random access memory such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0156] The network module 2300 can communicate with external devices. For example, the network module 2300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE TM ), Wimax, WLAN, UWB, Bluetooth, WI-DI, etc. In one embodiment, the network module 2300 may be included in the application processor 2100 .

[0157] The storage module 2400 may store data. For example, the storage module 2400 may store data received from the application processor 2100. Alternatively, the storage module 2400 may transmit the data stored therein to the application processor 2100. For example, the storage module 2400 may include a semiconductor memory device including, for example, PRAM, MRAM, RRAM, NAND flash memory, NOR flash memory, or a three-dimensional NAND flash memory.

[0158] The storage module 2400 may include a non-volatile memory device and a storage controller therein. The storage module 2400 may communicate with the application processor 2100 through an in-band interface and a sideband interface. When a fault occurs, the storage module 2400 receives a dump request by utilizing the sideband interface. If the dump data is completely stored, the storage module 2400 resets the in-band interface. The storage module 2400 may transmit the dump data to the application processor 2100 or the debugging device by utilizing the reset in-band interface.

[0159] The user interface 2500 may include an interface for inputting data or commands to the application processor 2100 or outputting data to an external device. The user interface 2500 may include a user input interface, such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, etc. The user interface 2500 may also include a user output interface, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, a light emitting diode (LED), a speaker, a motor, etc.

[0160] According to the embodiments of the present invention, dump data generated when a storage device fails or an error occurs can be obtained at high speed. In addition, the storage device of the present invention can generate dump data for debugging without losing the state data of the interface at the time point when the failure or error occurs or corresponding to the time point when the failure or error occurs. Therefore, the storage device of the present invention can achieve highly reliable debugging and can significantly reduce the debugging cost.

[0161] While the inventive concept has been described with reference to exemplary embodiments of the inventive concept, it will be apparent to those skilled in the art that various changes and modifications may be made to the exemplary embodiments without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A storage device, comprising: a storage device, the storage device comprising a dump area; as well as A storage controller, wherein the storage controller is configured to: receiving a dump request from a host via a first host interface when an error occurs, generating, in response to the dump request, dump data for debugging, the dump data including state information of the storage device, storing the dump data in the dump area, When the dump data is completely stored, resetting the second host interface, and After resetting the second host interface, transmitting the stored dump data to the host using the second host interface, wherein the first host interface comprises a sideband interface, and the second host interface comprises an in-band interface, and The in-band interface is reset in response to a reset request from the host.

2. The storage device according to claim 1, wherein: The storage controller is further configured to, after storing the dump data in the dump area, reset at least one component among a plurality of components of the storage device.

3. The storage device according to claim 1, wherein: The dump data includes first dump data and second dump data, the first dump data includes data that will be lost when the second host interface is reset, and the second dump data includes data that will not be lost when the second host interface is reset, The first dump data and the second dump data are stored in separate areas of the dump area.

4. The storage device according to claim 1, wherein: The storage controller is further configured to transmit a completion response to the host using the first host interface after storing the dump data in the dump area.

5. The storage device according to claim 1, wherein: The storage controller is further configured to receive, from the host using the second host interface, a reset request for resetting the second host interface.

6. The storage device according to claim 1, wherein: The storage controller comprises: a working memory configured to load a dump storage module and a dump transmission module, the dump storage module being configured to collect the dump data in response to the dump request and store the collected dump data in the dump area as the stored dump data, the dump transmission module being configured to transmit the stored dump data to the host using the second host interface; and A central processing unit is configured to execute the dump storage module and the dump transmission module.

7. The storage device according to claim 6, wherein: The central processing unit is configured to transmit the stored dump data to the host by executing the dump transmission module after resetting the second host interface.

8. The storage device according to claim 1, wherein: The first host interface includes at least one of an inter-integrated circuit bus interface, a system management bus interface, a universal asynchronous receiver-transmitter interface, a serial peripheral interface, and a high-speed chip-to-chip interconnect interface.

9. The storage device according to claim 1, wherein: The second host interface includes at least one of a Serial Advanced Technology Attachment interface, a Serial Attached SCSI, a Peripheral Component Interconnect interface, a PCI Express interface, a Non-Volatile Memory Host Controller interface, a Universal Flash Storage interface, and an Embedded MMC interface.

10. The storage device according to claim 1, wherein: The memory device includes a buffer memory and a non-volatile memory device, The dump data is stored in the buffer memory or the non-volatile memory device.

11. A debugging method for a storage device, wherein the storage device communicates with a host via a sideband interface and an in-band interface, the debugging method comprising: When an error occurs, the storage device receives a dump request from the host through the sideband interface; In response to the dump request, the storage device generates dump data for debugging, wherein the dump data includes status information of the storage device; The storage device stores the dump data in a storage device; When the dump data is completely stored, the storage device receives a reset request from the host to reset the in-band interface; Resetting the in-band interface by the storage device in response to the reset request; as well as After the in-band interface is completely reset, the storage device transmits the stored dump data to the host through the in-band interface.

12. The debugging method according to claim 11, wherein: The dump data includes first dump data and second dump data, the first dump data includes data that will be lost during the reset, and the second dump data includes data that will not be lost during the reset, The storing of the dump data comprises: the storage device first stores the first dump data in the storage device.

13. The debugging method according to claim 11, further comprising: After the dump data is stored in the storage device, at least one of a central processing unit, a work memory and the storage device included in the storage apparatus is reset.

14. The debugging method according to claim 11, wherein: The reset request is received as a command or control signal of the in-band interface.

15. A computing system, comprising: a storage device, the storage device comprising a first host interface and a second host interface, the storage device being configured to collect dump data including state information of the storage device for debugging, and to store the dump data in response to a dump request when an error occurs; as well as A host, the host being configured as: transmitting the dump request to the storage device using the first host interface, In response to information transmitted from the storage device indicating that the dump data is completely stored, transmitting a reset request for the second host interface to the storage device, After resetting the second host interface in response to the reset request for the second host interface, reading the stored dump data using the second host interface, Before receiving the reset request for the second host interface, the storage device resets at least one component among the multiple components of the storage device, and The second host interface is reset in response to a reset request from the host.

16. The computing system of claim 15, wherein: The dump data includes first state information of the second host interface, and the storage device is configured to first store the first state information as the dump data before the second host interface is reset.

17. The computing system of claim 15, wherein: The storage apparatus further includes a nonvolatile memory device configured to store the dump data.

18. The computing system of claim 15, wherein: The host is configured to transmit the reset request to the storage device as a control signal to the second host interface.

19. The computing system of claim 15, wherein: The host is configured to transmit the read dump data to a remote debugging host through a network.

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