Integrated fan-out package and manufacturing method thereof

Abstract

An integrated fan-out package includes a tube core, an encapsulation body, a rewiring structure, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulation body encapsulates the tube core. The rewiring structure is located on the tube core and the encapsulation body. The rewiring structure is electrically connected to the tube core and includes a plurality of dielectric layers stacked in sequence and a plurality of conductive patterns sandwiched between the dielectric layers. The Young's modulus of the dielectric layer farthest from the tube core is higher than the Young's modulus of each of the remaining dielectric layers in the dielectric layer. The conductive patterns are electrically connected to each other. The conductive pillar is arranged on the rewiring structure and is electrically connected to the rewiring structure. The seed layer is located between the conductive pillar and the rewiring structure. The conductive bump is arranged on the plurality of conductive pillars.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated fan-out package. More specifically, embodiments of the present invention relate to an integrated fan-out package with an anti-stress layer. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the repeated reduction of the minimum feature size, which enables more smaller components to be integrated into a given area. Currently, integrated fan-out packages are becoming increasingly popular due to their compactness. Integrated fan-out packages typically include a rewiring structure located on a molded integrated circuit device so that the integrated circuit device can be accessed. To meet the requirements of smaller size and higher packaging density, the manufacturing method of the rewiring structure has become an important issue in the field. Summary of the invention

[0003] An integrated fan-out package includes a tube core, an encapsulation body, a rewiring structure, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulation body encapsulates the tube core. The rewiring structure is located on the tube core and the encapsulation body. The rewiring structure is electrically connected to the tube core and includes a plurality of dielectric layers stacked in sequence and a plurality of conductive patterns sandwiched between the dielectric layers. The Young's modulus of the dielectric layer farthest from the tube core is higher than the Young's modulus of each of the remaining dielectric layers in the dielectric layer. The conductive patterns are electrically connected to each other. The conductive pillar is arranged on the rewiring structure and is electrically connected to the rewiring structure. The seed layer is located between the conductive pillar and the rewiring structure. The conductive bump is arranged on the conductive pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figures 1A to 1F Schematic cross-sectional views showing various processes of a method for manufacturing an integrated fan-out package according to some embodiments of the present invention.

[0006] Figures 2A to 2K It is a schematic enlarged cross-sectional view showing various processes of a method for manufacturing an exemplary package according to some embodiments of the present invention, with a region R as an emphasis.

[0007] FIG. 3A to FIG. 3JSchematic enlarged cross-sectional views showing various processes of a method for manufacturing an exemplary package according to some alternative embodiments of the present invention with emphasis on region R.

[0008] FIG. 4A to FIG. 4J Schematic enlarged cross-sectional views showing various processes of a method for manufacturing an exemplary package according to some alternative embodiments of the present invention with emphasis on region R.

[0009] Figure 5A is a schematic enlarged cross-sectional view showing exemplary packages according to some alternative embodiments of the present invention with emphasis on region R.

[0010] Figure 5B Show Figure 5A Schematic top view of the buffer layer and the conductive pillar shown in FIG.

[0011] FIG. 6A to FIG. 6I Schematic enlarged cross-sectional views showing various processes of a method for manufacturing an exemplary package according to some alternative embodiments of the present invention with emphasis on region R.

[0012] Fig. 7A is a schematic enlarged cross-sectional view showing exemplary packages according to some alternative embodiments of the present invention with emphasis on region R.

[0013] Figure 7B Show Fig. 7A Schematic top view of the buffer layer and the conductive pillar shown in FIG.

[0014] Figure 8 Shown including Figure 1F Schematic diagram of the stacked package structure of the integrated fan-out package.

[0015] Description of Figure Numbers

[0016] 10: Integrated fan-out packaging

[0017] 20: Substrate

[0018] 30: Printed Circuit Board

[0019] 100, 100a: tube core

[0020] 110: Semiconductor substrate

[0021] 120: Conductive pad

[0022] 130: Passivation layer

[0023] 140: Post passivation layer

[0024] 150, 150a: Conductive column

[0025] 160, 160a: Protective layer

[0026] 200: Encapsulation material

[0027] 200a: Encapsulated body

[0028] 300: Rewiring Structure

[0029] 310, 316: Dielectric material layer

[0030] 310a: first dielectric layer

[0031] 312a: Second dielectric layer

[0032] 314a: third dielectric layer

[0033] 316a: fourth dielectric layer

[0034] 320a: first conductive pattern

[0035] 322a: second conductive pattern

[0036] 324a: third conductive pattern

[0037] 410, 410a: seed layer

[0038] 412, 412a: second seed layer

[0039] 420: Conductive column

[0040] 420a: first conductive material

[0041] 420b: second conductive material

[0042] 430: Solder material

[0043] 500: Conductive bump

[0044] 600, 600a: Buffer layer

[0045] C: Carrier substrate

[0046] DB: Debonding layer

[0047] O 310a , O 316a , O 600a : Open mouth

[0048] P1: Part 1

[0049] P2: Part 2

[0050] PR: Photoresist pattern layer

[0051] PR1: First photoresist pattern layer

[0052] PR2: Second photoresist pattern layer

[0053] R: Area

[0054] SW 316a : Sidewall

[0055] W1: Maximum diameter

[0056] W2: Distance DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed "on" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, thereby making the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0058] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0059] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3D integrated circuit, 3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate to allow testing of a three-dimensional package or a three-dimensional integrated circuit, use of a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to improve yield and reduce cost.

[0060] Figures 1A to 1FSchematic cross-sectional views of various processes of a method for manufacturing an integrated fan-out package 10 according to some embodiments of the present invention are shown. Figure 1A , providing a carrier substrate C on which a peeling layer DB is formed. In some embodiments, the carrier substrate C may be a glass substrate, and the peeling layer DB may be a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some embodiments, a dielectric layer (not shown) may be optionally formed on the peeling layer DB.

[0061] like Figure 1A As shown in FIG. 1 , a plurality of dies 100 are provided and placed on a carrier substrate C. In some embodiments, the dies 100 may be placed on a peeling layer DB by a pick and place process. The dies 100 may be attached or bonded to the peeling layer DB by a die attach film (DAF), an adhesion paste, etc. For simplicity, FIG. Figure 1A Only one die 100 is shown. However, more than one die may be provided and the die may be arranged in an array. It should be understood that the scope of the present invention is not limited by the disclosed examples. In some embodiments, the current process steps may be considered as part of a wafer level packaging process.

[0062] In some embodiments, Figure 1AAs shown in , each die 100 includes a semiconductor substrate 110, a plurality of conductive pads 120, a passivation layer 130, a post-passivation layer 140, a plurality of conductive pillars 150, and a protective layer 160. In some embodiments, the semiconductor substrate 110 may be a silicon substrate, which includes active components (e.g., transistors, etc.) formed in the silicon substrate and passive components (e.g., resistors, capacitors, inductors, etc.) optionally formed in the silicon substrate. The conductive pads 120 are formed on the semiconductor substrate 110 and may be aluminum pads, copper pads, or other suitable metal pads. The conductive pillars 150 are disposed on the conductive pads 120 and are electrically connected to the conductive pads 120. In some embodiments, the conductive pillars 150 are formed on the conductive pads 120 by a plating process of a conductive material. In some embodiments, the conductive pillars 150 may be copper-plated pillars or other suitable metal pillars. In some alternative embodiments, the conductive pillar 150 is a copper pillar or other suitable metal pillar covered by a solder cap (e.g., a lead-free solder cap). In some embodiments, the protective layer 160 may be a polymer layer having a thickness sufficient to encapsulate and protect the conductive pillar 150. In some embodiments, the material of the protective layer 160 includes polybenzoxazole (PBO), polyimide (PI), or other suitable polymeric materials. In some alternative embodiments, the protective layer 160 may be made of an inorganic material. In some embodiments, the post-passivation layer 140 is optional.

[0063] Reference Figure 1B , an encapsulation material 200 is formed on the peeling layer DB to encapsulate the tube die 100. In other words, all the tube dies 100 (in Figure 1B In some embodiments, the encapsulation material 200 is formed by a molding process. The conductive pillars 150 and the protective layer 160 of the die 100 are completely covered by the encapsulation material 200. In other words, the conductive pillars 150 and the protective layer 160 of the die 100 are not exposed and are well protected by the encapsulation material 200. In some alternative embodiments, the material of the encapsulation material 200 includes epoxy resin or other suitable dielectric materials.

[0064] Reference Figure 1CThen, the encapsulation material 200 is ground until the conductive pillar 150 is exposed to form the encapsulation body 200a. In some embodiments, the encapsulation material 200 is ground by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process. During the grinding process of the encapsulation material 200, a portion of the protection layer 160 and a portion of the conductive pillar 150 are ground to form the protection layer 160a and the conductive pillar 150a. Figure 1C As shown in FIG. 1 , the encapsulant 200a surrounds the die 100a and laterally encapsulates the sidewalls of the die 100a. In other words, the encapsulant 200a surrounds and wraps the die 100a (in FIG. 1 ). Figure 1C In some embodiments, the top surface of the encapsulant 200a, the top surface of the conductive pillar 150a, and the top surface of the protection layer 160a are substantially coplanar and flush with each other.

[0065] Reference Figure 1D , a rewiring structure 300 covering the die 100a is formed on the encapsulation body 200a. In some embodiments, a seed layer 410a and a plurality of conductive pillars 420 are subsequently formed on the rewiring structure 300. Thereafter, a plurality of conductive bumps 500 are formed on the conductive pillars 420. In some embodiments, the conductive pillars 420 and the conductive bumps 500 are collectively referred to as controlled collapse chip connect (C4) bumps. Figure 1D, region R is surrounded by a dotted line, and region R will be further shown later to illustrate the connection between the rewiring structure 300, the conductive pillar 420, and the conductive bump 500. Such region R may be shown in a schematic enlarged view to further illustrate the manufacturing process and possible structural changes in the following paragraphs. In some embodiments, the rewiring structure 300 includes a first dielectric layer 310a, a second dielectric layer 312a, a third dielectric layer 314a, and a fourth dielectric layer 316a stacked in sequence. In some embodiments, the rewiring structure 300 also includes a plurality of first conductive patterns 320a, a plurality of second conductive patterns 322a, and a plurality of third conductive patterns 324a electrically connected to each other. The first conductive pattern 320a is sandwiched between the first dielectric layer 310a and the second dielectric layer 312a. Similarly, the second conductive pattern 322a and the third conductive pattern 324a are sandwiched between the second dielectric layer 312a and the third dielectric layer 314a and between the third dielectric layer 314a and the fourth dielectric layer 316a, respectively. In some embodiments, the redistribution structure 300 is electrically connected to the die 100a. For example, the first conductive pattern 320a may contact the conductive pillar 150a of the die 100a to achieve electrical connection between the two. In some embodiments, for a redistribution structure having four dielectric layers, the fourth dielectric layer 316a is referred to as being in contact with the die 100a (at Figure 1DIn certain embodiments, the dielectric layer farthest from the die 100a or the dielectric layer for receiving the conductive pillar 420 has a Young's modulus (elastic modulus) higher than other dielectric layers of the redistribution structure 300. Similarly, the third conductive pattern 324a is referred to as the conductive pattern farthest from the die 100a in a direction perpendicular to the top surface of the die 100a. In some embodiments, the Young's modulus of the fourth dielectric layer 316a is higher than the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, and the Young's modulus of the third dielectric layer 314a. In some embodiments, the Young's modulus of the fourth dielectric layer 316a is in the range of 0.5 GPa to 150 GPa. On the other hand, the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, and the Young's modulus of the third dielectric layer 314a are in the range of 0.1 GPa to 100 GPa. In a specific embodiment, the ratio of the Young's modulus of the fourth dielectric layer 316a to the Young's modulus of the first dielectric layer 310a, the second dielectric layer 312a, or the third dielectric layer 314a is in the range of 1.05 to 100. When the ratio of the Young's modulus is lower than 1.05, the fourth dielectric layer 316a cannot withstand the stress generated from the conductive pillars 420, and the conductive pattern in the redistribution structure 300 is deformed. On the other hand, when the ratio of the Young's modulus exceeds 100, the fourth dielectric layer 316a will exhibit a hardness similar to that of pure silicon, thereby increasing the difficulty of processing. In some embodiments, the thickness of the fourth dielectric layer 316a is greater than the thickness of the first dielectric layer 310a, the thickness of the second dielectric layer 312a, or the thickness of the third dielectric layer 314a. In some embodiments, the higher Young's modulus enables the fourth dielectric layer 316a to mitigate or block the stress applied from the conductive pillars 420 to the underlying redistribution structure 300, thereby protecting the conductive patterns in the redistribution structure 300 from damage due to stress generated during the assembly process and / or thermal process. In other words, the fourth dielectric layer 316a with a higher Young's modulus helps to mitigate the fine line deformation problem in the redistribution structure 300. Therefore, in some embodiments, the fourth dielectric layer 316a of the redistribution structure 300 can be referred to as an anti-stress layer. It should be noted that although Figure 1D Four dielectric layers and three conductive pattern layers are depicted, however this configuration serves only as an example. In some alternative embodiments, the redistribution structure 300 may include more or fewer layers of dielectric layers and conductive pattern layers.

[0066] like Figure 1DAs shown in FIG. 4 , in some embodiments, a seed layer 410a is formed before forming the conductive pillar 420 and the seed layer 410a is sandwiched between the conductive pillar 420 and the redistribution structure 300. In some embodiments, the conductive pillar 420 is electrically connected to the redistribution structure 300. For example, the conductive pillar 420 can be electrically connected to the third conductive pattern 324a. Figures 2A to 2K , FIG. 3A to FIG. 3J , FIG. 4A to FIG. 4J , Figure 5A , FIG. 6A to FIG. 6I ,and Fig. 7A The formation of the redistribution wiring structure 300 , the seed layer 410 a , the conductive pillars 420 , and the conductive bumps 500 will be discussed in more detail.

[0067] Reference Figure 1E , including the conductive bump 500, the conductive column 420, the redistribution structure 300, the encapsulation body 200a, and the tube core 100a (in Figure 1F The integrated fan-out package array (only one die is shown in the figure) is peeled off from the peeling layer DB so that the die 100a and the encapsulant 200a are separated from the carrier substrate C. In some embodiments, the peeling layer DB (for example, the light-to-heat conversion release layer) can be irradiated with an ultraviolet laser (UV laser) to peel the peeling layer DB from the die 100a and the encapsulant 200a to obtain the integrated fan-out package array.

[0068] Reference Figure 1F , the integrated fan-out package array is cut or singulated to form a plurality of integrated fan-out packages 10. In some embodiments, the cutting process or singulation process generally involves cutting using a rotating blade or a laser beam. In other words, the cutting process or singulation process is, for example, a laser cutting process, a mechanical cutting process, or other suitable processes.

[0069] Figures 2A to 2K It is a schematic enlarged cross-sectional view showing various processes of a method for manufacturing an exemplary package according to some embodiments of the present invention, with a region R as an emphasis. Figures 2A to 2K Shown for use in Figure 1C to Figure 1D Detailed process steps for forming the redistribution structure 300, the conductive pillar 420, and the conductive bump 500 on the package 200a and the die 100a having structures similar to those shown in FIG. Figure 2A, a dielectric material layer 310 is formed on the protective layer 160a, the conductive pillars 150a, and the encapsulation body 200a. In some embodiments, the material of the dielectric material layer 310 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer-based dielectric material. In some embodiments, the Young's modulus of the dielectric material layer 310 is in the range of 0.1 GPa to 100 GPa and the thickness is in the range of 1 micrometer (μm) to 50 μm. For example, the dielectric material layer 310 can be formed by suitable manufacturing techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0070] Reference Figure 2B In some embodiments, the dielectric material layer 310 is patterned to form a dielectric layer having a plurality of openings O 310a In some embodiments, the opening O 310a The conductive pillar 150a under the first dielectric layer 310a is exposed. The dielectric material layer 310 can be patterned by a photolithography process and an etching process. Thereafter, a first conductive pattern 320a is formed on the first dielectric layer 310a. In some embodiments, the first conductive pattern 320a extends to the opening O. 310a The first conductive pattern 320a may be formed by, for example, electroplating, deposition, and / or photolithography and etching. In some embodiments, the material of the first conductive pattern 320a includes aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof.

[0071] Reference Figure 2C , repeat with Figure 2BThe process steps described in the relevant context are to sequentially form the second dielectric layer 312a, the second conductive pattern 322a, the third dielectric layer 314a, and the third conductive pattern 324a. In some embodiments, the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, and the material of the third dielectric layer 314a may be the same. In some embodiments, the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, and the material of the third dielectric layer 314a may be different as long as their respective Young's moduli fall within the range of 0.1 GPa to 100 GPa. Similarly, the material of the first conductive pattern 320a, the material of the second conductive pattern 322a, and the material of the third conductive pattern 324a may be the same or different.

[0072] Reference Figure 2D and Figure 2E , a fourth dielectric layer 316a is formed on the third dielectric layer 314a and the third conductive pattern 324a. In some embodiments, a dielectric material layer 316 may be first formed on the third dielectric layer 314a and the third conductive pattern 324a. Subsequently, the dielectric material layer 316 is patterned to form a plurality of openings. 316a The fourth dielectric layer 316a. 316a The third conductive pattern 324a under the fourth dielectric layer 316a is exposed. In some embodiments, the dielectric material layer 316 may be patterned by a photolithography process and an etching process. In some embodiments, the material of the fourth dielectric layer 316a is different from the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, and the material of the third dielectric layer 314a. For example, the material of the fourth dielectric layer 316a may include a molding compound material such as an epoxy resin or a phenolic resin. In some embodiments, the fourth dielectric layer 316a may also include a filler. In some embodiments, the material of the fourth dielectric layer 316a may include polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer-based dielectric material. In some embodiments, the Young's modulus of the fourth dielectric layer 316a is higher than the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, and the Young's modulus of the third dielectric layer 314a. For example, the Young's modulus of the fourth dielectric layer 316a may be in the range of 0.5 GPa to 150 GPa.

[0073] Reference Figure 2F In some embodiments, a covering opening O is formed on the fourth dielectric layer 316a. 316a The seed layer 410 is Figure 2F As shown in the figure, to cover the opening O 316aThe seed layer 410 is formed in a conformal manner to the contour of the opening O. That is, the seed layer 410 extends to the opening O. 316a Thus covering the opening O 316a The seed layer 410 may be formed by, for example, a sputtering process, a physical vapor deposition (PVD) process, etc. In some embodiments, the seed layer 410 may include, for example, copper, a titanium-copper alloy, or other suitable material selections.

[0074] Reference Figure 2G , a photoresist pattern layer PR is formed on the seed layer 410. In some embodiments, the photoresist pattern layer PR exposes the opening O 316a The seed layer 410 in the fourth dielectric layer 316a and the opening O are exposed. 316a At least part of the surrounding area.

[0075] Reference Figure 2H In some embodiments, at the opening O 316a The conductive pillar 420 is formed on the seed layer 410 in the photoresist pattern layer PR. In some embodiments, a conductive material (not shown in the figure) is deposited on the exposed seed layer 410 to form the conductive pillar 420. Subsequently, a solder material 430 is deposited on the conductive pillar 420. The conductive pillar 420 and the solder material 430 are located in the opening of the photoresist pattern layer PR. In other words, the conductive pillar 420 and the solder material 430 are formed using the photoresist pattern layer PR as a mask. In some embodiments, the conductive material and the solder material 430 can be formed by a plating process. The plating process is, for example, electroplating, electroless-plating, immersion plating, etc. In some embodiments, the conductive material includes, for example, copper, copper alloy, etc.

[0076] Reference Fig.2I , the photoresist pattern layer PR is removed and the portion of the seed layer 410 not covered by the conductive pillars 420 and the solder material 430 is exposed. The photoresist pattern layer PR may be removed / stripped by, for example, an etching process, an ashing process, or other suitable removal processes.

[0077] Reference Figure 2J, remove the seed layer 410 that is not covered by the conductive pillar 420 and the solder material 430 to obtain the seed layer 410a sandwiched between the conductive pillar 420 and the fourth dielectric layer 316a and between the conductive pillar 420 and the third conductive pattern 324a. The exposed portion of the seed layer 410 can be removed by an etching process. In some embodiments, the material of the conductive pillar 420 can be different from the material of the seed layer 410, and thus the exposed portion of the seed layer 410 can be removed by selective etching. In some embodiments, the conductive pillar 420 can be divided into a first portion P1 and a second portion P2. The first portion P1 is embedded in the fourth dielectric layer 316a, and the second portion P2 is located on the fourth dielectric layer 316a. As Figure 2J As shown in FIG. 4 , the seed layer 410 a is located between the second portion P2 and the fourth dielectric layer 316 a , between the first portion P1 and the fourth dielectric layer 316 a , and between the first portion P1 and the third conductive pattern 324 a . Figure 2K , a reflow process is performed on the solder material 430 to transform the solder material 430 into the conductive bump 500. Figure 2K As shown in , after the reflow process, the conductive bump 500 presents a hemispherical shape. However, the embodiments of the present invention are not limited thereto. In some alternative embodiments, after the reflow process, the conductive bump 500 may present other shapes.

[0078] FIG. 3A to FIG. 3J Schematic enlarged cross-sectional views showing various processes of a method for manufacturing an exemplary package according to some alternative embodiments of the present invention with emphasis on region R. FIG. 3A to FIG. 3J The encapsulation body 200a and the die 100a are used to form Figure 1C to Figure 1D Detailed process steps of the redistribution structure 300, the conductive pillar 420, and the conductive bump 500 are similar to those shown in FIG. Figure 3A , a first dielectric layer 310a, a first conductive pattern 320a, a second dielectric layer 312a, a second conductive pattern 322a, a third dielectric layer 314a, and a third conductive pattern 324a are sequentially formed on the die 100a and the package 200a. The process steps for forming these elements are similar to FIG. 2A to FIG. 2C The process steps shown in are similar, so they will not be described in detail in this article.

[0079] Reference Figure 3B , a first seed layer 410 is formed on the third dielectric layer 314a and the third conductive pattern 324a. The first seed layer 410 can be formed by, for example, a sputtering process, a physical vapor deposition (PVD) process, etc. In some embodiments, the first seed layer 410 can include, for example, copper, a titanium-copper alloy, or other suitable material selections.

[0080] Reference Figure 3C , a first photoresist pattern layer PR1 is formed on the first seed layer 410. In some embodiments, the first photoresist pattern layer PR1 exposes at least a portion of the first seed layer 410 located on the third conductive pattern 324a.

[0081] Reference Figure 3D , using the first photoresist pattern layer PR1 as a mask, a first conductive material 420a is deposited onto the exposed first seed layer 410. In some embodiments, the first conductive material 420a may be formed by a plating process. The plating process is, for example, electroplating, electroless plating, immersion plating, etc. In some embodiments, the first conductive material 420a includes, for example, copper, copper alloy, etc.

[0082] Reference Figure 3D and Figure 3E , remove the first photoresist pattern layer PR1 and expose the portion of the first seed layer 410 not covered by the first conductive material 420a. The first photoresist pattern layer PR1 can be removed / stripped by, for example, an etching process, an ashing process, or other suitable removal processes. Subsequently, the first seed layer 410 not covered by the first conductive material 420a is removed to obtain the first seed layer 410a sandwiched between the first conductive material 420a and the third conductive pattern 324a. The exposed portion of the first seed layer 410 can be removed by an etching process.

[0083] Reference Figure 3F , a fourth dielectric layer 316a is formed around the first seed layer 410a and the first conductive material 420a. Figures 2A to 2K Similar to the embodiment shown, in some embodiments, the material of the fourth dielectric layer 316a is different from the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, and the material of the third dielectric layer 314a. For example, the Young's modulus of the fourth dielectric layer 316a is higher than the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, and the Young's modulus of the third dielectric layer 314a. In some embodiments, based on the higher Young's modulus, the fourth dielectric layer 316a of the redistribution structure 300 can be referred to as an anti-stress layer.

[0084] Reference Figure 3G , a second seed layer 412 may be formed on the fourth dielectric layer 316a and the first conductive material 420a. Subsequently, a second photoresist pattern layer PR2 is formed on the second seed layer 412. In some embodiments, the second photoresist pattern layer PR2 exposes at least a portion of the second seed layer 412 located on the first conductive material 420a. The second seed layer 412 may be similar to the first seed layer 410 and the second photoresist pattern layer PR2 may be similar to the first photoresist pattern layer PR1, and thus will not be described in detail herein.

[0085] Reference Figure 3H , using the second photoresist pattern layer PR2 as a mask, a second conductive material 420b and a solder material 430 are deposited onto the exposed second seed layer 412. The second conductive material 420b may be similar to the first conductive material 410b, and thus will not be described in detail herein.

[0086] Reference Figure 3H and Fig. 3I , remove the second photoresist pattern layer PR2 and expose the portion of the second seed layer 412 not covered by the second conductive material 420b and the solder material 430. The second photoresist pattern layer PR2 can be removed / stripped by, for example, an etching process, an ashing process, or other suitable removal processes. Subsequently, the second seed layer 412 not covered by the second conductive material 420b and the solder material 430 is removed to obtain a second seed layer (additional seed layer) 412a sandwiched between the second conductive material 420b and the first conductive material 420a and between the second conductive material 420b and the fourth dielectric layer 316a. The exposed portion of the second seed layer 412 can be removed by an etching process. Refer to Fig. 3I , the first conductive material 420a and the second conductive material 420b constitute a conductive pillar 420. In some embodiments, the first conductive material 420a may be referred to as a first portion P1 of the conductive pillar 420 embedded in the fourth dielectric layer 316a. On the other hand, the second conductive material 420b may be referred to as a second portion P2 of the conductive pillar 420 located on the fourth dielectric layer 316a. The first seed layer 410a is located between the first portion P1 and the third conductive pattern 324a. The second seed layer 412a is located between the first portion P1 and the second portion P2 and between the fourth dielectric layer 316a and the second portion P2. Figure 3J , a reflow process is performed on the solder material 430 to transform the solder material 430 into the conductive bump 500 .

[0087] FIG. 4A to FIG. 4J So Figure 1C A region R in FIG. 1 is a schematic enlarged cross-sectional view focusing on illustrating each process of a method for manufacturing an exemplary package according to some alternative embodiments of the present invention. FIG. 4A to FIG. 4J The encapsulation body 200a and the die 100a are used to form Figure 1C to Figure 1D Detailed process steps of the redistribution structure 300, the buffer layer 600a, the conductive pillar 420, and the conductive bump 500 are similar to those shown in FIG. Figure 4A , a first dielectric layer 310a, a first conductive pattern 320a, a second dielectric layer 312a, a second conductive pattern 322a, a third dielectric layer 314a, and a third conductive pattern 324a are sequentially formed on the die 100a and the package 200a. The process steps for forming these elements are similar to FIG. 2A to FIG. 2CThe process steps shown in are similar, so they will not be described in detail in this article.

[0088] Reference Figure 4B and Figure 4C , a fourth dielectric layer 316a is formed on the third dielectric layer 314a and the third conductive pattern 324a. A dielectric material layer 316 may be first formed on the third dielectric layer 314a and the third conductive pattern 324a. Subsequently, the dielectric material layer 316 is patterned to form a plurality of openings. 316a The fourth dielectric layer 316a. 316a At least a portion of the third conductive pattern 324a located under the fourth dielectric layer 316a is exposed. In some embodiments, the dielectric material layer 316 can be patterned by a photolithography process and an etching process. In some embodiments, the material of the fourth dielectric layer 316a is the same as the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, and the material of the third dielectric layer 314a. In some embodiments, the fourth dielectric layer 316a is referred to as the dielectric layer farthest from the tube core 100a in a direction perpendicular to the top surface of the tube core 100a. Similarly, the third conductive pattern 324a is referred to as the conductive pattern farthest from the tube core 100a in a direction perpendicular to the top surface of the tube core 100a. In some embodiments, the first dielectric layer 310a, the second dielectric layer 312a, the third dielectric layer 314a, the fourth dielectric layer 316a, the first conductive pattern 320a, the second conductive pattern 322a, and the third conductive pattern 324a constitute the rewiring structure 300.

[0089] Reference Figure 4D, a buffer layer 600 is formed on the fourth dielectric layer 316a and the third conductive pattern 324a. In some embodiments, the material of the buffer layer 600 is different from the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, the material of the third dielectric layer 314a, and the material of the fourth dielectric layer 316a. For example, the material of the buffer layer 600 may include a molding compound material such as an epoxy resin or a phenolic resin. In some embodiments, the buffer layer 600 may also include a filler. In some embodiments, the material of the buffer layer 600 may include polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer-based dielectric material. In some embodiments, the Young's modulus of the buffer layer 600 is higher than the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, the Young's modulus of the third dielectric layer 314a, and the Young's modulus of the fourth dielectric layer 316a. For example, the Young's modulus of the buffer layer 600 is in the range of 0.5 GPa to 150 GPa. On the other hand, the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, the Young's modulus of the third dielectric layer 314a, and the Young's modulus of the fourth dielectric layer 316a are in the range of 0.1 GPa to 100 GPa. In a specific embodiment, the ratio of the Young's modulus of the buffer layer 600 to the Young's modulus of the first dielectric layer 310a, the second dielectric layer 312a, the third dielectric layer 314a, or the fourth dielectric layer 316a is in the range of 1.05 to 100. When the ratio of the Young's modulus is lower than 1.05, the buffer layer 600 cannot withstand the stress generated from the conductive pillar 420, and the conductive pattern in the redistribution structure 300 is deformed. On the other hand, when the ratio of the Young's modulus exceeds 100, the buffer layer 600 will present a hardness similar to that of pure silicon, thereby increasing the difficulty of processing. In some embodiments, the thickness of the buffer layer 600 is greater than the thickness of the first dielectric layer 310a, the thickness of the second dielectric layer 312a, the thickness of the third dielectric layer 314a, or the thickness of the fourth dielectric layer 316a. In some embodiments, the higher Young's modulus enables the buffer layer 600 to alleviate or block the stress applied to the underlying rewiring structure 300 from the conductive pillar 420, thereby protecting the conductive pattern in the rewiring structure 300 from damage due to the stress generated during the assembly process and / or thermal process. In other words, the buffer layer 600 with a higher Young's modulus helps to alleviate the fine line deformation problem in the rewiring structure 300. Therefore, in some embodiments, the buffer layer 600 can be referred to as an anti-stress layer.

[0090] Reference Figure 4E The buffer layer 600 is patterned to form a plurality of openings O 600a The buffer layer 600a is provided. 600a Larger than opening O 316a, so that the opening O 600a The opening O exposing the fourth dielectric layer 316a 316a and at least a portion of the fourth dielectric layer 316a.

[0091] Reference Figure 4F In some embodiments, a covering opening O is formed on the buffer layer 600a. 316a and opening O 600a The seed layer 410 is Figure 4F As shown in the figure, to cover the opening O 316a and opening O 600a The seed layer 410 is formed in a conformal manner to the contour of the opening O. That is, the seed layer 410 extends to the opening O. 316a and opening O 600a Thus covering the opening O 316a and opening O 600a The seed layer 410 may be formed by, for example, a sputtering process, a physical vapor deposition (PVD) process, etc. In some embodiments, the seed layer 410 may include, for example, copper, a titanium-copper alloy, or other suitable material selections.

[0092] Reference Figure 4G , a photoresist pattern layer PR is formed on the seed layer 410. In some embodiments, the photoresist pattern layer PR exposes the opening O 316a and opening O 600a The photoresist pattern layer PR also exposes the seed layer 410 located on the buffer layer 600 and the opening O. 600a At least part of the surrounding area.

[0093] Reference Figure 4H In some embodiments, at the opening O 316a and opening O 600a The conductive pillar 420 is formed on the seed layer 410 in the exposed region. In some embodiments, a conductive material (not shown) is deposited on the exposed seed layer 410 to form the conductive pillar 420. Subsequently, a solder material 430 is deposited on the conductive pillar 420. In some embodiments, the conductive material and the solder material 430 can be formed by a plating process. The plating process is, for example, electroplating, electroless plating, immersion plating, etc. In some embodiments, the conductive material includes, for example, copper, copper alloy, etc.

[0094] Reference Figure 4H and Fig. 4I, remove the photoresist pattern layer PR and expose the portion of the seed layer 410 that is not covered by the conductive pillar 420 and the solder material 430. The photoresist pattern layer PR can be removed / stripped by, for example, an etching process, an ashing process, or other suitable removal processes. Subsequently, the seed layer 410 that is not covered by the conductive pillar 420 and the solder material 430 is removed to obtain a seed layer 410a sandwiched between the conductive pillar 420 and the buffer layer 600a, between the conductive pillar 420 and the fourth dielectric layer 316a, and between the conductive pillar 420 and the third conductive pattern 324a. The exposed portion of the seed layer 410 can be removed by an etching process. Refer to Figure 4J , a reflow process is performed on the solder material 430 to transform the solder material 430 into the conductive bump 500 .

[0095] Figure 5A is a schematic enlarged cross-sectional view showing exemplary packages according to some alternative embodiments of the present invention with emphasis on region R. Figure 5B Show Figure 5A Schematic top view of the buffer layer 600a and the conductive pillar 420 in FIG. In addition to the position or coverage of the buffer layer 600a, Figure 5A The structure shown in Figure 4J In other words, by FIG. 4A to FIG. 4J The process steps are similar to those shown in Figure 5A In some embodiments, an additional step of removing at least a portion of the buffer layer 600a located on the fourth dielectric layer 316a may be performed to obtain a ring-shaped buffer layer 600a surrounding the conductive pillar 420. Figure 5A and Figure 5B For illustrative purposes, the conductive pillars 420 are illustrated as circular conductive pillars and the annular buffer layer 600a surrounding each conductive pillar 420 is illustrated as an annular donut structure as an example, but it is not intended to limit the scope of the embodiments of the present invention. In some embodiments, each conductive pillar 420 has a maximum diameter of W1. On the other hand, the edge of the annular buffer layer 600a is at a distance of W2 from the sidewall of the conductive pillar 420. In some embodiments, the ratio of W2 to W1 (W2 / W1) is in the range of 0.01 to 0.6. Although Figure 5B The conductive pillar 420 is shown as a cylinder and the buffer layer surrounding the pillar has a corresponding shape, however, various shapes and different compatible shapes can be used, and the embodiments of the present invention are not limited to this. In some alternative embodiments, the conductive pillar 420 can be an elliptical cylinder or even a square cylinder or a polygonal cylinder. In addition, although Figure 5AThe outer sidewall of the annular buffer layer 600a is shown to be straight, but the embodiments of the present invention are not limited thereto. In some alternative embodiments, the outer sidewall of the annular buffer layer 600a may be inclined to further enhance the strength of the buffer layer 600a.

[0096] FIG. 6A to FIG. 6I So Figure 1C A region R in FIG. 1 is a schematic enlarged cross-sectional view focusing on illustrating each process of a method for manufacturing an exemplary package according to some alternative embodiments of the present invention. FIG. 6A to FIG. 6I The encapsulation body 200a and the die 100a are used to form Figure 1C to Figure 1D Detailed process steps of the redistribution structure 300, the buffer layer 600a, the conductive pillar 420, and the conductive bump 500 are similar to those shown in FIG. FIG. 6A to FIG. 6C , the process steps shown are similar to FIG. 4A to FIG. 4C The process steps are described in detail in this article.

[0097] Reference Fig.6D , a buffer layer 600a is formed on the fourth dielectric layer 316a and the third conductive pattern 324a. In some embodiments, the buffer layer 600a extends to the opening O 316a Thus covering the opening O 316a Side wall SW 316a The buffer layer 600a exposes the opening O 316aAt least a portion of the bottom surface of the buffer layer 600a. In other words, the buffer layer 600a exposes at least a portion of the third conductive pattern 324a. In some embodiments, the material of the buffer layer 600 is different from the material of the first dielectric layer 310a, the material of the second dielectric layer 312a, the material of the third dielectric layer 314a, and the material of the fourth dielectric layer 316a. For example, the material of the buffer layer 600a may include a molding compound material such as an epoxy resin or a phenolic resin. In some embodiments, the buffer layer 600a may also include a filler. In some embodiments, the material of the buffer layer 600a may include polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer-based dielectric material. In some embodiments, the Young's modulus of the buffer layer 600a is higher than the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, the Young's modulus of the third dielectric layer 314a, and the Young's modulus of the fourth dielectric layer 316a. For example, the Young's modulus of the buffer layer 600a is in the range of 0.5 GPa to 150 GPa. On the other hand, the Young's modulus of the first dielectric layer 310a, the Young's modulus of the second dielectric layer 312a, the Young's modulus of the third dielectric layer 314a, and the Young's modulus of the fourth dielectric layer 316a are in the range of 0.1 GPa to 100 GPa. In a specific embodiment, the ratio of the Young's modulus of the buffer layer 600a to the Young's modulus of the first dielectric layer 310a, the second dielectric layer 312a, the third dielectric layer 314a, or the fourth dielectric layer 316a is in the range of 1.05 to 100. When the ratio of the Young's modulus is lower than 1.05, the buffer layer 600a cannot withstand the stress generated from the conductive pillar 420, and the conductive pattern in the redistribution structure 300 is deformed. On the other hand, when the ratio of Young's modulus exceeds 100, the buffer layer 600a will present a hardness similar to that of pure silicon, thereby increasing the difficulty of processing. In some embodiments, the thickness of the buffer layer 600a is greater than the thickness of the first dielectric layer 310a, the thickness of the second dielectric layer 312a, the thickness of the third dielectric layer 314a, or the thickness of the fourth dielectric layer 316a. In some embodiments, the higher Young's modulus enables the buffer layer 600a to alleviate or block the stress applied to the underlying rewiring structure 300 from the conductive pillar 420, thereby protecting the conductive pattern in the rewiring structure 300 from damage due to the stress generated during the assembly process and / or thermal process. In other words, the buffer layer 600a with a higher Young's modulus helps to alleviate the fine line deformation problem in the rewiring structure 300. Therefore, in some embodiments, the buffer layer 600a can be referred to as an anti-stress layer.

[0098] Reference Fig. 6E In some embodiments, a seed layer 410 is formed on the buffer layer 600a and the exposed third conductive pattern 324a. Fig. 6EAs shown in FIG. 4 , the seed layer 410 is formed in a conformal manner. That is, the seed layer 410 extends to the opening O 316a In order to cover the opening O 316a The buffer layer 600a in the buffer layer 600a and covers the exposed third conductive pattern 324a. The seed layer 410 can be formed by, for example, a sputtering process, a physical vapor deposition (PVD) process, etc. In some embodiments, the seed layer 410 can include, for example, copper, a titanium-copper alloy, or other suitable material selections.

[0099] Reference Fig. 6F , a photoresist pattern layer PR is formed on the seed layer 410. In some embodiments, the photoresist pattern layer PR exposes the opening O 316a The photoresist pattern layer PR also exposes at least a portion of the seed layer 410 located on the buffer layer 600a. In some embodiments, the photoresist pattern layer PR may include a photosensitive resin.

[0100] Reference Figure 6G In some embodiments, a conductive pillar 420 is formed on the seed layer 410 on the buffer layer 600a. In some embodiments, a conductive material (not shown) is deposited on the exposed seed layer 410 to form the conductive pillar 420. The conductive pillar 420 contacts the seed layer 410 located on the third conductive pattern 324a to achieve electrical connection with the rewiring structure 300. Subsequently, a solder material 430 is deposited on the conductive pillar 420. In some embodiments, the conductive material and the solder material 430 can be formed by a plating process. The plating process is, for example, electroplating, electroless plating, immersion plating, etc. In some embodiments, the conductive material includes, for example, copper, copper alloy, etc.

[0101] Reference Figure 6G and Figure 6H , remove the photoresist pattern layer PR and expose the portion of the seed layer 410 not covered by the conductive pillar 420 and the solder material 430. The photoresist pattern layer PR can be removed / stripped by, for example, an etching process, an ashing process, or other suitable removal processes. Subsequently, the seed layer 410 not covered by the conductive pillar 420 and the solder material 430 is removed to obtain the seed layer 410a sandwiched between the conductive pillar 420 and the buffer layer 600a and between the conductive pillar 420 and the third conductive pattern 324a. The exposed portion of the seed layer 410 can be removed by an etching process. Referring to Fig.6I , a reflow process is performed on the solder material 430 to transform the solder material 430 into the conductive bump 500 .

[0102] Fig. 7A is a schematic enlarged cross-sectional view showing exemplary packages according to some alternative embodiments of the present invention with emphasis on region R. Figure 7B Show Fig. 7ASchematic top view of the buffer layer 600a and the conductive pillar 420 in FIG. In addition to the position or coverage of the buffer layer 600a, Fig. 7A The structure shown in Fig.6I In other words, by FIG. 6A to FIG. 6I The process steps are similar to those shown in Fig. 7A In some embodiments, an additional step of removing at least a portion of the buffer layer 600a located on the fourth dielectric layer 316a may be performed to obtain a ring-shaped buffer layer 600a surrounding the conductive pillar 420. Fig. 7A and Figure 7B For illustrative purposes, the conductive pillars 420 are illustrated as circular conductive pillars and the annular buffer layer 600a surrounding each conductive pillar 420 is illustrated as an annular donut structure as an example, but it is not intended to limit the scope of the embodiments of the present invention. In some embodiments, each conductive pillar 420 has a maximum diameter of W1. On the other hand, the edge of the annular buffer layer 600a is at a distance of W2 from the sidewall of the conductive pillar 420. In some embodiments, the ratio of W2 to W1 (W2 / W1) is in the range of 0.01 to 0.6. Although Figure 7B The conductive pillar 420 is shown as a cylinder and the buffer layer surrounding the pillar has a corresponding shape, however, various shapes and different compatible shapes can be used, and the embodiments of the present invention are not limited to this. In some alternative embodiments, the conductive pillar 420 can be an elliptical cylinder or even a square cylinder or a polygonal cylinder. In addition, although Fig. 7A The outer sidewall of the annular buffer layer 600a is illustrated as being straight, but the present invention is not limited thereto. In some alternative embodiments, the outer sidewall of the annular buffer layer 600a may be inclined to further enhance the strength of the buffer layer 600a.

[0103] Figure 8 Shown including Figure 1F Schematic diagram of the stacked package structure of the integrated fan-out package 10. Figure 8 , the integrated fan-out package 10 may be stacked on the substrate 20. In some embodiments, the substrate 20 may be a semiconductor substrate on which a passive device or a micro-electro-mechanical system (MEMS) device is formed. In some alternative embodiments, the substrate 20 may be an interposer. The integrated fan-out package 10 may be electrically connected to the substrate 20 through the conductive pillars 420 and the conductive bumps 500. In some embodiments, the substrate 20 on which the integrated fan-out package 10 is formed may be further disposed on a printed circuit board 30 to form a semiconductor device. The integrated fan-out package 10 may be electrically connected to the printed circuit board 30 through the substrate 20.

[0104] According to some embodiments of the present invention, an integrated fan-out package includes a die, an encapsulation body, a rewiring structure, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulation body encapsulates the die. The rewiring structure is located on the die and the encapsulation body. The rewiring structure is electrically connected to the die and includes a plurality of dielectric layers stacked in sequence and a plurality of conductive patterns sandwiched between the dielectric layers. The Young's modulus of the dielectric layer farthest from the die is higher than the Young's modulus of each of the remaining dielectric layers in the dielectric layer. The conductive patterns are electrically connected to each other. The conductive pillar is disposed on the rewiring structure and is electrically connected to the rewiring structure. The seed layer is located between the conductive pillar and the rewiring structure. The conductive bump is disposed on the conductive pillar.

[0105] According to some embodiments of the invention, the dielectric layer farthest from the die comprises a molding compound material.

[0106] According to some embodiments of the present invention, each of the conductive pillars includes a first portion and a second portion, the first portion is embedded in the dielectric layer farthest from the die, and the second portion is located on the dielectric layer farthest from the die.

[0107] According to some embodiments of the present invention, the integrated fan-out package further comprises an additional seed layer between the first portion and the second portion and between the dielectric layer farthest from the die and the second portion.

[0108] According to some embodiments of the present invention, the seed layer is located between the second portion and the dielectric layer farthest from the die, between the first portion and the dielectric layer farthest from the die, and between the first portion and the conductive pattern farthest from the die.

[0109] According to some embodiments of the present invention, a ratio of the Young's modulus of the dielectric layer farthest from the die to the Young's modulus of the remaining ones of the dielectric layers is in a range of 1.05-100.

[0110] According to some alternative embodiments of the present invention, an integrated fan-out package includes a die, an encapsulation, a rewiring structure, a buffer layer, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulation encapsulates the die. The rewiring structure is located on the die and the encapsulation. The rewiring structure is electrically connected to the die and includes a plurality of dielectric layers stacked in sequence and a plurality of conductive patterns sandwiched between the dielectric layers. The buffer layer is located on the rewiring structure. The Young's modulus of the buffer layer is higher than the Young's modulus of each of the dielectric layers of the rewiring structure. The conductive pillar is disposed on the buffer layer and is electrically connected to the rewiring structure. The seed layer is located between the conductive pillar and the buffer layer and between the conductive pillar and the rewiring structure. The conductive bump is disposed on the conductive pillar.

[0111] According to some embodiments of the present invention, the dielectric layer farthest from the tube core has a plurality of first openings, the plurality of first openings exposing at least a portion of the conductive pattern farthest from the tube core, and the buffer layer has a plurality of second openings, the plurality of second openings exposing the plurality of first openings, and the plurality of second openings are larger than the plurality of first openings.

[0112] According to some embodiments of the present invention, the buffer layer is an annular structure surrounding the plurality of conductive pillars and exposing at least a portion of the dielectric layer farthest from the die.

[0113] According to some embodiments of the present invention, a ratio of a distance between an edge of the annular buffer layer and sidewalls of the plurality of conductive pillars to a maximum diameter of the plurality of conductive pillars is in a range from 0.01 to 0.6.

[0114] According to some embodiments of the present invention, the dielectric layer farthest from the tube core has a plurality of first openings, the plurality of first openings expose at least a portion of the conductive pattern farthest from the tube core, and the buffer layer extends into the plurality of first openings to cover the side walls of the plurality of first openings.

[0115] According to some embodiments of the present invention, the plurality of conductive pillars contact the seed layer on the conductive pattern farthest from the die.

[0116] According to some embodiments of the present invention, the buffer layer is an annular structure surrounding the plurality of conductive pillars and exposing at least a portion of the dielectric layer farthest from the die.

[0117] According to some embodiments of the present invention, a ratio of a distance between an edge of the buffer layer and sidewalls of the plurality of conductive pillars to a maximum diameter of the plurality of conductive pillars is in a range from 0.01 to 0.6.

[0118] According to some embodiments of the present invention, a method for manufacturing an integrated fan-out package includes at least the following steps. A tube core is provided. The tube core is encapsulated with an encapsulation body. A plurality of dielectric layers are formed on the tube core and the encapsulation body. A plurality of conductive patterns are formed. At least a portion of the conductive patterns is sandwiched between the dielectric layers. The conductive patterns are electrically connected to each other. An anti-stress layer is formed on the dielectric layer. The Young's modulus of the anti-stress layer is higher than the Young's modulus of each of the dielectric layers. A plurality of conductive pillars are formed on the anti-stress layer. A plurality of conductive bumps are formed on the conductive pillars.

[0119] According to some embodiments of the present invention, the step of forming the plurality of conductive pillars includes at least the following steps: forming a plurality of openings in the anti-stress layer to expose the conductive pattern farthest from the die; forming a seed layer in the plurality of openings and on the anti-stress layer; forming a photoresist pattern layer on the seed layer, wherein the photoresist pattern layer exposes at least a portion of the seed layer located in the plurality of openings and on the anti-stress layer; forming a conductive material on the seed layer using the photoresist pattern layer as a mask; removing the photoresist pattern layer; and removing the seed layer exposed by the conductive material.

[0120] According to some embodiments of the present invention, the step of forming the plurality of conductive pillars and the step of forming the anti-stress layer include at least the following steps. A first seed layer is formed on the dielectric layer farthest from the tube core and on the conductive pattern farthest from the tube core. A first photoresist pattern layer is formed on the first seed layer, wherein the first photoresist pattern layer exposes at least a portion of the first seed layer located on the conductive pattern farthest from the tube core. A first conductive material is formed on the first seed layer using the first photoresist pattern layer as a mask. The first photoresist pattern layer is removed. The first seed layer exposed by the first conductive material is removed. The anti-stress layer is formed around the first seed layer and the first conductive material. A second seed layer is formed on the first conductive material and the anti-stress layer. A second photoresist pattern layer is formed on the second seed layer, wherein the second photoresist pattern layer exposes at least a portion of the second seed layer located on the first conductive material. A second conductive material is formed on the second seed layer using the second photoresist pattern layer as a mask. The second photoresist pattern layer is removed. The second seed layer exposed by the second conductive material is removed.

[0121] According to some embodiments of the present invention, the step of forming the plurality of conductive pillars includes at least the following steps: forming a plurality of first openings in the dielectric layer farthest from the tube core, wherein the plurality of first openings expose at least a portion of the conductive pattern farthest from the tube core; forming a plurality of second openings in the anti-stress layer, wherein the plurality of second openings expose the plurality of first openings and at least a portion of the dielectric layer farthest from the tube core; forming a seed layer in the plurality of first openings and the plurality of second openings and on the anti-stress layer; forming a photoresist pattern layer on the seed layer, wherein the photoresist pattern layer exposes the seed layer in the plurality of first openings and the plurality of second openings and exposes at least a portion of the seed layer on the anti-stress layer; forming a conductive material on the seed layer using the photoresist pattern layer as a mask; removing the photoresist pattern layer; removing the seed layer exposed by the conductive material.

[0122] According to some embodiments of the present invention, the step of forming the plurality of conductive pillars and the step of forming the anti-stress layer at least include the following steps. A plurality of first openings are formed in the dielectric layer farthest from the tube core, wherein the plurality of first openings expose at least a portion of the conductive pattern farthest from the tube core. The anti-stress layer is formed on the dielectric layer farthest from the tube core and in the plurality of first openings, so that the anti-stress layer covers the sidewalls of the plurality of first openings. A seed layer is formed on the anti-stress layer and on the exposed conductive pattern farthest from the tube core. A photoresist pattern layer is formed on the seed layer, wherein the photoresist pattern layer exposes the seed layer located in the plurality of first openings and exposes at least a portion of the seed layer located on the anti-stress layer. A conductive material is formed on the seed layer using the photoresist pattern layer as a mask. The photoresist pattern layer is removed. The seed layer exposed by the conductive material is removed.

[0123] According to some embodiments of the present invention, the method for manufacturing the integrated fan-out package further includes removing at least a portion of the anti-stress layer so that the anti-stress layer is an annular structure surrounding the plurality of conductive pillars.

[0124] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present invention.

Claims

1. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A redistribution structure is located on the tube core and the encapsulation body, wherein the redistribution structure is electrically connected to the tube core and comprises: A plurality of dielectric layers stacked in sequence; and a plurality of conductive patterns sandwiched between the plurality of dielectric layers, wherein the dielectric layer farthest from the die has a plurality of first openings, the plurality of first openings exposing at least a portion of the conductive pattern farthest from the die; a buffer layer disposed on the redistribution structure, wherein the Young's modulus of the buffer layer is higher than the Young's modulus of each of the plurality of dielectric layers of the redistribution structure, and the buffer layer extends into the plurality of first openings to cover sidewalls of the plurality of first openings; a plurality of conductive pillars disposed on the buffer layer, wherein the plurality of conductive pillars are electrically connected to the redistribution structure; a seed layer, located between the plurality of conductive pillars and the buffer layer and between the conductive pillars and the redistribution structure; and A plurality of conductive bumps are disposed on the plurality of conductive pillars. 2 . The integrated fan-out package according to claim 1 , wherein the plurality of conductive pillars contact the seed layer on the conductive pattern farthest from the die. 3 . The integrated fan-out package according to claim 1 , wherein the buffer layer is a ring-shaped structure surrounding the plurality of conductive pillars and exposing at least a portion of the dielectric layer farthest from the die. 4 . The integrated fan-out package according to claim 3 , wherein a ratio of a distance between an edge of the buffer layer and sidewalls of the plurality of conductive pillars to a maximum diameter of the plurality of conductive pillars is in a range of 0.01 to 0.

6. 5 . The integrated fan-out package according to claim 3 , wherein a sidewall of each of the plurality of conductive pillars is offset from an edge of the annular buffer layer. 6 . The integrated fan-out package according to claim 3 , wherein the plurality of conductive pillars partially expose a top surface of the buffer layer in a ring shape. 7 . The integrated fan-out package of claim 1 , wherein the buffer layer comprises a molding compound material. 8 . The integrated fan-out package of claim 1 , wherein a ratio of the Young's modulus of each of the plurality of dielectric layers of the redistribution structure to the Young's modulus of the buffer layer is in a range of 1.05 to 100.

9. A method for manufacturing an integrated fan-out package, characterized in that: include: Provide a tube die; encapsulating the tube core with an encapsulation body; forming a plurality of dielectric layers on the die and the encapsulation; forming a plurality of conductive patterns, wherein at least a portion of the plurality of conductive patterns are sandwiched between the plurality of dielectric layers, and the plurality of conductive patterns are electrically connected to each other; forming a first seed layer on the dielectric layer farthest from the die and on the conductive pattern farthest from the die; forming a first conductive material on the first seed layer; removing the first seed layer exposed by the first conductive material; forming an anti-stress layer around the first seed layer and the first conductive material, wherein the Young's modulus of the anti-stress layer is higher than the Young's modulus of each of the plurality of dielectric layers; forming a second seed layer on the first conductive material and the anti-stress layer; forming a second conductive material on the second seed layer; removing the second seed layer exposed by the second conductive material, wherein the first conductive material and the second conductive material form a plurality of conductive pillars; as well as A plurality of conductive bumps are formed on the plurality of conductive pillars.

10. The method for manufacturing an integrated fan-out package according to claim 9, wherein the step of forming the first conductive material comprises: forming a first photoresist pattern layer on the first seed layer, wherein the first photoresist pattern layer exposes at least a portion of the first seed layer located on the conductive pattern farthest from the die; forming the first conductive material on the first seed layer using the first photoresist pattern layer as a mask; as well as The first photoresist pattern layer is removed.

11. The method for manufacturing an integrated fan-out package according to claim 10, wherein the step of forming the second conductive material comprises: forming a second photoresist pattern layer on the second seed layer, wherein the second photoresist pattern layer exposes at least a portion of the second seed layer located on the first conductive material; forming the second conductive material on the second seed layer using the second photoresist pattern layer as a mask; as well as The second photoresist pattern layer is removed.

12. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A redistribution structure is located on the tube core and the encapsulation body, wherein the redistribution structure is electrically connected to the tube core and comprises: A plurality of dielectric layers stacked in sequence; and a plurality of conductive patterns sandwiched between the plurality of dielectric layers; a buffer layer disposed on the redistribution structure, wherein a Young's modulus of the buffer layer is higher than a Young's modulus of each of the plurality of dielectric layers of the redistribution structure; a plurality of conductive pillars disposed on the buffer layer, wherein the plurality of conductive pillars are electrically connected to the redistribution structure; a seed layer between the plurality of conductive pillars and the buffer layer and between the conductive pillars and the redistribution structure, wherein the seed layer is in direct contact with a top surface of the dielectric layer farthest from the die; and A plurality of conductive bumps are disposed on the plurality of conductive pillars.

13. An integrated fan-out package according to claim 12, wherein the dielectric layer farthest from the tube core has a plurality of first openings, the plurality of first openings expose at least a portion of the conductive pattern farthest from the tube core, and the buffer layer has a plurality of second openings, the plurality of second openings expose the plurality of first openings, and the plurality of second openings are larger than the plurality of first openings. 14 . The integrated fan-out package according to claim 13 , wherein sidewalls of the plurality of first openings are offset from sidewalls of the plurality of second openings. 15 . The integrated fan-out package of claim 12 , wherein the buffer layer is a ring-shaped structure surrounding the plurality of conductive pillars and exposing at least a portion of the dielectric layer farthest from the die. 16 . The integrated fan-out package according to claim 15 , wherein a ratio of a distance between an edge of the annular buffer layer and sidewalls of the plurality of conductive pillars to a maximum diameter of the plurality of conductive pillars is in a range of 0.01 to 0.

6. 17 . The integrated fan-out package according to claim 15 , wherein a sidewall of each of the plurality of conductive pillars is offset from an edge of the annular buffer layer. 18 . The integrated fan-out package according to claim 15 , wherein the plurality of conductive pillars partially expose a top surface of the buffer layer in a ring shape.

19. The integrated fan-out package of claim 12, wherein the buffer layer comprises a molding compound material. 20 . The integrated fan-out package of claim 12 , wherein a ratio of the Young's modulus of each of the plurality of dielectric layers of the redistribution structure to the Young's modulus of the buffer layer is in a range of 1.05 to 100.

21. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A redistribution structure, located on the tube core and the package, comprises: A plurality of dielectric layers stacked in sequence; and a plurality of conductive patterns sandwiched between the plurality of dielectric layers; A seed layer and a plurality of conductive pillars are sequentially stacked on the redistribution structure, wherein the seed layer is in direct contact with the conductive pattern closest to the plurality of conductive pillars; and A buffer layer is disposed on the redistribution structure, wherein the dielectric layer closest to the multiple conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive pattern closest to the multiple conductive pillars, and the Young's modulus of the buffer layer is higher than the Young's modulus of each of the multiple dielectric layers of the redistribution structure. 22 . The integrated fan-out package of claim 21 , further comprising a plurality of conductive bumps disposed on the plurality of conductive pillars.

23. An integrated fan-out package according to claim 21, wherein the dielectric layer closest to the multiple conductive pillars has a plurality of first openings, the plurality of first openings exposing at least a portion of the conductive pattern closest to the multiple conductive pillars, and the buffer layer has a plurality of second openings located in the plurality of first openings. 24 . The integrated fan-out package of claim 23 , wherein sidewalls of the plurality of first openings are offset from sidewalls of the plurality of second openings. 25 . The integrated fan-out package of claim 21 , wherein the buffer layer is a ring-shaped structure surrounding the plurality of conductive pillars and exposing at least a portion of the dielectric layer closest to the plurality of conductive pillars. 26 . The integrated fan-out package according to claim 25 , wherein a ratio of a distance between an edge of the buffer layer and sidewalls of the plurality of conductive pillars to a maximum diameter of the plurality of conductive pillars is in a range of 0.01 to 0.

6.

27. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A redistribution structure, located on the tube core and the package, comprises: a plurality of dielectric layers stacked in sequence, wherein the Young's modulus of the dielectric layer farthest from the die is higher than the Young's modulus of each of the remaining dielectric layers in the dielectric layers; and a plurality of conductive patterns sandwiched between the plurality of dielectric layers; a first seed layer embedded in the dielectric layer farthest from the die; A plurality of conductive pillars are arranged on the rewiring structure, including: a first portion embedded in the dielectric layer farthest from the die, wherein a sidewall of the first portion is in direct contact with the dielectric layer farthest from the die; and a second portion disposed on the first portion and the dielectric layer farthest from the die; and The second seed layer is sandwiched between the first portion and the second portion of the plurality of conductive pillars.

28. The integrated fan-out package of claim 27, further comprising a plurality of conductive bumps disposed on the plurality of conductive pillars.

29. The integrated fan-out package of claim 27, wherein a ratio of the Young's modulus of the dielectric layer farthest from the die to the Young's modulus of each of the remaining ones of the dielectric layers is in a range of 1.05 to 100.

30. The integrated fan-out package of claim 27, wherein the dielectric layer farthest from the die comprises a molding compound material.

31. The integrated fan-out package of claim 27, wherein the second seed layer is further sandwiched between the second portion and the dielectric layer farthest from the die.

32. The integrated fan-out package of claim 27, wherein the first portion has straight sidewalls.

33. The integrated fan-out package of claim 27, wherein a sidewall of the first portion is aligned with a sidewall of the first seed layer.

34. The integrated fan-out package of claim 27, wherein the first seed layer is interposed between the first portion and the conductive pattern farthest from the die.

35. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A redistribution structure, located on the tube core and the package, comprises: A plurality of dielectric layers stacked in sequence; and a plurality of conductive patterns sandwiched between the plurality of dielectric layers; a buffer layer disposed on the redistribution structure, wherein a Young's modulus of the buffer layer is higher than a Young's modulus of each of the plurality of dielectric layers of the redistribution structure; a seed layer located on the buffer layer and the dielectric layer farthest from the die, wherein the seed layer has a stepped bottom surface and the seed layer is in direct contact with a top surface of the dielectric layer farthest from the die; and A plurality of conductive pillars are disposed on the seed layer.

36. An integrated fan-out package according to claim 35, wherein the dielectric layer farthest from the tube core has a plurality of first openings, the plurality of first openings exposing at least a portion of the conductive pattern farthest from the tube core, and the buffer layer has a plurality of second openings, the plurality of second openings exposing the plurality of first openings, and the plurality of second openings are larger than the plurality of first openings. 37 . The integrated fan-out package of claim 36 , wherein sidewalls of the plurality of first openings are offset from sidewalls of the plurality of second openings.

38. The integrated fan-out package of claim 35, wherein the buffer layer is an annular structure surrounding the plurality of conductive pillars and exposing at least a portion of the dielectric layer farthest from the die. 39 . The integrated fan-out package according to claim 38 , wherein a ratio of a distance between an edge of the annular buffer layer and sidewalls of the plurality of conductive pillars to a maximum diameter of the plurality of conductive pillars is in a range of 0.01 to 0.

6.

40. The integrated fan-out package of claim 35, wherein the buffer layer comprises a molding compound material.

41. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A seed layer and a conductive column are sequentially stacked on the tube core and the package; A redistribution structure, located on the tube core and the package, comprises: a conductive pattern directly contacting the seed layer; and A dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar; and a buffer layer is located on the redistribution structure, wherein the seed layer is separated from the dielectric layer by the buffer layer, and the Young's modulus of the buffer layer is higher than the Young's modulus of the dielectric layer of the redistribution structure.

42. The integrated fan-out package of claim 41, further comprising a conductive bump disposed on the conductive pillar.

43. The integrated fan-out package according to claim 41, wherein the dielectric layer has a first opening, the first opening exposing at least a portion of the conductive pattern, and the buffer layer has a second opening located in the first opening.

44. The integrated fan-out package of claim 43, wherein a sidewall of the first opening is offset from a sidewall of the second opening.

45. The integrated fan-out package of claim 41, wherein the buffer layer is a ring-shaped structure surrounding the conductive pillar and exposing at least a portion of the dielectric layer. 46 . The integrated fan-out package of claim 45 , wherein a ratio of a distance between an edge of the buffer layer and a sidewall of the conductive pillar to a maximum diameter of the conductive pillar is in a range of 0.01 to 0.

6.

47. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A first seed layer, a first conductive portion, a second seed layer, and a second conductive portion are sequentially stacked on the die and the encapsulation body; as well as A redistribution structure, located on the tube core and the package, comprises: a plurality of dielectric layers stacked in sequence, wherein the Young's modulus of the dielectric layer directly contacting the first seed layer and the first conductive portion is higher than the Young's modulus of each of the remaining dielectric layers in the dielectric layer; as well as A plurality of conductive patterns are sandwiched between the plurality of dielectric layers.

48. The integrated fan-out package of claim 47, further comprising a conductive bump disposed on the second conductive portion.

49. An integrated fan-out package according to claim 47, wherein the ratio of the Young's modulus of the dielectric layer in direct contact with the first seed layer and the first conductive portion to the Young's modulus of each of the remaining dielectric layers in the dielectric layer is in the range of 1.05 to 100.

50. The integrated fan-out package of claim 47, wherein the dielectric layer in direct contact with the first seed layer and the first conductive portion comprises a molding compound material.

51. The integrated fan-out package of claim 47, wherein the second seed layer is further sandwiched between the second conductive portion and the dielectric layer in direct contact with the first seed layer and the first conductive portion.

52. The integrated fan-out package of claim 47, wherein the first conductive portion has straight sidewalls.

53. The integrated fan-out package of claim 47, wherein sidewalls of the first conductive portion are aligned with sidewalls of the first seed layer.

54. The integrated fan-out package of claim 47, wherein a thickness of the dielectric layer in direct contact with the first seed layer and the first conductive portion is greater than a thickness of each of the remaining ones of the dielectric layers.

55. An integrated fan-out package, characterized in that: include: Die; An encapsulation body encapsulating the tube core; A seed layer and a conductive column are sequentially stacked on the tube core and the package; A redistribution structure, located on the tube core and the package, comprises: a conductive pattern directly contacting the seed layer; and a dielectric layer covering the conductive pattern and surrounding the seed layer and the conductive pillar, wherein the seed layer is in direct contact with a top surface of the dielectric layer; and A buffer layer is located on the redistribution structure, wherein the Young's modulus of the buffer layer is higher than the Young's modulus of the dielectric layer of the redistribution structure, and the seed layer and the conductive pillar partially cover the top surface of the buffer layer.

56. An integrated fan-out package according to claim 55, wherein the dielectric layer has a first opening, the first opening exposes at least a portion of the conductive pattern, the buffer layer has a second opening, the second opening exposes the first opening, and the second opening is larger than the first opening.

57. The integrated fan-out package of claim 56, wherein a sidewall of the first opening is offset from a sidewall of the second opening.

58. The integrated fan-out package of claim 55, wherein the buffer layer is a ring-shaped structure surrounding the conductive pillar and exposing at least a portion of the dielectric layer.

59. The integrated fan-out package of claim 58, wherein a ratio of a distance between an edge of the annular buffer layer and a sidewall of the conductive pillar to a maximum diameter of the conductive pillar is in a range of 0.01 to 0.

6.

60. The integrated fan-out package of claim 55, wherein the buffer layer is disposed between the seed layer and the dielectric layer of the redistribution structure and surrounds the seed layer and the conductive pillar.

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