A SiC-based MOS device and its preparation method and application

Abstract

The present invention provides a method for preparing a SiC-based MOS device, comprising: cleaning a SiC epitaxial material substrate; depositing a two-dimensional material thin film layer on the SiC epitaxial material substrate; depositing an oxide thin film layer on the two-dimensional material thin film layer by chemical vapor deposition or physical vapor deposition, and then annealing the two-dimensional material / oxide composite thin film dielectric layer formed above; making an ohmic contact electrode layer on the back of the SiC epitaxial material substrate; and making a gate electrode layer on the oxide thin film material layer to complete the preparation of the SiC-based MOS device. The present invention also provides a SiC-based MOS device and its application, which utilizes a high-mobility, high-surface conductivity transmission layer to improve the thermal stability and high-voltage breakdown capability of the SiC-based MOS device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a SiC-based MOS device and a preparation method and application thereof. Background Art

[0002] Silicon carbide (SiC) is the fastest growing wide bandgap power semiconductor material. The physical and electrical properties of SiC materials have obvious advantages over traditional Si materials. SiC has the characteristics of wide bandgap, high thermal conductivity, high breakdown field strength, high saturated electron drift rate, etc. It also has excellent physical and chemical stability, strong radiation resistance and mechanical strength. Therefore, electronic devices based on wide bandgap SiC materials can be used in power electronics fields such as high temperature, high power, high frequency, and high radiation, and can give full play to the important advantages and outstanding characteristics of SiC-based devices in energy conservation and emission reduction.

[0003] Despite this, SiC-based metal-oxide-semiconductor (MOS) power devices have encountered great challenges in terms of channel electron mobility and reliability of the gate dielectric layer. The main reason is that there are many interface states between the SiO2 layer formed by thermal oxidation of the SiC substrate and the SiC substrate. The scattering of carriers by the interface states causes the carrier mobility of the MOS device channel to be one order of magnitude lower than that of the SiC bulk material. Therefore, the SiC-based MOS device has a higher channel resistance, which greatly increases the power conversion loss of the SiC switch device. At the same time, it also leads to a decrease in the reliability of the SiC-based MOS device gate dielectric under high field stress. This requires finding a new method to grow a high-speed electron transport layer. The transport layer with high mobility and high surface conductivity is conducive to reducing the channel resistance of the SiC-based MOS device, thereby helping to improve the thermal control capability at the gate dielectric interface of the SiC-based MOS device, and thus improve the high-temperature reliability of the device. Summary of the invention

[0004] One of the technical problems to be solved by the present invention is to provide a method for preparing a SiC-based MOS device, by providing a transmission layer with high mobility and high surface conductivity, so as to improve the thermal stability and high-voltage breakdown capability of the SiC-based MOS device.

[0005] One of the technical problems to be solved by the present invention is achieved as follows: A method for preparing a SiC-based MOS device comprises the following steps:

[0006] S1. Cleaning the SiC epitaxial material substrate;

[0007] S2. depositing a two-dimensional material thin film layer on a SiC epitaxial material substrate;

[0008] S3. depositing an oxide thin film layer on the two-dimensional material thin film layer by chemical vapor deposition or physical vapor deposition, and then annealing the two-dimensional material / oxide composite thin film dielectric layer formed in step S2 and step S3;

[0009] S4. Fabricating an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate;

[0010] S5. Fabricate a gate electrode layer on the oxide thin film material layer to complete the preparation of the SiC-based MOS device.

[0011] Furthermore, the two-dimensional material thin film layer is MoS2, BN material, Bi2Te3 or Bi2Se3, and the thickness of the two-dimensional material thin film layer ranges from 1 to 50 nm.

[0012] Furthermore, the oxide film layer is SiO2, Al2O3, Si x N y , AlN, AlON or HfO2, and the thickness of the oxide film layer ranges from 5 to 50 nm.

[0013] Furthermore, the conditions for annealing the formed two-dimensional material / oxide composite thin film dielectric layer in step S3 include: an annealing temperature range of 400°C to 1300°C, an annealing time of 0.5 to 3 hours, and an annealing atmosphere of N2, Ar, NO, N2O, POCl3, H2, NH3, P2O5 or Sb+NO.

[0014] Furthermore, the annealing temperature range of the ohmic contact electrode layer in step S4 is 600° C. to 1100° C., and the annealing atmosphere is nitrogen or argon.

[0015] Furthermore, the gate electrode layer in step S5 is Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof.

[0016] The second technical problem to be solved by the present invention is to provide a SiC-based MOS device, which improves the thermal stability and high-voltage breakdown capability of the SiC-based MOS device by setting a transmission layer with high mobility and high surface conductivity.

[0017] The second technical problem to be solved by the present invention is achieved as follows: a SiC-based MOS device includes an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer, an oxide film layer and a gate electrode layer arranged in sequence from bottom to top.

[0018] Furthermore, the two-dimensional material thin film layer is MoS2, BN material, Bi2Te3 or Bi2Se3, and the thickness of the two-dimensional material thin film layer ranges from 1 to 50 nm.

[0019] Furthermore, the oxide film layer is SiO2, Al2O3, Si x N y , AlN, AlON or HfO2, and the thickness of the oxide film layer ranges from 5 to 50 nm.

[0020] The third technical problem to be solved by the present invention is to provide an application of a SiC-based MOS device, and to improve the thermal stability and high-voltage breakdown capability of the SiC-based MOS device by setting a transmission layer with high mobility and high surface conductivity.

[0021] The third technical problem to be solved by the present invention is achieved as follows: a preparation and application of a SiC-based MOS device, using the SiC-based MOS device as a SiC-based MOS cell to manufacture a lateral MOSFET device, a vertical MOSFET device or an IGBT device, and the SiC-based MOS cell structure is a planar structure or a trench structure.

[0022] The present invention has the following advantages: utilizing the high mobility characteristics of the two-dimensional material and the lattice matching characteristics with the SiC material, depositing a certain thickness of the two-dimensional material on the upper surface of the three-dimensional SiC material, and growing an oxide film layer, so as to improve the channel carrier mobility at the interface between the two-dimensional material and the three-dimensional material SiC, improve the thermal stability and high-voltage breakdown capability of the SiC-based MOS device, and play an important innovative role. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0024] Figure 1 The present invention is a flowchart for executing the method.

[0025] Figure 2 This is a schematic diagram of the structure of a SiC-based MOS device according to Embodiment 1 of the present invention.

[0026] Figure 3 This is a schematic diagram of the structure of a SiC-based MOS device according to the second embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the structure of a SiC-based MOS device according to the third embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of the structure of a SiC-based MOS device according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0029] like Figure 1 As shown, a method for preparing a SiC-based MOS device of the present invention comprises the following steps:

[0030] S1. Cleaning the SiC epitaxial material substrate;

[0031] S2. depositing a two-dimensional material thin film layer on a SiC epitaxial material substrate;

[0032] S3. depositing an oxide thin film layer on the two-dimensional material thin film layer by chemical vapor deposition or physical vapor deposition, and then annealing the two-dimensional material / oxide composite thin film dielectric layer formed in step S2 and step S3;

[0033] S4. Fabricating an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate;

[0034] S5. Fabricate a gate electrode layer on the oxide thin film material layer to complete the preparation of the SiC-based MOS device.

[0035] A SiC-based MOS device of the present invention comprises an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer, an oxide film layer and a gate electrode layer which are sequentially arranged from bottom to top.

[0036] The present invention discloses a preparation and application of a SiC-based MOS device, wherein the SiC-based MOS device is used as a SiC-based MOS cell to manufacture a lateral MOSFET device, a vertical MOSFET device or an IGBT device, and the SiC-based MOS cell structure is a planar structure or a trench structure.

[0037] The present invention will be further described below in conjunction with specific embodiments:

[0038] Embodiment 1

[0039] like Figure 2 As shown, this embodiment relates to a SiC-based MOS device with a SiC / MoS2 / SiO2 gate dielectric structure and its preparation process and application. The specific preparation process is as follows:

[0040] Step 11: Clean the SiC epitaxial material substrate layer 100 and perform standard cleaning on the substrate sample, specifically:

[0041] a. Ultrasonic cleaning with acetone and ethanol three times in sequence, and then rinse with deionized water;

[0042] b. The organic ultrasonic SiC epitaxial material substrate layer 100 is placed in a concentrated sulfuric acid and hydrogen peroxide solution and boiled for at least 10 minutes;

[0043] c. The SiC epitaxial material substrate layer 100 that has been boiled in concentrated sulfuric acid is boiled in liquid No. 1 and liquid No. 2 for 15 minutes, then rinsed with deionized water and blown dry with nitrogen for standby use; wherein liquid No. 1 is a mixture of ammonia water, hydrogen peroxide and deionized water, with a volume ratio of ammonia water: hydrogen peroxide: deionized water = 1:2:5, and liquid No. 2 is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5;

[0044] d. The rinsed SiC epitaxial material substrate layer 100 is placed in diluted hydrofluoric acid (hydrogen fluoride: deionized water = 1:3 by volume) and soaked for 1 min to remove the surface oxide, and then washed with deionized water and dried;

[0045] Step 12: depositing a two-dimensional material thin film layer on the SiC epitaxial material substrate layer 100, specifically: growing a two-dimensional material MoS2 thin film on the cleaned SiC epitaxial material substrate layer 100 by chemical vapor deposition, physical vapor deposition, or thin film sputtering, wherein the thickness of the grown MoS2 thin film layer is 1-50 nm, forming a high-mobility electrical transport layer 200 of the two-dimensional MoS2;

[0046] Step 13: depositing an oxide film layer on the two-dimensional material film layer, specifically, depositing a high-quality SiO2 film 300 (i.e., a highly uniform and dense SiO2 film) on the high-mobility electrical transport layer 200 of the above-mentioned two-dimensional material MOS2 by chemical vapor deposition, physical vapor deposition, or thin film sputtering, wherein the thickness of the SiO2 film 300 is 5-50 nm, and the SiO2 film 300 can also be formed by indirect manufacturing methods such as depositing polysilicon and oxidizing it, and molecular beam epitaxy Si and oxidizing it;

[0047] Afterwards, the MOS2 / SiO2 composite thin film dielectric layer formed in step 12 and step 13 is annealed. The annealing temperature is any temperature between 400°C and 1300°C. The annealing time is 0.5 to 3 hours. The annealing atmosphere is N2 or Ar or NO or N2O, or POCl3, H2, NH3, P2O5, Sb+NO, etc.

[0048] Step 14: Fabricate an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate layer 100, specifically:

[0049] Step 141: using photoresist to cover and protect the SiO2 film 300, and using diluted HF to remove the oxide layer on the back side of the SiC epitaxial material substrate layer 100;

[0050] Step 142: depositing a metal film layer on the back side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering, the back side metal film layer may be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof, the composite metal layer being an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and other alloy layers, and removing the front side photoresist;

[0051] Step 143: annealing the back metal film layer in a temperature range of 600° C. to 1100° C. under nitrogen or argon conditions to form an ohmic contact electrode layer 400 on the back side;

[0052] Step 15: A gate electrode layer is formed on the oxide thin film material. Specifically, a metal film is deposited on the SiO2 film 300 on the front side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering. The metal film can be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof. The composite metal layer is an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W alloy layers. The deposited metal film is combined with photolithography and etching techniques to form a gate electrode layer 500.

[0053] Through the above preparation method, a SiC-based MOS device can be obtained, which includes an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer (MoS2), an oxide film layer (SiO2) and a gate electrode layer arranged in sequence from bottom to top. The SiC-based MOS device can be used as a basic cell to manufacture corresponding lateral MOSFET devices, vertical MOSFET devices or IGBT devices, etc. The SiC-based MOS cell structure can be a planar structure or a trench structure.

[0054] Embodiment 2

[0055] like Figure 3 As shown, this embodiment relates to a SiC-based MOS device with a SiC / MoS2 / Al2O3 gate dielectric structure and its preparation process and application. The specific preparation process is as follows:

[0056] Step 21: Clean the SiC epitaxial material substrate layer 100 and perform standard cleaning on the substrate sample, specifically:

[0057] a. Ultrasonic cleaning with acetone and ethanol three times in sequence, and then rinse with deionized water;

[0058] b. The organic ultrasonic SiC epitaxial material substrate layer 100 is placed in a concentrated sulfuric acid and hydrogen peroxide solution and boiled for at least 10 minutes;

[0059] c. The SiC epitaxial material substrate layer 100 that has been boiled in concentrated sulfuric acid is boiled in liquid No. 1 and liquid No. 2 for 15 minutes, then rinsed with deionized water and blown dry with nitrogen for standby use; wherein liquid No. 1 is a mixture of ammonia water, hydrogen peroxide and deionized water, with a volume ratio of ammonia water: hydrogen peroxide: deionized water = 1:2:5, and liquid No. 2 is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5;

[0060] d. The rinsed SiC epitaxial material substrate layer 100 is immersed in diluted hydrofluoric acid (hydrogen fluoride: deionized water = 1:3 by volume) for 1 min to remove the oxide on the surface, and then washed with deionized water and dried.

[0061] Step 22: depositing a two-dimensional material thin film layer on the SiC epitaxial material substrate layer 100, specifically: growing a two-dimensional material MoS2 thin film on the cleaned SiC epitaxial material substrate layer 100 by chemical vapor deposition, physical vapor deposition, or thin film sputtering, wherein the thickness of the grown MoS2 thin film layer is 1-50 nm, thereby forming a high-mobility electrical transport layer 200 of the two-dimensional MoS2;

[0062] Step 23: depositing an oxide film 310 on the two-dimensional material film layer, specifically: depositing a high-quality Al2O3 film 310 (here, high quality refers to high uniformity and high density) on the two-dimensional MoS2 high-mobility electrical transport layer 200 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or thin film sputtering, wherein the thickness of the Al2O3 film 310 is 5-50 nm;

[0063] Afterwards, the MoS2 / Al2O3 composite thin film dielectric layer formed in step 22 and step 23 is annealed, the annealing temperature is any temperature between 400°C and 1300°C, the annealing time is 0.5 to 3 hours, and the annealing atmosphere is N2 or Ar or NO or N2O, or POCl3, H2, NH3, P2O5, Sb+NO, etc.;

[0064] Step 24: Fabricate an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate 100, specifically:

[0065] Step 241: Use photoresist to cover and protect the above-mentioned Al2O3 film 310, and use diluted HF to remove the oxide layer on the back side of the SiC epitaxial material substrate 100.

[0066] Step 242: Deposit a metal film layer on the back side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering or other methods. The back metal film layer can be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof. The composite metal layer is an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and other alloy layers, and remove the front photoresist.

[0067] Step 243: annealing the back metal film layer in a temperature range of 600° C. to 1100° C. under nitrogen or argon conditions to form an ohmic contact electrode layer 400 on the back side.

[0068] Step 25: A gate electrode layer is formed on the oxide thin film material. Specifically, a metal film is deposited on the SiO2 film 300 on the front side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering. The metal film can be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof. The composite metal layer is an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and other alloy layers. The deposited metal film is combined with photolithography and etching techniques to form a gate electrode layer 500.

[0069] Through the above preparation method, a SiC-based MOS device can be obtained, which includes an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer (MoS2), an oxide film layer (Al2O3) and a gate electrode layer arranged in sequence from bottom to top. The SiC-based MOS device can be used as a basic cell to manufacture corresponding lateral MOSFET devices, vertical MOSFET devices or IGBT devices, etc. The SiC-based MOS cell structure can be a planar structure or a trench structure.

[0070] Embodiment 3

[0071] like Figure 4 As shown, this embodiment relates to a SiC-based MOS device with a SiC / BN / SiO2 gate dielectric structure and its preparation process and application. The specific preparation process is as follows:

[0072] Step 31: Clean the SiC epitaxial material substrate layer 100 and perform standard cleaning on the substrate sample, specifically:

[0073] a. Ultrasonic cleaning with acetone and ethanol three times in sequence, and then rinse with deionized water;

[0074] b. The organic ultrasonic SiC epitaxial material substrate layer 100 is placed in a concentrated sulfuric acid and hydrogen peroxide solution and boiled for at least 10 minutes;

[0075] c. The SiC epitaxial material substrate layer 100 that has been boiled in concentrated sulfuric acid is boiled in liquid No. 1 and liquid No. 2 for 15 minutes, then rinsed with deionized water and blown dry with nitrogen for standby use; wherein liquid No. 1 is a mixture of ammonia water, hydrogen peroxide and deionized water, with a volume ratio of ammonia water: hydrogen peroxide: deionized water = 1:2:5, and liquid No. 2 is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5;

[0076] d. The rinsed SiC epitaxial material substrate layer 100 is placed in diluted hydrofluoric acid (hydrogen fluoride: deionized water = 1:3 by volume) and soaked for 1 min to remove the surface oxide, and then washed with deionized water and dried;

[0077] Step 32: depositing a two-dimensional material thin film layer on the SiC epitaxial material substrate layer 100, specifically: growing a two-dimensional material BN thin film on the cleaned SiC epitaxial material substrate layer 100 by chemical vapor deposition, physical vapor deposition, or thin film sputtering, wherein the thickness of the grown BN thin film layer is 1-50 nm, forming a two-dimensional BN high-mobility electrical transport layer 210;

[0078] Step 33: depositing an oxide thin film layer on the two-dimensional material thin film layer, specifically, depositing a high-quality SiO2 thin film 300 on the high-mobility electrical transport layer 210 of the above-mentioned two-dimensional material BN by chemical vapor deposition, physical vapor deposition, thin film sputtering, etc., wherein the thickness of the SiO2 thin film 300 is 5-50 nm, and the SiO2 thin film 300 can also be formed by indirect manufacturing methods such as depositing polysilicon and oxidizing, molecular beam epitaxy Si and oxidizing;

[0079] Afterwards, the BN / SiO2 composite thin film dielectric layer formed in step 32 and step 33 is annealed. The annealing temperature is any temperature between 400°C and 1300°C. The annealing time is 0.5 to 3 hours. The annealing atmosphere is N2 or Ar or NO or N2O, or POCl3, H2, NH3, P2O5, Sb+NO, etc.

[0080] Step 34: Fabricate an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate layer 100, specifically:

[0081] Step 341: using photoresist to cover and protect the SiO2 film 300, and using diluted HF to remove the oxide layer on the back of the SiC epitaxial material substrate layer 100;

[0082] Step 342: depositing a metal film layer on the back side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering, the back side metal film layer may be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof, the composite metal layer being an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and other alloy layers, and removing the front side photoresist;

[0083] Step 343: annealing the back metal film layer in a temperature range of 600° C. to 1100° C. under nitrogen or argon conditions to form an ohmic contact electrode layer 400 on the back side;

[0084] Step 35: A gate electrode layer is formed on the oxide thin film material. Specifically, a metal film is deposited on the SiO2 film 300 on the front side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering. The metal film can be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof. The composite metal layer is an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and other alloy layers. The deposited metal film is combined with photolithography and etching techniques to form a gate electrode layer 500.

[0085] Through the above preparation method, a SiC-based MOS device can be obtained, which includes an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer (BN), an oxide film layer (SiO2) and a gate electrode layer arranged in sequence from bottom to top. The SiC-based MOS device can be used as a basic cell to manufacture corresponding lateral MOSFET devices, vertical MOSFET devices or IGBT devices, etc. The SiC-based MOS cell structure can be a planar structure or a trench structure.

[0086] Embodiment 4

[0087] like Figure 5 As shown, this embodiment relates to a SiC-based MOS device with a SiC / BN / Al2O3 gate dielectric structure and its preparation process and application. The specific preparation process is as follows:

[0088] Step 41: Clean the SiC epitaxial material substrate layer 100 and perform standard cleaning on the substrate sample, specifically:

[0089] a. Ultrasonic cleaning with acetone and ethanol three times in sequence, and then rinse with deionized water;

[0090] b. The organic ultrasonic SiC epitaxial material substrate layer 100 is placed in a concentrated sulfuric acid and hydrogen peroxide solution and boiled for at least 10 minutes;

[0091] c. The SiC epitaxial material substrate layer 100 that has been boiled in concentrated sulfuric acid is boiled in liquid No. 1 and liquid No. 2 for 15 minutes, then rinsed with deionized water and blown dry with nitrogen for standby use; wherein liquid No. 1 is a mixture of ammonia water, hydrogen peroxide and deionized water, with a volume ratio of ammonia water: hydrogen peroxide: deionized water = 1:2:5, and liquid No. 2 is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5;

[0092] d. The rinsed SiC epitaxial material substrate layer 100 is placed in diluted hydrofluoric acid (hydrogen fluoride: deionized water = 1:3 by volume) and soaked for 1 min to remove the surface oxide, and then washed with deionized water and dried;

[0093] Step 42: depositing a two-dimensional material thin film layer on the SiC epitaxial material substrate layer 100, specifically: growing a two-dimensional material BN thin film on the cleaned SiC epitaxial material substrate layer 100 by chemical vapor deposition, physical vapor deposition, or thin film sputtering, wherein the thickness of the grown BN thin film layer is 1-50 nm, to form a two-dimensional BN high-mobility electrical transport layer 210;

[0094] Step 33: depositing an oxide thin film layer on the two-dimensional material thin film layer, specifically, depositing a high-quality Al2O3 thin film 310 on the high-mobility electrical transport layer 210 of the above-mentioned two-dimensional material BN by chemical vapor deposition, physical vapor deposition, thin film sputtering, etc., wherein the thickness of the Al2O3 thin film 310 is 5-50 nm;

[0095] Afterwards, the BN / Al2O3 composite thin film dielectric layer formed in step 42 and step 43 is annealed. The annealing temperature is any temperature between 400°C and 1300°C. The annealing time is 0.5 to 3 hours. The annealing atmosphere is N2 or Ar or NO or N2O, or POCl3, H2, NH3, P2O5, Sb+NO, etc.

[0096] Step 44: Fabricate an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate layer 100, specifically:

[0097] Step 441: using photoresist to cover and protect the Al2O3 film 310, and using diluted HF to remove the oxide layer on the back side of the SiC epitaxial material substrate layer 100;

[0098] Step 442: depositing a metal film layer on the back side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering, the back side metal film layer may be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof, the composite metal layer being an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and the like alloy layer, and removing the front side photoresist;

[0099] Step 443: annealing the back metal film layer in a temperature range of 600° C. to 1100° C. under nitrogen or argon conditions to form a back ohmic contact electrode layer 400;

[0100] Step 45: A gate electrode layer is formed on the oxide thin film material. Specifically, a metal film is deposited on the Al2O3 film 310 on the front side of the SiC epitaxial material substrate layer 100 by electron beam evaporation or sputtering. The metal film can be Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof. The composite metal layer is an alloy layer obtained by mixing at least two of the above metals, such as Al / Ti, Ni / Ti, Ti / W and other alloy layers. The deposited metal film is combined with photolithography and etching techniques to form a gate electrode layer 500.

[0101] Through the above preparation method, a SiC-based MOS device can be obtained, which includes an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer (BN), an oxide film layer (Al2O3) and a gate electrode layer arranged in sequence from bottom to top. The SiC-based MOS device can be used as a basic cell to manufacture corresponding lateral MOSFET devices, vertical MOSFET devices or IGBT devices, etc. The SiC-based MOS cell structure can be a planar structure or a trench structure.

[0102] The above embodiments of the present invention disclose SiC / MoS 2 / SiO2, SiC / MoS2 / Al2O3, SiC / BN / SiO2, SiC / BN / Al2O3 composite thin film dielectric layer, its key role is as follows: MoS2 two-dimensional material has a certain hexagonal crystal structure and a high lattice matching degree with SiC material, which can reduce the defect state at the interface and improve the carrier mobility, exceeding the channel mobility value of traditional SiC-based MOS devices. Furthermore, high-k dielectric films such as SiO2 or Al2O3 are deposited on the surface to improve the band gap between the gate dielectric and SiC, enhance the anti-breakdown characteristics of the gate dielectric and protect the stability of the two-dimensional material electrical transmission layer. BN two-dimensional material also has a hexagonal crystal structure and a layered structure similar to graphite, so it can be used as an electrical transmission layer to improve channel mobility. At the same time, h-BN is an excellent thermal conductive material. As the thickness decreases, the phonon scattering between the h-BN layers is weakened, and the thermal conductivity increases. The thermal conductivity of a single layer of h-BN is about 600W / (m·K), thereby improving the thermal control capability of the MOS channel region. The surface is deposited with high-k dielectric films such as SiO2 or Al2O3, which protects the reaction between BN and air, plays a good passivation role, and reduces the gate leakage current of SiC-based MOS devices.

[0103] It should be noted that the two-dimensional material thin film layer material of the present invention is not limited to the above-mentioned MoS2 and BN materials, and can also be other topological insulating materials, such as Bi2Te3, Bi2Se3, etc. and their combination structures. The combination structure here is a layer structure formed by physically superimposing at least two of the above-mentioned materials, such as MoS2 layer + Bi2Te3 layer, etc., as a high-mobility electrical transport layer. The oxide thin film layer material of the present invention is not limited to SiO2 and Al2O3, and can also be Si x N y (x, y is the element ratio) and high-k dielectric materials such as AlN, AlON, HfO2 and their combinations, where the combined structure is a layer structure formed by physically superimposing at least two of the above materials, such as AlN layer + AlON layer, etc. Combining the high mobility characteristics of two-dimensional materials with the stability of traditional gate dielectrics themselves, using them as composite gate dielectric film layers of SiC-based MOS devices not only ensures the reduction of the interface state between the dielectric layer and SiC, but also ensures the stability and reliability of the device gate dielectric layer.

[0104] The technical solution of the present invention is to comprehensively consider aspects such as channel mobility and stability, select two-dimensional materials (such as molybdenum disulfide (MoS2) and boron nitride (BN) films, etc.), and combine them with traditional dielectric films SiO2 or Al2O3 high-k dielectric materials to form a gate dielectric film to improve the channel carrier mobility and surface conductivity of SiC-based MOS devices. Specifically: (1) By combining two-dimensional materials with three-dimensional SiC materials, the carrier scattering of the channel electrical transport layer by the SiC interface dangling bonds can be reduced, and the unique transport characteristics and lattice matching advantages of two-dimensional materials are utilized to improve the carrier mobility characteristics of the channel electrical transport layer of the SiC-based MOS device. (2) Some two-dimensional materials have the advantages of excellent electrical insulation, high thermal conductivity, excellent chemical stability and atomically flat surface, such as the critical breakdown electric field of h-BN is as high as 8MV / cm, and the melting point exceeds 3000°C. Therefore, as the gate dielectric layer of the field effect transistor, it is beneficial to improve the gate oxide reliability of the SiC-based MOS device. At the same time, the MOS device of the present invention can be used to manufacture lateral metal-oxide-semiconductor-field-effect transistors (MOSFETs), vertical MOSFET devices, and insulated gate bipolar transistors (IGBTs), etc., which should all be included in the protection scope of the present disclosure and have thermal stability and high-voltage breakdown capability.

[0105] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a SiC-based MOS device, characterized in that: The following steps are involved: S1. Cleaning the SiC epitaxial material substrate; S2. Depositing a two-dimensional material thin film layer on a SiC epitaxial material substrate, wherein the two-dimensional material thin film layer is MoS2, BN material, Bi2Te3 or Bi2Se3; S3. Depositing an oxide thin film layer on the two-dimensional material thin film layer by chemical vapor deposition or physical vapor deposition, wherein the oxide thin film layer is SiO2, Al2O3, AlON or HfO2, and then annealing the two-dimensional material / oxide composite thin film dielectric layer formed in step S2 and step S3; the conditions for annealing the formed two-dimensional material / oxide composite thin film dielectric layer in step S3 include: an annealing temperature range of 400°C to 1300°C, an annealing time of 0.5 to 3 hours, and an annealing atmosphere of N2, Ar, NO, N2O, POCl3, H2, NH3, P2O5 or Sb+NO; S4. Fabricating an ohmic contact electrode layer on the back side of the SiC epitaxial material substrate; S5. Fabricate a gate electrode layer on the oxide thin film material layer to complete the preparation of the SiC-based MOS device.

2. The method for preparing a SiC-based MOS device according to claim 1, characterized in that: The thickness of the two-dimensional material film layer ranges from 1 to 50 nm.

3. The method for preparing a SiC-based MOS device according to claim 1, characterized in that: The thickness of the oxide film layer ranges from 5 to 50 nm.

4. The method for preparing a SiC-based MOS device according to claim 1, characterized in that: The annealing temperature range of the ohmic contact electrode layer in step S4 is 600° C. to 1100° C., and the annealing atmosphere is nitrogen or argon.

5. The method for preparing a SiC-based MOS device according to claim 1, characterized in that: The gate electrode layer in step S5 is Al, Ni, Ti, W, Mo, Ag, Au, Pt or a composite metal layer thereof.

6. A SiC-based MOS device prepared by the method according to claim 1, characterized in that: It includes an ohmic contact electrode layer, a SiC epitaxial material substrate layer, a two-dimensional material film layer, an oxide film layer and a gate electrode layer arranged in sequence from bottom to top; the two-dimensional material film layer is MoS2, BN material, Bi2Te3 or Bi2Se3, and the oxide film layer is SiO2, Al2O3, AlON or HfO2.

7. A SiC-based MOS device according to claim 6, characterized in that: The thickness of the two-dimensional material thin film layer ranges from 1 to 50 nm.

8. A SiC-based MOS device according to claim 6, characterized in that: The thickness of the oxide film layer is in the range of 5 to 50 nm.

9. Application of a SiC-based MOS device according to any one of claims 6 to 8, characterized in that: The SiC-based MOS device is used as a SiC-based MOS cell to manufacture a lateral MOSFET device, a vertical MOSFET device or an IGBT device, and the SiC-based MOS cell structure is a planar structure or a trench structure.

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