Semiconductor device and method for providing gate structure for multiple components thereof

Abstract

The present disclosure provides a semiconductor device and a method for providing a gate structure for multiple components of the semiconductor device. The method comprises the following steps: providing a silicate layer. providing a high dielectric constant layer on the silicate layer. providing a work function metal layer on the high dielectric constant layer. performing low temperature annealing after providing the high dielectric constant layer. providing a contact metal layer on the work function metal layer. The method of the present disclosure is applicable to significantly smaller devices.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 575,357, filed on October 20, 2017, and entitled “METHOD FOR FORMING MULTI-Vt DEVICES FOR CMOS,” and U.S. Patent Application No. 15 / 898,420, filed on February 16, 2018, and entitled “METHOD FOR FORMING MULTI-Vt DEVICES FOR CMOS,” which are assigned to the assignee of this application and are incorporated herein by reference. Technical Field

[0003] The present application generally relates to methods of forming multi-threshold voltage devices and devices formed thereby. Background Art

[0004] For various applications, it may be desirable to provide a semiconductor device in which the component transistors have different threshold voltages. Such a semiconductor device is referred to as a multi-threshold voltage (multi-Vt) device. For example, a particular integrated circuit may combine static random access memory (SRAM) and logic. SRAM transistors generally require a higher threshold voltage than logic transistors. Low threshold voltage (LVt) transistors may therefore be used in the logic portion of the semiconductor device, while regular threshold voltage (RVt) transistors may be used in the SRAM portion of the semiconductor device. Therefore, a multi-threshold voltage semiconductor device including transistors having different threshold voltages is desirable.

[0005] Conventional methods for providing multi-threshold voltage devices rely heavily on stacks that include a reactive work function metal (e.g., Al and / or Ti) with a mid-gap work function metal (e.g., TaN and / or TiN) placed on top for adjusting the threshold voltage of the device. For example, a stack consisting of TiN / TaN / TiAlC / TiN may be provided on a high dielectric constant layer for use as a transistor gate. The change in the threshold voltage of the transistor depends on the thickness of the stacked layers. The TiN / TaN / TiAlC / TiN stack is typically of large thickness to provide the desired threshold voltage range. For example, while effective for pitches approaching twenty nanometers, for low replacement metal gate (RMG) pitches of a dozen nanometers, a TiN / TaN / TiAlC / TiN stack placed on top of a high dielectric constant layer (a few nanometers thick) may begin to merge.

[0006] The current scaling trend in semiconductor devices has provided a lower RMG spacing, thereby achieving a higher device density. There are architectures such as fin field effect transistors (finFET), gate all around FETs (GAA-FET) and replacement metal gate FETs (RMG-FET) to solve certain key problems at scaled nodes, such as short channel effect (SCE). However, this architecture will not specifically solve the problems in multi-threshold voltage devices. Although the use of work function metal stacks is very effective for current nodes, problems will arise at lower spacings at extremely scaled nodes. As the RMG spacing decreases due to scaling, relatively thick work function metal stacks may merge. In other words, considering the topology of the underlying surface at the extremely scaled node, a work function metal stack thick enough to provide the desired threshold voltage change may not be able to fit into the available RMG spacing. As described above, such stacks may begin to merge at lower spacings. As multi-threshold voltage devices are scaled to smaller sizes, the variation in threshold voltage (sigma Vt) may also increase. This is because random variations in the electron work function (eWF) are exacerbated for smaller polycrystalline work function metals.

[0007] There are mechanisms for changing the threshold voltage without increasing the thickness of the work function metal stack and for addressing eWF variations. However, each approach has its own drawbacks. Therefore, an improved mechanism is desired to control the threshold voltage of a multi-threshold voltage semiconductor device. Summary of the invention

[0008] A method provides a gate structure for multiple components of a semiconductor device. A silicate layer is provided. In one aspect, a silicate layer is provided on a channel of a complementary metal oxide semiconductor (CMOS) device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after providing the high dielectric constant layer. A contact metal layer is provided on the work function metal layer.

[0009] The methods described herein change the threshold voltage of a transistor by changing the thickness of the silicate layer by no more than 1 nanometer. In some embodiments, a thickness difference of a few angstroms may cause the threshold voltage to change by tens of volts or more. Thus, a multi-threshold voltage transistor may be provided at a more extreme scaling node. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flow chart illustrating an exemplary embodiment of a method for providing a multi-threshold voltage gate structure in a semiconductor device.

[0011] Figure 2a to Figure 2c Portions of an exemplary embodiment of a gate structure during fabrication are shown.

[0012] Figure 3 is a flow chart illustrating an exemplary embodiment of a method for providing a multi-threshold voltage transistor in a semiconductor device.

[0013] Figures 4 to 13 Portions of an exemplary embodiment of a multi-threshold voltage semiconductor device during fabrication are depicted. DETAILED DESCRIPTION

[0014] The exemplary embodiments relate to the formation of multi-threshold voltage semiconductor devices. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the exemplary embodiments and general principles and features described herein will be apparent. The exemplary embodiments are primarily described with respect to specific methods and systems provided in specific embodiments. However, the methods and systems will also function effectively in other embodiments.

[0015] Phrases such as "exemplary embodiment," "one embodiment," and "another embodiment" may refer to the same or different embodiments and multiple embodiments. The embodiments will be described with respect to systems and / or devices having certain components. However, the systems and / or devices may include more or fewer components than those shown in the figures, and the arrangement and types of components may vary without departing from the scope of the invention. Exemplary embodiments will also be described in the context of specific methods having certain steps. However, the methods and systems will also work effectively for other methods having different and / or additional steps and steps in different orders that do not contradict the exemplary embodiments. Therefore, the present invention is not intended to be limited to the embodiments shown in the figures, but is intended to be consistent with the widest scope consistent with the principles and features described herein.

[0016] The terms "a and an," "the," and similar referents used in the context of describing the invention (especially in the context of the following claims) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" should be construed as open-ended terms (i.e., meaning "including but not limited to") unless otherwise noted.

[0017] Unless otherwise defined, the meaning of all technical and scientific terms used herein is the same as that commonly understood by those of ordinary skill in the art to which the present invention belongs. It should be noted that, unless otherwise specified, any examples or exemplary terms provided herein are only intended to better illustrate the present invention and are not intended to limit the scope of the present invention. In addition, unless otherwise defined, all terms defined in commonly used dictionaries should not be over-interpreted.

[0018] A method provides a gate structure for multiple components of a semiconductor device. A silicate layer is provided. In one aspect, a silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after providing the work function metal layer. A contact metal layer is provided on the work function metal layer.

[0019] Figure 1 1 is a flow chart illustrating an exemplary embodiment of a method 100 for providing a gate structure for a component (i.e., a transistor) in a semiconductor device. For simplicity, some steps may be omitted, performed in another order, and / or combined. Additionally, the method 100 may begin after other steps for forming a semiconductor device have been performed. For example, the method may begin after source and drain regions have been defined and various structures have been provided. Figure 2a to Figure 2c Portions of an exemplary embodiment of a semiconductor device 200 (eg, a MOS device) during fabrication of a gate structure using method 100 are shown. Figure 2a to Figure 2c Not all components are shown and Figure 2a to Figure 2c The method 100 is not drawn to scale. For example, various structures that may have been formed before the gate structure are not shown. In addition, the thickness of various layers may be exaggerated for explanation purposes. The method 100 is described in the context of the semiconductor device 200. However, the method 100 may also be used in different semiconductor devices.

[0020] A silicate layer is provided on the underlying layer, via step 102. In some embodiments, an interfacial oxide layer (e.g., SiO 2 ). The silicate layer deposited in step 102 is used to form a dipole discussed below, which can effectively change the threshold voltage Vt of the formed component. For example, the silicate layer provided in step 102 may have a total thickness of no more than 2 nanometers. In some embodiments, the thickness of the silicate layer is at least 0.1 nm and no greater than 1 nanometer. Thicknesses in this range (one angstrom to ten angstroms) can be sufficient to change the threshold voltage of the fabricated device by up to hundreds of millivolts. In other words, very small changes in the thickness of the silicate layer can cause significant changes in the threshold voltage. Therefore, tailoring the thickness of the silicate layer provided in step 102 provides an effective mechanism to set the threshold voltage of the fabricated device to a desired level. Therefore, based on the desired threshold voltage, the silicate layer provided in step 102 may be thicker for some components, thinner for some components, and / or non-existent for other components.

[0021] The material used in the silicate layer provided in step 102 may be selected from a variety of silicates. For example, the silicate layer may include one or more of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx, and MgSiOx, where Ox represents an oxide with varying stoichiometry. In addition, the silicon content in each silicate layer may vary, for example, from 0 to no more than 70 atomic percent. The silicon content in the silicate may be used to customize the change in threshold voltage. The material selected depends on the sign of the desired voltage change and the specific device being formed (i.e., nFET or pFET). If the device being fabricated is an nFET and the threshold voltage is desired to be changed downward (negatively), in some embodiments, the silicate provided in step 102 may include one or more of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, and SrSiOx. If the device being fabricated is an nFET and the threshold voltage is desired to be changed upward (positively), the silicate provided in step 102 may include at least one of the following: AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx, and MgSiOx. If the device being fabricated is a pFET and the threshold voltage is desired to be changed upward, the silicate provided in step 102 may include at least one of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, and SrSiOx. If the device being provided is a pFET and a downward shift in threshold voltage is desired, the silicate provided in step 102 may include one or more of the following: AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx, and MgSiOx. Other silicates may be used in other embodiments to shift the voltage up or down. Thus, by selecting an appropriate silicate and configuring the thickness of the silicate, a desired shift in threshold voltage may be obtained.

[0022] The thickness of the silicate layer provided in step 102 varies for different regions / components being fabricated on the semiconductor device. This can be accomplished by depositing and etching sub-layers of silicate multiple times. In some embodiments, the sub-layers are all formed of the same silicate. In other embodiments, the sub-layers may be formed of different silicates as desired. However, the total thickness of the silicate layer is within the above range.

[0023] Figure 2aThe semiconductor device 200 is shown after performing step 102. For simplicity, the layers are shown only in the area where the device will be formed, and other structures (such as spacers, interconnects, or other features) are not shown. However, some or all of the layers may extend beyond the device being fabricated. The layers are also shown as being planar. However, in some embodiments, the layers may be three-dimensional, for example, when the underlying structure is a semiconductor fin. In addition, as mentioned previously, Figure 2a to Figure 2c The thickness and other dimensions shown are not drawn to scale.

[0024] Components 240, 242, 244, 246 are being fabricated and may each be a transistor. For example, each of components 240, 242, 244, 246 may be a gate all around FET or a replacement metal gate FET. In some embodiments, all transistors on semiconductor device 200 may include dipoles. In other embodiments, some transistors (not shown) may not include the dipoles described herein. An underlying semiconductor 202 is shown. In some embodiments, semiconductor 202 is Si. In other embodiments, other substrates include, but are not limited to, silicon germanium (SiGe) that allows the formation of native SiOx, silicon on insulator (SOI), strained silicon on insulator (sSOI), silicon germanium on insulator (SGOI), strained silicon germanium on insulator (sSGOI), and the like. An interface oxide 204 is also shown. In some embodiments, the interface oxide 204 is silicon dioxide. Silicate layers 210A, 210B, 210C, 210D are provided. The transistors (i.e., components 240, 242, 244, 246) include silicate layers 210A, 210B, 210C, 210D of different thicknesses, respectively. Therefore, components 240, 242, 244, 246 should have different Vt changes.

[0025] After the silicate layers 210A, 210B, 210C, 210D have been formed, a high dielectric constant (high K) layer is provided on the silicate layers 210A, 210B, 210C, 210D through step 104. For example, a layer of HfOx may be formed in step 104. In some embodiments, the formation of the high dielectric constant layer may be performed at a temperature of 200 degrees Celsius and not greater than 600 degrees Celsius.

[0026] A work function metal layer is provided on the high dielectric constant layer, via step 106. Although all metals can be characterized by a work function, the layer is referred to as a work function metal layer because the electron work function (eWF) of the metal is a factor that determines the threshold voltage of the device being formed. For example, the work function metal layer may include at least one of the following: TiN, TaN, TiSiN, TiTaN, WN, and TiTaSiN. Other metals may be used in other embodiments. The work function metal is also relatively thin. For example, the work function metal thickness may be no greater than 3 nanometers. Figure 2b The semiconductor device 200 is shown after performing step 106. Therefore, the work function metal ( Figure 2b The WFM layer 220 and the high dielectric constant (HK) layer 215 in the embodiment of the present invention.

[0027] By step 108, low temperature annealing is performed after forming the high dielectric constant layer 215 and the work function metal layer 220. Low temperature annealing can be used to homogenize the mixing of the silicate layer 210A, 210B, 210C, 210D and the high dielectric constant layer 215 at the interface. In addition, annealing can help control the final threshold voltage. Step 108 may include performing annealing at an annealing temperature of at least two hundred degrees Celsius and not more than eight hundred degrees Celsius. In some embodiments, the maximum annealing temperature is not more than six hundred degrees Celsius. In some embodiments, the annealing temperature is at least four hundred degrees Celsius. In some such embodiments, the temperature of annealing is at least five hundred degrees Celsius.

[0028] In some embodiments, the annealing in step 108 is performed using a sacrificial active metal layer ( Figure 2a to Figure 2c 240, 242, 244, 246 to provide additional control over the final threshold voltage. Alternatively, such a reactive metal layer may be omitted from some or all of the components 240, 242, 244, 246.

[0029] A contact metal layer is then provided on the work function metal layer, via step 110. In some embodiments, the contact metal layer may be W or Co. However, other metals may be used in other embodiments. Figure 2c The semiconductor device 200 is shown after performing step 110. Thus, a contact metal layer 230 has been provided for each of the components 240, 242, 244, 246 being formed. The fabrication of the semiconductor device 200 may then be completed.

[0030] Using the method 100, the threshold voltages of transistors (i.e., components 240, 242, 244, 246) can be adjusted separately to make the semiconductor device 200 a multi-threshold voltage device. The work function metal layer 220 used in the transistors (i.e., components 240, 242, 244, 246) sets a baseline threshold voltage for each of the transistors (i.e., components 240, 242, 244, 246). The dipole formed using the silicate layers 210A, 210B, 210C, 210D can change the baseline threshold voltage up or down depending on the thickness of the silicate layers 210A, 210B, 210C, 210D and the materials used. Assuming that the same silicate is used for all components 240, 242, 244, 246, component 246 has the largest change, component 242 has a mid-range change, component 240 has a smaller change, and component 244 has the smallest change. As described above, the use of a sacrificial active metal layer during low temperature annealing can provide fine adjustment of the threshold voltage. Thus, a multi-threshold voltage semiconductor device 200 can be provided.

[0031] The semiconductor device 200 and method 100 are applicable to significantly smaller devices. As indicated above, the work function metal layer 220 has a maximum thickness of approximately 3 nanometers in some embodiments. This thickness is significantly less than the total thickness of the work function metal stack (e.g., TiN / TaN / TiAlC / TiN). This work function metal layer 220 provides a reference threshold voltage. The silicate layer 210A, 210B, 210C, 210D can be used to provide a change in threshold voltage. The thickness of the combination of the silicate layer 210A, 210B, 210C, 210D and the high dielectric constant layer 215 can be less than 2 nanometers. In some embodiments, for all components 240, 242, 244, 246, the silicate layer 210A, 210B, 210C, 210D thickness can be at least 0.1 nanometers and no greater than 1 nanometer. A thickness variation of less than 1 nanometer of the silicate layers 210A, 210B, 210C, 210D can significantly change the reference threshold voltage. For example, a difference in silicate layer thickness of about a few angstroms between component 242 and component 246 can produce a threshold voltage difference of one hundred millivolts or more. Thus, a multi-threshold voltage device (i.e., semiconductor device 200) can be provided without requiring the stack of layers (i.e., silicate layers 210A, 210B, 210C, 210D, high dielectric constant layer 215, work function metal layer 220, and contact metal layer 230) to have a large total thickness. Using method 100, a multi-threshold voltage device (i.e., semiconductor device 200) consistent with an RMG pitch of about 7 nanometers to 8 nanometers or less can be made. The stack can also be thin enough to allow the remaining space to be used for contact metal filling. This can reduce resistivity. Other technologies with small pitches and / or larger RMG pitches can be easily implemented using method 100. Thus, the method 100 may provide a multi-threshold voltage device (ie, semiconductor device 200 ) that may be scaled to significantly smaller sizes.

[0032] Method 100 may also improve manufacturability. The stack for components 240, 242, 244, 246 does not contain aluminum in at least some embodiments. Thus, the high temperature sensitivity issues associated with aluminum may be avoided. Small changes (e.g., a few percentages) in Si (caused by the atomic layer deposition (ALD) process and by diffusion on silicon) may not significantly change the magnitude of the dipole voltage set by the silicate layers 210A, 210B, 210C, 210D. This is because the band offset is already fixed by the bulk La and Si content (e.g., from LaSiOx). In contrast, aluminum diffuses slightly (e.g., in an amount of 0.1%) into the HfO 2The high dielectric constant layer can cause a significant change in Vt from the target value. Silicates (e.g., LaSiOx) deposited at low temperatures of about 300°C are naturally amorphous. The induced dipole voltage may not have crystalline orientation dependence. This means that the local sigma Vtissue of thick conventional stacks can be alleviated or avoided. Therefore, the method 100 and the multi-threshold voltage device (i.e., semiconductor device 200) have improved performance and manufacturability, especially for smaller device sizes.

[0033] Figure 3 1 is a flow chart illustrating an exemplary embodiment of a method 120 for providing a gate structure for a transistor in a multi-threshold voltage semiconductor device. For simplicity, some steps may be omitted, performed in another order, and / or combined. Additionally, the method 120 may begin after other steps for forming a semiconductor device have been performed. For example, the method may begin after source and drain regions have been defined and various structures have been provided. Figures 4 to 13 Portions of an exemplary embodiment of a semiconductor device 250 (eg, a MOS device) are shown during fabrication of a gate structure using method 100. Figures 4 to 13 Not all components are shown and Figures 4 to 13 It is not drawn to scale. For example, various structures that may have been formed before the gate structure are not shown in the figure. In addition, the thickness of each layer may be exaggerated for explanation purposes. For clarity, only the structure located in the area where the transistor is formed is shown. Therefore, the underlying topology is not shown. However, the transistor formed is not limited to planar transistors. Instead, method 120 can be incorporated into other architectures including but not limited to FinFET, GAA-FET and RMG-FET. Method 120 is described in the context of semiconductor device 250. However, method 120 can also be used for different semiconductor devices.

[0034] A thin interfacial oxide layer is formed on the channel region, via step 122. The interfacial oxide may include SiOx and may be formed naturally on the channel. In some embodiments, the semiconductor is selected from Si, SiGe, SOI, sSOI, SGOI, sSGOI, and similar substrates that allow for the formation of native SiOx.

[0035] By step 124, a first silicate layer is provided on the channel. The silicate layer provided in step 124 has a total thickness of no more than 2 nanometers. In some embodiments, the thickness of the silicate layer is at least 0.1 nm and no more than 1 nanometer. Since method 120 utilizes multiple silicate layers, the thickness of the layer provided in step 124 can be at the lower end of this range. The material used in the first silicate layer provided in step 124 can be selected from various silicates. For example, the silicate layer can include one or more of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx. In addition, the silicon content in each silicate layer can be varied to control the maximum change in threshold voltage. For example, the silicon content can be in the range of 0 to no more than 70 atomic percent. The selected material depends on the sign and conductivity type of the desired voltage change of the device formed in the manner discussed above with reference to method 100.

[0036] Figure 4 Semiconductor device 250 is shown after step 124 is performed. Components 292, 294, and 296 are being fabricated and components 292, 294, 296 may each be a transistor. An underlying semiconductor 252 is shown. An interfacial oxide 254 is also shown. A first silicate layer 262 has been provided and is shown as being located on the transistors (i.e., components 292, 294, 296).

[0037] Since the transistors (i.e., components 292, 294, 296) are desired to have different threshold voltages, the first silicate layer 262 is selectively removed from some components by step 126. Step 126 includes providing a mask to cover the areas where it is desired to retain the first silicate layer 262. The first silicate layer is then removed from the exposed areas and the mask is removed. Figure 5 Semiconductor device 250 is shown after step 126 is performed. First silicate layer 262 still remains on components 292 and 294 , but has been removed from component 296 .

[0038] A second silicate layer is provided on the channel, via step 128. The material and thickness of the second silicate layer are selected in a similar manner as the material and thickness for the first silicate layer 262. In some embodiments, the same material and thickness are used. In other embodiments, one or both of the material and thickness may be different. Figure 6 The semiconductor device 250 is shown after performing step 128. Thus, a second silicate layer 264 has been provided on the transistors (ie, elements 292, 294, 296).

[0039] By step 130, the removal step 126 and the silicate layer deposition step 128 may be optionally repeated. Thus, a silicate layer having a desired thickness is accumulated on the transistors (i.e., components 292, 294, 296). This enables various threshold voltages to be set for the semiconductor device 250. In addition, although the deposition / mask / removal steps are described herein, in alternative embodiments, these steps may be replaced by mask / deposition steps to allow the silicate layer to be selectively deposited on desired areas of the semiconductor device 250.

[0040] Figure 7 The semiconductor device 250 is shown after one iteration of step 130 has been completed. Figure 6 and Figure 7 A comparison of the components 292 and 296 shows that the second silicate layer 264 has been removed from the components 292 and 296. Therefore, each component 292, 294, 294 has a silicate layer of different thickness. Component 296 has no silicate layer (e.g., zero thickness), component 292 has a thinner silicate layer 262, and component 294 has a thicker silicate layer 262 / 264. Figure 8 The semiconductor device 250 is depicted after another iteration of step 130 has been completed. Thus, a silicate layer 266 has been provided on each of the components 292, 294, 296. The change in threshold voltage is based on the thickness of the silicate layer of the transistor. Thus, component 296 has the smallest magnitude change (thin silicate layer 266). Component 292 has an intermediate magnitude change (the silicate layer 262 / 266 formed by the first silicate layer 262 and the third silicate layer 266 is thicker). Component 294 has the largest magnitude change (the silicate layer 262 / 264 / 266 formed by the first silicate layer 262, the second silicate layer 264, and the third silicate layer 266 is the thickest). Steps 124, 126, 128, and 130 are similar to step 102 of method 100.

[0041] A high dielectric constant layer is provided on the previously formed silicate layer, via step 132. For example, a layer of HfOx may be formed in step 132. In some embodiments, the formation of the high dielectric constant layer may be performed at a temperature of two hundred degrees Celsius and not greater than six hundred degrees Celsius. In some embodiments, the formation of the high dielectric constant layer may be performed at a temperature not exceeding three hundred degrees Celsius. Fig. 9 The semiconductor device 250 is depicted after step 132. Thus, a high dielectric constant (HK) layer 270 is shown as being located over the transistors (ie, components 292, 294, 296).

[0042] A work function metal layer is provided on the high dielectric constant layer, via step 134. For example, the work function metal layer may include at least one of the following: TiN, TaN, TiSiN, TiTaN, WN, and TiTaSiN. Other metals may be used in other embodiments. The work function metal layer is also relatively thin. For example, the thickness of the work function metal layer is no greater than 3 nanometers. Fig.10 The semiconductor device 250 is shown after performing step 134. Thus, a work function metal (WFM) layer 280 has been formed over the transistors (ie, elements 292, 294, 296).

[0043] A sacrificial active metal layer is provided, via step 136. The active metal layer may include one or more of Si, Ti, Zr, Hf, and La and may have a thickness of no greater than 4 nanometers. Other materials and other thicknesses may also be used. Such metals may be used during annealing to provide additional control over the final threshold voltage. In other words, the active metal layer provided in step 136 provides fine control over the change in threshold voltage. Fig.11 The multi-threshold voltage semiconductor device 250 is shown after performing step 136. Thus, a reactive metal layer (RM) 285 has been provided. In the illustrated embodiment, the reactive metal layer 285 is located on all transistors (i.e., components 292, 294, 296). In other embodiments, the reactive metal layer 285 may be omitted from some or all transistors (i.e., components 292, 294, 296).

[0044] A low temperature anneal is performed, via step 138. A low temperature anneal may be used to homogenize the mixture of silicate layer 262 / 264 / 266 and high dielectric constant layer 270. Step 138 may include performing the anneal at an annealing temperature of at least two hundred degrees Celsius and no greater than eight hundred degrees Celsius. In some embodiments, the maximum annealing temperature is no greater than six hundred degrees Celsius. In some such embodiments, the annealing temperature is at least four hundred degrees Celsius.

[0045] In addition to the above-mentioned beneficial effects, the annealing performed in step 138 can also improve the dipole modulation of the threshold voltage of the transistor (i.e., components 292, 294, 296) due to the use of the active metal layer 285. The active metal is an oxygen getter so that the material can scavenge oxygen atoms from the underlying oxygen-containing layer during the anneal. The oxygen atoms can then be redistributed in various layers including the work function metal layer 280. This will cause the modulation of the oxygen related dipoles around the high dielectric constant layer / work function metal layer interface, the high dielectric constant layer / silicate layer interface, and the silicate layer / native oxide SiOx interface. The thickness of the interfacial oxide layer may also vary. The degree of modulation varies with the thickness of the work function metal layer 280, the thickness of the active metal layer 285, and the annealing temperature. As a result, the threshold voltage can be further modulated in the range of tens of millivolts. This scavenging phenomenon can still occur even at intermediate temperatures and / or low temperatures of approximately 500 degrees Celsius to approximately 600 degrees Celsius. In other words, clearing may occur at the temperature used in the annealing of step 138. Thus, the threshold voltage of the transistors (ie, components 292, 294, 296) may be altered by both the presence of silicate layers 262 / 264 / 266 and the use of active metal layer 285.

[0046] Through step 140 , the active metal layer 285 is removed. Fig.12 The semiconductor device 250 is shown after removing the active metal layer 285. A contact metal layer is then provided on the work function metal layer, via step 142. In some embodiments, the contact metal layer may be W or Co. However, other metals may be used in other embodiments. Fig.13 The semiconductor device 250 is shown after performing step 142. Thus, a contact metal layer 290 has been provided for each of the components 292, 294, 296 being formed. Fabrication of the semiconductor device 250 may then be completed.

[0047] Method 120 and semiconductor device 250 may share the benefits of method 100 and semiconductor device 200. Using method 120, the threshold voltages of transistors (i.e., components 292, 294, 296) may be fine-tuned individually to provide a multi-threshold voltage semiconductor device 250. Work function metal layer 280 sets a reference threshold voltage for each of the transistors (i.e., components 292, 294, 296). The dipole formed using silicate layer 262 / 264 / 266 may change the reference threshold voltage up or down depending on the thickness of silicate layer 262 / 264 / 266 and the material used. Assuming the same silicate is used for all components, component 294 has the largest change. Component 292 has a smaller change. Component 296 has the smallest change. Using a sacrificial active metal layer during low temperature annealing may provide fine tuning of the threshold voltage. Thus, a multi-threshold voltage semiconductor device 250 may be provided.

[0048] The semiconductor device 250 and method 120 are applicable to significantly smaller devices. The thickness of the stack used can be significantly reduced while still achieving significant variation in threshold voltage between individual transistors. The method 120 can therefore be used for smaller devices regardless of whether the stacks are merged. No materials such as Al need to be used in the process 120, which can avoid temperature issues associated with aluminum. Therefore, the method 120 can provide a multi-threshold voltage device 250 that can be scaled to significantly smaller sizes.

[0049] Methods and systems for providing a multi-threshold voltage semiconductor device have been described. The methods and systems have been described according to the exemplary embodiments shown, and those skilled in the art will readily recognize that variations of the embodiments are possible, and any variations will be within the spirit and scope of the methods and systems. Therefore, many modifications may be made by those skilled in the art without departing from the spirit and scope of the appended claims.

Claims

1. A method for providing a gate structure for a plurality of components of a semiconductor device, characterized in that: The method comprises: providing a silicate layer; providing a high dielectric constant layer on the silicate layer; providing a work function metal layer on the high dielectric constant layer; After the step of providing the high dielectric constant layer, performing low temperature annealing; and providing a contact metal layer on the work function metal layer, A first portion of the plurality of components has a first thickness of the silicate layer, and a second portion of the plurality of components has a second thickness of the silicate layer, the second thickness being different from the first thickness, the step of providing the silicate layer further comprising: depositing a first silicate layer on at least the first portion and the second portion of the plurality of components; removing at least a portion of the first silicate layer from the first portion of the plurality of components; and A second silicate layer is provided on the first portion and the second portion of the plurality of components.

2. The method according to claim 1, characterized in that: The first thickness and the second thickness are each less than 2 nanometers.

3. The method according to claim 2, characterized in that The first thickness and the second thickness are each no greater than 1 nanometer and at least 0.1 nanometer.

4. The method according to claim 1, characterized in that: Each of the first silicate layer and the second silicate layer includes at least one of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx, and MgSiOx.

5. The method according to claim 1, characterized in that A third portion of the plurality of components has a third thickness of the silicate layer, the third thickness being different from the first thickness and different from the second thickness, the step of providing the silicate layer further comprising: depositing a third silicate layer on at least the first portion, the second portion, and the third portion of the plurality of components; and removing at least a portion of the third silicate layer from the first portion and the second portion of the plurality of components, wherein the step of depositing the first silicate layer comprises depositing the first silicate layer on the third portion of the plurality of components, wherein the step of removing the at least a portion of the first silicate layer from the first portion of the plurality of components is performed such that the first silicate layer remains on the third portion of the plurality of components, and Wherein the step of providing the second silicate layer on the first portion and the second portion of the plurality of components further provides the second silicate layer on the third portion of the plurality of components.

6. The method according to claim 1, characterized in that Also includes: Before the step of providing the contact metal layer and before the step of performing the low temperature annealing, providing an active metal layer on the work function metal layer, and the step of performing the low temperature annealing is performed before the step of providing the contact metal layer; as well as After the step of performing the low temperature annealing and before the step of providing the contact metal layer, the active metal layer is removed.

7. The method according to claim 6, characterized in that The active metal layer includes at least one of Si, Ti, Zr, Hf and La, and the active metal layer has a thickness of no greater than 4 nanometers.

8. The method according to claim 6, characterized in that During the low temperature annealing, the active metal layer resides on only a portion of the plurality of components, and the step of providing the active metal layer comprises: depositing a layer comprising a desired active metal; and A portion of the layer is removed such that the active metal layer remains on the portion of the plurality of components.

9. The method according to claim 1, characterized in that: The work function metal layer includes at least one of TiN, TaN, TiSiN, TiTaN, WN and TiTaSiN, and the work function metal layer has a thickness of no greater than 3 nanometers.

10. The method according to claim 1, characterized in that The low temperature annealing has an annealing temperature not greater than six hundred degrees Celsius.

11. The method according to claim 1, characterized in that: The high dielectric constant layer has a dielectric constant greater than a dielectric constant of silicon dioxide.

12. The method according to claim 11, characterized in that The high dielectric constant layer includes hafnium oxide.

13. The method according to claim 1, characterized in that Also includes: Prior to the step of providing the silicate layer, an interfacial oxide layer is provided.

14. A method for providing a plurality of transistors on a semiconductor device, characterized in that: The method comprises: providing a source and a drain for each of the plurality of transistors, and providing a channel for each of the plurality of transistors, the channel being located between the source and the drain; and Providing a gate structure on the channel of each transistor in the plurality of transistors, the step of providing the gate structure comprising: providing an interfacial oxide layer on at least the channel; A silicate layer is provided on the interface oxide layer, a first portion of the plurality of transistors having a first thickness of the silicate layer, a second portion of the plurality of transistors having a second thickness of the silicate layer, the second thickness being different from the first thickness, the step of providing the silicate layer comprising: depositing a first silicate layer on the first portion and the second portion of the plurality of transistors; removing at least a portion of the first silicate layer from the first portion of the plurality of transistors; A second silicate layer is provided on the first portion and the second portion of the plurality of transistors, each of the first silicate layer and the second silicate layer comprising at least one of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx; providing a high dielectric constant layer on the silicate layer; Providing a work function metal layer on the high dielectric constant layer, the work function metal layer comprising at least one of TiN, TaN, TiSiN, TiTaN, WN and TiTaSiN, the work function metal layer having a thickness of no greater than 3 nanometers; providing an active metal layer on at least a portion of the work function metal layer, the active metal layer comprising at least one of Si, Ti, Zr, Hf and La; performing low temperature annealing after the step of providing the active metal layer, the low temperature annealing having an annealing temperature of at least two hundred degrees Celsius and not higher than six hundred degrees Celsius; removing the active metal layer after the step of performing the low temperature annealing; and After the step of removing the active metal layer, a contact metal layer is provided on the work function metal layer.

15. A semiconductor device, characterized in that: include: substrate; as well as a plurality of components disposed on the substrate, each of the plurality of components comprising a source, a drain, a channel and a gate structure, the channel being disposed between the source and the drain, the gate structure being adjacent to the channel, the gate structure comprising a silicate layer, a high dielectric constant layer, a work function metal layer and a contact metal layer, the high dielectric constant layer being disposed between the silicate layer and the work function metal layer, the work function metal layer being disposed between the high dielectric constant layer and the contact metal layer, the silicate layer being closer to the substrate than the high dielectric constant layer, the semiconductor device being exposed to temperatures less than one thousand degrees Celsius only during and after the formation of the gate structure, the plurality of components having a plurality of threshold voltages, the silicate layer included in a first portion of the plurality of components has a first thickness and includes a first silicate layer and a second silicate layer stacked on the first silicate layer, and the silicate layer included in a second portion of the plurality of components has a second thickness different from the first thickness and includes a third silicate layer, The thickness of the third silicate layer is equal to the thickness of the second silicate layer.

16. The semiconductor device according to claim 15, wherein: The silicate layer includes at least one of the following: LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx.

17. The semiconductor device according to claim 15, wherein: The each of the plurality of components is a gate-around field effect transistor.

18. The semiconductor device according to claim 15, wherein: The each of the plurality of components is a replacement metal gate field effect transistor.

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