Film for packaging substrates, semiconductor packaging and display devices

Abstract

A display device comprises: a film substrate comprising a first surface and a second surface, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and comprising an input terminal and a test terminal arranged along a first direction; a first line extending from the input terminal on the first surface along a second direction intersecting the first direction; and a second line comprising: a first extension extending on the first surface, a second extension extending on the second surface, and a first through hole penetrating the film substrate and connecting the first extension with the second extension, wherein the first extension extends from the test terminal along the second direction and is connected to the first through hole, and the second extension extends from the first through hole to an edge of the second surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0137369 filed on October 23, 2017, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2018-0012957 filed on February 1, 2018, in the Korean Intellectual Property Office, which are hereby incorporated by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a thin film for packaging a substrate, a semiconductor package, a display device, and methods of manufacturing the thin film, the semiconductor package, and the display device. Background Art

[0004] As electronic products become smaller, thinner, and lighter, tape film packaging has been proposed as a high integration density semiconductor chip mounting technology. Examples of tape film packaging include tape carrier packaging and chip-on-film (COF) packaging.

[0005] In COF packaging, the semiconductor chip can be directly bonded on the substrate through flip-chip bonding and can be connected to the external circuit through wires. Summary of the invention

[0006] An embodiment can be implemented by providing a display device, which includes: a thin film substrate including a first surface and a second surface, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface, the semiconductor chip including an input terminal and a test terminal arranged along a first direction; a first line extending from the input terminal on the first surface along a second direction intersecting the first direction; and a second line including: a first extension portion extending on the first surface, a second extension portion extending on the second surface, and a first through hole penetrating the thin film substrate and connecting the first extension portion with the second extension portion, wherein the first extension portion extends from the test terminal along the second direction and is connected to the first through hole, and the second extension portion extends from the first through hole to an edge of the second surface.

[0007] An embodiment can be implemented by providing a semiconductor package, which includes: a thin film substrate, including a packaging area and a first test area adjacent to each other, the thin film substrate including a first surface and a second surface, the first surface being opposite to the second surface; a semiconductor chip, arranged on the first surface and including a first chip pad and a second chip pad arranged along a first direction; a first test pad, arranged on the second surface of the first test area; a first line, arranged on the first surface of the packaging area and the first surface of the first test area, the first line extending from the first chip pad along a second direction intersecting the first direction; and a second line connecting the second chip pad and the first test pad, wherein the second line includes a first through hole, the first through hole penetrating a portion of the packaging area between the semiconductor chip and the first test area.

[0008] An embodiment can be implemented by providing a film for a packaging substrate, the film comprising: a film substrate including a packaging area, a first test area, and a second test area, the first test area being adjacent to one side of the packaging area, and the second test area being adjacent to an opposite side of the packaging area relative to the first test area, the film substrate having a first surface and a second surface, the first surface being opposite to the second surface; a chip mounting area being arranged on the first surface of the packaging area; a first line including a first line end arranged in the chip mounting area; a second line including a second line end, the second line end being arranged in the chip mounting area and opposite to the first line end together arranged along the first direction; a third line, including a third line end, the third line end is arranged in the chip mounting area, and together with the first line end, is arranged along a second direction intersecting the first direction; a first test pad and a second test pad are arranged on a second surface of the first test area; and a third test pad is arranged on a second surface of the second test area, wherein the first line includes a first through hole, the first through hole penetrates the first test area and is connected to the first test pad, the second line includes a second through hole, the second through hole penetrates a portion of the packaging area located between the chip mounting area and the first test area and is connected to the second test pad, and the third line is connected to the third test pad.

[0009] An embodiment can be implemented by providing a method for manufacturing a thin film for a packaging substrate, the method comprising: providing a thin film substrate, so that the thin film substrate includes a packaging area and a first test area adjacent to each other, the thin film substrate having a first surface and a second surface, the first surface being opposite to the second surface; forming a first line including a first line end on the first surface of the packaging area; forming a first test pad on the second surface of the first test area; forming a second line including a second line end on the first surface of the packaging area; and forming a second test pad on the second surface of the first test area, wherein the first line includes a first through hole, the first through hole penetrates the first test area and is connected to the first test pad, and the second line includes a second through hole, the second through hole penetrates a portion of the packaging area located between the second line end and the first test area and is connected to the second test pad.

[0010] An embodiment can be implemented by providing a method for manufacturing a semiconductor package, the method comprising providing a film for a packaging substrate, the film comprising a packaging area and a first test area adjacent to each other, and the film having a first surface and a second surface, the first surface being opposite to the second surface; and forming a semiconductor chip on the first surface of the film, wherein providing the film comprises: forming a first line comprising a first line end on the first surface of the packaging area; forming a first test pad on the second surface of the first test area; forming a second line comprising a second line end on the first surface of the packaging area; and forming a second test pad on the second surface of the first test area, wherein the first line comprises a first through hole, the first through hole penetrates the first test area and is connected to the first test pad, and wherein the second line comprises a second through hole, the second through hole penetrates a portion of the packaging area located between the semiconductor chip and the first test area and is connected to the second test pad.

[0011] An embodiment can be implemented by providing a method for manufacturing a display device, the method comprising: providing a semiconductor package; and attaching a printed circuit and a display panel on the semiconductor package, wherein: the semiconductor package comprises a thin film substrate having a first surface and a second surface, the first surface being opposite to the second surface; a semiconductor chip is disposed on the first surface, the semiconductor chip comprising an input terminal and a test terminal arranged along a first direction; a first line is disposed on the first surface, the first line extending from the input terminal along a second direction intersecting the first direction; and the second line comprises a first extension portion extending on the first surface, a second extension portion extending on the second surface, and a first through hole connecting the first extension portion and the second extension portion, wherein the first extension portion extends from the test terminal along the second direction and is connected to the first through hole, and the second extension portion extends from the first through hole to an edge of the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 A design diagram of a first surface of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0014] Figure 2 Shows Figure 1 Magnified view of region R.

[0015] Figure 3 A design diagram of a second surface of a film according to some exemplary embodiments of the present disclosure is shown.

[0016] Figure 4 Shown along Figure 1 and Figure 3 A cross-sectional view taken along line AA′.

[0017] Figure 5 Shown along Figure 1 and Figure 3 A cross-sectional view taken along line BB′.

[0018] Figure 6 A design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0019] Figure 7 A design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0020] Figure 8 A design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0021] Fig. 9 A design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0022] Fig.10 Shown along Fig. 9 A cross-sectional view taken along line CC′.

[0023] Fig.11 and Fig.12 A cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure is shown.

[0024] Fig.13 and Fig.14 A cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure is shown.

[0025] Fig.15 A perspective view showing a display device according to some exemplary embodiments of the present disclosure is shown.

[0026] Fig.16A cross-sectional view of a display device according to some exemplary embodiments of the present disclosure is shown.

[0027] Fig.17 A cross-sectional view of a display device according to some exemplary embodiments of the present disclosure is shown.

[0028] Fig.18 A flow chart of a method of manufacturing a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0029] Figures 19 to 20 Cross-sectional views showing stages in a method of manufacturing a substrate for packaging according to some exemplary embodiments of the present disclosure.

[0030] Fig.21 A flow chart of a method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure is shown.

[0031] Fig. 22 A flowchart of a method of manufacturing a display device according to some exemplary embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0032] The following will refer to Figures 1 to 10 A thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is described.

[0033] Figure 1 A design diagram of a first surface of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown. Figure 2 Shows Figure 1 Magnified view of region R. Figure 3 A design diagram of a second surface of a film according to some exemplary embodiments of the present disclosure is shown. Figure 4 Shown along Figure 1 and Figure 3 A cross-sectional view taken along line AA′. Figure 5 Shown along Figure 1 and Figure 3 A cross-sectional view taken along line BB′.

[0034] Reference Figures 1 to 5 According to some exemplary embodiments of the present disclosure, the film may include a film substrate 110, a first line 120, a second line 130, a third line 140, a fourth line 150, a first test pad 162, a second test pad 164, a third test pad 166, a fourth test pad 168, a first protectant (resist) film 172 and a second protectant film 174.

[0035] The film substrate 110 may have a first surface 110a and a second surface 110b opposite to each other. For example, the first surface 110a may be an upper surface of the film substrate 110, and the second surface 110b may be a lower surface of the film substrate 110 (eg, Figure 4 ).

[0036] The film substrate 110 may include a package region PR, a first test region TR1, and a second test region TR2. The package region PR may be adjacent to the first test region TR1 and the second test region TR2. For example, the first test region TR1 and the second test region TR2 may be adjacent to corresponding ones of both sides (e.g., opposite sides) of the package region PR, respectively. Therefore, the package region PR may be between the first test region TR1 and the second test region TR2.

[0037] The package region PR may include a chip mounting region CR. The chip mounting region CR may be formed at the center of the package region PR. The chip mounting region CR may be a portion of the film substrate 110 where a chip is to be mounted. Fig.11 region of the semiconductor chip 200.

[0038] The film substrate 110 may be, for example, a flexible film. For example, the film substrate 110 may be a flexible film including polyimide or epoxy resin.

[0039] The first wire 120 may extend on the film substrate 110. A plurality of first wires 120 may be disposed to extend on the film substrate 110.

[0040] In an implementation, the first line 120 may be an input line of a semiconductor package. For example, the first line 120 may include a first line end 120t and a first connection portion 120c.

[0041] The first wire end 120t may be an end portion of the first wire 120 formed in the chip mounting region CR. For example, the first wire end 120t may be an end portion of the first wire 120 connected to the chip mounting region CR. Fig.11 The first wire 120 may extend from the first wire end 120t along the first direction X1. For example, the first wire 120 may extend on the first surface 110a of the package region PR and the first test region TR1.

[0042] The first connection portion 120c may be a portion of the first line 120 formed in the package region PR. The first connection portion 120c may be a portion of the first line 120 connected to the package region PR. Fig.15 In an implementation, the first connection portion 120c may be formed on the first surface 110a of a portion of the package region PR adjacent to the first test region TR1.

[0043] The first line 120 may further include a first through hole 120v. The first through hole 120v may partially penetrate the film substrate 110. For example, the first through hole 120v may be a portion of the first line 120 that penetrates the first test region TR1.

[0044] In an implementation, each first line terminal 120t (eg Figure 1 ) can be a single conductive line. In an implementation, as shown Figure 2 As shown, each first wire end 120t may include six conductive wires.

[0045] Similar to the first wire 120, the second wire 130 may extend on the film substrate 110. A plurality of second wires 130 may be provided to extend on the film substrate 110.

[0046] In an implementation, the second line 130 may be a test line of a semiconductor package. For example, the second line 130 may include a second line terminal 130t.

[0047] The second wire end 130t may be an end portion of the second wire 130 formed in the chip mounting region CR. For example, the second wire end 130t may be an end portion of the second wire 130 connected to the chip mounting region CR. Fig.11 In an implementation, as Figure 1 and Figure 3 As shown, the first line end 120t and the second line end 130t may be arranged along a second direction Y intersecting the first direction X1. The second direction Y may be, for example, a direction intersecting the first direction X1 at a right angle. The second line 130 may extend from the second line end 130t along the first direction X1.

[0048] The second wire 130 may further include a first extension portion 132 , a second extension portion 134 , and a second through hole 130 v .

[0049] The first extension 132 of the second wire 130 may extend on the first surface 110a of the package region PR. The second extension 134 of the second wire 130 may extend on the second surface 110b of the package region PR. The second through hole 130v of the second wire 130 may partially penetrate the film substrate 110 and may connect the first extension 132 and the second extension 134.

[0050] The first extension 132 may connect the second line end 130t and the second through hole 130v. The second extension 134 may connect the second through hole 130v and the second test pad 164. In an implementation, the second through hole 130v may penetrate a portion of the package region PR located between the chip mounting region CR and the first test region TR1. For example, the first extension 132 may extend from the second line end 130t along the first direction X1 and may be connected to the second through hole 130v. In an implementation, the second extension 134 may extend from the second through hole 130v along the first direction X1 and may be connected to the second test pad 164. The second extension 134 may extend from the second through hole 130v to an edge of the package region PR on the second surface 110b.

[0051] In an implementation, the second extension 134 may at least partially overlap the first line 120. As used herein, the expression "overlap" means that two elements overlap each other or are at least partially aligned with each other in a direction perpendicular to the upper surface of the film substrate 110. For example, the second extension 134 on the second surface 110b of the package region PR may at least partially overlap the first line 120 on the first surface 110a of the package region PR.

[0052] In an implementation, the first extension portion 132 may not overlap with the first line 120. Figure 1 As shown, the first extension 132 on the first surface 110 a of the package region PR may not overlap with the first line 120 on the first surface 110 a of the package region PR.

[0053] In the implementation, Figure 1 As shown, the second line end 130t may be a single conductive line. Figure 2 As shown, each second wire end 130t may include six conductive wires.

[0054] In an implementation, the second terminal 130t (eg Figure 1 As shown) can be connected to the second through hole 130v. In an implementation, as Figure 2 As shown, each second wire end 130t may include six conductive wires, and each second via 130v may include three conductive wires.

[0055] Similar to the first wire 120, the third wire 140 may extend on the film substrate 110. A plurality of third wires 140 may be provided to extend on the film substrate 110.

[0056] In an implementation, the third line 140 may be a first output line of the semiconductor package. For example, the third line 140 may include a third line end 140t and a second connection portion 140c.

[0057] The third line terminal 140t may be an end portion of the third line 140 formed in the chip mounting region CR. For example, the third line terminal 140t may be an end portion of the third line 140 connected to the chip mounting region CR. Fig.11 portion of the semiconductor chip 200 .

[0058] In the implementation, Figure 1 and Figure 3 As shown, the first line end 120t and the third line end 140t may be arranged along the first direction X1. The third line 140 may extend from the third line end 140t along a third direction X2 different from the first direction X1. The third direction X2 may be, for example, a direction opposite to (for example, and parallel to) the first direction X1. The third line 140 may extend along the first surface 110a and the second surface 110b of the package region PR.

[0059] The second connection portion 140c may be a portion of the third line 140 formed in the package region PR. The second connection portion 140c may be a portion of the third line 140 connected to the package region PR. Fig.15 In an implementation, the second connection portion 140c may be formed on the second surface 110b of a portion of the package region PR adjacent to the second test region TR2.

[0060] The third line 140 may further include a third through hole 140v. The third through hole 140v may partially penetrate the film substrate 110. For example, the third through hole 140v may be a portion of the third line 140 that penetrates a portion of the package region PR adjacent to the second test region TR2.

[0061] Similar to the first line 120, the fourth line 150 may extend on the film substrate 110. A plurality of fourth lines 150 may be provided to extend on the film substrate 110.

[0062] In an implementation, the fourth line 150 may be a second output line of the semiconductor package. For example, the fourth line 150 may include a fourth line terminal 150t and a third connection portion 150c.

[0063] The fourth line terminal 150t may be an end portion of the fourth line 150 formed in the chip mounting region CR. For example, the fourth line terminal 150t may be an end portion of the fourth line 150 connected to the chip mounting region CR. Fig.11 portion of the semiconductor chip 200 .

[0064] In the implementation, Figure 1 and Figure 3As shown, the fourth line end 150t can be arranged between the first line end 120t and the third line end 140t. In an implementation, the fourth line end 150t can be arranged between the second line end 130t and the third line end 140t. Therefore, the first line end 120t, the third line end 140t and the fourth line end 150t can be arranged along the first direction X1. In an implementation, the second line end 130t, the third line end 140t and the fourth line end 150t can be arranged along the first direction X1. The fourth line 150 can extend from the fourth line end 150t along the first direction X1, and then can extend along the third direction X2. The fourth line 150 can extend on the first surface 110a and the second surface 110b of the packaging region PR.

[0065] The third connection portion 150c may be a portion of the fourth line 150 formed in the package region PR. The third connection portion 150c may be a portion of the fourth line 150 connected to the package region PR. Fig.15 The third connection portion 150c may be formed on the second surface 110b of the portion of the package region PR adjacent to the second test region TR2. In an implementation, the second connection portion 140c and the third connection portion 150c may be arranged along the first direction X1. The second connection portion 140c may be disposed closer to the second test region TR2 than the third connection portion 150c (e.g., such that the second connection portion 140c is located between the second test region TR2 and the third connection portion 150c).

[0066] The fourth wire 150 may further include a fourth through hole 150v. The fourth through hole 150v may partially penetrate the film substrate 110. For example, the fourth through hole 150v may be a portion of the fourth wire 150 that penetrates the chip mounting region CR.

[0067] The first wire 120, the second wire 130, the third wire 140, and the fourth wire 150 may include, for example, aluminum (Al) or copper (Cu). For example, the first wire 120, the second wire 130, the third wire 140, and the fourth wire 150 may be formed of Al or Cu foil.

[0068] The first wire 120, the second wire 130, the third wire 140, the fourth wire 150, the first connection part 120c, the second connection part 140c and the third connection part 150c may be partially plated conductive wires. For example, the first wire 120, the second wire 130, the third wire 140, the fourth wire 150, the first connection part 120c, the second connection part 140c and the third connection part 150c may be partially plated with at least one of tin (Sn), gold (Au), nickel (Ni), lead (Pb) or a combination thereof.

[0069] The first test pad 162 may be formed in the first test region TR1. The first test pad 162 may be electrically connected to the first line 120. For example, the first test pad 162 may be formed on the second surface 110b of the first test region TR1. The first line 120 may be electrically connected to the first test pad 162 via the first via 120v.

[0070] In an implementation, the first line 120 and the first test pad 162 may be separate elements. In an implementation, the first line 120 and the first test pad 162 may be integrally formed. For example, the first test pad 162 may be a plated portion of the first line 120 .

[0071] The second test pad 164 may be formed in the first test region TR1. The second test pad 164 may be electrically connected to the second line 130. For example, the second test pad 164 may be formed on the second surface 110b of the first test region TR1. The second extension 134 of the second line 130 may be electrically connected to the second test pad 164.

[0072] In an implementation, the first test pads 162 and the second test pads 164 may be arranged along the first direction X1.

[0073] In an implementation, the second line 130 and the second test pad 164 may be separate elements. In an implementation, the second line 130 and the second test pad 164 may be integrally formed. For example, the second test pad 164 may be a plated portion of the second line 130 .

[0074] In an implementation, the third test pad 166 may be formed in the second test region TR2. In an implementation, the third test pad 166 may be formed in the first test region TR1 or in a region that is neither the first test region TR1 nor the second test region TR2.

[0075] The third test pads 166 may be electrically connected to the third lines 140. For example, the third test pads 166 may be formed on the second surface 110b of the second test region TR2, and some third lines 140 formed on the second surface 110b of the package region PR may be electrically connected to the third test pads 166.

[0076] In an implementation, the third line 140 and the third test pad 166 may be separate elements. In an implementation, the third line 140 and the third test pad 166 may be integrally formed. For example, the third test pad 166 may be a plated portion of the third line 140 .

[0077] In an implementation, the fourth test pad 168 may be formed in the first test region TR1. In an implementation, the fourth test pad 168 may be formed in the second test region TR2 or in a region that is neither the first test region TR1 nor the second test region TR2.

[0078] The fourth test pads 168 may be electrically connected to the fourth lines 150. For example, the fourth test pads 168 may be formed on the second surface 110b of the first test region TR1, and some of the fourth lines 150 formed on the second surface 110b of the package region PR may be electrically connected thereto.

[0079] The fourth line 150 and the fourth test pad 168 have been described as separate elements, but the present disclosure is not limited thereto. For example, the fourth line 150 and the fourth test pad 168 may be integrally formed. For example, the fourth test pad 168 may be a plated portion of the fourth line 150.

[0080] The first protectant film 172 and the second protectant film 174 may at least partially expose the first line 120 , the second line 130 , the third line 140 , and the fourth line 150 .

[0081] For example, the first protectant film 172 may expose the first wire end 120t and the first connection portion 120c of the first wire 120, and may also expose the second wire end 130t of the second wire 130, the third wire end 140t of the third wire, and the fourth wire end 150t of the fourth wire 150. Thus, the first wire end 120t, the second wire end 130t, and the third wire end 140t may be connected to Fig.11 The semiconductor chip 200 and the first connection portion 120c may be connected to Fig.15 A printed circuit 300 is provided.

[0082] For example, the second protectant film 174 may expose the second connection portion 140c of the third line 140, and may also expose the third connection portion 150c of the fourth line 150. Thus, the second connection portion 140c and the third connection portion 150c may be connected to Fig.15 The display panel 400 is provided.

[0083] In an implementation, the second protectant film 174 may not expose the second extension portion 134 of the second wire 130. For example, the second protectant film 174 may completely cover the second extension portion 134 of the second wire 130.

[0084] As electronic products become smaller, thinner, and lighter, the demand for thin films for compact packaging substrates for such electronic products has increased. Thin films according to some exemplary embodiments of the present disclosure can provide test lines that can avoid input lines. Therefore, thin films for compact packaging substrates can be provided.

[0085] In an implementation, the second through hole 130v may be used to provide the second wire 130 that can avoid the first wire 120 formed on the first surface 110a. This structure may provide a sufficiently large space for the first wire 120 on the first surface 110a. Therefore, a minimum spacing may be ensured between the first wires 120, and the size of the film used for the encapsulation substrate may be reduced.

[0086] Figure 6 1 shows a design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure. Figures 1 to 5 A description of an element or feature described. Figure 6 A first surface 110 a of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0087] refer to Figure 6 , some of the plurality of second through holes 130v may not penetrate the package region PR.

[0088] For example, some of the plurality of second lines 130 may include second through holes 130v penetrating the test region TR1. Therefore, some of the second lines 130 may extend on the first surface 110a of the package region PR and the first surface 110a of the first test region TR1. Some of the second lines 130 may include second through holes 130v penetrating the package region PR.

[0089] In an implementation, the second via 130 v penetrating the first test region TR1 may be connected to the second test pad 164 .

[0090] In an implementation, some of the second test pads 164 may be arranged in parallel with the first test pads 162. For example, some of the second test pads 164 may be arranged along the second direction Y together with the first test pads 162.

[0091] Figure 7 1 shows a design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure. Figures 1 to 5 A description of an element or feature described. Figure 7 A second surface 110 b of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0092] refer to Figure 7 , a second test pad 164 may be formed in the second test region TR2 . The second test pad 164 may be electrically connected to the second line 130 .

[0093] For example, the second test pad 164 may be formed on the second surface 110 b of the second test region TR2 . The second extension portion 134 of the second line 130 may be electrically connected to the second test pad 164 .

[0094] For example, the second extension 134 may extend from the second through hole 130v in the third direction X2 and may be connected to the second test pad 164. Thus, the second extension 134 may extend from the second through hole 130v to an edge of the package region PR on the second surface 110b.

[0095] Therefore, according to Figure 7 The thin film of the exemplary embodiment of can ensure that there is a sufficiently large space in the first test region TR1, and thus can improve the characteristics of the semiconductor chip to be mounted thereon. Figure 7 The thin film of the exemplary embodiment can ensure that there is a space for forming a power region or a ground region in the test region TR1, and thus can improve the characteristics of the semiconductor chip to be mounted thereon.

[0096] Figure 8 1 shows a design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure. Figures 1 to 5 A description of an element or feature described. Figure 8 A second surface 110 b of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0097] Reference Figure 8 , the film substrate 110 may further include a third test region TR3.

[0098] The third test region TR3 may be adjacent to the package region PR. For example, the third test region TR3 may be formed along one side of the package region PR where the first and second test regions TR1 and TR2 are not formed (eg, between ends of the first and second test regions TR1 and TR2).

[0099] In an implementation, the second test pad 164 may be formed in the third test region TR3 The second test pad 164 may be electrically connected to the second line 130 .

[0100] For example, the second test pad 164 may be formed on the second surface 110b of the third test region TR3. The second extension 134 of the second wire 130 may be electrically connected to the second test pad 164. Therefore, the second extension 134 may extend from the second through hole 130v to the edge of the package region PR on the second surface 110b.

[0101] Fig. 9 A design diagram of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown. Fig.10 Shown along Fig. 9 For convenience, the above referenced Figures 1 to 5 A description of an element or feature described. Fig. 9 A first surface 110 a of a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown.

[0102] refer to Fig. 9 and Fig.10 , the first test pads 162 may be formed on the first surface 110 a of the first test region TR1 .

[0103] For example, the first test pad 162 may be adjacent to the first connection portion 120c of the first wire 120. The first wire 120 may not include the first through hole 120v. Therefore, the first wire 120 may extend on the first surface 110a of the package region PR and may be connected to the first test pad 162.

[0104] In an implementation, the first test pad 162 may overlap with the second test pad 164. Fig.10 As shown, the first test pads 162 formed on the first surface 110 a of the first test region TR1 may overlap with the second test pads 164 formed on the second surface 110 b of the first test region TR1 .

[0105] The following will refer to Figures 11 to 14 Semiconductor packages according to some exemplary embodiments of the present disclosure are described.

[0106] Fig.11 1 shows a cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure. Figures 1 to 10 A description of an element or feature described.

[0107] Reference Fig.11 and Fig.12 , a semiconductor package according to some exemplary embodiments of the present disclosure may include a thin film for a package substrate and a semiconductor chip 200 .

[0108] The film may be the above reference Figures 1 to 10 Any film described.

[0109] The semiconductor chip 200 may be mounted on a thin film. For example, the semiconductor chip 200 may be mounted in a chip mounting region of the film substrate 110. In an implementation, the semiconductor chip 200 may include a display driver integrated circuit (DDI).

[0110] The semiconductor chip 200 may include a first chip pad 202 , a second chip pad 204 , a third chip pad 206 , and a fourth chip pad 208 .

[0111] The first chip pad 202 of the semiconductor chip 200 may be electrically connected to the first line 120. For example, Fig.11 As shown, the first chip pad 202 may be connected to the upper surface of the first wire end 120t. Therefore, the first wire 120 may extend from the first chip pad 202 along the first direction X1.

[0112] In an implementation, the first chip pad 202 may be an input terminal of the DDI. Therefore, the input terminal of the semiconductor chip 200 may be connected to the first line 120 as an input line.

[0113] The second chip pad 204 of the semiconductor chip 200 may be electrically connected to the second line 130. For example, Fig.12 As shown, the second chip pad 204 may be connected to the upper surface of the second wire end 130t. Therefore, the first extension portion 132 of the second wire 130 may extend from the second chip pad 204 along the first direction X1.

[0114] In an implementation, the second chip pad 204 may be a test terminal of the DDI. Therefore, the test terminal of the semiconductor chip 200 may be connected to the second line 130 as a test line. For example, the second chip pad 204 may be a test terminal for testing a semiconductor package, rather than an input or output terminal for driving a display.

[0115] In an implementation, the second through hole 130 v may penetrate a portion of the package region PR between the semiconductor chip 200 and the first test region TR1 .

[0116] The third chip pad 206 of the semiconductor chip 200 may be electrically connected to the third line 140. For example, Fig.11 As shown, the third chip pad 206 may be connected to the upper surface of the third wire terminal 140t. Therefore, the third wire 140 may extend from the third chip pad 206 along the third direction X2.

[0117] In an implementation, the third chip pad 206 may be a first output terminal of the DDI. Therefore, the first output terminal of the semiconductor chip 200 may be connected to the third line 140 as a first output line.

[0118] The fourth chip pad 208 of the semiconductor chip 200 may be electrically connected to the fourth line 150. For example, Fig.11 As shown, the fourth chip pad 208 may be connected to the upper surface of the fourth wire terminal 150 t . Therefore, the fourth wire 150 may extend from the fourth chip pad 208 .

[0119] In an implementation, the fourth chip pad 208 may be a second output terminal of the DDI. Therefore, the second output terminal of the semiconductor chip 200 may be connected to the fourth line 150 as a second output line.

[0120] Fig.13 and Fig.14 1 shows a cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure. Figures 1 to 12 A description of an element or feature described.

[0121] refer to Fig.13 and Fig.14 , the semiconductor package according to some exemplary embodiments of the present disclosure may not include a test area.

[0122] For example, the film substrate 110 may not include the first test region TR1 and the second test region TR2 adjacent to the package region PR. Fig.11 and Fig.12 The semiconductor package of the exemplary embodiment removes the first test region TR1 and the second test region TR2 to obtain Fig.13 and Fig.14 A semiconductor package of an exemplary embodiment of the present invention is provided.

[0123] Therefore, if Fig.13 As shown, the first wire 120 may extend from the first chip pad 202 to an edge of the second surface 110 b of the film substrate 110 . The first connection portion 120 c of the first wire 120 may be disposed adjacent to an edge of the second surface 110 b of the film substrate 110 .

[0124] Moreover, if Fig.12 As shown, the second extension portion 134 of the second wire 130 may extend from the second through hole 130v to the edge of the second surface 110b of the film substrate 110. The second protectant film 174 may completely cover the upper surface of the second extension portion 134 of the second wire 130.

[0125] In the following we will refer to Figures 15 to 17A display device according to some exemplary embodiments of the present disclosure is described.

[0126] Fig.15 A perspective view showing a display device according to some exemplary embodiments of the present disclosure is shown. Fig.16 1 shows a cross-sectional view of a display device according to some exemplary embodiments of the present disclosure. Figures 1 to 14 A description of an element or feature described.

[0127] Reference Fig.15 and Fig.16 , a display device according to some exemplary embodiments of the present disclosure may include a semiconductor package 100 , a printed circuit 300 , and a display panel 400 .

[0128] The semiconductor package 100 may be electrically connected to the printed circuit 300 and the display panel 400. Each semiconductor package 100 may receive a signal provided by the printed circuit 300, and may output the received signal to the display panel 400.

[0129] The semiconductor package 100 may be a chip on film (COF) semiconductor package. For example, the semiconductor package 100 may have a semiconductor chip 200 mounted thereon. The semiconductor chip 200 may realize color by controlling a plurality of pixels of the display panel 400. In an implementation, the semiconductor chip 200 may be a DDI. Each semiconductor package 100 may be a semiconductor package as described above with reference to FIG. Figures 11 to 14 Any of the semiconductor packages described.

[0130] The printed circuit 300 may be connected to the first side of the semiconductor package 100. For example, the printed circuit 300 may include printed circuit lines 302 formed on a surface of the printed circuit 300. Each printed circuit line 302 of the printed circuit 300 may be electrically connected to the first connection portion 120c of the first line 120. The printed circuit 300 may be, for example, a flexible printed circuit (FPC).

[0131] In an implementation, the printed circuit 300 may include one or more driver integrated circuit (IC) chips that simultaneously apply power and signals to the semiconductor package 100 .

[0132] The display panel 400 may be connected to the second side of the semiconductor package 100. For example, the display panel 400 may include display panel lines 402 formed on a surface of the display panel 400. Each display panel line 402 may be electrically connected to the second connection portion 140c of the third line 140 and the third connection portion 150c of the fourth line 150.

[0133] The display panel 400 may include a display substrate 410 and an image area 420 formed on the display substrate 410. The display substrate 410 may be, for example, a glass substrate or a flexible substrate. In the image area 420, a plurality of pixels may be formed. The pixels of the image area 420 may operate according to a signal provided by the semiconductor package 100.

[0134] The semiconductor package 100 may be electrically connected to the display panel 400 and may perform the function of a gate driver or a source driver. For example, the semiconductor package 100 may be connected to a gate line of the display panel 400 and may perform the function of a gate driver. Alternatively, the semiconductor package 100 may be connected to a source line of the display panel 400 and may perform the function of a source driver.

[0135] The display panel 400 may include, for example, at least one of a liquid crystal display (LCD) panel, a light emitting diode (LED) panel, an organic LED (OLED) panel, and a plasma display panel (PDP).

[0136] In an implementation, a single semiconductor package 100 may be connected between the printed circuit 300 and the display panel 400. For example, in the case where the display panel 400 is used to provide a small-sized screen such as a mobile phone or to support low resolution, the display device according to some exemplary embodiments of the present disclosure may include only one semiconductor package 100.

[0137] In an implementation, a plurality of semiconductor packages 100 may be connected between the printed circuit 300 and the display panel 400. For example, in the case where the display panel 400 is used to provide a large-size screen such as a television (TV) or to support high resolution, the display device according to some exemplary embodiments of the present disclosure may include a plurality of semiconductor packages 100.

[0138] Fig.17 1 shows a cross-sectional view of a display device according to some exemplary embodiments of the present disclosure. Figures 1 to 16 A description of an element or feature described.

[0139] refer to Fig.17 , the semiconductor package 100 may be partially bent.

[0140] For example, a portion of the semiconductor package 100 adjacent to the display panel 400 may be bent. Thus, the printed circuit 300 and the display panel 400 may face each other. In an implementation, the second surface 110b of the semiconductor package 100 may be placed in contact with the lower surface of the display panel 400. In an implementation, the semiconductor chip 200 may be disposed below the display panel 400.

[0141] Therefore, the display device according to some exemplary embodiments of the present disclosure can help reduce the size of electronic products. For example, when the display panel 400 is applied to a mobile phone or a TV, the frame size of the mobile phone or the TV can be reduced.

[0142] The following will refer to Figures 1 to 5 and Figures 18 to 20 A method of manufacturing a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is described.

[0143] Fig.18 A flow chart of a method of manufacturing a thin film for encapsulating a substrate according to some exemplary embodiments of the present disclosure is shown. Figures 19 to 20 1 shows a cross-sectional view of a stage in a method of manufacturing a substrate for packaging according to some exemplary embodiments of the present disclosure. Figures 1 to 17 A description of an element or feature described.

[0144] refer to Figures 18 to 20 , a film substrate 110 may be provided ( S10 ).

[0145] The film substrate 110 may include a first surface 110 a and a second surface 110 b opposite to each other.

[0146] The film substrate 110 may further include a packaging region PR, a first test region TR1, and a second test region TR2. The packaging region PR may be adjacent to both the first test region TR1 and the second test region TR2.

[0147] Thereafter, the first line 120 , the second line 130 , the third line 140 , and the fourth line 150 may be formed ( S12 ).

[0148] For example, the first wire 120, the second wire 130, the third wire 140, and the fourth wire 150 may be formed by patterning a metal layer. The patterning of the metal layer may be performed by, for example, casting, lamination, or electroplating.

[0149] In an implementation, the first test pad 162, the second test pad 164, the third test pad 166, and the fourth test pad 168 may be formed together with the first line 120, the second line 130, the third line 140, and the fourth line 150. For example, the first test pad 162, the second test pad 164, the third test pad 166, and the fourth test pad 168 may be formed integrally with the first line 120, the second line 130, the third line 140, and the fourth line 150, respectively.

[0150] Reference Figures 1 to 5 and Fig.18, a first protective agent film 172 and a second protective agent film 174 may be formed ( S14 ).

[0151] For example, the solder resist may be applied to the film substrate 110 by screen printing or inkjet printing. For example, the photoimageable solder resist may be applied to the entire film substrate 110 by screen printing or spraying. In an implementation, the film type solder resist material may be attached to the film substrate 110 by lamination.

[0152] Thereafter, unnecessary portions of the solder resist formed on the film substrate 110 may be removed by exposure or development. For example, the solder resist may be formed on the film substrate 110 to at least partially expose the first, second, third, and fourth lines 120, 130, 140, and 150.

[0153] Thereafter, the solder resist formed on the film substrate 110 may be hardened by, for example, heat, ultraviolet (UV) light, or infrared (IR) light.

[0154] As a result, the first protectant film 172 may be formed to expose the first terminal 120 t , the first connection portion 120 c , the second terminal 130 t , the third terminal 140 t , and the fourth terminal 150 t .

[0155] Also, the second protector film 174 may be formed to expose the second connection portion 140 c and the third connection portion 150 c. In an implementation, the second protector film 174 may not expose the second extension portion 134 of the second wire 130 .

[0156] The following will refer to Figures 11 to 14 and Fig.19 A method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure is described.

[0157] Fig.21 A flow chart of a method for manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure is shown. Figures 1 to 20 A description of an element or feature described.

[0158] refer to Fig.21 , a thin film for encapsulating the substrate may be provided ( S20 ).

[0159] The film may be the above reference Figures 1 to 10 Any film described.

[0160] It is possible to manufacture according to Fig.18 An exemplary embodiment of a thin film encapsulation substrate is provided by a method for forming a thin film.

[0161] Reference Fig.11 , Fig.12 and Fig.21 , the semiconductor chip 200 may be mounted on the film ( S22 ).

[0162] For example, the semiconductor chip 200 may be mounted in the chip mounting region CR of the film substrate 110. In an implementation, the semiconductor chip 200 may be a DDI.

[0163] The first chip pad 202 of the semiconductor chip 200 may be electrically connected to the first line 120. The second chip pad 204 of the semiconductor chip 200 may be electrically connected to the second line 130. The third chip pad 206 of the semiconductor chip 200 may be electrically connected to the third line 140. The fourth chip pad 208 of the semiconductor chip 200 may be electrically connected to the fourth line 150.

[0164] refer to Fig.13 , Fig.14 and Fig.21 , the first test region TR1 and the second test region TR2 of the thin film may be removed ( S24 ).

[0165] Before removing the first and second test regions TR1 and TR2 , characteristics of the semiconductor chip 200 may be tested.

[0166] For example, a measuring device having a probe may be used to test the characteristics of the semiconductor chip 200. For example, the measuring device may be disposed on the second surface 110b of the film substrate 110. Thereafter, the probe of the measuring device may be placed in contact with the first test pad 162, the second test pad 164, the third test pad 166, and / or the fourth test pad 168 to test the characteristics of the semiconductor chip 200.

[0167] The following will refer to Figures 15 to 17 and Fig. 22 A method of manufacturing a display device according to some exemplary embodiments of the present disclosure is described.

[0168] Fig. 22 A flowchart of a method for manufacturing a display device according to some exemplary embodiments of the present disclosure is shown. Figures 1 to 21 A description of an element or feature described.

[0169] refer to Fig. 22 , a semiconductor package 100 may be provided ( S30 ).

[0170] The semiconductor package 100 may be the Figures 11 to 14 Any of the semiconductor packages described.

[0171] Thereafter, the printed circuit 300 and the display panel 400 may be attached to the semiconductor package 100 ( S32 ).

[0172] For example, Fig.15 and Fig.16 As shown, the printed circuit 300 may be formed to be electrically connected to the first connection portion 120 c of the first line 120 , and the display panel 400 may be formed to be electrically connected to the second connection portion 140 c of the third line 140 and the third connection portion 150 c of the fourth line 150 .

[0173] Thereafter, the semiconductor package 100 may be partially bent, such as Fig.17 For example, a portion of the semiconductor package 100 adjacent to the display panel 400 may be bent. As a result, a display device having the printed circuit 300 and the display panel 400 facing each other may be manufactured.

[0174] By summarizing and reviewing, fine line patterns can be formed in COF packages, and COF packages have attracted attention as high integration density packages.

[0175] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a general descriptive sense only, and not for purposes of limitation. In some cases, those skilled in the art will recognize that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A display device, comprising: A film substrate, comprising a first surface and a second surface, wherein the first surface is opposite to the second surface; A semiconductor chip is disposed on the first surface, the semiconductor chip comprising an input terminal and a test terminal arranged in a line along a first direction on the first surface; a first line extending from the input end on the first surface along a second direction intersecting the first direction; as well as The second line includes: a first extension portion extending on the first surface, a second extension extending on the second surface, and a first through hole, penetrating the film substrate and connecting the first extension portion with the second extension portion; in: The first extension portion extends from the test end along the second direction and is connected to the first through hole, and The second extension portion extends from the first through hole to an edge of the second surface.

2. The display device according to claim 1, wherein: The second extending portion extends along the second direction.

3. The display device according to claim 1, wherein: The second extension at least partially overlaps the first line.

4. The display device according to claim 1, wherein: The first extension portion does not overlap the first line.

5. The display device according to claim 1, further comprising: Protective agent film, wherein: The first line includes a connection portion adjacent to an edge of the first surface, and The protective agent film exposes the upper surface of the connecting portion.

6. The display device according to claim 1, further comprising: The protective agent film completely covers the upper surface of the second extension portion.

7. The display device according to claim 1, wherein: The semiconductor chip is a display driver integrated circuit "DDI".

8. The display device according to claim 1, further comprising: A flexible printed circuit "FPC" is connected to the first wire.

9. The display device according to claim 1, further comprising a third line, wherein: The semiconductor chip further includes a first output terminal, and The third line extends from the first output terminal.

10. The display device according to claim 9, further comprising: a printed circuit connected to the first wire; as well as A display panel is connected to the third line.

11. The display device according to claim 9, further comprising a fourth line and a display panel, wherein: The semiconductor chip further includes a second output terminal, The fourth line extends from the second output terminal, and The display panel is connected to the third line and the fourth line.

12. A semiconductor package, comprising: A film substrate, comprising a packaging area and a first test area adjacent to each other, the film substrate comprising a first surface and a second surface, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and comprising a first chip pad and a second chip pad arranged in a row along a first direction; A first test pad is disposed on the second surface of the first test area; A first line is disposed on a first surface of the packaging area and a first surface of the first test area, the first line extending from the first chip pad along a second direction intersecting the first direction; as well as A second line connects the second chip pad to the first test pad, The second line includes a first through hole, and the first through hole penetrates a portion of the packaging area between the semiconductor chip and the first test area.

13. The semiconductor package according to claim 12, wherein: The first chip pad is an input terminal, and The second chip pad is a test terminal.

14. The semiconductor package according to claim 12, wherein: The second line also includes: A first extension portion extending on a first surface of the packaging region, and A second extension portion extends on the second surface of the packaging area, The first extension connects the second chip pad to the first through hole, and The second extending portion connects the first through hole and the first test pad.

15. The semiconductor package according to claim 12, further comprising: A second test pad is disposed on a second surface of the first test area, The first line connects the first chip pad to the second test pad.

16. The semiconductor package according to claim 12, further comprising: A second test pad; as well as The third line, in: The film substrate further includes a second test area, the second test area being adjacent to the packaging area and spaced apart from the first test area. The semiconductor chip further includes a third chip pad, and the third chip pad is arranged along the second direction together with the first chip pad. The second test pad is disposed on the second surface of the second test area, and The third line connects the third chip pad and the second test pad.

17. A film for encapsulating a substrate, the film comprising: A film substrate, comprising a packaging area, a first test area, and a second test area, wherein the first test area is adjacent to one side of the packaging area, and the second test area is adjacent to an opposite side of the packaging area relative to the first test area, the film substrate having a first surface and a second surface, the first surface being opposite to the second surface; A chip mounting area, disposed on the first surface of the packaging area; a first line including a first line end disposed in the chip mounting area; a second line including a second line end, the second line end being disposed in the chip mounting region and arranged along a first direction together with the first line end; a third line including a third line end, the third line end being disposed in the chip mounting region and arranged together with the first line end in a second direction intersecting the first direction; A first test pad and a second test pad are disposed on a second surface of the first test area; as well as A third test pad is disposed on the second surface of the second test area, in: The first line includes a first through hole penetrating the first test area and connected to the first test pad, the second line includes a second through hole penetrating a portion of the package region between the chip mounting region and the first test region and connected to the second test pad, and The third line is connected to the third test pad.

18. The film according to claim 17, wherein The third line includes a third via penetrating the package area and connected to the third test pad.

19. The film of claim 17, further comprising: a fourth line including a fourth line terminal disposed in the chip mounting area, Wherein, the fourth line end is arranged between the first line end and the third line end.

20. The film according to claim 17, wherein The first test pad and the second test pad are arranged along the second direction.

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