Method for producing an IGBT with dV / dt controllability

Abstract

A method (2) for processing a power semiconductor device (1) comprises: providing a semiconductor body (10) having a drift region (100) of a first conductivity type; creating (20) a plurality of trenches (14, 15, 16), wherein the trenches (14, 15, 16) extend into the semiconductor body (10) along a vertical direction (Z) and are arranged adjacent to each other along a first lateral direction (X); providing (22) a mask arrangement (30) at the semiconductor body (10), wherein the mask arrangement (30) has a lateral structure (301) according to which some of the trenches (14, 15, 16) are exposed and the trenches (14, 15, 16) have a plurality of grooves (14, 15, 16) arranged adjacent to each other along a first lateral direction (X); at least one of which is covered by a mask arrangement (30); subjecting the semiconductor body (10) and the mask arrangement (30) to a (24) dopant material providing step, thereby creating a plurality of doped regions (1059) of a second conductivity type complementary to the first conductivity type below the bottom of the exposed trenches (14, 15, 16); removing (26) the mask arrangement (30); subjecting the semiconductor body (10) to a (28) temperature annealing step, thereby causing the plurality of doped regions (1059) to extend parallel to a first lateral direction (X) so as to overlap and form a barrier region (105) of the second conductivity type adjacent to the bottom of the exposed trenches (14, 15, 16).

Description

Technical Field

[0001] The present specification relates to embodiments of power semiconductor devices, such as IGBTs, and embodiments of processing power semiconductor devices. In particular, the present specification relates to embodiments of methods of processing an IGBT having a micro-patterned trench (MPT) configuration including dummy trenches, wherein a plurality of trenches extend into an electrically floating barrier region. Background Art

[0002] Modern devices in automotive, consumer, and industrial applications rely on power semiconductor devices for many functions, such as converting electrical energy and driving electric motors or motors. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] An IGBT generally comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the IGBT. Further, the load current path can be controlled by means of an insulated electrode (sometimes referred to as a gate electrode). For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the IGBT in one of a conducting state and a blocking state.

[0004] In some cases, the gate electrode may be included within a trench of the IGBT, wherein the trench may exhibit, for example, a stripe configuration or a needle configuration.

[0005] Furthermore, the trenches of the IGBT may integrate different types of electrodes; some of the electrodes may be connected to the IGBT gate terminal and others may be connected to the IGBT load terminals (eg source / emitter terminals).

[0006] It is generally desirable to keep the losses (eg switching losses) of an IGBT low. For example, low switching losses may be achieved by ensuring short switching durations (eg short on-durations and / or short off-durations).

[0007] On the other hand, in a given application there may also be requirements regarding a maximum voltage slope (dV / dt) and / or a maximum load current slope (dI / dt).

[0008] Furthermore, the switching behavior of an IGBT may depend on its operating temperature, wherein it may be desirable to achieve the stated provisions regarding power losses and voltage / current slopes within a wide range of possible operating temperatures. Summary of the invention

[0009] According to an embodiment, a power semiconductor device includes an active cell region having a drift region of a first conductivity type; a plurality of IGBT cells at least partially arranged within the active cell region, wherein each of the IGBT cells includes at least one trench extending into the drift region along a vertical direction; an edge termination region surrounding the active cell region; a transition region arranged between the active cell region and the edge termination region, the transition region having a width from the active cell region toward the edge termination region along a lateral direction, wherein at least some of the IGBT cells are arranged within the transition region or extend into the transition region accordingly; and an electrically floating barrier region of a second conductivity type, wherein the electrically floating barrier region is arranged within the active cell region and contacts at least some of the trenches of the IGBT cells, and wherein the electrically floating barrier region does not extend into the transition region.

[0010] According to another embodiment, a power semiconductor device includes a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current between the terminals along a vertical direction and includes: an active cell region having a drift region of a first conductivity type; an edge termination region having a well region of a second conductivity type; a plurality of IGBT cells arranged in the active cell region, wherein each of the IGBT cells includes a plurality of trenches extending into the drift region along a vertical direction and laterally limiting a plurality of mesas. The plurality of trenches include: at least one control trench having a control electrode; at least one dummy trench having a dummy electrode electrically coupled to the control electrode; at least one source trench having a source electrode electrically connected to the first load terminal. The plurality of mesas include at least one active mesa arranged between at least one control trench and at least one source trench; and at least one passive mesa arranged adjacent to at least one dummy trench. The power semiconductor device further includes an electrically floating barrier region of a second conductivity type, wherein at least the bottom of the dummy trench and the bottom of the source trench both extend at least partially into the electrically floating barrier region, and wherein a portion of the drift region located in the lateral direction between the electrically floating barrier region and the well region has a lateral extension of at least 1 μm in the lateral direction.

[0011] According to another embodiment, a method for processing a power semiconductor device is provided. The power semiconductor device includes an active cell region having a drift region of a first conductivity type; a plurality of IGBT cells at least partially arranged in the active cell region, wherein each of the IGBT cells includes at least one trench extending into the drift region along a vertical direction; an edge termination region surrounding the active cell region; and a transition region arranged between the active cell region and the edge termination region, the transition region having a width from the active cell region toward the edge termination region along a lateral direction, wherein at least some of the IGBT cells are arranged in the transition region or extend into the transition region accordingly. The method includes: providing an electrically floating barrier region of a second conductivity type, wherein the electrically floating barrier region is arranged in the active cell region and contacts at least some of the trenches of the IGBT cells, and wherein the electrically floating barrier region does not extend into the transition region.

[0012] According to another embodiment, another method for processing a power semiconductor device is proposed. The power semiconductor device includes a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current between the terminals along a vertical direction and includes: an active cell region having a drift region of a first conductivity type; an edge termination region having a well region of a second conductivity type; a plurality of IGBT cells arranged in the active cell region, wherein each of the IGBT cells includes a plurality of trenches extending into the drift region along a vertical direction and laterally limiting a plurality of mesas. The plurality of trenches include: at least one control trench having a control electrode; at least one dummy trench having a dummy electrode electrically coupled to the control electrode; at least one source trench having a source electrode electrically connected to the first load terminal. The plurality of mesas include at least one active mesa arranged between at least one control trench and at least one source trench; and at least one passive mesa arranged adjacent to at least one dummy trench. The further method comprises providing an electrically floating barrier region of a second conductivity type, wherein at least both the bottom of the dummy trench and the bottom of the source trench extend at least partially into the electrically floating barrier region, and wherein a portion of the drift region located in the lateral direction between the electrically floating barrier region and the well region has a lateral extension of at least 1 μm in the lateral direction.

[0013] According to another embodiment, a method for processing a power semiconductor device includes: providing a semiconductor body having a drift region of a first conductivity type; creating a plurality of trenches, wherein the trenches extend into the semiconductor body along a vertical direction and are arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, wherein the mask arrangement has a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement; subjecting the semiconductor body and the mask arrangement to a dopant material providing step, thereby creating a plurality of doped regions of a second conductivity type complementary to the first conductivity type below the bottom of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step, thereby causing the plurality of doped regions to extend parallel to the first lateral direction so as to overlap and form a barrier region of the second conductivity type adjacent to the bottom of the exposed trenches.

[0014] According to another embodiment, a power semiconductor device includes a first load terminal and a second load terminal. The power semiconductor device is configured to conduct a load current between the terminals along a vertical direction, and includes: a drift region of a first conductivity type; a plurality of IGBT cells, wherein each of the IGBT cells includes a plurality of grooves extending into the drift region along a vertical direction and laterally limiting at least one active mesa, the at least one active mesa including an upper section of the drift region; and an electrically floating barrier region of a second conductivity type spatially limited in the vertical direction and in the vertical direction by the drift region. The total volume of all active mesas is divided into a first share and a second share, the first share does not overlap laterally with the barrier region and the second share overlaps laterally with the barrier region. The first share is configured to carry a load current in the range of at least 0% to 100% of the rated load current for which the power semiconductor device is designed. If the load current exceeds at least 0.5% of the rated load current, the second share is configured to carry the load current.

[0015]

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The various parts in the figures are not necessarily to scale, but the emphasis is placed on illustrating the principles of the present invention. In addition, in the figures, like reference numerals refer to corresponding parts. In the drawings:

[0017] Figure 1 schematically and exemplarily illustrates a section of a horizontal projection of a power semiconductor device according to one or more embodiments;

[0018] Figure 2-4B Each schematically and exemplarily illustrates a segment of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0019] Figure 5 schematically and exemplarily illustrates the progression of dopant concentration in a power semiconductor device according to one or more embodiments;

[0020] Fig. 6A - C schematically and exemplarily illustrates a section of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0021] Figure 7-8D Each schematically and exemplarily illustrates a horizontally projected section of a power semiconductor device according to one or more embodiments;

[0022] Fig. 9 schematically and exemplarily illustrates a perspective projection of a power semiconductor device according to one or more embodiments;

[0023] Figure 10-11 Each schematically and exemplarily illustrates a segment of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0024] Figure 12-19 Each schematically and exemplarily illustrates a horizontally projected section of a power semiconductor device according to one or more embodiments;

[0025] Fig. 20 schematically and exemplarily illustrate steps of a method for processing a power semiconductor device according to one or more embodiments;

[0026] Figure 21-25 Each schematically and exemplarily illustrates steps of a method of processing a power semiconductor device based on one or more sections of a vertical cross section according to one or more embodiments. DETAILED DESCRIPTION

[0027] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0028] In this regard, directional terms such as "top," "bottom," "below," "front," "rear," "back," "leading," "trailing," "below," "above," and the like may be used with respect to the orientation of the various figures being described. Because portions of the embodiments can be positioned in a variety of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0029] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the various figures. Each example is provided by way of explanation and is not meant to be a limitation of the present invention. For example, a feature illustrated or described as a part of one embodiment can be used with respect to other embodiments or in combination with other embodiments to produce yet another embodiment. The present invention is intended to include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustration purposes only. For clarity, if not otherwise stated, the same elements or manufacturing steps have been designated by the same reference in different drawings.

[0030] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, a surface of a semiconductor wafer or a die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0031] The term "vertical" as used in this specification is intended to describe an orientation that is arranged substantially perpendicular to a horizontal surface (i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die). For example, the vertical direction Z mentioned below may be an extending direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0032] In this specification, n-doping is referred to as “first conductivity type” and p-doping is referred to as “second conductivity type.” Alternatively, the opposite doping relationship can be adopted so that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0033] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, regions, parts or portions of a semiconductor device, or between different terminals of one or more devices, or between a part or portion of a semiconductor device and a terminal or metallization or electrode. Further, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device, e.g., a transition between two elements that are in contact with each other may not include additional intermediate elements, etc.

[0034] Additionally, in the context of this specification, if not otherwise specified, the term "electrically insulated" is used in its generally reasonably understood context, and is therefore intended to describe two or more components being located apart from each other, and there being no ohmic connection connecting those components. However, components that are electrically insulated from each other may nevertheless be coupled to each other, such as mechanically and / or capacitively and / or inductively. For example, two electrodes of a capacitor may be electrically insulated from each other, and at the same time mechanically and capacitively coupled to each other, such as by means of insulation (e.g., a dielectric).

[0035] The specific embodiments described in this specification pertain to, but are not limited to, semiconductor devices (such as IGBTs) that exhibit, for example, stripe cell or honeycomb cell configurations, such as IGBTs that can be used in power converters or power supplies. Thus, in an embodiment, such an IGBT can be configured to carry a load current to be fed to a load and / or provided by a power source, respectively. For example, the IGBT may include one or more active power semiconductor cells, such as a monolithically integrated IGBT cell, and / or a monolithically integrated RC-IGBT cell. Such a transistor cell can be integrated in a power semiconductor module. A plurality of such cells can constitute a cell field in which an active cell region of an IGBT is arranged.

[0036] The term "power semiconductor device" as used in this specification is intended to describe a semiconductor device on a single chip having high voltage blocking and / or high current carrying capabilities. In other words, such power semiconductor devices (e.g., IGBTs) are intended for high currents typically in the ampere range (e.g., up to tens or hundreds of amperes) and / or high voltages typically above 15V, more typically 100V and above (e.g., up to at least 1200V).

[0037] For example, the power semiconductor device described below may be an IGBT exhibiting a stripe trench cell configuration or a honeycomb trench cell configuration and may be configured to be employed as a power component in low voltage, medium voltage, and / or high voltage applications.

[0038] For example, the term "power semiconductor device" as used in this specification does not target logic semiconductor devices that are used, for example, to store data, compute data, and / or other types of semiconductor-based data processing.

[0039] Figure 1 A horizontally projected section of a power semiconductor device 1 according to one or more embodiments is schematically and exemplarily illustrated. Figure 2 A section of a vertical cross section of a power semiconductor device 1 according to one or more embodiments is schematically and exemplarily illustrated. Figure 1 and Figure 2 Each of the .

[0040] The power semiconductor device 1 may be an IGBT or respectively a power semiconductor device having a configuration based on an IGBT configuration such as a reverse conducting (RC) IGBT.

[0041] For example, the power semiconductor device 1 comprises a semiconductor body 10 coupled to a first load terminal 11 and a second load terminal 12. For example, the first load terminal 11 is an emitter terminal and the second load terminal 12 may be a collector terminal.

[0042] The semiconductor body 10 may include a drift region 100 of a first conductivity type. The drift region 100 may be n-doped. In an embodiment, the drift region 100 has a first conductivity type of 2e12 cm -3 to 4e14 cm -3 The (electrically activated) dopant concentration of the drift zone 100 is within a range of . For example, as it is known to the skilled person, the extension of the drift zone 100 along the vertical direction Z and its dopant concentration are selected depending on the rated blocking voltage for which the power semiconductor device 1 is to be designed. Within the present description, the term "drift zone" is intended to describe such a zone which the skilled person of a power semiconductor device (e.g. an IGBT) usually designates as a drift zone or respectively a drift region.

[0043] Furthermore, the first load terminal 11 may be arranged on the front side of the power semiconductor device 1 and may include front side metallization. The second load terminal 12 may be arranged opposite to the front side (e.g. on the back side of the power semiconductor device 1) and may include, for example, back side metallization. Thus, the power semiconductor device 1 may exhibit a vertical configuration and the load current may be conducted along the vertical direction Z. In another embodiment, each of the first load terminal 11 and the second load terminal 12 may be arranged on a common side of the power semiconductor device 1 (e.g. both on the front side).

[0044] Now refer to it in more detail Figure 1 , the power semiconductor device 1 may further include an active cell region 1-2, an edge termination region 1-3 and a chip edge 1-4. The edge termination region 1-3 may surround the active cell region 1-2. The transition region 1-5 may be arranged between the active cell region 1-2 and the edge termination region 1-3. For example, the transition region 1-5 surrounds the active cell region 1-2. The transition region 1-5 may be surrounded by the edge termination region 1-3.

[0045] In an embodiment, the semiconductor body 10 essentially consists of an edge termination region 1 - 3 , a transition region 1 - 5 , and an active cell region 1 - 2 .

[0046] For example, each of the edge termination region 1-3, the transition region 1-5, and the active cell region 1-2 extends from the front side of the power semiconductor device 1 to the back side of the power semiconductor device 1 entirely through the semiconductor body 10 along the vertical direction Z. Each of the edge termination region 1-3, the transition region 1-5, and the active cell region 1-2 may include not only components of the semiconductor body 10, but also components outside thereof, such as components of the first load terminal 11 and / or the second load terminal 12.

[0047] Further, in the example, along the lateral direction, there is no overlap between the edge termination region 1-3, the transition region 1-5 and the active cell region 1-2 in the semiconductor body 10. Therefore, the active cell region 1-2 may be entirely surrounded by the transition region 1-5, and within the semiconductor body 10, there is no lateral overlap between the transition region 1-5 and the active cell region 1-2, for example, along the first lateral direction X, the second lateral direction Y, and a linear combination thereof. Similarly, the transition region 1-5 may be entirely surrounded by the edge termination region 1-3, and within the semiconductor body 10, there is no lateral overlap between the transition region 1-5 and the edge termination region 1-3, for example, along the first lateral direction X, the second lateral direction Y, and a linear combination thereof.

[0048] In an embodiment, the transition region 1-5 has a width W of at least 1 μm along a lateral direction from the active cell region 1-2 toward the edge termination region 1-3 (e.g., in a first lateral direction X / opposing the first lateral direction X and in a second lateral direction Y / opposing the second lateral direction Y and / or in a linear combination of these lateral directions). The width W of the transition region 1-5 may therefore be the distance between the active cell region 1-2 and the edge termination region 1-3. This (minimum) width W may occur along the entire periphery of the transition region 1-5. The width of the transition region 1-5 may be greater than 1 μm, for example, greater than 3 μm, greater than 5 μm, or even greater than 10 μm. Further exemplary features of the transition region 1-5 and the edge termination region 1-3 will be described below. Along the width W, a portion of the drift region 100 may be present.

[0049] The chip edge 1 - 4 may terminate the semiconductor body 10 in a lateral direction, for example the chip edge 1 - 4 may have been formed by means of wafer dicing, for example, and may extend along a vertical direction Z. Figure 1 As illustrated in FIG. 1 , the edge termination region 1 - 3 may be arranged between the active cell region 1 - 2 and the chip edge 1 - 4 .

[0050] In this specification, the terms "active cell region" and "edge termination region" are employed in a conventional manner, ie the active cell regions 1-2 and the edge termination regions 1-3 may be configured to provide the principal technical functions that a skilled person typically associates therewith.

[0051] For example, according to an embodiment, the active cell area 1-2 of the power semiconductor device 1 is configured to conduct the main part of the load current between the terminals 11, 12, while the edge termination area 1-3 does not conduct the load current, but rather implements the function of defining the electric field profile, thereby ensuring the blocking capability, safely terminating the active cell area 1-2 and the transition area 1-5, etc.

[0052] The power semiconductor device 1 includes a plurality of IGBT cells 1-1, wherein the plurality of IGBT cells 1-1 are mainly arranged in an active cell area 1-2. For example, most of the plurality of IGBT cells 1-1 of the power semiconductor device 1 are arranged in the active cell area 1-2. The number of the IGBT cells 1-1 may be greater than 100, greater than 1000, or even greater than 10,000. For example, at least 85%, at least 95%, or at least 98% of the total number of IGBT cells 1-1 are arranged in the active cell area 1-2. In an embodiment, the remaining IGBT cells 1-1 are arranged in a transition area 1-5. Some of the IGBT cells 1-1 may be arranged entirely in the transition area 1-5, and others may be arranged both in the active cell area 1-2 and extending into the transition area by means of their respective lateral ends, such as in Figure 1 Schematically illustrated in FIG.

[0053] In an embodiment, each IGBT cell 1-1 extends at least partially into the transition region 1-5, as in Figure 1 Schematically and exemplarily illustrated in FIG.

[0054] Thus, for example, in Figure 1 As schematically and exemplarily illustrated in FIG. 1 , some of the IGBT cells 1-1 are arranged in the transition region 1-5 or extend into the transition region 1-5, respectively. In this respect, the transition region 1-5 can also be understood as a form of an active region of the power semiconductor device 1. For example, by means of the share of the total number of IGBT cells 1-1 arranged in the transition region 1-5 or extending into the transition region 1-5, the transition region 1-5 can also be configured to conduct a portion of the load current.

[0055] According to an embodiment, the IGBT cell 1-1 is not arranged in the edge termination region 1-3. However, in the edge termination region 1-3, a specially configured charge carrier discharge unit (e.g., shortly before and / or during a turn-off operation) may be included. Figure 1 Not shown in the figure, see Fig. 6A -B).

[0056] Each IGBT unit 1-1 can be shown as Figure 1, wherein the total lateral extension of each IGBT cell 1 - 1 in one lateral direction (eg together with the second lateral direction Y) and its components may substantially correspond to or respectively slightly exceed the total extension of the active cell area 1 - 2 along this lateral direction.

[0057] In another embodiment, each IGBT cell 14 may exhibit a honeycomb configuration, wherein the lateral extension of each IGBT cell 1 - 1 may be significantly smaller than the total lateral extension of the active cell area 1 - 2 .

[0058] However, the embodiments described herein more particularly relate to an IGBT cell 1 - 1 having a stripe configuration with respect to a second lateral direction Y, as exemplarily and schematically illustrated in most of the drawings.

[0059] In an embodiment, each of the plurality of IGBT cells 1-1 included in the active cell region 1-2 exhibits the same configuration. Figure 2 1 and 2 to describe sections of an exemplary IGBT cell arrangement.

[0060] The configuration of the IGBT cells 1-1 that may be included in the transition region 1-5 may be the same as the configuration of the IGBT cells 1-1 included in the active cell region 1-2. Additionally or alternatively, the transition region 1-5 includes IGBT cells having different configurations compared to the IGBT cells 1-1 of the active cell region 1-2, for example in terms of MPT contact scheme / neighboring relations (see more detailed explanation below).

[0061] Each IGBT cell 1-1 comprises at least one trench extending into the drift region along the vertical direction Z. Each IGBT cell 1-1 may extend at least partially into the semiconductor body 10 and include at least one section of the drift region 100. Furthermore, each IGBT cell 1-1 may be electrically connected to a first load terminal 11. Each IGBT cell 1-1 may be configured to conduct a portion of a load current between the terminals 11 and 12 and to block a blocking voltage applied between the terminals 11 and 12.

[0062] In order to control the power semiconductor device 1 , each IGBT cell 14 may be equipped with a control electrode 141 included in the control trench 14 , the control electrode being configured to selectively set the corresponding IGBT cell 1 - 1 to one of a conducting state and a blocking state.

[0063] For example, refer to Figure 2 In the example illustrated in , a source region 101 of the first conductivity type may be electrically connected to the first load terminal 11 . The source region 101 may be n-doped, for example with a significantly greater dopant concentration than the drift region 100 .

[0064] Furthermore, the channel region 102 of the second conductivity type may separate the source region 101 and the drift region 100, for example, the channel region 102 may isolate the source region 101 from the drift region 100, as is known to a person skilled in the art who is familiar with the general principles of IGBT configurations. The channel region 102 may be p-doped, for example, with a p-doping ratio of 1e15 cm -3 to 5e18 cm -3 The transition between the channel region 102 and the drift region 100 may form a first pn junction 1021 .

[0065] In order to connect the source region 101 with the first load terminal 11 , a first contact plug 113 may extend from the first load terminal 11 along a vertical direction Z so as to contact each of the source region 101 and the channel region 102 .

[0066] The drift zone 100 may extend along the vertical direction Z until it butts against a doped contact zone 108 arranged to be in electrical contact with the second load terminal 12. The section of the drift zone 100 arranged between the zone 105 (explained in more detail below) and the doped contact zone 108 may form the main part of the drift zone 100. In an embodiment, as it is known to the skilled person, the dopant concentration of the drift zone 100 is increased in a lower section of the drift zone 100 forming an interface with the doped contact zone 108, e.g. in order to form a field stop zone of the first conductivity type.

[0067] The doped contact region 108 may be formed according to the configuration of the power semiconductor device 1; for example, the doped contact region 108 may be an emitter region of the second conductivity type, for example a p-type emitter. To form an RC-IGBT, the doped contact region 108 may consist of an emitter region of the second conductivity type interrupted by a small section of the first conductivity type that is also electrically connected to the second load terminal 12 and is usually referred to as an "n-short".

[0068] For example, each IGBT unit 1-1 includes at least one control trench 14 having the control trench electrode 141 and at least one dummy trench 15 having a dummy trench electrode 151, wherein each of the trenches 14, 15 can extend into the semiconductor body 10 along the vertical direction Z and include an insulator 142, 152 that insulates the corresponding trench electrode 141, 151 from the semiconductor body 10.

[0069] According to an embodiment, the trench electrodes 141 , 151 of the at least one control trench 14 and the at least one dummy trench 15 may each be electrically coupled to a control terminal 13 of the power semiconductor device 1 .

[0070] Although Figure 2The dummy trench 15 is exemplarily illustrated to be arranged adjacent to the control trench 14, but it should be understood that the IGBT cell 1-1 may include one or more further trenches of a type different from the control trench type and the dummy trench type, and this at least one further trench may be arranged adjacent to the control trench 14. For example, the at least one further trench may be a source trench (reference number 16 in other drawings) whose trench electrode (reference 161 in other drawings) is electrically connected to the first load terminal 11. This will be explained in more detail below.

[0071] For example, the control terminal 13 is a gate terminal. Furthermore, the control terminal 13 may be electrically connected to the control trench electrode 141 and electrically insulated from the first load terminal 11 , the second load terminal 12 and the semiconductor body 10 , for example by means of at least one insulating structure 132 .

[0072] In an embodiment, the power semiconductor device 1 may be controlled by applying a voltage between the first load terminal 11 and the control terminal 13 , for example in order to selectively set the power semiconductor device 1 to one of a conducting state and a blocking state.

[0073] For example, the power semiconductor device 1 is configured based on the gate-emitter voltage V GE To control, for example, in the principle manner known to the skilled person for controlling an IGBT.

[0074] In an embodiment, the dummy trench electrode 151 may also be electrically connected to the control terminal 13 and thus receive the same control signal as the control trench electrode 141. In another embodiment, the dummy trench electrode 151 may be electrically connected to the control terminal 13 and thus receive the same control signal as the control trench electrode 141. -3 A resistor having a resistance in the range of 10 Ohm to 1 Ohm, in the range of 1 Ohm to 10 Ohm, or in the range of 10 Ohm to 100 Ohm is electrically coupled to the control terminal 13. In another embodiment, the dummy trench electrode 151 is electrically connected to a second control terminal (not shown) and thus receives a control signal different from the control trench electrode 141.

[0075] Furthermore, each IGBT cell 1-1 of the power semiconductor device 1 may have at least one active mesa 18 electrically connected to the first load terminal 11, the active mesa 18 comprising a source region 101, a channel region 102 and a portion of a drift region 100, wherein in the active mesa 18, respective sections of these regions 101, 102, 100 may be arranged adjacent to a sidewall 144 of the control trench 14, as in Figure 2 For example, each of the source region 101 and the channel region 102 is electrically connected to the first load terminal 11 , for example by means of a first contact plug 113 .

[0076] In an embodiment of the power semiconductor device 1 , the doped contact region 108 is a p-type emitter, and the active mesa 18 may completely overlap the p-type emitter 108 laterally.

[0077] Furthermore, the control trench electrode 141 (also referred to herein as control electrode 141) may be configured to receive a control signal from the control terminal 13 and control a load current in the active mesa 18 to set the power semiconductor device 1 to a conducting state, for example by inducing an inversion channel in the channel region 102. Thus, a transition 181 between the first load terminal 11 and the active mesa 18 may provide an interface for transferring a load current from the first load terminal 11 into the semiconductor body 10 and / or vice versa.

[0078] In an embodiment, once an inversion channel threshold voltage, for example, within an active mesa 18 is exceeded, an inversion channel may be induced in the corresponding active mesa 18. For example, the inversion channel threshold voltage depends on at least one of the work function of the control electrode 141, the dopant concentration of the source region 101, the dopant concentration of the channel region 102, the relative thickness of the trench insulator 142, and the dielectric constant of the trench insulator 142.

[0079] In an embodiment, all active mesas 18 of the power semiconductor device 1 are configured with the same inversion channel threshold voltage.

[0080] For example, the control electrodes 141 of all the IGBT cells 1 - 1 included in the active cell region 1 - 2 may be electrically connected to the control terminal 13 .

[0081] In addition to the active mesas 18, each IGBT cell 1-1 of the power semiconductor device 1 may have, for example, at least one passive mesa 19 arranged adjacent to the at least one dummy trench 15, wherein a transition 191 between the first load terminal 11 and the active mesa 19 provides electrical insulation at least for charge carriers of the first conductivity type.

[0082] In an embodiment, the IGBT cell 1-1 may be configured to prevent the load current from crossing the transition 191 between the passive mesa 19 and the first load terminal 11. For example, the passive mesa 19 is not allowed to induce an inversion channel. Compared to the active mesa 18, according to an embodiment, the passive mesa 19 does not conduct the load current during the on-state of the power semiconductor device 1. For example, the passive mesa 19 may be regarded as a decommissioned mesa that is not used for the purpose of carrying the load current.

[0083] In a first embodiment of the passive mesa 19, the passive mesa 19 is not electrically connected to the first load terminal 11, but is electrically insulated, for example, by means of an insulating layer 112. In this embodiment, the transition 191 between the first load terminal 11 and the passive mesa 19 provides electrical insulation not only for charge carriers of the first conductivity type but also for charge carriers of the second conductivity type. To this end, in a variant, the passive mesa 19 comprises neither a section of the source region 101 nor a section of the channel region 102, nor is the passive mesa 19 contacted by means of a contact plug (see reference numeral 111), as in Figure 2 In another variant, the passive mesa 19 may be configured in a similar manner to the active mesa 18, for example by also comprising a segment of the source region 101 and / or a segment of the channel region 102, the difference from the active mesa 18 consisting in that neither the segment of the source region 101 (if present) nor the segment of the channel region 102 of the passive mesa 19 is electrically connected to the first load terminal 11. According to a first embodiment of the passive mesa 19, no current flows across the transition 191 at all.

[0084] In a second embodiment of the passive mesa 19, the passive mesa 19 may be electrically connected to the first load terminal 11, wherein a transition 191 between the first load terminal 11 and the passive mesa 19 provides electrical insulation only for charge carriers of the first conductivity type, but not for charge carriers of the second conductivity type. In other words, in this second embodiment, the passive mesa 19 may be configured to allow a current of charge carriers of the second conductivity type, such as a hole current, to pass through the transition 191. For example, depending on the potential of the dummy trench electrode 151, such a hole current may only form temporarily (e.g. shortly before a disconnection operation is performed), for example in order to reduce the total charge carrier concentration present in the semiconductor body 10. In an embodiment, this can also occur for passive mesas 19, wherein the electrical insulation serves only for reverse conduction of charge carriers of the first conductivity type in an IGBT configuration, wherein in diode mode operation the load current will be temporarily carried through these passive mesas 19, wherein the back side (see doped contact region 108) will be constructed to include both an emitter of the second conductivity type and an emitter of the first conductivity type (previously referred to as an "n-short"). As explained above, in this second embodiment, the passive mesas 19 can be electrically connected to the first load terminal 11. For example, a doped contact region (not shown) of the second conductivity type of the passive mesas 19 (which is different from the electrically floating barrier region 105 mentioned below) can be electrically connected to the first load terminal 11, for example by means of one of the first contact plugs 113, as in Figure 3BThe doped contact region of the second conductivity type (not shown) may isolate the section of the drift region 100 present in the passive mesa 19 from the first load terminal 11. For example, according to the second embodiment of the passive mesa 19, within the passive mesa 19, there is no region doped with a dopant of the first conductivity type electrically connected to the first load terminal 11.

[0085] The above illustrated first and second embodiments of the passive mesa 19 may allow providing a configuration of the IGBT cell 1 - 1 that prevents the load current from crossing said transition 191 between the passive mesa 19 and the first load terminal 11 .

[0086] The passive mesa 19 may be bounded laterally by the control trench 14 and the dummy trench 15 or by the dummy trench 15 and another trench type, which will be further elucidated below. Additional optional aspects of the passive mesa 19 will be described below. For example, according to an embodiment, even though the dummy trench electrode 151 may be electrically connected to the control terminal 13, in the example, the dummy trench electrode 151 is not configured to control the load current in the passive mesa 19 because the passive mesa 19 does not allow an inversion channel to be induced in the passive mesa 19.

[0087] As in Figure 2 As schematically and exemplarily illustrated in FIG. 1 , the power semiconductor device 1 may further include an electrically floating barrier region 105 of a second conductivity type (hereinafter also simply referred to as a “barrier region”). Exemplary features of this barrier region 105 will be explained in more detail further below. Prior to a more detailed description of the barrier region 105, exemplary aspects of the micro-patterned trench structure (MPT) of the power semiconductor device 1 should be explained.

[0088] Reference Figure 3A -B, each IGBT cell 1-1 of the active cell area 1-2 may further include at least one source trench 16, which extends into the semiconductor body 10 along the vertical direction Z and includes an insulator 162 insulating a source trench electrode 161 from the semiconductor body 10, the source trench electrode 161 being electrically connected to the first load terminal 11. For example, as in Figure 3A -B, the at least one source trench 16 is arranged between the control trench 14 and the dummy trench 15. In an embodiment, each IGBT cell 1-1 may include more than one source trench 16, for example, two source trenches 16 (see Figure 4A ) or four source trenches 16 (see Fig. 6A ), wherein each of the trench electrodes 161 of the source trenches may be electrically connected to the first load terminal 11. For example, more than one source trench 16 is arranged between the control trench 14 on one side and the dummy trench 15 on the other side.

[0089] In an embodiment, the active mesa 18 may be bounded in the lateral direction by the control trench 14 and the source trench 16. For example, the sidewall 144 of the control trench 14 and the sidewall 164 of the source trench 16 bound the active mesa 18 along the first lateral direction X. The active mesa 18 may be bounded in the lateral direction X by the control trench 14 and the source trench 16. Figure 2 The configuration is described in an exemplary manner; for example, the first contact plug 113 may electrically connect each of the segments of the channel region 102 and the segments of the source region 101 to the first load terminal 11 .

[0090] In addition, according to Figure 3A -B and 4A-B, each IGBT cell 1-1 of the active cell area 1-2 may include more than one passive mesas 19, wherein at least one of the passive mesas 19 may be laterally bounded by a source trench 16 and a dummy trench 15. Another passive mesa 19 may be laterally bounded by two source trenches 16. Another passive mesa 19 may be laterally bounded by two dummy trenches 15. Yet another passive mesa 19 may be laterally bounded by a dummy trench 15 and one of the control trenches 14. As illustrated, each of the active mesas 19 may include a respective section of the channel region 102, wherein in an embodiment, these sections are not electrically connected to the first load terminal 11 but are electrically insulated, for example by means of an insulating layer 112, as already explained above.

[0091] Reference Figure 3A In the embodiment schematically illustrated in FIG. 1-B, in addition to or as a replacement for at least one source trench 16, each IGBT cell 1-1 of the active cell area may further include at least one floating trench 17, which extends into the semiconductor body 10 along the vertical direction Z and includes an insulator 172 that insulates a trench electrode 171 from the semiconductor body 10, and the trench electrode 171 of the floating trench 17 is electrically floating. In an embodiment, the trench electrode 171 of the floating trench 17 is neither electrically connected to the first load terminal 11, nor to the second load terminal 12, nor to the control terminal 13, nor to a section of the semiconductor body 10.

[0092] In an embodiment, the electrically floating trench electrode 171 is connected to a defined potential (e.g., to the potential of a contact or to the potential of another semiconductor region) by means of a connection having a high ohmic resistance. For example, by means of the high ohmic connection, during a switching operation, the potential of the electrically floating trench electrode 171 is temporarily decoupled from the defined potential. The decoupling may occur over a time scale of the switching operation, for example, up to at least 10ns, or at least 100ns, or at least 10μs. For example, the resistance of the high ohmic connection amounts to more than 1e2Ω or amounts to more than 1e6Ω. In an embodiment, the ohmic resistance between the first load terminal 11 and the electrically floating trench electrode 171 (e.g., measured during a pause condition) amounts to more than 1e2Ω or amounts to more than 1e6Ω.

[0093] For example, if present, at least one floating trench 17 may be arranged between the control trench 14 and the dummy trench 15. Figure 3A -B, the IGBT cell 1-1 may further include the at least one source trench 16, wherein the source trench 16 and the floating trench 17 may be arranged between the control trench 14 on one side and the dummy trench 15 on the other side. In an embodiment, the active mesa 18 is laterally bounded by the sidewall 144 of the control trench 14 and the sidewall 164 of the source trench 16. The inactive mesa 19 may be laterally bounded by at least two of the group of the sidewall 164 of the source trench 16, the sidewall 174 of the floating trench 17, and the sidewall 154 of the dummy trench 15.

[0094] Therefore, according to an embodiment, each IGBT cell 1-1 of the active area includes at least one control trench 14, at least one dummy trench 15, at least one source trench 16, and optionally at least one floating trench 17, wherein the at least one source trench 16 (if present) and the at least one floating trench 17 (if present) can be arranged between the control trench 14 and the dummy trench 15.

[0095] In an embodiment, the power semiconductor device 1 may be an IGBT and each of its IGBT cells 1 - 1 of its active region 1 - 2 may exhibit a micro-patterned trench (MPT) structure.

[0096] For example, each of at least a majority of the trenches 14, 15, 16, 16, 17 that may be included in the IGBT cell 1-1 may exhibit equal spatial dimensions and may be arranged according to a regular pattern. For example, each of the trenches 14, 15, 16, 16, 17 may exhibit a depth in the range of 3 μm to 8 μm along the vertical direction Z, and a width in the range of 0.4 μm to 1.6 μm along the first lateral direction X. The trenches 14, 15, 16, 17 may be formed according to a first layout having a first pitch, wherein the first layout may define each of the trench width and the mesa width.

[0097] Furthermore, each or at least most of the trench electrodes 141, 151, 161, 171 of all trenches 14, 15, 16, 16, 17 that may be included in the IGBT cell 1-1 may exhibit equal spatial dimensions, for example with respect to the total extension along the vertical direction (which terminates with the respective trench bottom 145, 155, 165, 175) and the total extension in the first lateral direction (i.e. the trench width, which terminates with the respective sidewall 144, 154, 164, 174), and / or with respect to the dimensions of the insulator 142, 152, 162, 172. Furthermore, each of the trenches 14, 15, 16, 16, 17 that may be included in the IGBT cell 1-1 may be arranged equidistantly along the first lateral direction X. For example, each of the mesas 18 and 19 of the IGBT cell 1 - 1 may exhibit the same width, which may be in the range of 0.1 μm to 0.3 μm, in the range of 0.3 μm to 0.8 μm, or in the range of 0.8 μm to 1.4 μm.

[0098] Furthermore, some of the trenches 14, 15, 16, 16, 17 that may be included in the IGBT cell 1-1 may extend into the barrier region 105, for example by at least 100 nm, by at least 500 nm or by at least 1000 nm. This aspect will also be explained in more detail below.

[0099] For the following explanations, these abbreviations may be used:

[0100] G = Control groove 14

[0101] D=dummy groove 15

[0102] S=source trench 16

[0103] F = floating groove 17

[0104] k = Active table 18

[0105] o=passive table 19.

[0106] As already explained above, the power semiconductor device 1 may include a plurality of identically configured IGBT cells 1-1 within an active cell area 1-2. In an embodiment, using the abbreviations introduced above, an exemplary neighbor relationship within each IGBT cell 1-1 of an active cell field 1-2 may be expressed as follows:

[0107] .

[0108] Without being limited to this exemplary neighbor relationship (also referred to herein as a contact scheme), embodiments according to most of the remaining drawings are based on the exemplary neighbor relationship identified above. Thus, it should be understood that according to embodiments, the IGBT cell 1 - 1 must not necessarily include the floating trench 17 .

[0109] For example, in another embodiment, each of the IGBT cells 1-1 includes only one or more control trenches 14 and one or more source trenches 16. Furthermore, in such an embodiment, each of the IGBT cells 1-1 includes only one or more active mesas 18, without passive mesas 19. For example, the contact scheme can then be "kGkS" or the like. Then, each trench electrode connected to the control terminal 13 will actually control the active mesas, for example by controlling the corresponding inversion channel, and therefore there will be no dummy trenches. In yet another embodiment, the IGBT cell 1-1 includes only one or more control trenches 14 and one or more active mesas, without passive mesas, dummy trenches, source trenches, or floating trenches.

[0110] As indicated above, regardless of the contact scheme, the power semiconductor device 1 may further include an electrically floating barrier region 105 of the second conductivity type (also simply referred to as “barrier region” in the following).

[0111] In an embodiment, the barrier region 105 is configured to provide a conductive path between a segment of the active mesa 18 and the bottom 155 of the dummy trench 15. Thus, the barrier region 105 may be configured to direct the potential of the segment of the active mesa 18 to the bottom 155 of the dummy trench 15. For example, the barrier region 105 may extend into the active mesa 18 and from there under the bottom 165 of the source trench 16 and across the passive mesa 19 to interface with the bottom 155 of the dummy trench 15.

[0112] As already explained above, the power semiconductor device 1 may include a plurality of IGBT cells 1-1, for example, most of which are included in the active cell area 1-2. For example, the barrier region 105 interconnects the passive mesas 19 in the plurality of IGBT cells 1-1 included in the active area 1-2. For example, to this end, the barrier region 105 may partially extend into each of the passive mesas 19. The barrier region 105 may further at least partially extend into some of the active mesas 18. Each of the dummy trench bottoms 155 may extend into the barrier region 105. Thus, the barrier region 105 may guide the potential in the active mesas toward the dummy trench electrode 151.

[0113] As will be explained in more detail below, the barrier region 105 may laterally overlap with some (parts) of the active mesas 18 and may not laterally overlap with other (parts) of the active mesas 18. For example, to this end, the barrier region 105 may exhibit a lateral structure formed by one or more channels 1053 (as will be explained in more detail below) and / or the barrier region 105 may be laterally displaced from the edge termination region 1-3 by means of a transition region 1-5, which (as explained above) may be equipped with one or more active mesas 18.

[0114] Thus, more generally, according to an embodiment, a power semiconductor device 1 is proposed comprising a first load terminal 11 and a second load terminal 12. The power semiconductor device 1 is configured to conduct a load current between the terminals 11, 12 along a vertical direction Z and comprises: a drift region 100 of a first conductivity type; a plurality of IGBT cells 1-1, wherein each of the IGBT cells 1-1 comprises a plurality of trenches (e.g. 14, 15, 16) extending into the drift region 100 along the vertical direction Z and laterally delimiting at least one active mesa 18 comprising an upper section 100-1 of the drift region 100. An electrically floating barrier region 105 of a second conductivity type is spatially delimited by the drift region 100 in and towards the vertical direction Z.

[0115] The total volume of all active mesas 18 can be divided into a first share, which does not overlap with the barrier region 105 in the lateral direction, and a second share, which overlaps with the barrier region 105 in the lateral direction. For example, the first share of the active mesas 18 overlaps with at least one channel 1053 (see further explanation below) of the barrier region 105 in the lateral direction or with another section of the drift region 100 where the barrier region 105 is not present (e.g., in the transition region 1-5). In contrast, the second share of the active mesas 18 overlaps with the barrier region 105 in the lateral direction. For example, the load current conducted by the second share traverses the barrier region 105.

[0116] In an embodiment, the first share is configured to carry a load current at least in the range of 0% to 100% of the rated load current for which the power semiconductor device is designed. If the load current exceeds at least 0.5% of the rated load current, the second share may be configured to carry the load current.

[0117] Thus, a first portion of the active mesa 18 can be considered as a "firing volume" which, for example, starts to conduct the load current during the switch-on of the power semiconductor device 1, while the second portion initially remains inactive. The barrier region 105 can then become more conductive so that the second portion can also carry the load current, if, for example, only the load current exceeds a threshold value of, for example, at least 0.5% of the rated load current (wherein this threshold value can be higher than 0.5%, for example higher than 1%, for example at least 5% or at least 10%).

[0118] For example, for a small load current of less than 10%, or less than 1% or less than 0.5% of the rated load current of the power semiconductor device 1, the active mesa 18 (i.e., the first portion of the total volume) that does not laterally overlap with the barrier region 105 can act as an emitter of charge carriers of the first conductivity type, and for example, by this, a snapback in the transfer or output characteristics of the power semiconductor device 1 is avoided. For a larger load current (greater than 0.5%, 1%, 5% or 10% of the rated load current), the upper pn junction 1051 is in a forward bias mode relative to the charge carriers of the first conductivity type. This can then also allow the emission of charge carriers of the first conductivity type by the active mesa 18 (i.e., the second portion of the total volume) that laterally overlaps with the barrier region 105.

[0119] As already explained above, each active mesa 18 can be configured to induce an inversion channel in the corresponding active mesa 18. For example, all active mesas 18 are configured with the same inversion channel threshold voltage. Therefore, the delay between the start time of the conduction of the load current in the second volume fraction described above by way of example and the start time of the conduction of the load current in the first volume fraction (according to which, for example, during the switch-on period, as soon as the load current exceeds the threshold value of, for example, at least 0.5%, the second volume fraction of the active mesa 18 laterally overlapping the barrier region 105 carries the load current) is, for example, neither caused by providing a control signal to the control electrode for controlling the first volume fraction (which is different from the control signal provided to the control electrode for controlling the second volume fraction) nor by the difference between the inversion channel threshold voltages. More precisely, according to an embodiment, the same control signal is provided to the first volume fraction and the second volume fraction, and the first volume fraction and the second volume fraction are configured with the same inversion channel threshold voltage, and the delay is achieved only by correspondingly positioning and / or laterally configuring the barrier region 105.

[0120] Therefore, in an embodiment, the only distinguishing feature between the first volume fraction of the active mesa 18 and the second volume fraction of the active mesa 18 is that the first volume fraction does not laterally overlap the barrier region 105 and the second volume fraction does laterally overlap the barrier region 105. For example, thereby, the delay described exemplarily between the start of load current conduction (start time) is achieved.

[0121] For example, once the load current is conducted by two volume shares, it can be distributed between the volume shares according to the ratio between the volume shares. In an embodiment, if the load current exceeds 50% of the rated load current, the ratio between the first load current share conducted by the first volume share of the active mesas 18 and the second load current share conducted by the second volume share of the active mesas 18 can be at least within 10% of the ratio between the first volume share and the second volume share, or correspondingly, the ratio between the first load current share conducted by the first volume share of the active mesas 18 and the second load current share conducted by the second volume share of the active mesas 18 can be (at least substantially) the same as the ratio between the first volume share and the second volume share.

[0122] The electrically floating barrier region 105 may be spatially limited by the drift region 100 in the vertical direction Z and in relation to the vertical direction Z. Thus, the barrier region 105 may form each of an upper pn junction 1051 and a lower pn junction 1052 with the drift region 100, wherein the lower pn junction 1052 may be arranged lower than each of the bottoms 155 of the dummy trenches 15. For example, the upper pn junction 1051 is arranged within the (multiple) passive mesas 19 and is therefore above the bottoms 155 of the dummy trenches 15. The distance along the vertical direction Z between the first pn junction 1021 and the upper pn junction 1051 may amount to at least 0.5 μm. Thus, according to an embodiment, the two pn junctions 1021 and 1051 are different from each other, but are separated from each other by means of the drift region 100.

[0123] In other words, the barrier region 105 may be separated from the channel region 102 by means of at least a portion of the drift region 100. For example, along the vertical direction Z, the barrier region 105 is bounded on one side by an upper section 100-1 of the drift region 100 and on the other side by a lower section 100-2 of the drift region 100, wherein the upper section 100-1 forms a transition to the channel region 102 of the IGBT cell 1-1. The lower section 100-2 may extend along the vertical direction Z until it butts against a doped contact region 108, which may be a p-type emitter as illustrated above.

[0124] In an embodiment, the barrier region 105 does not contact any other semiconductor region of the second conductivity type, but is separated from it, for example, by means of (multiple) segments of the drift region 100. For example, the distance between the barrier region 105 and the nearest other semiconductor region of the second conductivity type amounts to at least 1 μm or at least 2 μm. Thus, for example, there is no p-type connection between the channel region 102 and the barrier region 105, and there is no p-type connection between the barrier region 105 and the well region 109 of the edge termination region 109 (further mentioned below). Along the distance, a portion of the drift region 100 may be present.

[0125] With respect to all the embodiments discussed above, it should be understood that, according to one variant, a segment of the drift region 100 included in the mesas 18 and 19 (e.g., the upper segment 100-1 forming the first pn junction 1021 with the channel region 102 and the upper pn junction 1051 with the barrier region 105 (see explanation below)) may exhibit a dopant concentration that is at least twice as great as a dopant concentration of a segment of the drift region 100 arranged below the barrier region 105 (e.g., the lower segment 100-2 of the drift region 100 forming the lower pn junction 1052 with the barrier region 105).

[0126] The sections (upper sections 100 - 1 ) of the drift region 100 included in the mesas 18 and 19 may each exhibit a -3 to 4e17 cm -3 The maximum dopant concentration is in the range of, for example, at least 1e16 cm -3 For example, the section of the drift region 100 included in the mesas 18 and 19 and which may exhibit the increased dopant concentration may be referred to as an “n barrier region”. For example, the dopant concentration of the section of the drift region 100 included in the mesas 18 and 19 is selected so that the upper pn junction 1051 remains at a level slightly above the trench bottoms 145 and 155.

[0127] Reference now Figure 4BAccording to one variant, the increased dopant concentration in the upper section (section 100-1) of the drift zone 100 is provided only locally. For example, only one of the active mesas 18 or only several of the active mesas 18 or only all of the active mesas 18 comprises a local n barrier region 100-3. For example, each of the local n barrier regions 100-3 is arranged above the barrier region 105, or respectively above the barrier region channel 1053, and below the corresponding channel region 102. For example, each n barrier region 100-3 is arranged in contact with the corresponding channel region 102 and extends downwardly from there along the vertical direction Z until it butts against the (p-) barrier region 105, or respectively terminates at the corresponding Z level if the (p-) barrier 105 does not exist / exhibits the channel 1053 at the corresponding position. Along the first lateral direction X, each n barrier region 100-3 may fill the corresponding active mesa 18. Each n barrier region 100-3 may exhibit a maximum dopant concentration that is at least twice as large as the dopant concentration of the lower section 100-2 of the drift region 100. For example, each n barrier region 100-3 exhibits a maximum dopant concentration of 1e14 cm -3 to 4e17 cm -3 The maximum dopant concentration is in the range of, for example, at least 1e16 cm -3 In contrast, according to this variant, the upper section 100-1 of the drift region included in the passive mesa 19 may exhibit a maximum dopant concentration substantially equal to the maximum dopant concentration of the lower section 100-2 of the drift region 100; for example, there is no n barrier region 100-3 provided within the active mesa 19.

[0128] In a variant (not shown), the upper pn junction 1051 may even be arranged below each of the bottom 155 of the dummy trench 15 and the bottom 145 of the control trench 14 (this example not shown). In that case, the distance along the vertical direction Z between the bottom 155 of the dummy trench 15 and the upper pn junction 1051 may be smaller than 3 μm, smaller than 2 μm or even smaller than 1 μm.

[0129] For example, the barrier region 105 exhibits a thickness along the vertical direction Z in the range of 0.1 μm to 0.5 μm, in the range of 0.5 μm to 1 μm, or in the range of 1 μm to 5 μm.

[0130] For example, a common vertical extension between the barrier region 105 and the trenches extending into the barrier region 105 may be in the range of 50 nm to 3000 nm along the vertical direction Z. In an embodiment, the barrier region 105 extends further along the vertical direction Z (i.e. down to a deeper level within the semiconductor body 10) than all trenches or respectively at least a majority of the trenches.

[0131] According to an embodiment, the barrier region 105 may exhibit a resistivity of more than 10 Ωcm and less than 1000 Ωcm, for example more than 100 Ωcm and less than 500 Ωcm.

[0132] The barrier region 105 may include boron (B), aluminum (Al), difluoroboryl (BF 2 ), Boron trifluoride (BF 3 ), or at least one of a combination thereof. According to an embodiment, a corresponding one of these exemplary materials may be used as a dopant material. In addition, a corresponding one of these exemplary materials may be implanted into the semiconductor body 10 to form the barrier region 105.

[0133] For example, the barrier region 105 exhibits a ratio of 1e14 cm -3 Larger than 4e17 cm -3 A smaller electrically active dopant concentration may be present with an extension along the vertical direction Z of at least 0.5 μm, or at least 1 μm (for example approximately 1e16 cm in total). -3 ). In addition, the barrier region 105 may exhibit a maximum dopant concentration in a region where the bottom 155 of the dummy trench 15 extends into the barrier region 105 .

[0134] In an embodiment, the barrier region 105 has a dopant concentration that is less than the dopant concentration present in the channel region 102. For example, the maximum dopant concentration of the barrier region 105 is in a range of 1% to 80% of the dopant concentration present in the channel region 102.

[0135] exist Figure 5 : an exemplary progression of the dopant concentration (CC) of the dopant of the second conductivity type along the vertical direction Z is illustrated in FIG. 1 , wherein the solid line indicates the dopant concentration (N A ) and the dotted line indicates the dopant concentration of the first conductivity type (N D ). Therefore, in the upper section (eg, close to the first load terminal 11), the dopant concentration N A may be relatively high in order to provide a channel region 102 (which, in the case of an inactive mesa 19, is not the first load terminal or is not electrically connected to the first load terminal, depending on the configuration of the inactive mesa 19 as explained above). Then, the dopant concentration N AThe transition between the channel region 102 and the upper section 100-1 of the drift region 100 can form the first pn junction 1021 in the corresponding mesa. In the case of the inactive mesa 19 not comprising a section of the channel region 102, the dopant concentration CC between the start at the first load terminal 11 and the start of the barrier region 105 will therefore be at a value corresponding to Figure 5 Then, for example, before the corresponding trench bottom 155, the dopant concentration N A (again) increases in order to form the barrier region 105. The transition between the upper section 100-1 of the drift region 100 and the barrier region 105 forms an upper pn junction 1051. As illustrated, the barrier region 105 may exhibit its dopant concentration maximum CCM at a depth level substantially equal to the level at which the corresponding trench ends, for example at the level of the bottom 155 of the dummy trench 15. The dopant concentration N A It then drops again to form a lower pn junction 1052 with the lower section 100 - 2 of the drift region 100 .

[0136] For example, the electrically floating barrier region 105 is not electrically connected to a defined potential, for example neither to the first load terminal 11, nor to the second load terminal 2, nor to the control terminal 13. In an embodiment, the electrically floating barrier region 105 is connected to a defined potential (for example to the potential of a contact or to the potential of another semiconductor region) by means of a connection with a high ohmic resistance. For example, by means of the high ohmic connection, during a switching operation, the potential of the barrier region 105 is temporarily decoupled from the defined potential. The decoupling may occur on a time scale of the switching operation, for example up to at least 10ns, or at least 100ns, or at least 10μs. For example, the resistance of the high ohmic connection amounts to more than 1e2Ω or amounts to more than 1e6Ω.

[0137] In an embodiment, the ohmic resistance between the first load terminal 11 and the barrier region 105 (eg measured during a standstill condition) amounts to more than 1e2Ω or amounts to more than 1e6Ω.

[0138] For example, in order to ensure that the barrier region 105 is electrically floating, the barrier region 105 does not extend into the transition region 1-5; for example, the barrier region 105 can be arranged exclusively in the active cell region 1-2, such as in Figure 1 As shown in the figure.

[0139] For example, the barrier region 105 does not extend into the transition region 1-5. As already explained above, the transition region 1-5 may be equipped with some of the IGBT cells 1-1 and is therefore considered an active region of the power semiconductor device 1, ie a part of the power semiconductor device 1 which also conducts a part of the load current.

[0140] In an embodiment, the transition region 1 - 5 includes neither a section of the electrically floating barrier region 105 nor any further electrically floating semiconductor region of the second conductivity type. For example, there is no floating p-doped semiconductor region included in the transition region 1 - 5.

[0141] The barrier region 105 is electrically floating and at the same time the barrier region 105 can be arranged to contact at least some of the trenches of the IGBT cell 1-1, as already explained above. Thus, the barrier region 105 can interface with the trench insulators 142, 152 and 162. For example, at least the source trench bottom 165 and / or at least the dummy trench bottom 155 extend into the barrier region 105, for example so that the source trench electrode 161, the dummy trench electrode 151 and the barrier region 105 have a common vertical extension range of at least 100 nm, at least 50 nm or at least 1000 nm along the vertical direction Z (wherein the barrier region 105 can extend further along the vertical direction Z than the trench bottom).

[0142] Should be about Fig. 6A -C clarifies this aspect in more detail. Fig. 6A -C exemplarily and schematically illustrates a section of a vertical cross section of a power semiconductor device 1 according to one or more embodiments, wherein Figure 6B Shown from Fig. 6A The section continues along the first transverse direction X, and wherein Figure 6C Shown from Figure 6B Continuation of the section along the first transverse direction X.

[0143] exist Fig. 6A Starting from , the first load terminal 11 may be partially covered by an insulating structure 80 (e.g., a package). Within the active cell area 1-2, there are a plurality of IGBT cells 1-1 arranged, each of which exhibits the exemplary contact scheme / neighboring relationship, i.e., "oDoSoSkGkSoSoD". In another embodiment, a different contact scheme is employed.

[0144] The active mesa 18 is electrically connected to the first load terminal 11 by means of the first contact plug 113, and the source electrode 161 of the source trench 16 is electrically connected to the first load terminal 11 by means of the second contact plug 115. The control electrode 141 of the control trench 14 and the dummy electrode 151 of the dummy trench 15 are electrically connected to the first load terminal 11 by means of the gate runner 135 (see Figure 6B ) is electrically connected to the control terminal 13.

[0145] In the transition region 1-5, a further IGBT cell 1-1 is arranged, which may also exhibit the contact scheme "oDoSoSkGkSoSoD" or a contact scheme different therefrom. Further along the first lateral direction X, a further dummy trench 15, a further source trench 16 and a control trench 14 are arranged, adjacent to which two active mesas 18 are arranged. Thus, in the transition region 1-5, part of the load current can be conducted.

[0146] The trench pattern may also continue in the edge termination region 1-3 along the first lateral direction X, wherein such trenches in the edge termination region 1-3 may be source trenches 16. The mesas between the source trenches 16 may be electrically connected to the first load terminal 11 by means of the first contact plugs 113. Thus, the arrangement of the source trenches 16 and the mesas between these trenches electrically connected to the first load terminal 11 may form a charge carrier discharge unit.

[0147] Within the edge termination regions 1-3, there may be a further arranged semiconductor well region 109 of the second conductivity type. For example, the well region 109 is p-doped and extends from the insulating layer 112 along the vertical direction Z, for example beyond the depth of the trenches 14, 15, 16. For example, the well region 109 extends into the semiconductor body at approximately the same depth as the barrier region 105.

[0148] Still refer to Fig. 6A The barrier region 105 may terminate at the transition between the active cell region 1-2 and the transition region 1-5. For example, the barrier region 105 may be arranged exclusively in the active cell region 1-2 and may not extend into the transition region 1-5 or the edge termination region 1-3.

[0149] On the other side, the well region 109 may be arranged exclusively in the edge termination region 1-3 and may not extend into the transition region 1-5 nor into the active cell region 1-2. As already explained above, the transition region 1-5 may entirely surround the active cell region 1-2 and may in turn be entirely surrounded by the edge termination region 1-3. The minimum width W of the transition region 1-5 (i.e., the minimum distance between the barrier region 105 and the well region 109) amounts to 1 μm, wherein the minimum width may be greater than 1 μm, for example, greater than 3 μm, greater than 5 μm, or even greater than 10 μm or greater than 20 μm. Along the width W, a portion of the drift region 100 may be present.

[0150] When the well region 109 is electrically connected to the first load terminal 11, for example by means of the first contact plug 113 (as exemplarily shown), the potential in the well region 109 can be substantially the same as the potential of the first load terminal 11. Therefore, by means of the transition region 1-5 and its minimum width W, it can be more easily ensured that the barrier region 105 is actually electrically floating.

[0151] In an embodiment, the well region 109 has a -3 to 5e18cm -3 It may extend along the vertical direction Z, for example further as trenches 14 , 15 , 16 , for example down to a level substantially corresponding to a lower pn junction 1052 formed between the barrier region 105 and the drift region 100 .

[0152] Reference now Figure 6B , the well region 109 may extend along the first lateral direction X until it butts against the semiconductor VLD (variation of lateral doping) or JTE (junction termination extension) region 107. Moreover, the VLD / JTE region 107 may be of the second conductivity type and may have a lower dopant concentration than the well region 109. Generally speaking, the concept of such a VLD or JTE region within the termination structure of a power semiconductor device is known to the skilled person, and therefore a more detailed explanation of the function of the VLD or JTE region 107 is avoided here. For safety reasons, the VLD / JTE region 107 may be isolated from the potential of the gate runner 135 by means of a thicker oxide layer 85 (which may be a LOCOS layer or a recessed field oxide). Alternatively, other termination concepts known to the skilled person may be used.

[0153] For example, the gate runner 135 laterally overlaps each of the well region 109 and the VLD region 107 .

[0154] Reference now Figure 6C , the VLD region 107 may terminate at a position within the edge termination region 1-3 well before the chip edge 1-4. The region between the chip edge 1-4 and the termination of the VLD region 107 may consist essentially of an unstructured section of the drift region 100, wherein close to the chip edge 1-4 a channel stop ring arrangement may be provided. In general, the concept of a channel stop ring arrangement close to the chip edge of a power semiconductor device is also known to the skilled person. For example, according to Fig. 6A In the embodiment exemplarily illustrated in Figure 1-C, in order to form a channel stop ring arrangement, a collector contact 121 is provided which exhibits the potential of the second load terminal 12. Connected thereto is the electrode of the trench 125. For example, the trench 125 follows the course of the termination region 1-3, since it also entirely surrounds the transition region 1-5. Further trenches 1251 and 1252 for forming a channel stop ring arrangement may be provided. The trenches 125, 1251 and 1252 may be flanked by semiconductor regions 127 of the second conductivity type.

[0155] In an embodiment, the barrier region 105 has a lateral structure. For example, the barrier region 105 is formed as a lateral structured layer extending throughout the entire active cell region 1-2, for example until it abuts against the transition region 1-5. Therefore, the barrier region 105 can be exclusively arranged in the active cell region 1-2 and will not extend into the transition region 1-5. In the active cell region 1-2, the barrier region 105 can be constructed in the lateral direction.

[0156] For example, the IGBT cell 1-1 is configured with a lateral structure according to a first layout having a first pitch, and wherein the lateral structure of the barrier region 105 is configured according to a second layout having a second pitch at least twice as large as the first pitch. Therefore, the lateral structure of the barrier region 105 may be rougher than the trench pattern.

[0157] The lateral structure of the barrier region 105 may be formed by a plurality of through channels 1053 (hereinafter also simply referred to as “channels”). Figure 7 Such a concept is exemplarily illustrated in a general manner in For example, according to the second layout, each of the via channels 1053 may exhibit a maximum lateral extension that is at least twice as large as a minimum trench width and / or a minimum mesa width formed according to the first layout.

[0158] In an embodiment, one or more channels 1053 provide a load current channel for a current below 10% or even below 1% of the rated load current of the power semiconductor device 1. For a larger load current, the entire active cell region 1-2 carries the load current regardless of whether a portion overlaps bilaterally with the barrier region 105. Therefore, according to an embodiment, for a load current below 10% or even below 1% of the rated load current, it is not necessary to pass through the barrier region 105, but can pass through one or more channels 1053. For example, in a vertical projection (along the vertical direction Z) that can cause an inversion channel in the active mesa 18 (e.g., in a vertical projection of the source region 101), the barrier region 105 is absent, i.e., the channel 1053 is revealed.

[0159] The possible effects described in the preceding paragraphs regarding the first fraction of the total volume of the active mesa 18 which does not laterally overlap the barrier region 105 and the second fraction of the total volume of the active mesa 18 which does laterally overlap the barrier region 105 have also been explained above in more detail.

[0160] In an embodiment, one or more channels 1053 are positioned and / or dimensioned to laterally overlap at least a subset of source regions 101 .

[0161] For example, the barrier region 105 may form a “carpet” arranged within the active cell field 1-2 and, for example, substantially parallel to each of the first load terminal 11 and the second load terminal 12 and separated from each of these terminals 11, 12 at least by means of the drift region 100. Such a carpet-like configuration of the barrier region 105 may be positioned within the semiconductor body 10 so that the trench bottoms 145 and 155 and / or 165 may sink into the barrier region 105.

[0162] The channels 1053 may laterally overlap one or more of the active mesas 18. Following the visual vocabulary introduced above, the barrier region 105 may thus be implemented as a "stitched blanket" where one or more channels 1053 may entirely fill a section of the drift region 100. The location and number of channels 1053 may be selected, for example, depending on the cell configuration.

[0163] The barrier region 105 may be implemented as an adjacent barrier layer within the active cell field 1-2 of the power semiconductor device 1, for example as the “blanket cover”. As already indicated above, each of the dummy trench bottom 155 and / or the control trench bottom 145 and / or the source trench bottom 165 may extend into the barrier region 105, for example the dummy trench 15 and / or the control trench 14 and / or the source trench 16 may extend into the barrier region 105 by at least 100 nm, by at least 500 nm or by at least 1000 nm.

[0164] Still refer to Figure 7 For example, according to variant A, the channel may have a stripe configuration arranged substantially perpendicular to the stripe configuration of the IGBT cell 1-1. In another embodiment, a large extended central through channel 1053 is provided (variant B). According to variants B and D, a plurality of smaller channels 1053 are provided, which may be distributed according to various patterns.

[0165] Each of the plurality of channels 1053 may be filled with a segment of the drift region 100. Thus, within the channels 1053, there may be an n-doped semiconductor region exhibiting a dopant concentration corresponding to the dopant concentration of the drift region. In another embodiment, which will be explained in more detail further below, some or all of the channels 1053 may also be filled by means of (deeper) trenches.

[0166] Some embodiments provide a barrier region 105, which is positioned and dimensioned according to predefined design rules through a channel 1053. For example, the second layout can be configured according to the design rules. The location and dimensions of the channel 1053 may have a significant impact on the dynamic behavior of the power semiconductor device 1, for example with respect to the voltage slope (dV / dt) during the turn-on operation.

[0167] For example, according to a first provision of such a design rule, the distance between two arbitrary through-channels 1053 of the through-channels 1053 arranged adjacent to each other is less than 1 mm.

[0168] A second provision of such a design rule may be that the barrier region 105 is arranged in a semiconductor layer of the semiconductor body 10, which extends completely and exclusively in the active cell region 1-2 and exhibits a total volume, wherein the through channel 1053 forms at least 1% and at most 50% of the total volume. The remaining volume of the semiconductor layer (i.e. the p-doped part of the barrier region 105) may be formed by semiconductor regions of the second conductivity type. As already indicated above, the remaining volume may have a relative volume of 1e14 cm -3 Larger than 4e17 cm -3 Smaller dopant concentrations (see Figure 5 The concentration CC in the dopant concentration is present within an extension of at least 0.1 μm or at least 0.5 μm along the vertical direction Z.

[0169] A third provision of such a design rule may be that the barrier region 105 (regardless of its channel 1053 ) connects the inactive mesas 19 included in the plurality of IGBT cells 1 - 1 in the active cell region 1 - 2 to each other.

[0170] A fourth provision of such a design rule may be that the channel 1053 laterally overlaps at least a subset of the active mesas 18 of the active cell region 1 - 2 . For example, one or more channels 1053 are positioned and / or dimensioned to laterally overlap at least a subset of the source regions 101 .

[0171] A fifth provision of such a design rule may be that the channel 1053 laterally overlaps at least a subset of the control trenches 14 of the active cell region 1 - 2 .

[0172] Another provision of such a design rule may be that the barrier region 105 at least partially extends into a subset of the active mesas 18, for example without contacting the corresponding control trench 14, which is located on the lateral side of the corresponding active mesas 18. For example, thereby, the barrier region 105 can be configured to provide a conductive path between the bottom 155 of the dummy trench 15 and a section of a corresponding one of the subset of active mesas 18. Therefore, one design rule may be: the through channel 1053 is laterally overlapped with one or more of the active mesas 18 of the IGBT cell 1-1. For example, the design rule may specify that the through channel 1053 is laterally overlapped with respect to the total number of active mesas 18 present in the active cell area 1-2 (where at least 1% and at most 50% of the active mesas 18). As explained above, the lateral overlap between the barrier region 105 and a respective one of the active mesas 18 may occur partially; i.e. the barrier region 105 must not necessarily completely overlap the respective active mesa 18, but for example up to 10%, up to 30%, or up to 70% of the mesa width of the respective active mesa 18.

[0173] about Fig. 8A -D, should present an exemplary lateral structure of the barrier region 105, which Fig. 8A -D each schematically and exemplarily illustrate a section of a horizontal projection of a power semiconductor device 1 according to some embodiments.

[0174] refer to Fig. 8A -D, the barrier region 105 may extend completely and exclusively within the active cell region 1-2. Within the active cell region 1-2, the plurality of IGBT cells 1-1 may be provided, wherein each IGBT cell includes at least one control trench 14, which may be laterally arranged on the side of the corresponding active mesa 18, and each IGBT cell includes a source region 101, the source region being electrically connected to the first load terminal 11. The IGBT cells 1-1 included in the active region 1-2 may exhibit the Fig. 6A -C explained configuration. The IGBT cells 1-1 exhibit a stripe configuration oriented substantially along the second lateral direction Y, also as already explained above. For example, each IGBT cell 1-1 extends along the second lateral direction throughout the entire active cell area 1-2.

[0175] exist Fig. 8A In FIG. 1-D, a plurality of source regions 101 are illustrated, of which only some are provided with corresponding reference symbols. For example, each of the illustrated source regions 101 forms part of two active mesas 18, as in FIG. Fig. 6A As shown in the figure, a corresponding control trench 14 is arranged between the two active mesas 18 .

[0176] The active cell region 1-2 may be entirely surrounded by the transition region 1-5, which in turn may be entirely surrounded by the edge termination region 1-3. Fig. 6A -C exemplarily explains the way to configure the transition regions 1-5 and the edge termination regions 1-3.

[0177] As in Fig. 8A -D, the lateral structure of the barrier region 105 (which is formed or respectively defined by the number, size and position of the channels 1053) may exhibit a significantly larger pitch than the pitch of the layout from which the trench pattern is formed.

[0178] For example, refer to Fig. 8A , the channels 1053 may exhibit an orientation that is substantially parallel to the orientation of the stripe configuration of the IGBT cell 1-1. A respective one of the channels 1053 may laterally overlap with a plurality of adjacent trenches and mesas. As noted above, it may be appropriate to position the channels 1053 so that they laterally overlap with at least a subset of the active mesas 18, based on Fig. 8A There, the location of the channel 1053 is selected so that the channel 1053 overlaps with a subset of the source regions 101. Therefore, the load current of the subset of active mesas 18 does not pass through the barrier region 105, but flows through its channel 1053. Fig. 8A As further illustrated in FIG. 1 , according to an embodiment, the channel 1053 may also terminate at the transition between the active cell region 1 - 2 and the transition region 1 - 5 .

[0179] Figure 8B The embodiment illustrated in FIG. 1 corresponds substantially to Fig. 8A , in which the channel 1053 is sized and positioned so as to be entirely integrated within the barrier region 105 and so as not to intersect the transition regions 1-5.

[0180] According to Figure 8C In the embodiment schematically and exemplarily illustrated in FIG. 1 , the channel 1053 exhibits an orientation substantially perpendicular to the orientation of the stripe configuration of the IGBT cell 1-1. Such an orientation (which is also Fig. 9 ) can support damping phenomena (ie reduce or smoothen amplitude changes) and / or correspondingly reduce or avoid voltage swing phenomena during switching operation of the power semiconductor device 1. Fig.8D The embodiment illustrated in the figure corresponds essentially to Figure 8C , in which the channel 1053 is sized and positioned so as to be entirely integrated within the barrier region 105 and so as not to intersect the transition regions 1-5.

[0181] Now refer to Fig.10 and 11In the embodiment schematically and exemplarily illustrated in FIG. 1 , in addition to or as an alternative to the drift region 100 , some or all of the channel 1053 may be filled with the lower section of the trench of the IGBT cell 1 - 1 . For example, some or all of the channel 1053 is filled with the lower section of the control trench 14 . Fig.10 In the embodiment illustrated in FIG. 1 , this can be achieved by designing the control grooves 14 to have a greater overall extension along the vertical direction Z than the grooves that do not fill the channel 1053. Fig.11 In the embodiment illustrated in FIG. 1 , this can be achieved by providing the barrier region 105 so that the channel 1053 is arranged at a corresponding local height (with respect to the vertical direction Z). Fig.10 and 11 An exemplary method of generating a structure is illustrated in FIG.

[0182] As in Fig.10 and 11 As further illustrated in FIG. 1 , in an embodiment, the contact scheme is different from the exemplary contact scheme mentioned above, for example, the contact scheme of each IGBT cell 1 - 1 within the active cell region 1 - 2 is “oSkGkSoDoD”, but also according to this contact scheme, the active mesas 18 are laterally confined by the corresponding source trenches 16 .

[0183] Reference now Figure 12-19 , another exemplary lateral structure of the barrier region 105 should be presented. Figures 12 to 19 In each of the embodiments schematically and exemplarily illustrated in , the contact scheme for each IGBT cell 1 - 1 within the active region 1 - 2 is “oDoSoSkGkSoSoD”. However, as indicated above, in other embodiments, different contact schemes are employed, examples of which have been presented further above.

[0184] For example, refer to Fig.12 , the channel 1053 extends parallel to the stripe configuration of the control trenches 14. The barrier region 105 partially extends into some of the active mesas 18 arranged adjacent to each side of the corresponding control trench 14. As illustrated, the channel 1053 can appear at each fifth IGBT cell 1-1 along the first lateral direction X. Therefore, the distance D between two adjacent channels 1053 along the first lateral direction X can be greater than 500 μm, for example approximately 700 μm in total. For example, the barrier region 105 thus always overlaps overall laterally with at least exactly 80% of the total number of IGBT cells 1-1 within the active region 1-2. The remaining 20% ​​of the total number of IGBT cells 1-1 within the active region 1-2 can, for example, laterally overlap with the channel 1053 by means of their corresponding control trenches 14 and their corresponding active mesas 18 (as in Fig.12 In addition, as shown in Fig.12 As shown in FIG. 1 , the well region 109 does not extend into the transition region 1 - 5 , and the barrier region 105 does not extend into the transition region 1 - 5 . More specifically, the transition region 1 - 5 separates the barrier region 105 from the well region 109 .

[0185] according to Fig.13 In the embodiment shown in FIG. 1 , each of the channels 1053 may also be provided with a smaller rectangular cross-section and positioned according to the island pattern within the active cell region 1 - 2. Each of the channels 1053 may have a width in the range of 5 μm to 20 μm along the first lateral direction X and a length in the range of 5 μm to 20 μm along the second lateral direction Y.

[0186] In an embodiment, for each of the channels 1053, the width along the first lateral direction X is greater than the length along the second lateral direction Y of the corresponding channel 1053, for example, the width-to-length ratio of each channel is greater than 2, or even greater than 3. Therefore, the channels can have a geometric configuration so as to extend more precisely perpendicular to the stripe configuration of the IGBT cell 1-1 and not parallel thereto. Such a configuration can be beneficial for avoiding / reducing undesirable voltage swings / oscillations on the control electrode 141.

[0187] Along the first lateral direction X, each IGBT unit 1-1 may laterally overlap with one of the channels 1053 (wherein Fig.13 , only the source regions 101 and the control trenches 14 are illustrated, wherein each of the illustrated source regions 101 is electrically connected to two corresponding active mesas 18 separated from each other by means of the corresponding control trenches 14). Along the second lateral direction Y, each IGBT cell 1-1 may laterally overlap with a plurality of channels 1053. For example, a distance Dx between two adjacent channels 1053 along the first lateral direction X is in the range of several microns (e.g., 3 μm to 5 μm). Furthermore, a distance Dy between two adjacent channels 1053 along the second lateral direction Y may be in the range of several microns (e.g., 5 μm to 20 μm), for example, approximately 15 μm.

[0188] Along the second lateral direction Y, the source regions 101 may be positioned with a distance Ds in the range of 0.1 μm to 20 μm. For example, along the second lateral direction Y, each channel 1053 laterally overlaps at least three of the source regions 101 .

[0189] exist Fig.14 A similar configuration is schematically and exemplarily illustrated in FIG. 1 . Along a first lateral direction X, each IGBT unit 1-1 may laterally overlap with one of the channels 1053. Along a second lateral direction Y, each IGBT unit 1-1 may laterally overlap with a plurality of channels 1053, wherein the channels 1053 are Fig.13Compared to the embodiment shown in , the distance Dy along the second lateral direction is increased.

[0190] For example, the channel 1053 does not laterally overlap with the dummy trenches 15. More specifically, each of the dummy trenches 15 extends into the barrier region 105. For example, the channel 1053 partially overlaps with the control trench 14 and the source trench 16.

[0191] Fig.15 The lateral structure of the barrier region 105 schematically and exemplarily illustrated in FIG. 1 corresponds essentially to that in FIG. Fig.13 and 14 Thus, along the first lateral direction X, each IGBT unit 1-1 may laterally overlap with one of the channels 1053. Along the second lateral direction Y, each IGBT unit 1-1 may laterally overlap with multiple channels 1053, wherein the channels 1053 are Fig.14 Compared with the embodiment shown in FIG. 1 , the distance Dy along the second lateral direction is increased. For example, the distance Dy between two adjacent channels 1053 along the second lateral direction is in the range of several micrometers (eg, 1 μm to 2000 μm).

[0192] according to Fig.16 In a variant schematically and exemplarily illustrated in FIG. 1 , the lateral structure of the barrier region 105 has a checkerboard pattern. According to this embodiment, approximately 50% of the total volume of the barrier region 105 is constituted by channels 1053 (e.g. filled with corresponding sections of the drift region 100) and the remaining 50% of the barrier region 105 is a p-doped region. For example, each channel 1053 may exhibit a rectangular cross-section. Each of the channels 1053 may have a width along a first lateral direction X so as to overlap with three adjacent IGBT cells 1-1, and a length along a second lateral direction Y so as to overlap with three adjacent source regions 101. Along the second lateral direction Y, the source region 101 may be positioned within a distance Ds within the range given above. As illustrated, according to Fig.16 and with Fig.14 In contrast to the embodiment shown in , the channel 1053 may laterally overlap the dummy groove 15 .

[0193] according to Fig.17 Another variant schematically and exemplarily shown in Fig.16 Compared to the lateral structure shown in FIG. 1 , the volume share of the channel 1053 can be reduced from 50% to less than 20%. Each of the channels 1053 can have a width along the first lateral direction X so as to overlap with three adjacent IGBT cells 1-1, and a length along the second lateral direction Y so as to overlap with three adjacent source regions 101. Along the second lateral direction Y, the source regions 101 can be positioned within a distance Ds within the range given above. Again, as illustrated, also according to Fig.17and with Fig.14 1-1 , the channel 1053 may laterally overlap with the dummy trench 15. In addition, the distance Dx between two adjacent channels 1053 along the first lateral direction X may amount to the total width of three adjacent IGBT cells 1-1. The distance Dy along the second lateral direction Y may be greater than the distance Dx. For example, the distance Dy between two adjacent channels along the second lateral direction Y may amount to at least eight times the distance Ds.

[0194] Although about Fig.17 The embodiment shown in FIG. 104 keeps the dimensions of channel 1053 unchanged, but according to Fig.18 In the embodiment schematically and exemplarily shown in FIG. 1 , the density of channels 1053 can be increased and thus the distances Dx and Dy can be reduced. Fig.17 and 18 As further illustrated in FIG. 1 , the channels 1053 may be positioned such that two channels 1053 adjacent to each other at a distance Dy along the second lateral direction Y do not exhibit lateral overlap along the first lateral direction X (e.g., Fig.17 ) or so that two channels 1053 adjacent to each other at a distance Dx along the first lateral direction X do not exhibit lateral overlap along the second lateral direction Y (as shown in Fig.18 ).

[0195] Although about Fig.17 The embodiment shown in FIG. 104 keeps the dimensions of channel 1053 unchanged, but according to Fig.19 In the embodiment schematically and exemplarily shown in FIG. 1 , the density of channels 1053 may be reduced and thus the distances Dx and Dy increased.

[0196] Other variations of the lateral structure of the barrier region 105 are possible. For example, each variation of the lateral structure of the barrier region 105 (for example, if they are Figures 7 to 19 ) follows one or more of the following provisions of the design rules:

[0197] (i) the distance between any two through channels in the through channels 1053 arranged adjacent to each other (for example, the distances Dx and Dy) is less than 1 mm;

[0198] (ii) the barrier region 105 is arranged in the semiconductor layer of the semiconductor body 10, the semiconductor layer extending completely and exclusively in the active cell area 1-2 and exhibiting a total volume, wherein the through channel 1053 forms at least 1% and at most 50% of the total volume. The remaining volume of the semiconductor layer (i.e. the p-doped part of the barrier region 105) is formed by a semiconductor region of the second conductivity type;

[0199] (iii) the barrier region 105 (regardless of its channel 1053 ) connects the inactive mesas 19 included in the plurality of IGBT cells 1 - 1 in the active cell region 1 - 2 to each other;

[0200] (iv) the channels 1053 laterally overlap at least a subset of the active mesas 18 of the active cell regions 1 - 2 (eg, one or more channels 1053 are positioned and / or dimensioned to laterally overlap at least a subset of the source regions 101 );

[0201] (v) the channel 1053 laterally overlaps at least a subset of the control trenches 14 of the active cell region 1-2;

[0202] (vi) the barrier region 105 extends completely and exclusively within the active cell region 1-2 (and does not enter the transition region 1-5);

[0203] (vii) the barrier region 105 at least partially extends into a subset of the active mesas 18 (e.g. without establishing contact with a corresponding control trench 14 laterally flanked by the corresponding active mesa 18). For example, thereby, the barrier region 105 can be configured to provide a conductive path between a segment of a corresponding one of the subset of active mesas 18 and a bottom 155 of the dummy trench 15;

[0204] (viii) the lateral structure of the barrier region 105 is configured according to a second layout having a second pitch at least twice as large as the first pitch (as indicated above, the IGBT cell 1 - 1 is configured with a lateral structure according to a first layout having a first pitch);

[0205] (ix) If present (eg when the power semiconductor device 1 is configured as an RC-IGBT), the channel 1053 may laterally overlap with the n-type emitter electrically connected to the second load terminal 12 .

[0206] As already explained above, the position and / or lateral structure of the barrier region 105 (e.g. Figure 7-19105 ) can allow the total volume of the active mesa 18 to be divided into a first portion and a second portion, the first portion not lateral overlap with the barrier region 105 and the second portion lateral overlap with the barrier region 105. As explained above, the first portion of the active mesa 18 lateral overlaps with at least one channel 1053 of the barrier region 105 or with another section of the drift region 100 where there is no barrier region 105 (e.g., within the transition region 1-5). In contrast, the second portion of the active mesa 18 lateral overlaps with the barrier region 105. For example, the load current conducted through the second portion passes through the barrier region 105. As already explained further above, in an embodiment, the first portion is configured to carry a load current in the range of at least 0% to 100% of the rated load current for which the power semiconductor device is designed. The second portion is configured to carry the load current only if the load current exceeds at least 0.5% of the rated load current. Thus, a first portion of the active mesa 18 can be considered as a "firing volume" which, for example, starts to conduct the load current during the switch-on of the power semiconductor device 1, while the second portion initially remains passive. If the load current then exceeds a threshold value of at least 0.5% of the rated load current (wherein this threshold value can be higher than 0.5%, for example higher than 1%, for example at least 5% or at least 10%), the barrier region 105 can become more conductive so that the second portion can also carry the load current.

[0207] A method of processing a power semiconductor device is also presented. Fig. 20 A flow chart of an exemplary method 2 is schematically illustrated in . For example, in a first step 2100 , a semiconductor body is provided.

[0208] Method 2 can be implemented to provide a power semiconductor device, which includes an active cell region having a drift region of a first conductivity type; a plurality of IGBT cells at least partially arranged within the active cell region, wherein each of the IGBT cells includes at least one trench extending into the drift region along a vertical direction; an edge termination region surrounding the active cell region; and a transition region arranged between the active cell region and the edge termination region, the transition region having a width along a lateral direction from the active cell region toward the edge termination region, wherein at least some of the IGBT cells are arranged within the transition region or extend into the transition region accordingly.

[0209] For example, method 2 may further include step 2200, during which an electrically floating barrier region of the second conductivity type is provided, wherein the electrically floating barrier region is arranged in the active cell region and contacts at least some of the trenches of the IGBT cell, and wherein the electrically floating barrier region does not extend into the transition region.

[0210] According to another embodiment, method 2 is implemented to provide a power semiconductor device including a first load terminal and a second load terminal, the power semiconductor device being configured to conduct a load current between the terminals along a vertical direction and comprising: an active cell region having a drift region of a first conductivity type; an edge termination region having a well region of a second conductivity type; a plurality of IGBT cells arranged in the active cell region, wherein each of the IGBT cells comprises a plurality of trenches extending into the drift region along a vertical direction and laterally confining a plurality of mesas. The plurality of trenches comprises: at least one control trench having a control electrode; at least one dummy trench having a dummy electrode electrically coupled to the control trench; at least one source trench having a source electrode electrically connected to the first load terminal. The plurality of mesas comprises at least one active mesa arranged between at least one control trench and at least one source trench; and at least one passive mesa arranged adjacent to at least one dummy trench. Step 2200 can be implemented by providing an electrically floating barrier region of a second conductivity type, wherein at least the bottom of the dummy trench and the bottom of the source trench both extend at least partially into the electrically floating barrier region, and wherein a portion of the drift region located in the lateral direction between the electrically floating barrier region and the well region has a lateral extension of at least 1 μm in the lateral direction.

[0211] For example, with respect to the two embodiments of method 2 described above, the barrier region may be formed before the trenches of the IGBT cell are formed. In another embodiment, the barrier region is formed after the trenches of the IGBT cell have been formed. In yet another embodiment, the barrier region is formed during the formation of the IGBT cell (e.g., after the trenches have been etched and before the trenches are filled with trench electrodes).

[0212] The exemplary embodiment of the method 2 may correspond to the exemplary embodiment of the power semiconductor device 1 explained above. In particular, the method 2 may be implemented in order to form a barrier region having a lateral structure, as has already been described above, for example, with regard to Figures 7 to 19 Examples thereof are presented.

[0213] In an embodiment of method 2 , the lateral structure of the barrier region 105 is formed by creating a uniformly doped p-layer and by locally providing an n-type counter-doping in order to form the channel 1053 .

[0214] In another embodiment of method 2, a uniformly doped p-layer is created and the trench depth is varied (see Fig.10 ) by at least partially pinching the layer to a value exceeding the maximum dopant concentration (see Figure 5 The lateral structure of the barrier region 105 is formed by a depth of the CCM in the barrier region 105.

[0215] In yet another embodiment, the lateral structure of the barrier region 105 is formed by using a mask arrangement.

[0216] By way of example, the barrier region 105 is produced by means of deep implantation, for example after the trenches are formed by means of providing trench insulators 142, 152, 162, 172 and polysilicon filling for forming trench electrodes 141, 151, 161, 171. The realization of the projection range of the barrier region 105 (e.g. 5 μm, depending on the trench depth as explained above) may then require high implantation energies, for example in the range of 4 MeV, for example in the case of boron as implantation material. For example, masking of the implantation may be simplified by the presence of a flat surface, followed by the polysilicon filling of the trenches. The implantation may take place at high energy, but the dose may be low. Thus, the trench insulators 142, 152, 162, 172 are not damaged. The variants described in this paragraph may be compared with the further description below regarding Figure 21-25 A trench bottom implant combination is described.

[0217] In an alternative embodiment, the barrier region 105 is created prior to the trench fabrication process. For example, this can be implemented by performing a local shallow p-type implantation followed by epitaxial growth with a target thickness substantially equal to the trench depth. In this case, a slowly diffusing p-type species can be used as the implant material. For example, such a variant can be used to form a substrate according to Fig.10 The deeper control trench 14 can be formed, for example, by tuning the trench layout width and / or by providing separate trench etching blocks for shallow and deeper trenches. The deeper control trench 14 then extends along the vertical direction Z beyond the barrier region 105 and into the drift region 100 (i.e., its lower section 100-2), as shown in Fig.10 About Fig.11 , the local height of the barrier region 105 can be achieved, for example, by means of locally providing a counter doping, for example by locally performing an n-type implantation. Alternatively, only a p-type implantation is performed, wherein an implantation damping element can be provided at selected locations on the surface of the semiconductor body 10, for example at locations where one or more of the specified control trenches 14 are to be formed. Due to the damping element, the penetration depth of the implanted ions is reduced, thereby causing a local height in the barrier region 105 in the result. Then, all trenches 14, 15, 16, 17 can exhibit the same depth, while those that laterally overlap with the local height of the barrier region 105 can extend along the vertical direction Z beyond the barrier region 105 and into the drift region 100 (i.e. its lower section 100-2), as in Fig.11 . Thus, according to an embodiment, a through channel 1053 may be formed. For example, the damping element is formed by generating a local step on the semiconductor body surface (e.g. by plasma etching or sacrificial recessed LOCOS), wherein this may be followed by a p-type implant and silicon epitaxial regrowth of appropriate thickness so that the trench will be properly aligned with the p-type implant profile.

[0218] According to another embodiment, a method for processing a power semiconductor device includes: providing a semiconductor body having a drift region of a first conductivity type; creating a plurality of trenches, wherein the trenches extend into the semiconductor body along a vertical direction and are arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, wherein the mask arrangement has a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement; subjecting the semiconductor body and the mask arrangement to a dopant material providing step (e.g., an implantation processing step), thereby creating a plurality of doped regions (e.g., implanted regions) of a second conductivity type complementary to the first conductivity type below the bottom of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step, thereby causing the plurality of doped regions to extend parallel to the first lateral direction so as to overlap and form a barrier region of the second conductivity type adjacent to the bottom of the exposed trenches.

[0219] Now we will discuss below Figures 21 to 25 Describing exemplary aspects of this method in more detail, Figures 21 to 25 Each of them schematically and exemplarily illustrates one or more steps of a method of processing a power semiconductor device according to one or more embodiments based on one or more sections of a vertical cross section.

[0220] It should be understood that the following Figure 21-25 Exemplary embodiments of the described methods may be used to form Figure 1-19 (eg corresponding barrier region 105 ) to describe one or more of the embodiments of the power semiconductor device.

[0221] Reference now Fig.21 In the embodiment illustrated in , a semiconductor body 10 is provided with a drift region 100 of a first conductivity type. For example, the semiconductor body 10 is provided as part of a semiconductor wafer. With regard to exemplary aspects of the drift region 100, such as its overall extension along the vertical direction Z and / or its dopant concentration, it is referred to above.

[0222] In a step 20 , a plurality of trenches 14 , 15 , 16 are created, wherein the trenches 14 , 15 , 16 extend along a vertical direction Z into the semiconductor body 10 and are arranged adjacent to each other along a first lateral direction X.

[0223] For example, creating the plurality of trenches 14, 15, 16 may include performing an etching process step, such as a plasma etching process step. In general, there are a plurality of etching formation techniques available, wherein the embodiments described herein are not limited to a specific one of such techniques.

[0224] In an embodiment, the semiconductor body 10 may be covered with a hard mask during the (plasma) etching. The hard mask may be removed after the trench formation or may be kept as a masking layer for further processing steps.

[0225] For example, the grooves 14, 15, 16 are arranged equidistantly along the first lateral direction X. With regard to exemplary dimensions of the grooves 14, 15, 16 (e.g. their respective width along the first lateral direction X), their respective depth along the vertical direction Z (or respectively the total extension), and / or the distance between the grooves 14, 15, 16 (i.e. the mesa width), it is referred to above.

[0226] In such Fig.24 In the variants illustrated in FIG. 1 , some of the trenches may be formed with a greater total extension than other trenches along the vertical direction Z. For example, some of the trenches that are designated source trenches 16 and that are laterally arranged adjacent to designated control trenches 14 are formed with a greater depth. For example, the greater depth of the trenches may amount to at least 110%, at least 120%, or at least 130% of the depth of the remaining trenches.

[0227] After the trenches 14, 15, 16 have been created, in a subsequent step 21 a protective layer 300 is provided at least at the trench sidewalls. Fig.21 As shown in FIG. 3 , the surfaces of the trenches 14 , 15 , 16 are completely covered by the protective layer 300 . For example, the surface section 10 - 1 of the semiconductor body 10 and the trench bottom may also be covered by the protective layer 300 .

[0228] For example, the protective layer 300 is a sacrificial oxide. Providing the protective layer 300 may include at least one of a deposition process step and a thermal growth process step. As an example, the thickness of the protective layer 300 may be in the range of 5 nm to 150 nm or more.

[0229] In a step 22 , a mask arrangement 30 is provided at the semiconductor body 10 , wherein the mask arrangement 30 has a lateral structure according to which some of the trenches 14 , 15 , 16 are exposed and at least one of the trenches 14 , 15 , 16 is covered by the mask arrangement 30 .

[0230] For example, after providing the protective layer 300, the trenches 14, 15, 16 are filled with a mask material 302 (e.g. a photoresist material or part of a photoresist composite system), i.e. an anti-reflective coating material or a combination thereof, wherein the mask material 302 may initially cover / fill all trenches 14, 15, 16 as well as the surface section 10-1. Thereafter, the mask material 302 may be structured laterally in order to create one or more openings 301. Thus, after such lateral structuring, as in Fig.21As schematically and exemplarily illustrated in relation to step 22, some of the trenches 14, 15, 16 are exposed and at least some of the trenches 14, 15, 16 are covered by the mask arrangement 30. For example, as in Fig.24 As illustrated in FIG. 3 , the deeper trenches and the trenches between the deeper trenches are covered by the mask material 302 , while the other trenches are exposed.

[0231] As will become apparent in more detail from the following description, the barrier region 105 to be created may exhibit a lateral structure which essentially corresponds to the lateral structure of the mask arrangement 30. For example, the trenches 14, 15, 16 are formed according to a first layout having a first pitch, wherein the lateral structure of the mask arrangement 30 may be configured according to said second layout having a second pitch or, respectively, a feature size which is at least twice as large as the first pitch.

[0232] Structuring the mask material 302 in the lateral direction may comprise a lithographic processing step, for example by using a negative tone resist material as the mask material 302. For example, such a lithographic processing step may be performed based on a feature size that is at least twice as large as the second pitch or the first pitch according to which the trenches 14, 15, 16 have been created. Thus, the lateral structure of the mask arrangement 30 may be more coarsely scaled than the trench pattern.

[0233] In a variant, before carrying out the next step 24 or before or after providing the mask arrangement 30, an etch-back processing step can be carried out in order to at least partially remove the protective layer 300 at the surface sections 10-1 between the trenches 14, 15, 16 and at the trench bottoms 145, 155, 165, while the protective layer 300 remains at the trench sidewalls 144, 154, 164. Fig.23 , step 211 explains this in more detail.

[0234] In another variant, the mask arrangement 30 is provided as a stencil mask. Then, no resist material is used and the step of performing a photolithography process step on the resist material can be omitted. For example, such a stencil mask can be aligned with the trench layout during implantation.

[0235] In step 24 , the semiconductor body 10 and the mask arrangement 30 are subjected to a dopant material providing step (eg an implantation processing step), thereby creating a plurality of doped regions (eg implanted regions) 1059 of a second conductivity type (which is complementary to the first conductivity type) below the bottom of the exposed trenches 14 , 15 , 16 .

[0236] The following explanation is for an example where the dopant material providing step comprises an implantation processing step and accordingly the region created below the trench bottom 1059 is an implanted region. However, in other examples, the doped region 1059 may be created using a process other than implantation.

[0237] The implantation may be an ion implantation. For example, boron may be implanted during step 24. The implantation may be a low energy implantation; for example, the implantation may be performed at an energy in the range of 5 keV to 1000 keV. Further, a ion implantation may be performed at 1e11 cm -2 to 1e13 cm -2 The implantation is performed with an implantation dose within a range of .

[0238] In an embodiment, the implantation direction and the orientation of the trenches 14, 15, 16 can be matched to each other in such a way that the trench sidewalls of the exposed trenches are not subjected to the implantation or at least hardly subjected to the implantation. As such, in an embodiment, the creation of the trenches 14, 15, 16 (see step 20) is performed so that for at least the first 80% of the total extension of the respective trenches along the vertical direction Z, the respective trench width along the first lateral direction remains within the range of at least 95% of the trench width present at the trench opening of the respective trench. For example, in the upper 80% of the respective trenches, the trench width is not reduced or is correspondingly only reduced by 5%. Of course, an increase in the trench width in the upper 80% of the respective trenches may also be possible in order to avoid that the trench sidewalls in the upper 80% are not subjected to the implantation.

[0239] In an embodiment, the created trenches 14, 15, 16 exhibit trench sidewalls that are substantially parallel to the vertical direction Z, and the implantation (see step 26) is performed along the vertical direction Z and, for example, not angled or tilted with respect to the vertical direction Z. Thus, the implantation may be a 0° implantation. Alternatively, an angled implantation may be performed aligned along the direction of the trenches 14, 15, 16 to minimize implantation of the sidewalls.

[0240] Furthermore, as already explained above, during the implantation, the exposed trench sidewalls can be covered with the protective layer 300. Since in the example the implanted ions are accelerated in the vertical direction Z and since the exposed trench sidewalls are covered with the protective layer 300, the implanted ions do not penetrate the trench sidewalls, or respectively only an insignificant portion thereof, at least within the respective upper 80% of the exposed trench.

[0241] However, surface sections 10-1 between exposed trenches may also be subjected to implantation and thus implanted regions 1029 may be formed below such surface sections 10-1. However, when channel regions 102 of the second conductivity type may be created in these regions of the semiconductor body 10, such implanted regions 1029 are not necessarily removed.

[0242] The implantation may further be performed in such a way that an average penetration depth of the implanted ions (eg an average distance traversed by the ions after having entered the semiconductor body 10 at the trench bottom of the exposed trenches) may be in the range of 10 nm to 2000 nm.

[0243] In step 26, the mask arrangement 30 and the protective layer 300 may be removed. This may include performing one or more etching process steps, for example removing the mask material 302 by means of a first etching process step and removing the protective layer 300 by means of a second etching process step.

[0244] In step 28, the semiconductor body 10 is subjected to a temperature annealing step, thereby causing the plurality of implanted regions 1059 to extend parallel to the first lateral direction X so as to overlap and form a barrier region 105 of the second conductivity type adjacent to the bottom of the exposed trenches 14, 15, 16, as in Fig.21 and 24 For example, the implant region 1059 may diffuse out so as to unify the barrier region 105 and form an adjacent barrier region 105 .

[0245] According to an embodiment, forming the barrier region 105 is implemented as a self-aligned process with respect to the depth of the previously formed trenches. For example, variations similar to the final variation of the depth of some of the exposed trenches 14, 15, 16 may also exist within the barrier region 105. The position of the barrier region 105 with respect to the vertical direction Z may essentially be defined by the trenches 14, 15, 16. Because the correct relative position of the barrier region 105 with respect to the trenches 14, 15, 16 (in terms of the vertical direction Z) may be desirable so that the barrier region 105 can achieve its designated function, the above process may be considered a self-aligned process. Therefore, according to an embodiment, the lateral structure of the barrier region 105 may be adjusted according to the lateral structure of the mask arrangement 30, and the position and extension of the barrier region 105 with respect to the vertical direction may be defined by the previously formed trenches 14, 15, 16.

[0246] The temperature annealing step 28 may be performed so that the barrier region 105 exhibits a temperature of 1e14 cm -3 to 4e17 cm -3 The electrically active dopant concentration may be present in an extension of at least 0.1 μm or at least 0.5 μm along the vertical direction Z. Figure 5 For further aspects of its variation along the vertical direction Z) and / or its spatial scale, reference is made to the above.

[0247] For example, the barrier region 105 is formed such that it is spatially confined by the drift region 100 in and with respect to the vertical direction Z. For example, thereby, both the upper pn junction 1051 and the lower pn junction 1052 as explained above are formed.

[0248] Still refer to Fig.21 and 24 In an embodiment, a temperature annealing step 28 may be performed such that the barrier region 105 extends laterally at least until it reaches the bottom and / or sidewalls of the trench covered by the mask arrangement 30 during the implantation (see step 24 ).

[0249] For example, according to Fig.21 In the embodiment shown in FIG. 1 , a temperature annealing step 28 may be performed to allow the barrier region 105 to extend laterally or even beyond the bottom of the trench, as described in relation to step 28. Fig.21 . Thus, the created barrier region 105 may completely laterally overlap the trench covered by the mask arrangement 30 during the implantation (i.e., the trench that was not subjected to implantation during which the implantation region 1059 was created). The barrier region 105 may even extend beyond this trench and slightly into the mesa region formed by the two adjacent trenches that were not subjected to implantation due to the mask coverage. For example, in order to achieve such a controlled diffusion, either the full process thermal budget is adjusted accordingly after the implantation 24, or the trench layout is modified to align the position of the last exposed trench with the adjacent trench if the thermal budget is constrained by other requirements, so that the resulting diffusion provides a barrier region 105 with a desired profile.

[0250] According to another embodiment, for example, Fig.24 1054, the lateral diffusion of the implanted region 1059 may be blocked by the deeper trench; therefore, the barrier region 105 "only" extends until it reaches the sidewall 164 of the deeper trench. Thus, the barrier region 105 neither reaches the trenches between the deeper trenches nor the mesas 18 formed between the deeper trenches and the trenches between the deeper trenches; more precisely, the barrier region 105 exhibits a through channel 1053 in this region.

[0251] about Fig. 22 , some further exemplary and optional steps of method 2 will be presented. As already explained introductory, method 2 can be used to form Figure 1-19 In one or more of the embodiments of the power semiconductor device 1 presented above. For example, the method 2 is implemented to form a power semiconductor device 1 having a plurality of IGBT cells 1 - 1 , in Fig. 22, a section of a vertical cross section thereof is schematically and exemplarily illustrated in . In an embodiment, the method 2 thus comprises forming trenches 14, 15, 16 in at least one control trench 14 with a control electrode 141, in at least one dummy trench 15 with a dummy electrode 151, and in at least one source trench 16 with a source electrode 161. The method 2 may further comprise forming at least one active mesa 18 arranged adjacent to at least one control trench 14 in the semiconductor body 10 and between the trenches 14, 15, 16 (wherein the control electrode 141 is configured to receive a control signal and control a load current in the active mesa 18); and forming at least one passive mesa 19 arranged adjacent to at least one dummy trench 15.

[0252] The illustrated IGBT cell 1 - 1 exhibits the contact scheme “oDoSoSkGkSoSoD” explained above. In other embodiments, different contact schemes may be employed.

[0253] For example, after the barrier region 105 has been created, the trenches 14, 15, 16 may be provided with respective trench insulators (see reference numerals 142, 152, 162 in other drawings) and respective trench electrodes 141, 151, 161. Furthermore, within the mesas 18 and 19, a channel region 102 may be created, and within the first mesa 18, a source region 101 may be created which is electrically connected to the first load terminal 11 by means of a first contact plug 113. According to an embodiment, before the trenches 14, 15, 16 are provided with the trench insulators 142, 152, 162 and the trench electrodes 141, 151, 161, it is possible to carry out a further sacrificial thermal oxidation treatment step, for example for the purpose of trench corner rounding.

[0254] exist Fig. 22 In FIG. 1 , the dotted area 402 indicates the area where the mask material 302 was present during the implantation and the cross-hatched area indicates the implantation area 1059 created during the implantation step 24. In the example, the trenches designated as at least one control trench 14 and the trenches 16 adjacent thereto are covered by the mask arrangement 30. The barrier region 105 is created such that the barrier region 105 extends laterally until it almost reaches the bottom 165 and / or the sidewalls 164 of the adjacent trench 16 covered by the mask arrangement 30 during the implantation 24. This adjacent trench may be designated as a source trench 16. Fig. 22 Not shown in the figure (but in Fig.21 ), the temperature annealing step 28 may be performed such that the barrier region 105 extends laterally even beyond the trench bottom 165 into at least one active mesa 18.

[0255] Depending on the lateral structure of the mask arrangement 30, the barrier region 105 can exhibit a plurality of through channels 1053, which has been explained above. For example, the barrier region 105 extends into the active mesa 18 but is separated from the control trench 14 by means of the drift region 100. In an embodiment, the through channels 1053 are designed by means of the mask arrangement 30 so that at least some of the control trenches 14 are separated from the barrier region 105 by means of the drift region 100.

[0256] In summary, the creation of the barrier region 105 can occur according to one or more of the provisions of the design rules explained above. One or more provisions of the design rules can be met by correspondingly structuring the mask material 302 laterally, by correspondingly forming the trenches 14, 15, 16 and / or by correspondingly performing an implantation step and / or by correspondingly performing a temperature annealing step.

[0257] For example, the provided semiconductor body 10 comprises the active cell region 1-2 having the drift region 100, and trenches 14, 15, 16 are formed at least in the active cell region 1-2. The provided semiconductor body 10 may further comprise the edge termination region 1-3 having a well region 109 of the second conductivity type extending along the vertical direction Z at least as deep as the barrier region 105. The provided semiconductor body 10 may further comprise the transition region 1-5 arranged between the active cell region 1-2 and the edge termination region 1-3. As explained above, the transition region 1-5 may have a width W of at least 1 μm along the lateral direction from the active cell region 1-2 towards the edge termination region 1-3.

[0258] In an embodiment of method 2, trenches or sections thereof formed in transition region 1-3 are covered by mask arrangement 30. In other words, according to an embodiment, barrier region 105 does not extend into transition region 1-3. For example, a laterally structured barrier region 105 is created exclusively in active cell region 1-2.

[0259] This is just one example of how one or more of the provisions of the design rules may be met. Other examples are possible that consider one or more alternative or additional provisions of the design rules.

[0260] Fig.23 The embodiments shown schematically and exemplarily in the drawings are based on Fig.21 The method is exemplarily illustrated in FIG. ; therefore, the same reference numerals designate the same method steps. Fig.23In the variant illustrated in FIG. 2 , the step of providing a protective layer 300 (step 21 ) is performed so that the protective layer 300 exhibits a relatively large thickness, for example a thickness of about 100 nm. For example, a protective layer 300 is provided at all trenches 14 , 15 , 16 . This protective layer 300 may be a thick sacrificial oxide. In step 211 , an etch-back processing step is performed in order to at least partially remove the protective layer 300 at the surface section 10 - 1 and at the trench bottoms 145 , 155 , 165 . Thereafter, in steps 22 and 24 , a mask arrangement 30 is provided and, for example, the protective layer 300 is provided as described above with reference to FIG. 2 . Fig.21 However, unlike Fig.21 Compared to a variant of , due to the etch-back processing step 211 , the implantation can be performed with a reduced implantation energy. The etch-back process can be an anisotropic reactive ion etching (RIE) etching process. Furthermore, due to the relatively thick protection layer 300 still present at the trench sidewalls during the implantation, it can be ensured that no implanted ions / particles pass through the trench sidewalls. For example, in this way, it can be ensured that the barrier region 105 remains separated from the channel region 102 by means of a portion of the drift region 100; for example, no p-type connection exists between the channel region 102 and the barrier region 105. In a variant, the providing of the mask arrangement 30 in step 22 is performed before the etch-back processing step 211 takes place. For example, after the mask arrangement 30 has been provided (i.e. in case a relatively thick protective layer 300 is still present at the surface section 10-1 and the trench bottom 145, 155, 165), the etch-back processing step 211 is carried out in order to at least partially remove the protective layer 300 at the surface section 10-1 and the trench bottom 145, 155, 165 in those areas exposed (not covered) by the mask arrangement 30. The thicker protective layer 300 below the mask material 302 can facilitate the removal of the mask arrangement 30. In a variant, if the thickness of the protective layer 300 is sufficient to act as a mask during the dopant material providing step 24 of the trench (the trench is masked during the etch-back processing step 211), the mask arrangement 30 can be removed before the dopant material providing step 24 (e.g. the implantation step). Regardless of the selection of the order, for example in step 261, the mask arrangement 30 is removed and thereafter the remaining part of the protective layer 300 is removed in step 262. Then, a temperature annealing step 28 may be performed and subsequently a trench forming step may be performed thereto.

[0261] refer to Fig.25 In a variant, instead of or in addition to providing the protective layer 300, the method 2 may comprise forming a sacrificial planarization structure 309 in the trenches 14, 15, 16 and on top thereof in a step 212, wherein a mask arrangement 30 is provided on top of the sacrificial planarization structure 309. For example, in order to form the sacrificial planarization structure 309, a mask arrangement 30 may be used, such as an oxide (e.g. SiO 2) material or amorphous carbon. The formation of the sacrificial planarization structure 309 can be implemented so that the lower part of the grooves 14, 15, 16 remains empty and only the groove opening is closed. For example, this can be achieved by maximizing the deposition rate at the corner of the upper groove so that the groove opening is closed. For example, the deposition is implemented as a highly non-conformal and / or line-of-sight process. In an embodiment, deposition materials are implemented in two directions for forming the sacrificial planarization structure 309; thereby, the illustrated crack 3091 can be formed. For example, a mask arrangement 30 is formed on the top of the sacrificial planarization structure 309 and is thereafter constructed. Then, at least the exposed portion of the sacrificial planarization structure 309 in the top portion can be removed. Because the lower part of the grooves 14, 15, 16 remains empty, it is easy to implement the removal of the material of the sacrificial planarization structure 309. Thereafter, the implantation 24 can be implemented, for example, without previously providing further groove sidewall protection, and the mask arrangement 30 and the remaining portion of the sacrificial planarization structure 309 can be removed thereafter.

[0262] Now refer to it again Fig.21 In an alternative embodiment, after the trenches 14, 15, 16 have been formed in step 20 and a protective layer 300 is optionally provided at least at the sidewalls of the trenches, polysilicon or a doped oxide source (e.g. boron-doped SiO 2 or Al-doped SiO 2 ) or another dopant source of the second conductivity type. For example, depositing the dopant source (e.g., a doped oxide) may include a spin coating process or a CVD process, such as a super conformal CVD process. The deposited dopant source may then be constructed, for example, by means of photolithography and etching (e.g., wet etching, dry etching, or a combination of wet and dry etching) processing steps. For example, the dopant source is thereby removed from one or more of the trenches 14, 15, 16. Alternatively, a corresponding mask may be provided before or simultaneously with the deposition of the dopant source. Once the deposited dopant source is present only in the selected trenches 14, 15, 16 (which may be considered to correspond to the exposed trenches subjected to implantation during step 24), a diffusion processing step (e.g., a hot furnace processing step) may be performed to diffuse the deposited dopant source from the trenches into the semiconductor body 10, thereby forming a region that may ultimately be uniformly doped so as to form the barrier region 105. Thereafter, according to an embodiment, remaining dopant sources (eg polysilicon or doped oxide) may be removed from all trenches and a regular trench formation process may be performed to form, for example, control trenches 14 , source trenches 16 and dummy trenches 15 .

[0263] According to one or more embodiments described herein, an IGBT having a plurality of IGBT cells configured according to an MPT structure is proposed, wherein each IGBT cell has a control trench for controlling a load current in at least one active mesa, and at least one dummy trench having a trench electrode (which is also electrically connected to a control terminal and arranged adjacent to at least one passive mesa), wherein the bottoms of the active mesa and the dummy trench are connected to each other by means of a lateral structure and an electrically floating p-doped barrier region. According to an embodiment, due to such a connection, during the switching operation of the IGBT, the voltage swing on the control terminal can be reduced. This can allow, for example, improved control of the dV / dt of the gate signal during the switching of the IGBT. In addition, in an embodiment, the lateral structure of the p barrier region can avoid a sudden jump in the transfer and output characteristics of the IGBT. For example, at a current below 10% or even 1% of the rated current, the load current is carried by an active mesa that is not covered by the p barrier region (for example, there is a barrier channel there). For larger currents, the upper pn junction formed by the transition between the barrier region and the drift region above the barrier region is in forward bias mode with respect to electron current and all active mesas within the active cell region carry the load current whether they are covered by the p barrier region or not.

[0264] In the above, embodiments of power semiconductor devices and corresponding processing methods are explained. For example, these power semiconductor devices are based on silicon (Si). Therefore, single-crystal semiconductor regions or layers (such as semiconductor body 10 and its regions / areas 100, 101, 102, 105, 107, 108, 109) can be single-crystal Si regions or Si layers. In other embodiments, polycrystalline or amorphous silicon can be used.

[0265] However, it should be understood that the semiconductor body 10 and its doped regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. To give a few examples, examples of such materials include the following without limitation: basic semiconductor materials such as silicon (Si) or germanium (Ge), IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe). The above semiconductor materials are also referred to as "homojunction semiconductor materials". A heterojunction semiconductor material is formed when two different semiconductor materials are combined. Examples of heterojunction semiconductor materials include, without limitation, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs, and GaN materials are currently used.

[0266] Spatially relative terms such as "below," "below," "below," "above," "on," etc. are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the corresponding device in addition to orientations different from those depicted in the various figures. Further, terms such as "first," "second," etc. are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout this specification, similar terms refer to similar elements.

[0267] As used herein, the terms “having,” “containing,” “including,” “comprising,” “exhibiting,” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

[0268] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A method (2) for processing a power semiconductor device (1), comprising: - providing a semiconductor body (10) having a drift region (100) of a first conductivity type; - creating (20) a plurality of trenches (14, 15, 16), wherein the trenches (14, 15, 16) extend into the semiconductor body (10) along a vertical direction (Z) and are arranged adjacent to each other along a first lateral direction (X); - providing (22) a mask arrangement (30) at the semiconductor body (10), wherein the mask arrangement (30) has a lateral structure (301) according to which some of the trenches (14, 15, 16) are exposed and at least one of the trenches (14, 15, 16) is covered by the mask arrangement (30) along a first lateral direction; - subjecting the semiconductor body (10) and the mask arrangement (30) to (24) a dopant material providing step, thereby creating a plurality of doped regions (1059) of a second conductivity type complementary to the first conductivity type below the bottoms of the exposed trenches (14, 15, 16); - removing (26) the mask arrangement (30); - subjecting the semiconductor body (10) to a temperature annealing step (28), thereby causing a plurality of doped regions (1059) to extend parallel to the first lateral direction (X) so as to overlap and form a barrier region (105) of the second conductivity type adjacent to the bottom of the exposed trenches (14, 15, 16); The temperature annealing step (28) is performed such that the barrier region (105) extends laterally beyond the trench covered by the mask arrangement (30) during the dopant material providing step (24).

2. The method (2) of claim 1, wherein the dopant material providing step (24) comprises an implantation processing step.

3. The method (2) according to claim 1, wherein the temperature annealing step (28) is performed so that the barrier region (105) exhibits a temperature of 1e14 cm -3 to 4e17 cm -3 An electrically active dopant concentration within a range of , wherein the electrically active dopant concentration exists within an extension of at least 0.1 μm along the vertical direction (Z).

4. The method (2) according to one of the preceding claims 1 to 3, wherein the barrier region (105) is spatially delimited in the vertical direction (Z) by the drift region (100).

5. A method (2) according to one of the preceding claims 1 to 3, wherein the creation of the grooves (14, 15, 16) is implemented so that for at least a first 80% portion of the total extension of the corresponding groove along the vertical direction (Z), the corresponding groove width along the first lateral direction (X) remains within the range of at least 95% of the groove width existing at the groove opening of the corresponding groove.

6. Method (2) according to one of the preceding claims 1 to 3, wherein each of the created trenches (14, 15, 16) exhibits trench sidewalls substantially parallel to a vertical direction (Z) and wherein the implantation (26) is performed along the vertical direction (Z).

7. The method (2) according to one of the preceding claims 1 to 3, further comprising providing a protective layer (300) at least at the trench sidewalls, and wherein the dopant material providing step (24) is performed when the protective layer (300) is present at the exposed trench sidewalls.

8. A method (2) according to claim 7, wherein a protective layer (300) is formed at all trenches (14, 15, 16), and wherein before or after providing the mask arrangement (30), an etch-back processing step is performed in order to at least partially remove the protective layer (300) at the surface sections (10-1) between the trenches (14, 15, 16) and at the trench bottom (145, 155, 165) while maintaining the protective layer (300) at the trench sidewalls (144, 154, 164).

9. The method (2) according to one of the preceding claims 1 to 3, wherein providing (22) the mask arrangement (30) comprises performing a photolithographic processing step.

10. The method (2) according to one of the preceding claims 1 to 3, wherein providing (22) a mask arrangement (30) comprises using a stencil mask.

11. The method (2) according to one of the preceding claims 1 to 3, further comprising forming (212) a sacrificial planarization structure (309) within the trenches (14, 15, 16) and on top of the trenches (14, 15, 16), wherein a mask arrangement (30) is provided on top of the sacrificial planarization structure (309).

12. A method (2) according to one of the preceding claims 1 to 3, wherein the grooves (14, 15, 16) are formed according to a first layout having a first pitch, and wherein the lateral structures (301) of the mask arrangement (30) are configured according to a second layout having a second pitch or feature size that is at least twice as large as the first pitch.

13. A method (2) according to one of the preceding claims 1 to 3, wherein the semiconductor body (10) comprises an active cell region (1-2) having a drift region (100), wherein a trench (14, 15, 16) is formed at least in the active cell region (1-2); an edge termination region (1-3), which comprises a well region (109) of a second conductivity type extending along a vertical direction (Z) at least as deep as the barrier region (105); and a transition region (1-5) arranged between the active cell region (1-2) and the edge termination region (1-3), the transition region (1-5) having a width (W) of at least 1 μm along a lateral direction (X, Y) from the active cell region (1-2) towards the edge termination region (1-3); wherein - Its trenches or sections formed in the transition region are covered by a mask arrangement (30).

14. The method (2) according to one of the preceding claims 1 to 3, further comprising: - forming grooves (14, 15, 16) in: - at least one control trench (14) having a control electrode (141); and - at least one dummy trench (15) having a dummy electrode (151); - forming in the semiconductor body (10) and between the trenches (14, 15, 16): - at least one active mesa (18) arranged adjacent to at least one control trench (14), wherein the control electrode (141) is configured to receive a control signal and control a load current in the active mesa (18); and - at least one passive mesa (19) arranged adjacent to at least one dummy trench (15); The barrier region (105) is created so as to laterally overlap at least one passive mesa (19).

15. A method (2) according to claim 14, wherein the trenches of at least one control trench (14) and the trenches adjacent thereto (16) are covered by the mask arrangement (30) along a first lateral direction, and wherein the barrier region (105) extends at least laterally until it reaches the bottom (165) and / or sidewalls (164) of the adjacent trench (16) covered by the mask arrangement (30) during the dopant material providing step (24).

16. The method (2) according to claim 15, wherein the temperature annealing step (28) is performed such that the barrier region (105) extends laterally beyond the trench bottom (165) into at least one active mesa (18).

17. The method (2) according to claim 16, wherein the barrier region (105) is separated from the control trench (14) by means of a drift region (100).

18. A method (2) according to claim 15, wherein the adjacent trench (16) is formed with a larger total extension along the vertical direction (Z) than the control trench (14), wherein a lateral extension of the barrier region (105) is prevented by the adjacent trench (16) during the temperature annealing step (28).

19. A method (2) of processing a power semiconductor device (1), wherein the power semiconductor device (1) comprises a first load terminal (11) and a second load terminal (12), the power semiconductor device (1) being configured to conduct a load current between the terminals (11, 12) along a vertical direction (Z) and further comprising: An active cell region (1-2) having a drift region (100) of a first conductivity type; An edge termination region (1-3) having a well region (109) of a second conductivity type; a plurality of IGBT cells (1-1) arranged in an active cell region (1-2), wherein each of the IGBT cells (1-1) comprises a plurality of trenches extending into a drift region (100) along a vertical direction (Z) and laterally confining a plurality of mesas, wherein the plurality of trenches comprises: at least one control trench (14) having a control electrode (141); at least one dummy trench (15) having a dummy electrode (151) electrically coupled to the control electrode (141); at least one source trench (16) having a source electrode (161) electrically connected to a first load terminal (11), and wherein the plurality of mesas comprises at least one active mesa (18) arranged between the at least one control trench (14) and the at least one source trench (16); and at least one passive mesa (19) arranged adjacent to the at least one dummy trench (14), wherein the method (2) comprises: -Providing (2200) an electrically floating barrier region (105) of a second conductivity type, wherein at least the bottom (155) of the dummy trench (15) and the bottom (165) of the source trench (16) both extend at least partially into the electrically floating barrier region (105), and wherein a portion of the drift region (100) located between the electrically floating barrier region (105) and the well region (109) in a lateral direction (X, Y) has a lateral extension of at least 1 μm in said lateral direction.

20. A power semiconductor device (1) comprising a first load terminal (11) and a second load terminal (12), the power semiconductor device (1) being configured to conduct a load current between the terminals (11, 12) along a vertical direction (Z) and comprising: - a drift region (100) of a first conductivity type; - a plurality of IGBT cells (1-1), wherein each of the IGBT cells (1-1) comprises a plurality of trenches (14, 15, 16) extending into the drift region (100) along a vertical direction (Z) and laterally delimiting at least one active mesa (18), the at least one active mesa (18) comprising an upper section (100-1) of the drift region (100); - an electrically floating barrier region (105) of a second conductivity type, which is spatially confined in a vertical direction (Z) by the drift region (100); in: - the total volume of all active mesas (18) is divided into a first portion which does not laterally overlap the barrier region (105) and a second portion which laterally overlaps the barrier region (105); - the first share is configured to carry a load current in the range of 0% to 100% of the rated load current for which the power semiconductor device (1) is designed; and If the load current exceeds the rated load current by at least 0.5%, the second share is configured to carry the load current.

21. The power semiconductor device (1) of claim 20, wherein each active mesa (18) is configured to induce an inversion channel within the respective active mesa (18), and wherein all active mesas (18) are configured with the same inversion channel threshold voltage.

22. The power semiconductor device (1) according to one of the preceding claims 20 to 21, wherein: If the load current exceeds 50% of the rated load current, the ratio between a first load current share conducted by a first portion of the active mesas (18) and a second load current share conducted by a second portion of the active mesas (18) is within 10% of the ratio between the first share and the second share.

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