A display panel, a driving method, a driving device and a display device thereof

Abstract

The application discloses a display panel, a driving method, a driving device and a display device. In each data input stage of a charging period, a gate-on signal is loaded on a gate signal line, corresponding data signals are loaded on each source input signal line in sequence, and opening control signals are loaded on each control signal line in sequence, so that the sub-pixel can be charged in a cycle mode. In adjacent two data input stages, the sequence of loading the opening control signals on at least part of the control signal lines is different, and the interval between the opening control signals loaded on the same control signal line is at least one time length of the opening control signal. In the charging period, the number of the opening control signals of the same loading sequence corresponding to each control signal line is the same, so that the voltage variation amount sum of each color sub-pixel in the charging period is equal, and the display uniformity is improved.

Description

[0001] The present disclosure claims the priority of Chinese patent publication No. 201810711913.2, published on June 29, 2018, entitled "A display panel, a driving method thereof, a driving device and a display device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel, a driving method thereof, a driving device and a display device. BACKGROUND

[0003] With the development of display technology, the full screen has a large screen ratio and an ultra-narrow frame, and can greatly improve the visual effect of the viewer compared with the ordinary display, so it has received extensive attention. At present, in the display device such as mobile phone using full screen, in order to realize the functions of self-timer and call, the front camera, earpiece and the like are usually arranged on the front surface of the display device. In order to realize the full screen display, the display panel shown in the prior art has a hollow structure 110 for arranging the front camera, earpiece and the like. Figure 1 As shown in the plan structure diagram of the display panel, the hollow structure 110 for arranging the front camera, earpiece and the like is generally arranged in the display panel. However, due to the existence of the hollow structure 110, in order to make each row of pixels input the data signal, the data signal line in the area 1 where the hollow structure 110 is located needs to be arranged around the hollow structure 110. This results in that the distance between the data signal lines around the hollow structure 110 is small, which causes large signal coupling, and further causes the display panel to have the problem of uneven display. SUMMARY

[0004] The present application provides a display panel, a driving method thereof, a driving device and a display device to solve the problem of uneven display in the prior art.

[0005] Therefore, the present application provides a driving method of a display panel, the display panel comprising: an array substrate; the array substrate comprising: a hollow structure, a display area, a first non-display area and a second non-display area, the first non-display area surrounding the hollow structure, the display area surrounding the first non-display area, and the second non-display area surrounding the display area;

[0006] The display area comprises: a plurality of pixel units, a plurality of gate signal lines, and a plurality of data signal lines; wherein each of the pixel units comprises M sub-pixels of different colors, M is an integer greater than or equal to 3; one column of sub-pixels corresponds to one data signal line; the plurality of data signal lines comprises a plurality of first data signal lines passing through the first non-display area, each of the first data signal lines comprises a first sub-data signal line located in the display area and a second sub-data signal line located in the first non-display area, and the first sub-data signal line and the second sub-data signal line of the same first data signal line are electrically connected;

[0007] The second non-display area comprises: a plurality of source input signal lines, a plurality of multiplexers, and a plurality of control signal lines connected with all the multiplexers ; wherein N is the number of adjacent pixel units corresponding to adjacent two multiplexers; and one source input signal line is electrically connected with N data signal lines through one multiplexer; N is an even integer greater than or equal to 2;

[0008] The driving method comprises:

[0009] In each data input stage of a charging period, a gate-on signal is loaded to the gate signal line, a corresponding data signal is loaded to each source input signal line in turn, and an on control signal is loaded to each control signal line in turn, so as to charge the sub-pixels; wherein the charging period comprises adjacent Y data input stages, M is less than or equal to Y which is an integer, and Y is less than or equal to 3K which is an integer, and K is an integer greater than or equal to 1; in adjacent two data input stages, the order of at least part of the control signal lines loaded with the on control signal is different, and the on control signals loaded on the same control signal line are separated by at least one time length of the on control signal; and for the on control signals of the same loading order in each data input stage, the number of the on control signals of the same loading order corresponding to each control signal line in the charging period is the same;

[0010] The data input stage is a time period in which the gate-on signal is loaded to one gate signal line in the display panel; or the data input stage is a time period of one frame scanning in which the gate-on signal is loaded to each gate signal line in the display panel in turn.

[0011] Correspondingly, the embodiment of the present application also provides a driving device of a display panel, which is used to execute the steps of the driving method of the display panel provided by the embodiment of the present application.

[0012] Correspondingly, the embodiment of the present application also provides a display panel, which is driven by the driving method provided by the embodiment of the present application.

[0013] ​Correspondingly, the embodiment of the present application further provides a display device, comprising the driving device and the display panel provided by the embodiment of the present application.

[0014] The present application has the following advantages:

[0015] The display panel, the driving method thereof, the driving device and the display device provided by the embodiment of the present application can charge the sub-pixels in a periodic cycle manner by loading the gate-on signal on the gate signal line, loading the corresponding data signal on each source input signal line in turn, and loading the on-control signal on each control signal line in turn in each data input stage of a charging period. In addition, the order of loading the on-control signal on at least part of the control signal lines is different in the adjacent two data input stages, and the on-control signals loaded on the same control signal line are separated by at least one time length of the on-control signal, so that the on-control signals loaded on different control signal lines in the data input stage can be adjusted in sequence, and the on-control signals on the same control signal line are not adjacent. In addition, the number of the on-control signals with the same loading order corresponding to each control signal line is the same in the charging period, so that the voltage variation amount sum of each color sub-pixel in a charging period is equal, that is, the coupling interference received by each color sub-pixel is equal, thereby improving the display uniformity. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 FIG. 1 is a structural schematic diagram of a display panel in the prior art;

[0017] Figure 2 FIG. 2 is a specific structural schematic diagram of a display panel in the related art;

[0018] Figure 3 FIG. 3 is a circuit timing diagram of the display panel shown in FIG. 1; Figure 2

[0019] Figure 4 FIG. 4 is a specific structural schematic diagram of a display panel provided by the embodiment of the present application;

[0020] Figure 5 FIG. 5 is another specific structural schematic diagram of a display panel provided by the embodiment of the present application;

[0021] Figure 6 FIG. 6 is a circuit timing diagram of the display panel provided by the embodiment of the present application;

[0022] Figure 7 FIG. 7 is another circuit timing diagram of the display panel provided by the embodiment of the present application;

[0023] Figure 8 FIG. 8 is a specific structural schematic diagram of a display panel provided by the embodiment of the present application; ​

[0024] Figure 9 The third circuit timing diagram of the display panel provided in the embodiment of the present invention;

[0025] Figure 10 This is the fourth schematic diagram of the specific structure of the display panel provided in the embodiment of the present invention;

[0026] Figure 11 The fourth circuit timing diagram of the display panel provided in the embodiment of the present invention;

[0027] Figure 12 Fifth schematic diagram of the specific structure of the display panel provided in the embodiment of the present invention;

[0028] Figure 13 The fifth circuit timing diagram of the display panel provided in the embodiment of the present invention;

[0029] Figure 14 The sixth circuit timing diagram of the display panel provided in the embodiment of the present invention;

[0030] Figure 15 Seventh of the circuit timing diagrams for the display panel provided in the embodiments of the present invention;

[0031] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0032] like Figure 2 As shown, the display panel may include: a cutout structure 110, multiple data signal lines Data, and multiple gate signal lines G_e (1≤e≤E and are integers, where E is the total number of gate signal lines in the display panel); Figure 2For example, E=7), a plurality of pixel units PX, a plurality of multiplexers 200, control signal lines CK_1-CK_3, source input signal lines S_1-S_2. Among them, the pixel unit PX can include: a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B. The data signal line Data is arranged around the hollow structure 110, and one column of sub-pixels corresponds to one data signal line Data. The source input signal lines S_1-S_2 are respectively connected with the three data signal lines Data through one multiplexer 200. One multiplexer 200 can include: transistors M0_1-M0_3. Each transistor is connected with one data signal line Data. The data signal line Data connected with the transistor M0_1 corresponds to the red sub-pixel R, and the gate of all transistors M0_1 is connected with the control signal line CK_1. The data signal line Data connected with the transistor M0_2 corresponds to the green sub-pixel G, and the gate of all transistors M0_2 is connected with the control signal line CK_2. The data signal line Data connected with the transistor M_3 corresponds to the blue sub-pixel B, and the gate of all transistors M_3 is connected with the control signal line CK_3. A general sub-pixel can include: a pixel electrode and a thin film transistor connected between the pixel electrode and the data signal line, and the gate of the thin film transistor is connected with a gate signal line.

[0033] Figure 2 The driving timing diagram shown can be as shown in Figure 3 , in Figure 3 , g_1 represents the signal loaded on the gate signal line G_1, ck_1-ck_3 are respectively the signals loaded on the control signal lines CK_1-CK_3, and s_1 is the data signal loaded on the source input signal line S_1. And, the high level signal in g_1 is the gate on signal, and the low level signal in g_1 is the gate off signal.

[0034] From Figure 3 , it can be seen that, due to the action of the gate on signal in g_1, the thin film transistors in the first row of sub-pixels are all turned on. When the gate on signal is loaded on the gate signal line G_1, the on control signal (i.e. high level signal) of ck_1 is loaded on the control signal line CK_1, the transistor M0_1 is controlled to be turned on, so as to provide the data signal loaded on the source input signal line S_1 to the pixel electrode in the first row of red sub-pixels R, so as to make the red sub-pixel R charge the voltage V1. At this time, the off control signal (i.e. low level signal) of ck_2 is loaded on the control signal line CK_2, the transistor M0_2 is controlled to be turned off. And, the off control signal (i.e. low level signal) of ck_3 is loaded on the control signal line CK_3, the transistor M0_3 is controlled to be turned off.

[0035] Afterwards, the on control signal (i.e. high level signal) in ck_2 is loaded to the control signal line CK_2, the transistor M0_2 is turned on to provide the data signal loaded on the source input signal line S_1 to the first row of green sub-pixels G, so that the green sub-pixels G are charged with the voltage V1. And since the off control signal (i.e. low level signal) in ck_1 is loaded to the control signal line CK_1, the transistor M0_1 is turned off, however, the thin film transistor in the red sub-pixels R in the first row is still in the on state due to the effect of the gate on signal in g_1. Since the data signal lines are arranged around the hollow structure 110, the spacing between the data signal lines is small, thus when the green sub-pixels G are charged, the voltage charged in the red sub-pixels R changes due to the coupling effect between the data signal lines, and the changed voltage is V2. And the off control signal (i.e. low level signal) in ck_3 is loaded to the control signal line CK_3, the transistor M0_3 is turned off.

[0036] Afterwards, the on control signal (i.e. high level signal) in ck_3 is loaded to the control signal line CK_3, the transistor M0_3 is turned on to provide the data signal loaded on the source input signal line S_1 to the first row of blue sub-pixels B, so that the blue sub-pixels B are charged with the voltage V1. And since the off control signal (i.e. low level signal) in ck_1 is loaded to the control signal line CK_1, the transistor M0_1 is turned off, and the off control signal (i.e. low level signal) in ck_2 is loaded to the control signal line CK_2, the transistor M0_2 is turned off, however, the thin film transistor in the red sub-pixels R and the thin film transistor in the green sub-pixels G in the first row are still in the on state due to the effect of the gate on signal in g_1. Due to the coupling effect between the data signal lines, when the blue sub-pixels B are charged, the voltages charged in the red sub-pixels R and the green sub-pixels G also change, so that the changed voltage of the red sub-pixels R is V3, and the changed voltage of the green sub-pixels G is V4. Thus the voltage variation of the red sub-pixels R, i.e. the difference between the changed voltage V3 and the initial charged voltage V1: V3-V1 is the largest, the voltage variation of the green sub-pixels G V4-V1 is the second, and the voltage variation of the blue sub-pixels B is almost zero, thus due to the different voltage variations, color cast occurs, thus the display is not uniform.

[0037] Afterwards, the off control signal in g_1 is loaded to the gate of the thin film transistor in each sub-pixel in the first row.

[0038] The driving method of the display panel can improve the display uniformity.

[0039] The present invention will now be described in detail with reference to specific embodiments. It should be noted that these embodiments are for better explanation of the present invention and do not limit the scope of the invention.

[0040] Example 1

[0041] In specific implementation, such as Figure 4 As shown, the display panel may include: an array substrate 100; the array substrate 100 may include: a cutout structure 110, a display area AA, a first non-display area BB_1 and a second non-display area BB_2, the first non-display area BB_1 surrounds the cutout structure 110, the display area AA surrounds the first non-display area BB_1, and the second non-display area BB_2 surrounds the display area AA. The display area AA may include: multiple pixel units PX, multiple gate signal lines G_e, and multiple data signal lines; wherein, each pixel unit PX may include M sub-pixels of different colors, M≥3 and is an integer. One column of sub-pixels corresponds to one data signal line; the multiple data signal lines may include multiple first data signal lines D1 passing through the first non-display area BB_1, each first data signal line D1 may include a first sub-data signal line located in the display area AA and a second sub-data signal line located in the first non-display area BB_1, and the first sub-data signal line and the second sub-data signal line of the same first data signal line D1 are electrically connected. The second non-display area BB_2 may include: multiple source input signal lines S_i (1≤i≤I and are integers, where I is the total number of source input signal lines in the display panel); where Figure 2 Taking I=4 as an example), multiple multiplexers 200, and connections to all multiplexers 200. One control signal line CK_j( (and is an integer); where N is the number of adjacent pixel units PX corresponding to two adjacent multiplexers 200; and a source input signal line S_i passes through a multiplexer 200 and is connected to... A data signal line is electrically connected; N ≥ 2 and is an even number. Furthermore, when an enable control signal is applied to a control signal line CK_j, the multiplexer 200 can be turned on, so that the multiplexer 200 provides the data signal applied to its connected source input signal line to the connected data signal line.

[0042] The driving method provided in this embodiment of the invention may include:

[0043] In each data input stage of a charging cycle, a gate enable signal is applied to the gate signal line, a corresponding data signal is sequentially applied to each source input signal line, and an enable control signal is sequentially applied to each control signal line to charge the sub-pixel. The charging cycle may include Y adjacent data input stages, where M ≤ Y ≤ 3K and Y is an integer, and K ≥ 1 and K is an integer. In two adjacent data input stages, at least some control signal lines are applied with enable control signals in a different order, and the enable control signals applied to the same control signal line are spaced apart by at least one enable control signal duration. Furthermore, for enable control signals of the same loading order in each data input stage, the number of enable control signals of the same loading order corresponding to each control signal line is the same in the charging cycle. Because the enable control signals are applied sequentially to each control signal line, the order in which the enable control signals are applied to each control signal line within a data input stage is sequential. For example, combining... Figure 4 As shown, in a data input phase, the enable control signal can be applied to control signal line CK_1 first, and this enable control signal can be used as the first enable control signal in the data input phase. Next, the enable control signal is applied to control signal line CK_2, and this enable control signal can be used as the second enable control signal in the data input phase. Finally, the enable control signal is applied to control signal line CK_3, and this enable control signal can be used as the third enable control signal in the data input phase.

[0044] Furthermore, in specific implementation, the driving method provided in this embodiment of the invention can set the data input stage as the time period for loading a gate enable signal onto a gate signal line in the display panel, that is, one data input stage corresponds to one line scan time.

[0045] The driving method provided in this invention charges sub-pixels by loading a gate enable signal onto the gate signal line, sequentially loading corresponding data signals onto each source input signal line, and sequentially loading enable control signals onto each control signal line during each data input phase of a charging cycle. Furthermore, by differentiating the order in which at least some control signal lines are loaded with enable control signals in adjacent data input phases, and by spacing the enable control signals loaded on the same control signal line by at least one enable control signal duration, the order of enable control signals loaded on different control signal lines can be adjusted during the data input phase, ensuring that enable control signals on the same control signal line are not adjacent. Moreover, by ensuring that the number of enable control signals with the same loading order corresponding to each control signal line is the same during the charging cycle, the total voltage change of each color sub-pixel during a charging cycle is equal, meaning that the coupling interference experienced by each color sub-pixel is equal, thereby improving display uniformity.

[0046] It should be noted that, in this embodiment of the invention, taking a color sub-pixel as an example, the total voltage change of the color sub-pixel in one charging cycle is obtained by adding the voltage change of the color sub-pixel in each data input stage.

[0047] In specific implementations, the display panel may also include a substrate on which various data signal lines and gate signal lines are disposed. This substrate can be a glass substrate, a flexible substrate, a silicon substrate, etc., and is not limited thereto. When the display panel is applied to a display device, devices such as cameras and earpieces are generally also disposed there. Therefore, in order to dispose of devices such as cameras and earpieces, such as… Figure 4 As shown, the cutout structure 110 can be a cutout area of ​​the substrate in the display panel. In the actual manufacturing process, the area corresponding to the cutout structure 110 in the substrate is cut to create a cutout area, such as a through-hole, for mounting devices such as cameras and earpieces in the display device. The shape of the through-hole's projection onto the substrate can be a regular shape such as a circle, ellipse, or rectangle, or it can be an irregular shape; no limitation is made here. Alternatively, the substrate can be left uncut, and instead, a film layer or circuitry on the substrate can be removed to create a transparent area corresponding to the cutout structure 110, thus forming the cutout area.

[0048] In specific implementation, in the embodiments of the present invention, such as Figure 4 and Figure 5 As shown, the gate signal line G_e extends along the first direction. The gate signal lines G_2 to G_3 may extend to the cutout structure 110 and then terminate, or they may also be arranged around the cutout structure 110; this is not limited here.

[0049] In a specific implementation, in the embodiment of the present application, as shown in Figure 4 As shown in Figure 5 The first sub-data signal line located in the display area AA extends along the second direction, that is, the first sub-data signal line is a straight line extending along the second direction, and the second sub-data signal line located in the first non-display area BB_1 is a curve arranged around the hollow structure 110. The data signal line can also include a second data signal line D2 located in the display area AA and extending along the second direction, that is, the second data signal line D2 is a straight line extending along the second direction. Moreover, N can be set to 3, and the pixel PX can include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along the first direction. Among them, the first sub-pixel can be a red sub-pixel R, the second sub-pixel can be a green sub-pixel G, and the third sub-pixel can be a blue sub-pixel B. Of course, the first sub-pixel can also be a green sub-pixel G, the second sub-pixel can be a red sub-pixel R, and the third sub-pixel can be a blue sub-pixel B, which needs to be designed and determined according to the actual application environment, and is not limited herein. Among them, the first direction can be the row direction of the pixel PX, and the second direction can be the column direction of the pixel PX; or vice versa, the first direction can be the column direction of the pixel PX, and the second direction can be the row direction of the pixel PX. Moreover, it should be noted that the surrounding in the embodiment of the present application is not arranged around the hollow structure 110 once, but as shown in Figure 4 As shown in Figure 5 The second sub-data signal line in the hollow structure 110 is arranged along the edge.

[0050] The following will be described taking the first sub-pixel as a red sub-pixel R, the second sub-pixel as a green sub-pixel G, and the third sub-pixel as a blue sub-pixel B as an example.

[0051] In a specific implementation, in the embodiment of the present application, as shown in Figure 4 As shown in Figure 5 Each multiplexer 200 can include a plurality of switch transistors Tf_p (p is an integer greater than or equal to 1 and less than or equal to P, P is the total number of switch transistors included in a multiplexer, Figure 4 As shown in Figure 5The switch transistor Tf_p and the data signal line correspond to each other. The gate of each switch transistor Tf_p is electrically connected with a different control signal line CK_j, the first pole of each switch transistor Tf_p is electrically connected with a corresponding source input signal line S_i, and the second pole of each switch transistor Tf_p is electrically connected with a corresponding data signal line. Further, when the control signal line CK_j is loaded with an opening control signal, the switch transistor Tf_p can be controlled to be turned on, and in addition to loading the control signal line CK_j with the opening control signal, the control signal line CK_j also needs to be loaded with a closing control signal to control the switch transistor Tf_p to be turned off. In a specific implementation, the switch transistor Tf_p can be set as an N-type transistor, which can be turned on under the control of a high-level signal and turned off under the control of a low-level signal, so that the level of the opening control signal is high and the level of the closing control signal is low. Alternatively, the switch transistor Tf_p can also be set as a P-type transistor, which can be turned on under the control of a low-level signal and turned off under the control of a high-level signal, so that the level of the opening control signal is low and the level of the closing control signal is high.

[0052] In a specific implementation, in the embodiment of the present application, as shown in Figure 4 As shown in Figure 5 M can be set to 2, that is, the two adjacent multiplexers 200 correspond to the adjacent two pixel units, that is, the two adjacent multiplexers 200 correspond to the adjacent six sub-pixels. In addition, one source input signal line S_i is electrically connected with three data signal lines through one multiplexer 200, and all the multiplexers 200 are electrically connected with three control signal lines CK_j. In addition, the three control signal lines can include a first control signal line CK_1 corresponding to the data signal line connected with the first sub-pixel, a second control signal line CK_2 corresponding to the data signal line connected with the second sub-pixel, and a third control signal line CK_3 corresponding to the data signal line connected with the third sub-pixel. Specifically, since one switch transistor Tf_p is connected with one data signal line, and one column of sub-pixels is also connected with one data signal line, that is, one column of sub-pixels is connected with one switch transistor Tf_p through the connected data signal line. As shown in Figure 6 As shown in Figure 6As shown, the red sub-pixel R is connected to the switching transistor Tf_1 via a data signal line, and the switching transistor Tf_1 corresponding to the red sub-pixel R is electrically connected to the first control signal line CK_1. This can be considered as the first control signal line CK_1 being configured to correspond with the data signal line connected to the red sub-pixel R. The green sub-pixel G is connected to the switching transistor Tf_2 via a data signal line, and the switching transistor Tf_2 corresponding to the green sub-pixel G is electrically connected to the second control signal line CK_2. This can be considered as the second control signal line CK_2 being configured to correspond with the data signal line connected to the green sub-pixel G. The blue sub-pixel B is connected to the switching transistor Tf_3 via a data signal line, and the switching transistor Tf_3 corresponding to the blue sub-pixel B is electrically connected to the third control signal line CK_3. This can be considered as the third control signal line CK_3 being configured to correspond with the data signal line connected to the blue sub-pixel B.

[0053] In specific implementation, in this embodiment of the invention, an interval time period can be set between at least two adjacent data input stages. In this embodiment, during the interval time period, a gate cutoff signal is applied to the gate signal line, and a cutoff control signal is applied to each of the control signal lines. This allows the data signal input to the data signal lines to stabilize in the previous data input stage before proceeding to the next data input stage, thereby improving the stability of the display panel. In practical applications, the length of this interval time period can be designed and determined according to the actual application environment, and is not limited here.

[0054] In specific implementation, in the embodiments of the present invention, such as Figure 6 As shown, an interval time period T00 can be set between each pair of adjacent data input stages, which can further improve stability. Alternatively, an interval time period can be set between adjacent data input stages in some data input stages, while no interval time period is set between other data input stages. Of course, the method of setting the interval time period can be designed and determined according to the actual application environment, and is not limited here.

[0055] In practice, a charging cycle can include three data input phases, i.e., Y=3. Specifically, as follows: Figure 6As shown, g_1~g_3 represent signals loaded on the gate signal lines G_1~G_3 respectively, and ck_1~ck_3 represent signals loaded on the first to third control signal lines CK_1~CK_3 respectively. One charging period T1 can include: a first data input stage T11, a second data input stage T12, and a third data input stage T13. And, an interval period T00 is set between the first data input stage T11 and the second data input stage T12, and an interval period T00 is also set between the second data input stage T12 and the third data input stage T13.

[0056] In the first data input stage T11, i.e. when the gate signal line G_1 is loaded with the gate-on signal g_1 of high level to control the thin film transistor in the first row of sub-pixels to be turned on, the first to third control signal lines CK_1~CK_3 are sequentially loaded with the on control signals ck_1~ck_3 of high level. Specifically, first, the first control signal line CK_1 is loaded with the on control signal ck_1 of high level, the second control signal line CK_2 is loaded with the off control signal ck_2 of low level, and the third control signal line CK_3 is loaded with the off control signal ck_3 of low level, to control all the switching transistors Tf_1 to be turned on and all the switching transistors Tf_2, Tf_3 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the red sub-pixel R (taking the data signal s_1 loaded on the source input signal line S_1 as an example), so that the data signal line connected to the red sub-pixel R is loaded with the corresponding data signal, to charge the first row of red sub-pixels R in each column. Figure 6

[0057] Secondly, the second control signal line CK_2 is loaded with the on control signal ck_2 of high level, the first control signal line CK_1 is loaded with the off control signal ck_1 of low level, and the third control signal line CK_3 is loaded with the off control signal ck_3 of low level, to control all the switching transistors Tf_2 to be turned on and all the switching transistors Tf_1, Tf_3 to be turned off, at this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the green sub-pixel G, so that the data signal line connected to the green sub-pixel G is loaded with the corresponding data signal, to charge the first row of green sub-pixels G in each column.

[0058] ​Finally, the third control signal line CK_3 is loaded with the high level on-off control signal in ck_3, the first control signal line CK_1 is loaded with the low level off control signal in ck_1, and the second control signal line CK_2 is loaded with the low level off control signal in ck_2, so as to control all the switch transistors Tf_3 to be turned on and all the switch transistors Tf_1 and Tf_2 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the blue sub-pixel B, so that the data signal line connected to the blue sub-pixel B is loaded with the corresponding data signal, so as to charge the first row of blue sub-pixels B in each column.

[0059] In the second data input stage T12, that is, when the gate signal line G_2 is loaded with the high level on-off signal in g_2 to control the thin film transistors in the second row of sub-pixels to be turned on, the second control signal line CK_2, the third control signal line CK_3, and the first control signal line CK_1 are loaded with the high level on-off control signal in ck_2, ck_3, and ck_1 in turn. Specifically, first, the second control signal line CK_2 is loaded with the high level on-off control signal in ck_2, the first control signal line CK_1 is loaded with the low level off control signal in ck_1, and the third control signal line CK_3 is loaded with the low level off control signal in ck_3, so as to control all the switch transistors Tf_2 to be turned on and all the switch transistors Tf_1 and Tf_3 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the green sub-pixel G, so that the data signal line connected to the green sub-pixel G is loaded with the corresponding data signal, so as to charge the second row of green sub-pixels G in each column.

[0060] Secondly, the third control signal line CK_3 is loaded with the high level on-off control signal in ck_3, the first control signal line CK_1 is loaded with the low level off control signal in ck_1, and the second control signal line CK_2 is loaded with the low level off control signal in ck_2, so as to control all the switch transistors Tf_3 to be turned on and all the switch transistors Tf_1 and Tf_2 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the blue sub-pixel B, so that the data signal line connected to the blue sub-pixel B is loaded with the corresponding data signal, so as to charge the second row of blue sub-pixels B in each column.

[0061] Finally, the first control signal line CK_1 is loaded with the high level on-off control signal in ck_1, the second control signal line CK_2 is loaded with the low level off control signal in ck_2, and the third control signal line CK_3 is loaded with the low level off control signal in ck_3, so as to control all the switch transistors Tf_1 to be turned on and all the switch transistors Tf_2 and Tf_3 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the red sub-pixel R, so that the data signal line connected to the red sub-pixel R is loaded with the corresponding data signal, so as to charge the second row of red sub-pixels R in each column.

[0062] In the third data input stage T13, that is, when the gate signal line G_3 is loaded with the high level gate on signal in g_3 to control the thin film transistors in the third row of sub-pixels to be turned on, the third control signal line CK_3, the first control signal line CK_1, and the second control signal line CK_2 are loaded with the high level on-off control signals in ck_3, ck_1, and ck_2 in turn. Specifically, first, the third control signal line CK_3 is loaded with the high level on-off control signal in ck_3, the first control signal line CK_1 is loaded with the low level off control signal in ck_1, and the second control signal line CK_2 is loaded with the low level off control signal in ck_2, so as to control all the switch transistors Tf_3 to be turned on and all the switch transistors Tf_1 and Tf_2 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the blue sub-pixel B, so that the data signal line connected to the blue sub-pixel B is loaded with the corresponding data signal, so as to charge the third row of blue sub-pixels B in each column.

[0063] Secondly, the first control signal line CK_1 is loaded with the high level on-off control signal in ck_1, the second control signal line CK_2 is loaded with the low level off control signal in ck_2, and the third control signal line CK_3 is loaded with the low level off control signal in ck_3, so as to control all the switch transistors Tf_1 to be turned on and all the switch transistors Tf_2 and Tf_3 to be turned off. At this time, the source input signal line S_i is loaded with the data signal s_i corresponding to the red sub-pixel R, so that the data signal line connected to the red sub-pixel R is loaded with the corresponding data signal, so as to charge the third row of red sub-pixels R in each column.

[0064] Finally, the on control signal of high level in ck_2 is loaded to the second control signal line CK_2, the off control signal of low level in ck_1 is loaded to the first control signal line CK_1, and the off control signal of low level in ck_3 is loaded to the third control signal line CK_3, so as to control all the switch transistors Tf_2 to be turned on and all the switch transistors Tf_1 and Tf_3 to be turned off. At this time, the data signal s_i corresponding to the green sub-pixel G is loaded to the source input signal line S_i, so that the data signal line connected to the green sub-pixel G is loaded with the corresponding data signal, so as to charge the green sub-pixel G in the third row of each column.

[0065] In summary, in the first data input stage T11, the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the first row are sequentially charged, so that due to the coupling effect of the data signal line, the voltage variation of each color sub-pixel is: the voltage variation of the red sub-pixel R is the largest, the voltage variation of the green sub-pixel G is the second, and the voltage variation of the blue sub-pixel B is the smallest. Similarly, in the second data input stage T12, the voltage variation of the green sub-pixel G is the largest, the voltage variation of the blue sub-pixel B is the second, and the voltage variation of the red sub-pixel R is the smallest. In the third data input stage T13, the voltage variation of the blue sub-pixel B is the largest, the voltage variation of the red sub-pixel R is the second, and the voltage variation of the green sub-pixel G is the smallest. Therefore, in the charging period T1, the three rows of sub-pixels in the same column can be regarded as a whole, so that the sum of the voltage variation of the red sub-pixel R, the sum of the voltage variation of the green sub-pixel G and the sum of the voltage variation of the blue sub-pixel B can be equal, so that the sum of the voltage variation of the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B can be regarded as mutual offset, so that color cast can be avoided and display uniformity can be improved.

[0066] Similarly, the charging process of the above first data input stage T11 to the third data input stage T13 can be repeated for the subsequent sub-pixels, which will not be repeated here. In this way, the gate signal lines in the display panel can be grouped into three adjacent lines, and the gate signal lines in each group can be sequentially input Figure 6The number of gate signal lines in the display panel cannot be divided by 3, for example, the number of gate signal lines in the display panel is 10 or 11, which will remain 1 or 2 gate signal lines. Among them, when there is 1 gate signal line remaining, the charging mode of one data input stage in the first data input stage T11 to the third data input stage T13 can be used to charge the sub-pixels corresponding to the gate signal line. When there are 2 gate signal lines remaining, the charging mode of two data input stages in the first data input stage T11 to the third data input stage T13 can be used to charge the sub-pixels corresponding to the two gate signal lines. And in actual application, if the number of gate signal lines cannot be divided by 3, due to the large number of gate signal lines in the display panel and the small area of the sub-pixels, the color deviation of the remaining 1 or 2 rows of sub-pixels can be ignored during display.

[0067] In specific implementation, in the embodiment of the present application, as shown in the figure, Figure 6 The first data input stage T11 to the third data input stage T13 can appear in sequence. Alternatively, the second data input stage T12 can be made to appear first, that is, when the gate signal line G_1 is loaded with the gate-on signal, the loading sequence of each on-off control signal in the second data input stage T12 is used. Secondly, the first data input stage T11 appears, that is, when the gate signal line G_2 is loaded with the gate-on signal, the loading sequence of each on-off control signal in the first data input stage T11 is used. Finally, the third data input stage T13 appears, that is, when the gate signal line G_3 is loaded with the gate-on signal, the loading sequence of each on-off control signal in the third data input stage T13 is used. Of course, the third data input stage T13 can be made to appear first, the second data input stage T12 can be made to appear secondly, and the third data input stage T13 can be made to appear last. In actual application, this needs to be designed and determined according to the actual application environment, which is not limited here.

[0068] And, the interval period T00 is set between the first data input stage T11 and the second data input stage T12, to load the gate-off signals in g_1-g_3 to the gate signal lines G_1-G_3 respectively, control the thin film transistors in the first to third rows of sub-pixels to be all off. And load the off control signals in ck_1-ck_3 to each control signal line CK_1-CK_3, control all the switching transistors Tf_1, Tf_2 and Tf_3 to be off. In this way, the data signal line can input the data signal stably before the second data input stage T12 is performed in the first data input stage T11, thereby improving the stability of the display panel.

[0069] Similarly, an interval period T00 is arranged between the second data input stage T12 and the third data input stage T13 to load the gate-off signals in g_1-g_3 to the gate signal lines G_1-G_3 respectively, so as to control the thin film transistors in the first to third rows of sub-pixels to be all turned off, and load the off control signals in ck_1-ck_3 to the control signal lines CK_1-CK_3 respectively, so as to control the switch transistors Tf_1, Tf_2 and Tf_3 to be all turned off. In this way, the third data input stage T13 can be performed after the data signal lines input the data signals stably in the second data input stage T12, so as to improve the stability of the display panel.

[0070] In a specific implementation, the on control signals loaded on the same control signal line are separated by at least one time length of the on control signal. Specifically, as shown in Figure 4 the on control signal of ck_1 loaded on the first control signal line CK_1, the on control signal of ck_1 loaded in the second data write stage T12 and the on control signal of ck_1 loaded in the third data write stage T13 are separated by one time length t01 of the on control signal. The on control signal of ck_1 in the first data write stage T11 and the on control signal of ck_1 in the second data write stage T12 are separated by four time lengths t01 of the on control signal. Of course, in actual application, the number of on control signals separated between the on control signals loaded on the same control signal line can be designed according to the actual application environment, which is not limited herein.

[0071] It should be noted that, Figure 5 the data signal s_1 has high and low levels, which is only used to distinguish the different data signals input into the red, green and blue sub-pixels, and is not the voltage of the data signal actually input into the sub-pixels of each color. In actual application, the voltage value and polarity of the voltage of the data signal input into the sub-pixels of each color can be designed according to the actual application environment, which is not limited herein.

[0072] It should be noted that the adjacent mentioned in the embodiment of the present application refers to the nearest neighbor. Moreover, the equal mentioned in the embodiment of the present application refers to the equal within an error allowable range.

[0073] Embodiment two,

[0074] The structure diagram of the display panel corresponding to the embodiment is as shown in Figure 7 and Figure 7 which is deformed in the number of data input stages included in one charging period in the embodiment one. Only the differences between the embodiment and the embodiment one will be described below, and the same parts will not be described herein.

[0075] In practice, a charging cycle can include six data input stages, i.e., Y=6. Specifically, as follows: Figure 8 As shown, a charging cycle T1 may include: a first data input stage T11, a second data input stage T12, a third data input stage T13, a fourth data input stage T14, a fifth data input stage T15, and a sixth data input stage T16. In the first data input stage T11, when the gate enable signal in g_1 is applied to the gate signal line G_1 to control the conduction of the thin-film transistors in the first row of sub-pixels, the enable control signals in ck_1 to ck_3 are sequentially applied to the first to third control signal lines CK_1 to CK_3, thereby sequentially controlling the charging of the red sub-pixel R, green sub-pixel G, and blue sub-pixel B in the first row.

[0076] In the second data input stage T12, when a high-level gate enable signal is applied to the gate signal line G_2 to control the conduction of the thin-film transistors in the second row of sub-pixels, high-level enable control signals are sequentially applied to the second control signal line CK_2, the third control signal line CK_3, and the first control signal line CK_1, thereby sequentially controlling the charging of the green sub-pixel G, the blue sub-pixel B, and the red sub-pixel R in the second row.

[0077] In the third data input stage T13, when a high-level gate enable signal is applied to the gate signal line G_3 to control the conduction of the thin-film transistors in the third row of sub-pixels, high-level enable control signals are sequentially applied to the third control signal line CK_3, the first control signal line CK_1, and the second control signal line CK_2, thereby sequentially controlling the charging of the blue sub-pixel B, the red sub-pixel R, and the green sub-pixel G in the third row.

[0078] In the fourth data input stage T14, when a high-level gate enable signal is applied to the gate signal line G_4 to control the conduction of the thin-film transistor in the fourth row of sub-pixels, high-level enable control signals are sequentially applied to the third control signal line CK_3, the second control signal line CK_2, and the first control signal line CK_1, thereby sequentially controlling the charging of the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R in the fourth row.

[0079] In the fifth data input stage T15, that is, when the gate on signal in the high level in g_5 is loaded to the gate signal line G_5 to control the thin film transistor in the fifth row of sub-pixels to be turned on, the on control signals in the high level in ck_2, ck_1, ck_3 are sequentially loaded to the second control signal line CK_2, the first control signal line CK_1, the third control signal line CK_3, so as to sequentially control the green sub-pixel G, the red sub-pixel R, and the blue sub-pixel B in the fifth row to be charged.

[0080] In the sixth data input stage T16, that is, when the gate on signal in the high level in g_6 is loaded to the gate signal line G_6 to control the thin film transistor in the sixth row of sub-pixels to be turned on, the on control signals in the high level in ck_1, ck_3, ck_2 are sequentially loaded to the first control signal line CK_1, the third control signal line CK_3, the second control signal line CK_2, so as to sequentially control the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G in the sixth row to be charged.

[0081] Similarly, in the charging period T1, the six rows of sub-pixels in the same column can be taken as a whole, so that the sum of the voltage variation corresponding to the red sub-pixel R, the sum of the voltage variation corresponding to the green sub-pixel G, and the sum of the voltage variation corresponding to the blue sub-pixel B can be equal, so that the sum of the voltage variation corresponding to the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B can be regarded as mutual cancellation, so as to avoid color cast and improve display uniformity.

[0082] In the specific implementation, in the embodiment of the application, as shown in Figure 8 The first data input stage T11 to the sixth data input stage T16 can be sequentially arranged in order. Alternatively, the second data input stage T12 can be arranged first, that is, when the gate on signal is loaded to the gate signal line G_1, the loading order of the on control signals in the second data input stage T12 is adopted. Then, the first data input stage T11 is arranged, that is, when the gate on signal is loaded to the gate signal line G_2, the loading order of the on control signals in the first data input stage T11 is adopted. Then, the third data input stage T13 to the sixth data input stage T16 are sequentially arranged. In actual application, this needs to be designed and determined according to the actual application environment, which is not limited herein.

[0083] Of course, in the specific implementation, the Y=9, 12, 15, … data input stages can also be arranged, and the specific implementation process can be referred to the embodiment one and the embodiment two, which is not repeated here.

[0084] Embodiment three,

[0085] The structure diagram of the display panel corresponding to the embodiment is as shown in Figure 8As shown, the number of switch transistors included in the multiplexer 200 in Embodiment One is changed. Only the differences between this embodiment and Embodiment One are described below, and the same parts are not described again. In the implementation, in this embodiment of the present application, as shown Figure 8 As shown (taking P=6 as an example), each multiplexer 200 can include a plurality of switch transistors Tf_p, wherein one switch transistor Tf_p corresponds to one data signal line. The gate of each switch transistor Tf_p is electrically connected to a different control signal line CK_j (taking J=6 as an example), the first pole of each switch transistor Tf_p is electrically connected to a corresponding source input signal line S_i (taking I=2 as an example), and the second pole of each switch transistor Tf_p is electrically connected to a corresponding data signal line. Figure 8 As shown (taking J=6 as an example), the gate of each switch transistor Tf_p is electrically connected to a different control signal line CK_j (taking J=6 as an example), the first pole of each switch transistor Tf_p is electrically connected to a corresponding source input signal line S_i (taking I=2 as an example), and the second pole of each switch transistor Tf_p is electrically connected to a corresponding data signal line. Figure 8 As shown (taking I=2 as an example), the gate of each switch transistor Tf_p is electrically connected to a different control signal line CK_j (taking J=6 as an example), the first pole of each switch transistor Tf_p is electrically connected to a corresponding source input signal line S_i (taking I=2 as an example), and the second pole of each switch transistor Tf_p is electrically connected to a corresponding data signal line.

[0086] In the implementation, in this embodiment of the present application, as shown Figure 9 As shown, M can be set to 4, that is, two adjacent multiplexers 200 correspond to four adjacent pixel units. That is, two adjacent multiplexers 200 correspond to 12 adjacent sub-pixels. And one source input signal line S_i is electrically connected to six data signal lines through one multiplexer 200, and all multiplexers 200 are electrically connected to six control signal lines CK_j. The six control signal lines can include a first control signal line CK_1 and a fourth control signal line CK_4 corresponding to the data signal lines connected to the first sub-pixel, a second control signal line CK_2 and a fifth control signal line CK_5 corresponding to the data signal lines connected to the second sub-pixel, and a third control signal line CK_3 and a sixth control signal line CK_6 corresponding to the data signal lines connected to the third sub-pixel. And since one switch transistor Tf_p corresponds to one data signal line, and one column of sub-pixels also corresponds to one data signal line, that is, one column of sub-pixels is connected to one switch transistor Tf_p through the connected data signal line. As shown Figure 9As shown, for the data signal line connected with the red sub-pixel R, the switch transistor Tf_1 connected with the first data signal line corresponding to each multiplexor 200 is electrically connected with the first control signal line CK_1, and the switch transistor Tf_4 connected with the second data signal line is electrically connected with the fourth control signal line CK_4, that is, the first control signal line CK_1 and the fourth control signal line CK_4 can be regarded as being arranged corresponding to the data signal line connected with the red sub-pixel R. For the data signal line connected with the green sub-pixel G, the switch transistor Tf_2 connected with the first data signal line corresponding to each multiplexor 200 is electrically connected with the second control signal line CK_2, and the switch transistor Tf_5 connected with the second data signal line is electrically connected with the fourth control signal line CK_5, that is, the first control signal line CK_2 and the fourth control signal line CK_5 can be regarded as being arranged corresponding to the data signal line connected with the green sub-pixel G. For the data signal line connected with the blue sub-pixel B, the switch transistor Tf_3 connected with the first data signal line corresponding to each multiplexor 200 is electrically connected with the second control signal line CK_3, and the switch transistor Tf_6 connected with the second data signal line is electrically connected with the fourth control signal line CK_6, that is, the first control signal line CK_3 and the fourth control signal line CK_6 can be regarded as being arranged corresponding to the data signal line connected with the blue sub-pixel B.

[0087] Hereinafter, the red sub-pixel R corresponding to the first control signal line CK_1 is regarded as the first type of red sub-pixel R, the red sub-pixel R corresponding to the fourth control signal line CK_4 is regarded as the second type of red sub-pixel R, the green sub-pixel G corresponding to the second control signal line CK_2 is regarded as the first type of green sub-pixel G, the green sub-pixel G corresponding to the fifth control signal line CK_5 is regarded as the second type of green sub-pixel G, the blue sub-pixel B corresponding to the third control signal line CK_3 is regarded as the first type of blue sub-pixel B, and the blue sub-pixel B corresponding to the sixth control signal line CK_6 is regarded as the second type of blue sub-pixel B.

[0088] In a specific implementation, one charging period can include 6 data input stages, that is, Y = 6. Specifically, as shown in FIG. 6, the first type of red sub-pixel R is selected in the first data input stage, the second type of red sub-pixel R is selected in the second data input stage, the first type of green sub-pixel G is selected in the third data input stage, the second type of green sub-pixel G is selected in the fourth data input stage, the first type of blue sub-pixel B is selected in the fifth data input stage, and the second type of blue sub-pixel B is selected in the sixth data input stage. Figure 10As shown, one charging period T1 can include: a first data input stage T11, a second data input stage T12, a third data input stage T13, a fourth data input stage T14, a fifth data input stage T15, and a sixth data input stage T16. In the first data input stage T11, i.e. when a high-level gate-on signal in g_1 is loaded to the gate signal line G_1 to control the thin film transistors in the first row of sub-pixels to be turned on, the first to sixth control signal lines CK_1~CK_6 are sequentially loaded with high-level on control signals in ck_1~ck_6 to sequentially charge the first type of red sub-pixels R, the first type of green sub-pixels G, the first type of blue sub-pixels B, the second type of red sub-pixels R, the second type of green sub-pixels G, and the second type of blue sub-pixels B in the first row.

[0089] In the second data input stage T12, i.e. when a high-level gate-on signal in g_2 is loaded to the gate signal line G_2 to control the thin film transistors in the second row of sub-pixels to be turned on, the second control signal line CK_2 is loaded with an on control signal in ck_2, the third control signal line CK_3 is loaded with an on control signal in ck_3, the fourth control signal line CK_4 is loaded with an on control signal in ck_4, the fifth control signal line CK_5 is loaded with an on control signal in ck_5, the sixth control signal line CK_6 is loaded with an on control signal in ck_6, and the first control signal line CK_1 is loaded with an on control signal in ck_1, to sequentially charge the first type of green sub-pixels G, the first type of blue sub-pixels B, the second type of red sub-pixels R, the second type of green sub-pixels G, the second type of blue sub-pixels B, and the first type of red sub-pixels R in the second row.

[0090] In the third data input stage T13, i.e. when a high-level gate-on signal in g_3 is loaded to the gate signal line G_3 to control the thin film transistors in the third row of sub-pixels to be turned on, the third control signal line CK_3 is loaded with an on control signal in ck_3, the fourth control signal line CK_4 is loaded with an on control signal in ck_4, the fifth control signal line CK_5 is loaded with an on control signal in ck_5, the sixth control signal line CK_6 is loaded with an on control signal in ck_6, the first control signal line CK_1 is loaded with an on control signal in ck_1, and the second control signal line CK_2 is loaded with an on control signal in ck_2, to sequentially charge the first type of blue sub-pixels B, the second type of red sub-pixels R, the second type of green sub-pixels G, the second type of blue sub-pixels B, the first type of red sub-pixels R, and the first type of green sub-pixels G in the third row.

[0091] In the fourth data input stage T14, i.e. when the gate on signal in the high level in g_4 is loaded to the gate signal line G_4 to control the thin film transistor in the fourth row of sub-pixels to turn on, the opening control signal in ck_4 is loaded to the fourth control signal line CK_4, the opening control signal in ck_5 is loaded to the fifth control signal line CK_5, the opening control signal in ck_6 is loaded to the sixth control signal line CK_6, the opening control signal in ck_1 is loaded to the first control signal line CK_1, the opening control signal in ck_2 is loaded to the second control signal line CK_2, and the opening control signal in ck_3 is loaded to the third control signal line CK_3 in sequence, so as to charge the second type of red sub-pixel R, the second type of green sub-pixel G, the second type of blue sub-pixel B, the first type of red sub-pixel R, the first type of green sub-pixel G, and the first type of blue sub-pixel B in the fourth row in sequence.

[0092] In the fifth data input stage T15, i.e. when the gate on signal in the high level in g_5 is loaded to the gate signal line G_5 to control the thin film transistor in the fifth row of sub-pixels to turn on, the opening control signal in ck_5 is loaded to the fifth control signal line CK_5, the opening control signal in ck_6 is loaded to the sixth control signal line CK_6, the opening control signal in ck_1 is loaded to the first control signal line CK_1, the opening control signal in ck_2 is loaded to the second control signal line CK_2, the opening control signal in ck_3 is loaded to the third control signal line CK_3, and the opening control signal in ck_4 is loaded to the fourth control signal line CK_4 in sequence; so as to charge the second type of green sub-pixel G, the second type of blue sub-pixel B, the first type of red sub-pixel R, the first type of green sub-pixel G, the first type of blue sub-pixel B, and the second type of red sub-pixel R in the fifth row in sequence.

[0093] In the sixth data input stage T16, i.e. when the gate on signal in the high level in g_6 is loaded to the gate signal line G_6 to control the thin film transistor in the fifth row of sub-pixels to turn on, the opening control signal in ck_6 is loaded to the sixth control signal line CK_6, the opening control signal in ck_1 is loaded to the first control signal line CK_1, the opening control signal in ck_2 is loaded to the second control signal line CK_2, the opening control signal in ck_3 is loaded to the third control signal line CK_3, the opening control signal in ck_4 is loaded to the fourth control signal line CK_4, and the opening control signal in ck_5 is loaded to the fifth control signal line CK_5 in sequence; so as to charge the second type of blue sub-pixel B, the first type of red sub-pixel R, the first type of green sub-pixel G, the first type of blue sub-pixel B, the second type of red sub-pixel R, and the second type of green sub-pixel G in the sixth row in sequence.

[0094] Similarly, in the charging period T1, the six rows of sub-pixels in the same column can be taken as a whole, so that the sum of the voltage variation corresponding to the first type of red sub-pixel R, the sum of the voltage variation corresponding to the second type of red sub-pixel R, the sum of the voltage variation corresponding to the first type of green sub-pixel G, the sum of the voltage variation corresponding to the second type of green sub-pixel G, the sum of the voltage variation corresponding to the first type of blue sub-pixel B, and the sum of the voltage variation corresponding to the second type of blue sub-pixel B can be equal, so that the sum of the voltage variation corresponding to the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B can be regarded as mutually offset, thereby avoiding color cast and improving display uniformity.

[0095] In a specific implementation, in the embodiment of the present application, as shown in Figure 10 , the first data input stage T11 to the sixth data input stage T16 can appear in sequence. Alternatively, the second data input stage T12 can be made to appear first, that is, when the gate signal line G_1 is loaded with the gate-on signal, the loading sequence of each of the on control signals in the second data input stage T12 is adopted. The first data input stage T11 is made to appear second, that is, when the gate signal line G_2 is loaded with the gate-on signal, the loading sequence of each of the on control signals in the first data input stage T11 is adopted. The third data input stage T13 to the sixth data input stage T16 are made to appear in sequence. In actual application, this needs to be designed and determined according to the actual application environment, which is not limited herein.

[0096] Embodiment Four,

[0097] The structural schematic diagram of the display panel corresponding to the present embodiment is as shown in Figure 10 , which is deformed for the number of sub-pixels included in the pixel PX in Embodiment One, that is, the value of M. Only the differences between the present embodiment and Embodiment One will be described below, and the same parts will not be described herein. In a specific implementation, as shown in Figure 10 , M can also be set to 4, that is, the pixel PX can include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in the first direction in sequence. Among them, the first sub-pixel can be a red sub-pixel R, the second sub-pixel can be a green sub-pixel G, the third sub-pixel can be a blue sub-pixel B, and the fourth sub-pixel can be a white sub-pixel W.

[0098] In a specific implementation, in the embodiment of the present application, as shown in Figure 11As shown, M can be set to 2, that is, two adjacent multiplexers 200 correspond to two adjacent pixel units, that is, two adjacent multiplexers 200 correspond to eight adjacent sub-pixels. And one source input signal line S_i is electrically connected to four data signal lines through one multiplexer 200, and all multiplexers 200 are electrically connected to four control signal lines CK_j. And the four control signal lines can include: a first control signal line CK_1 corresponding to the data signal line connected to the first sub-pixel, a second control signal line CK_2 corresponding to the data signal line connected to the second sub-pixel, a third control signal line CK_3 corresponding to the data signal line connected to the third sub-pixel, and a fourth control signal line CK_4 corresponding to the data signal line connected to the fourth sub-pixel. And since one switch transistor Tf_p corresponds to one data signal line, and one column of sub-pixels also corresponds to one data signal line, that is, one column of sub-pixels is connected to one switch transistor Tf_p through the connected data signal line. As shown in Figure 11 As shown, the red sub-pixel R is connected to the switch transistor Tf_1 through the connected data signal line, and the switch transistor Tf_1 corresponding to the red sub-pixel R is electrically connected to the first control signal line CK_1, that is, the first control signal line CK_1 can be considered to be set corresponding to the data signal line connected to the red sub-pixel R. Similarly, the second control signal line CK_2 can be considered to be set corresponding to the data signal line connected to the green sub-pixel G, the third control signal line CK_3 can be considered to be set corresponding to the data signal line connected to the blue sub-pixel B, and the fourth control signal line CK_4 can be considered to be set corresponding to the data signal line connected to the white sub-pixel W.

[0099] In specific implementation, one charging period can include four data input stages, that is, Y=4. Specifically, as shown in Figure 12 As shown, one charging period T1 can include: a first data input stage T11, a second data input stage T12, a third data input stage T13, and a fourth data input stage T14. Specifically, in the first data input stage T11, that is, when the gate on signal in g_1 is loaded into the gate signal line G_1 to control the thin film transistor in the first row of sub-pixels to be turned on, the on control signals ck_1~ck_4 are sequentially loaded into the first to fourth control signal lines CK_1~CK_4, and the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W in the first row are sequentially charged.

[0100] In the second data input stage T12, i.e. when the gate on signal in the high level in g_2 is loaded to the gate signal line G_2 to control the thin film transistor in the second row of sub-pixels to be turned on, the on control signal in ck_2 is loaded to the second control signal line CK_2, the on control signal in ck_3 is loaded to the third control signal line CK_3, the on control signal in ck_4 is loaded to the fourth control signal line CK_4, and the on control signal in ck_1 is loaded to the first control signal line CK_1 in sequence, and the green sub-pixel G, the blue sub-pixel B, the white sub-pixel W and the red sub-pixel R in the second row are charged in sequence.

[0101] In the third data input stage T13, i.e. when the gate on signal in the high level in g_3 is loaded to the gate signal line G_3 to control the thin film transistor in the third row of sub-pixels to be turned on, the on control signal in ck_3 is loaded to the third control signal line CK_3, the on control signal in ck_4 is loaded to the fourth control signal line CK_4, the on control signal in ck_1 is loaded to the first control signal line CK_1, and the on control signal in ck_2 is loaded to the second control signal line CK_2 in sequence, and the blue sub-pixel B, the white sub-pixel W, the red sub-pixel R and the green sub-pixel G in the third row are charged in sequence.

[0102] In the fourth data input stage T14, i.e. when the gate on signal in the high level in g_4 is loaded to the gate signal line G_4 to control the thin film transistor in the fourth row of sub-pixels to be turned on, the on control signal in ck_4 is loaded to the fourth control signal line CK_4, the on control signal in ck_1 is loaded to the first control signal line CK_1, the on control signal in ck_2 is loaded to the second control signal line CK_2, and the on control signal in ck_3 is loaded to the third control signal line CK_3 in sequence, and the white sub-pixel W, the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row are charged in sequence.

[0103] In the specific implementation, in the embodiment of the present application, as shown in Figure 12 the first data input stage T11 to the fourth data input stage T14 can be sequentially arranged in sequence. Alternatively, the second data input stage T12 can be arranged first, i.e. when the gate on signal is loaded to the gate signal line G_1, the loading sequence of the on control signals in the second data input stage T12 is adopted. Then the first data input stage T11 is arranged, i.e. when the gate on signal is loaded to the gate signal line G_2, the loading sequence of the on control signals in the first data input stage T11 is adopted. Then the third data input stage T13 to the fourth data input stage T14 are sequentially arranged. In actual application, this needs to be designed and determined according to the actual application environment, which is not limited herein.

[0104] Example 5

[0105] The structural diagram of the display panel corresponding to this embodiment is shown below. Figure 13 As shown, the number of switching transistors included in the multiplexer 200 in Embodiment 4 has been modified. The differences between this embodiment and Embodiment 1 will be described below; their similarities will not be repeated. In specific implementation, in the embodiments of the present invention, as... Figure 13 (Taking P=8 as an example) Each multiplexer 200 may include multiple switching transistors Tf_p. One source input signal line S_i is electrically connected to eight data signal lines through one multiplexer 200, and all multiplexers 200 are electrically connected to eight control signal lines CK_j. These eight control signal lines may include: the first control signal line CK_1 and the fifth control signal line CK_5 corresponding to the data signal line connected to the first sub-pixel; the second control signal line CK_2 and the sixth control signal line CK_6 corresponding to the data signal line connected to the second sub-pixel; the third control signal line CK_3 and the seventh control signal line CK_7 corresponding to the data signal line connected to the third sub-pixel; and the fourth control signal line CK_4 and the eighth control signal line CK_8 corresponding to the data signal line connected to the fourth sub-pixel.

[0106] The following explanation uses the following sub-pixels as examples: the red sub-pixel R corresponding to the first control signal line CK_1 as the first type of red sub-pixel R; the red sub-pixel R corresponding to the fifth control signal line CK_5 as the second type of red sub-pixel R; the green sub-pixel G corresponding to the second control signal line CK_2 as the first type of green sub-pixel G; the green sub-pixel G corresponding to the sixth control signal line CK_6 as the second type of green sub-pixel G; the blue sub-pixel B corresponding to the third control signal line CK_3 as the first type of blue sub-pixel B; the blue sub-pixel B corresponding to the seventh control signal line CK_7 as the second type of blue sub-pixel B; the white sub-pixel W corresponding to the fourth control signal line CK_4 as the first type of white sub-pixel W; and the white sub-pixel W corresponding to the eighth control signal line CK_8 as the second type of white sub-pixel W.

[0107] In practice, a charging cycle can include eight data input stages, i.e., Y=8. Specifically, as follows: Figure 4 As shown, a charging cycle T1 may include: a first data input stage T11, a second data input stage T12, a third data input stage T13, a fourth data input stage T14, a fifth data input stage T15, a sixth data input stage T16, a seventh data input stage T17, and an eighth data input stage T18.

[0108] In the first data input stage T11, i.e. when the gate on signal in the high level in g_1 is loaded to the gate signal line G_1 to control the thin film transistor in the first row of sub-pixels to be turned on, the on control signals in the high level in ck_1~ck_8 are sequentially loaded to the first to eighth control signal lines CK_1~CK_8.

[0109] In the second data input stage T12, i.e. when the gate on signal in the high level in g_2 is loaded to the gate signal line G_2 to control the thin film transistor in the second row of sub-pixels to be turned on, the on control signals in ck_2~ck_8 are sequentially loaded to the second to eighth control signal lines CK_2~CK_8, and the on control signal in ck_1 is loaded to the first control signal line CK_1.

[0110] In the third data input stage T13, i.e. when the gate on signal in the high level in g_3 is loaded to the gate signal line G_3 to control the thin film transistor in the third row of sub-pixels to be turned on, the on control signals in ck_3~ck_8 are sequentially loaded to the third to eighth control signal lines CK_3~CK_8, and the on control signal in ck_1 is loaded to the first control signal line CK_1.

[0111] In the fourth data input stage T14, i.e. when the gate on signal in g_4 is loaded on the gate signal line G_4 to control the thin film transistors in the fourth row of sub-pixels to turn on, the on control signal in ck_4 is loaded on the fourth control signal line CK_4, the on control signal in ck_5 is loaded on the fifth control signal line CK_5, the on control signal in ck_6 is loaded on the sixth control signal line CK_6, the on control signal in ck_7 is loaded on the seventh control signal line CK_7, the on control signal in ck_8 is loaded on the eighth control signal line CK_8, the on control signal in ck_1 is loaded on the first control signal line CK_1, the on control signal in ck_2 is loaded on the second control signal line CK_2, and the on control signal in ck_3 is loaded on the third control signal line CK_3 in sequence.

[0112] In the fifth data input stage T15, i.e. when the gate on signal in g_5 is loaded on the gate signal line G_5 to control the thin film transistors in the fifth row of sub-pixels to turn on, the on control signal in ck_5 is loaded on the fifth control signal line CK_5, the on control signal in ck_6 is loaded on the sixth control signal line CK_6, the on control signal in ck_7 is loaded on the seventh control signal line CK_7, the on control signal in ck_8 is loaded on the eighth control signal line CK_8, the on control signal in ck_1 is loaded on the first control signal line CK_1, the on control signal in ck_2 is loaded on the second control signal line CK_2, the on control signal in ck_3 is loaded on the third control signal line CK_3, and the on control signal in ck_4 is loaded on the fourth control signal line CK_4 in sequence.

[0113] In the sixth data input stage T16, i.e. when the gate on signal in g_6 is loaded on the gate signal line G_6 to control the thin film transistors in the sixth row of sub-pixels to turn on, the on control signal in ck_6 is loaded on the sixth control signal line CK_6, the on control signal in ck_7 is loaded on the seventh control signal line CK_7, the on control signal in ck_8 is loaded on the eighth control signal line CK_8, the on control signal in ck_1 is loaded on the first control signal line CK_1, the on control signal in ck_2 is loaded on the second control signal line CK_2, the on control signal in ck_3 is loaded on the third control signal line CK_3, the on control signal in ck_4 is loaded on the fourth control signal line CK_4, and the on control signal in ck_5 is loaded on the fifth control signal line CK_5 in sequence.

[0114] In the seventh data input stage T17, that is, when a high-level gate enable signal is applied to the gate signal line G_7 to control the thin-film transistor in the seventh row sub-pixel to turn on, the enable control signal in ck_7 is applied to the seventh control signal line CK_7, the enable control signal in ck_8 is applied to the eighth control signal line CK_8, the enable control signal in ck_1 is applied to the first control signal line CK_1, the enable control signal in ck_2 is applied to the second control signal line CK_2, the enable control signal in ck_3 is applied to the third control signal line CK_3, the enable control signal in ck_4 is applied to the fourth control signal line CK_4, the enable control signal in ck_5 is applied to the fifth control signal line CK_5, and the enable control signal in ck_6 is applied to the sixth control signal line CK_6.

[0115] In the eighth data input stage T18, that is, when a high-level gate enable signal is applied to the gate signal line G_8 to control the thin-film transistor in the eighth row sub-pixel to turn on, the enable control signal in ck_8 is applied to the eighth control signal line CK_8 in sequence, the enable control signal in ck_1 is applied to the first control signal line CK_1 in sequence, the enable control signal in ck_2 is applied to the second control signal line CK_2 in sequence, the enable control signal in ck_3 is applied to the third control signal line CK_3 in sequence, the enable control signal in ck_4 is applied to the fourth control signal line CK_4 in sequence, the enable control signal in ck_5 is applied to the fifth control signal line CK_5 in sequence, the enable control signal in ck_6 is applied to the sixth control signal line CK_6 in sequence, and the enable control signal in ck_7 is applied to the seventh control signal line CK_7 in sequence.

[0116] In specific implementation, in the embodiments of the present invention, such as Figure 5 As shown, the first data input stage T11 to the eighth data input stage T18 can appear sequentially.

[0117] Example 6

[0118] The structural diagram of the display panel corresponding to this embodiment is shown below. Figure 14 and Figure 14 As shown, this embodiment modifies the data input stage of Embodiment 1. The differences between this embodiment and Embodiment 1 will be described below; their similarities will not be repeated here.

[0119] The general display panel can realize display and touch functions, and in actual application, display and touch are driven in time division. In one frame display time, a time period of scanning a gate signal line and a time period of touch are included. In specific implementation, the driving method provided by the embodiment of the application can also set a data input stage as one frame scanning time period of sequentially loading a gate-on signal of each gate signal line in the display panel, that is, one data input stage corresponds to one frame scanning time period.

[0120] In specific implementation, one charging period can include three data input stages, that is, Y=3. Taking loading the gate-on signal in g_1 to the gate signal line G_1 as an example, as shown in the figure, Figure 10 one charging period T1 can include: a first data input stage T11, a second data input stage T12, and a third data input stage T13. Specifically, the first data input stage T11 can correspond to the scanning time period in the first display frame of the three continuous display frames, wherein when the gate-on signal in g_1 is loaded to the gate signal line G_1, the opening control signals in ck_1-ck_3 are sequentially loaded to the first to third control signal lines CK_1-CK_3. Similarly, when the gate-on signals are loaded to the remaining gate signal lines, the opening control signals in ck_1-ck_3 are also sequentially loaded to the first to third control signal lines CK_1-CK_3.

[0121] The second data input stage T12 can correspond to the scanning time period in the second display frame of the three continuous display frames, wherein when the gate-on signal in g_1 is loaded to the gate signal line G_1, the opening control signals in ck_2 and ck_3 are sequentially loaded to the second and third control signal lines CK_2 and CK_3, and the opening control signal in ck_1 is loaded to the first control signal line CK_1. Similarly, when the gate-on signals are loaded to the remaining gate signal lines, the opening control signals in ck_2 and ck_3 are sequentially loaded to the second and third control signal lines CK_2 and CK_3, and the opening control signal in ck_1 is loaded to the first control signal line CK_1.

[0122] The third data input stage T13 can correspond to a scanning time period in the third of the three continuous display frames, wherein the third control signal line CK_3 is loaded with the opening control signal in ck_3, the first control signal line CK_1 is loaded with the opening control signal in ck_1, and the second control signal line CK_2 is loaded with the opening control signal in ck_2 in sequence while the gate signal line G_1 is loaded with the gate opening signal in g_1. Similarly, the third control signal line CK_3 is loaded with the opening control signal in ck_3, the first control signal line CK_1 is loaded with the opening control signal in ck_1, and the second control signal line CK_2 is loaded with the opening control signal in ck_2 in sequence while the gate signal lines are loaded with the gate opening signals.

[0123] Thus, in the charging period T1, the same color sub-pixel in the three continuous frames can be taken as a whole, so that the sum of the voltage variation corresponding to the red sub-pixel R, the sum of the voltage variation corresponding to the green sub-pixel G, and the sum of the voltage variation corresponding to the blue sub-pixel B in the three continuous frames can be equal, so that the sum of the voltage variation corresponding to the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B can be regarded as mutual cancellation, so that color cast can be avoided and display uniformity can be improved.

[0124] Further, the interval time period T00 is arranged between the first data input stage T11 and the second data input stage T12, so as to load the gate signal lines G_1 to G_3 with the gate cutoff signals in g_1 to g_3 respectively, control the thin film transistors in the first to third rows of sub-pixels to be all cutoff, and load the control signal lines CK_1 to CK_3 with the cutoff control signals in ck_1 to ck_3 respectively, control all the switching transistors Tf_1, Tf_2, and Tf_3 to be all cutoff. Thus, the data signal line can be stabilized after inputting the data signal in the first data input stage T11, and then the second data input stage T12 is performed, so that the stability of the display panel can be improved.

[0125] Similarly, the interval time period T00 is arranged between the second data input stage T12 and the third data input stage T13, so as to load the gate signal lines G_1 to G_3 with the gate cutoff signals in g_1 to g_3 respectively, control the thin film transistors in the first to third rows of sub-pixels to be all cutoff, and load the control signal lines CK_1 to CK_3 with the cutoff control signals in ck_1 to ck_3 respectively, control all the switching transistors Tf_1, Tf_2, and Tf_3 to be all cutoff. Thus, the data signal line can be stabilized after inputting the data signal in the second data input stage T12, and then the third data input stage T13 is performed, so that the stability of the display panel can be improved.

[0126] In specific implementation, for example, Figure 15As shown, the first data input stage T11 to the third data input stage T13 can appear in turn.

[0127] Of course, in specific implementation, Y = 6, 9, 12, 15… and other data input stages can also be made, and the specific implementation process can be referred to in this embodiment, which will not be repeated here.

[0128] Embodiment seven,

[0129] The structure diagram of the display panel corresponding to this embodiment is as shown in Figure 15 As shown, the number of sub-pixels included in the pixel PX in Embodiment Six is deformed. Only the differences between this embodiment and Embodiment Six will be described below, and the same parts will not be repeated here.

[0130] In specific implementation, one charging period can include 4 data input stages, that is, Y = 4. Taking loading the gate-on signal in g_1 on the gate signal line G_1 as an example for description, as shown in Figure 16 As shown, one charging period T1 can include: the first data input stage T11, the second data input stage T12, the third data input stage T13, and the fourth data input stage T14. Specifically, the first data input stage T11 can correspond to the scanning time period in the first of the four consecutive display frames, wherein when the gate-on signal in g_1 is loaded on the gate signal line G_1, the on control signals in ck_1-ck_4 are loaded on the first to fourth control signal lines CK_1-CK_4 in turn. Similarly, when the gate-on signals are loaded on the remaining gate signal lines, the on control signals in ck_1-ck_4 are also loaded on the first to fourth control signal lines CK_1-CK_4 in turn. The remaining second to fourth data input stages T12-T14 are the same, and will not be repeated here.

[0131] In this way, in this charging period T1, the same color sub-pixels in the four consecutive frames can be taken as a whole, so that the sum of the voltage variation amounts corresponding to the red sub-pixels R, the sum of the voltage variation amounts corresponding to the green sub-pixels G, and the sum of the voltage variation amounts corresponding to the blue sub-pixels B in the four consecutive frames can be equal, so that the sum of the voltage variation amounts corresponding to the red sub-pixels R, the green sub-pixels G and the blue sub-pixels B can be regarded as mutual cancellation, thereby avoiding color cast and improving display uniformity.

[0132] In specific implementation, as shown in ​ As shown, the first data input stage T11 to the fourth data input stage T14 can appear in turn.

[0133] Of course, in specific implementation, Y = 8, 12… and other data input stages can also be made, and the specific implementation process can be referred to in this embodiment, which will not be repeated here.

[0134] Based on the same inventive concept, the embodiment of the present application provides a driving device of a display panel, which can be used to execute the steps of the driving method of the display panel provided by the embodiment of the present application. Since the principle of solving the problem of the display panel is similar to the driving method of the display panel, the implementation of the driving device can refer to the implementation of the driving method, and the repeated parts will not be described herein.

[0135] In the implementation, the driving device provided by the embodiment of the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware, which is not limited herein.

[0136] Further, in the implementation, the driving device provided by the embodiment of the present application can be an integrated circuit (IC).

[0137] Based on the same inventive concept, the embodiment of the present application provides a display panel, which is driven by the driving method of the display panel provided by the embodiment of the present application. Since the principle of solving the problem of the display panel is similar to the driving method of the display panel, the implementation of the display panel can refer to the implementation of the driving method, and the repeated parts will not be described herein.

[0138] Based on the same inventive concept, the embodiment of the present application further provides a display device, which, as shown in the drawings, comprises the driving device and the display panel provided by the embodiment of the present application. The principle of solving the problem of the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be described herein. ​

[0139] In the implementation, the display device provided by the embodiment of the present application can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, and will not be described herein, nor should it be regarded as a limitation on the present application.

[0140] ​The display panel, the driving method, the driving device and the display device provided by the embodiment of the present application can charge the sub-pixel through the periodic cycle by loading the gate-on signal to the gate signal line, loading the corresponding data signal to each source input signal line in turn and loading the on control signal to each control signal line in turn in each data input stage of a charging period. In addition, the order of loading the on control signal to at least part of the control signal line is different in the adjacent two data input stages, and the on control signals loaded on the same control signal line are separated by at least one time length of the on control signal, so that the on control signals loaded on different control signal lines in the data input stage can be adjusted in sequence, and the on control signals on the same control signal line are not adjacent. In addition, the number of the on control signals with the same loading order corresponding to each control signal line is the same in the charging period, so that the voltage variation of each color sub-pixel in a charging period is equal, that is, the coupling interference of each color sub-pixel is equal, and the display uniformity is improved.

[0141] Obviously, various modifications and variations of the present application can be made by those skilled in the art without departing from the spirit and scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A driving method for a display panel, characterized in that, The method is used to improve the display uniformity of the same frame of a display panel with a cutout structure. The display panel includes an array substrate. The array substrate includes a cutout structure, a display area, a first non-display area, and a second non-display area. The first non-display area surrounds the cutout structure, the display area surrounds the first non-display area, and the second non-display area surrounds the display area. The display area includes: multiple pixel units, multiple gate signal lines, and multiple data signal lines; wherein, each pixel unit includes M sub-pixels of different colors, M≥3 and is an integer; one column of sub-pixels corresponds to one data signal line; the multiple data signal lines include multiple first data signal lines passing through the first non-display area, each first data signal line includes a first sub-data signal line located in the display area and a second sub-data signal line located in the first non-display area, and the first sub-data signal line and the second sub-data signal line of the same first data signal line are electrically connected; The second non-display area includes: multiple source input signal lines, multiple multiplexers, and connections to all of the multiplexers. There are 1 control signal line; where N is the number of adjacent pixel units corresponding to two adjacent multiplexers; and one source input signal line is connected to a multiplexer via a multiplexer. A data signal line is electrically connected; N ≥ 2 and is an even number; The driving method includes: In each data input phase of each charging cycle, a gate enable signal is applied to the gate signal line, a corresponding data signal is sequentially applied to each of the source input signal lines, and an enable control signal is sequentially applied to each of the control signal lines to charge the sub-pixel. Each of the charging cycles includes Y data input stages, where M≤Y≤3K and Y is an integer, and K≥1 and K is an integer; In every two adjacent data input phases, at least some control signal lines are loaded with start control signals in different orders, and the start control signals loaded on the same control signal line are spaced apart by at least the duration of the start control signal. Furthermore, for the start control signal of the same loading order in each of the data input stages, the number of start control signals of the same loading order corresponding to each control signal line is the same in the same charging cycle, so that for the same frame, the total voltage change of each color sub-pixel in the same charging cycle is equal. The data input phase is a time period during which the gate enable signal is applied to one of the gate signal lines in the display panel; or, the data input phase is a one-frame scan time period during which the gate enable signal is applied sequentially to each of the gate signal lines in the display panel.

2. The driving method as described in claim 1, characterized in that, M=3, N=2, Y=3, the pixel unit includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; The three control signal lines include: a first control signal line corresponding to the data signal line connected to the first sub-pixel, a second control signal line corresponding to the data signal line connected to the second sub-pixel, and a third control signal line corresponding to the data signal line connected to the third sub-pixel; During the first data input phase of the charging cycle, enable control signals are sequentially applied to the first to third control signal lines; In the second data input stage, the enable control signal is sequentially applied to the second control signal line, the third control signal line, and the first control signal line; In the third data input stage, the start control signal is applied sequentially to the third control signal line, the first control signal line, and the second control signal line.

3. The driving method as described in claim 1, characterized in that, M=3, N=2, Y=6, the pixel unit includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; The three control signal lines include: a first control signal line corresponding to the data signal line connected to the first sub-pixel, a second control signal line corresponding to the data signal line connected to the second sub-pixel, and a third control signal line corresponding to the data signal line connected to the third sub-pixel; During the first data input phase of the charging cycle, enable control signals are sequentially applied to the first to third control signal lines; In the second data input stage, the enable control signal is sequentially applied to the second control signal line, the third control signal line, and the first control signal line; In the third data input stage, the enable control signal is applied sequentially to the third control signal line, the first control signal line, and the second control signal line. In the fourth data input stage, the third control signal line, the second control signal line, and the first control signal line are loaded with the start control signal; In the fifth data input stage, the enable control signal is sequentially applied to the second control signal line, the first control signal line, and the third control signal line; In the sixth data input stage, the start control signal is applied sequentially to the first control signal line, the third control signal line, and the second control signal line.

4. The driving method as described in claim 1, characterized in that, M=4, N=2, Y=4, the pixel unit includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel; The four control signal lines include: a first control signal line corresponding to the data signal line connected to the first sub-pixel, a second control signal line corresponding to the data signal line connected to the second sub-pixel, a third control signal line corresponding to the data signal line connected to the third sub-pixel, and a fourth control signal line corresponding to the data signal line connected to the fourth sub-pixel; During the first data input phase of the charging cycle, enable control signals are sequentially applied to the first to fourth control signal lines; In the second data input stage, the enable control signal is sequentially applied to the second control signal line, the third control signal line, the fourth control signal line, and the first control signal line; In the third data input stage, the enable control signal is sequentially applied to the third control signal line, the fourth control signal line, the first control signal line, and the second control signal line; In the fourth data input stage, the enable control signal is sequentially applied to the fourth control signal line, the first control signal line, the second control signal line, and the third control signal line.

5. The driving method according to any one of claims 2-4, characterized in that, When M=3, N=2, Y=3, the first data input stage to the third data input stage appear sequentially. When M=3, N=2, Y=6, the first data input stage to the sixth data input stage appear sequentially. When M=4, N=2, Y=4, the first data input stage to the fourth data input stage appear sequentially.

6. The driving method as described in claim 1, characterized in that, M=3, N=4, Y=6, the pixel unit includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; The six control signal lines include: a first control signal line and a fourth control signal line corresponding to the data signal line connected to the first sub-pixel; a second control signal line and a fifth control signal line corresponding to the data signal line connected to the second sub-pixel; and a third control signal line and a sixth control signal line corresponding to the data signal line connected to the third sub-pixel. During the first data input phase of the charging cycle, enable control signals are sequentially applied to the first to sixth control signal lines. In the second data input stage, the enable control signal is sequentially applied to the second control signal line, the third control signal line, the fourth control signal line, the fifth control signal line, the sixth control signal line, and the first control signal line; In the third data input stage, the enable control signal is sequentially applied to the third control signal line, the fourth control signal line, the fifth control signal line, the sixth control signal line, the first control signal line, and the second control signal line; In the fourth data input stage, the enable control signal is sequentially applied to the fourth control signal line, the fifth control signal line, the sixth control signal line, the first control signal line, the second control signal line, and the third control signal line; In the fifth data input stage, the enable control signal is sequentially applied to the fifth control signal line, the sixth control signal line, the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line; In the sixth data input stage, the start control signals are sequentially applied to the sixth control signal line, the first control signal line, the second control signal line, the third control signal line, the fourth control signal line, and the fifth control signal line.

7. The driving method as described in claim 1, characterized in that, M=4, N=4, Y=8, the pixel unit includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel; The eight control signal lines include: a first control signal line and a fifth control signal line corresponding to the data signal line connected to the first sub-pixel; a second control signal line and a sixth control signal line corresponding to the data signal line connected to the second sub-pixel; a third control signal line and a seventh control signal line corresponding to the data signal line connected to the third sub-pixel; and a fourth control signal line and an eighth control signal line corresponding to the data signal line connected to the fourth sub-pixel. During the first data input phase of the charging cycle, enable control signals are sequentially applied to the first to eighth control signal lines. In the second data input stage, the enable control signal is sequentially applied to the second control signal line, the third control signal line, the fourth control signal line, the fifth control signal line, the sixth control signal line, the seventh control signal line, the eighth control signal line, and the first control signal line; In the third data input stage, the enable control signal is sequentially applied to the third control signal line, the fourth control signal line, the fifth control signal line, the sixth control signal line, the seventh control signal line, the eighth control signal line, the first control signal line, and the second control signal line; In the fourth data input stage, the activation control signals are sequentially applied to the fourth control signal line, the fifth control signal line, the sixth control signal line, the seventh control signal line, the eighth control signal line, the first control signal line, the second control signal line, and the third control signal line. In the fifth data input stage, the activation control signals are sequentially applied to the fifth control signal line, the sixth control signal line, the seventh control signal line, the eighth control signal line, the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line. In the sixth data input stage, the activation control signals are sequentially applied to the sixth control signal line, the seventh control signal line, the eighth control signal line, the first control signal line, the second control signal line, the third control signal line, the third control signal line, and the fifth control signal line. In the seventh data input stage, the activation control signals are sequentially applied to the seventh control signal line, the eighth control signal line, the first control signal line, the second control signal line, the third control signal line, the fourth control signal line, the fifth control signal line, and the sixth control signal line. In the eighth data input stage, the enable control signals are sequentially applied to the eighth control signal line, the first control signal line, the second control signal line, the third control signal line, the fourth control signal line, the fifth control signal line, the sixth control signal line, and the seventh control signal line.

8. The driving method as described in claim 6 or 7, characterized in that, When M=3, N=4, and Y=6, the first data input stage to the sixth data input stage appear sequentially. When M=4, N=4, and Y=8, the first data input stage to the eighth data input stage appear sequentially.

9. The driving method as described in claim 1, characterized in that, At least two adjacent data input stages are separated by an interval time period; During the specified time interval, a gate cutoff signal is applied to the gate signal line, and a cutoff control signal is applied to each of the control signal lines.

10. The driving method as described in claim 9, characterized in that, The interval time period is set between each two adjacent data input stages.

11. A driving device for a display panel, characterized in that, The driving device is used to perform the steps of the driving method for the display panel as described in any one of claims 1-10.

12. A display panel, characterized in that, The driving method described in any one of claims 1-10 is used.

13. A display device, characterized in that, include: The driving device as claimed in claim 11 and the display panel as claimed in claim 12.

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