Method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure on a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming doped regions on the sidewalls and bottom surface of the recess and partially removing the doped regions to change the shape of the recess. The method also includes forming a source / drain structure on the remaining portion of the doped regions.

Description

Technical Field

[0001] This invention relates to a method for forming a semiconductor structure, and particularly to a method for forming a source / drain structure. Background Technology

[0002] Semiconductor devices are used in various electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements thereon.

[0003] One of the key drivers of improved computer performance is the high level of circuit integration. This is achieved by shrinking or reducing the size of devices on a given chip. Tolerances play a crucial role in reducing chip size.

[0004] However, while existing semiconductor manufacturing processes largely meet the intended purpose, they are not entirely satisfactory in all aspects as devices continue to shrink. Summary of the Invention

[0005] This invention includes a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a gate structure on a substrate, forming a recess in the substrate adjacent to the gate structure, forming a doped region on the sidewalls and bottom surface of the recess, partially removing the doped region to change the shape of the recess, and forming a source / drain structure on the remaining portion of the doped region.

[0006] This invention also includes a method for forming a semiconductor structure. The method includes forming a fin structure on a substrate. The fin structure has sloping sidewalls. The method also includes forming a gate structure on the fin structure, etching the fin structure to form a recess, implanting arsenic around the recess to form a doped region, etching the doped region to partially remove the doped region, and forming a source / drain structure on the remaining portion of the doped region.

[0007] This invention also includes a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate and having inclined sidewalls, a gate structure spanning the fin structure, and a source / drain structure formed within the fin structure. The source / drain structure includes a first region, a second region formed on the first region, and a third region formed on the second region. The phosphorus concentration in the second region is greater than the phosphorus concentration in the first region. The phosphorus concentration in the second region is greater than the phosphorus concentration in the third region. The semiconductor structure also includes an arsenic-doped region formed below the source / drain structure and in direct contact with the first region. Attached Figure Description

[0008] The various aspects of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only used for illustrative purposes. In fact, for the purpose of clear explanation, the dimensions of each feature may be arbitrarily enlarged or reduced.

[0009] Figures 1A to 1E Cross-sectional schematic diagrams of various stages in the fabrication of semiconductor structures are shown according to some embodiments.

[0010] Figure 2 A cross-sectional schematic diagram of a semiconductor structure is shown according to some embodiments.

[0011] Figure 3 A cross-sectional schematic diagram of a semiconductor structure is shown according to some embodiments.

[0012] Figure 4 A cross-sectional schematic diagram of a semiconductor structure is shown according to some embodiments.

[0013] Figures 5A to 5H Three-dimensional views of various stages in the fabrication of a semiconductor structure are shown according to some embodiments.

[0014] Figure 6 A perspective view of semiconductor structure 200a is shown according to some embodiments.

[0015] Figures 7A to 7C Three-dimensional views of various stages in the fabrication of a semiconductor structure are shown according to some embodiments.

[0016] Figures 8A to 8D Cross-sectional schematic diagrams of various stages in the fabrication of semiconductor structures are shown according to some embodiments.

[0017] Explanation of reference numerals in the attached figures:

[0018] 100, 100a, 100c, 300 ~ Semiconductor Structure

[0019] 102~Substrate

[0020] 104 gate structure

[0021] 106 ~ Gate Dielectric Layer

[0022] 108 ~ Gate electrode layer

[0023] 112 ~ Hard mask layer

[0024] 114 ~ Spacers

[0025] 116 - First dielectric layer of spacer

[0026] 118 - Second dielectric layer of spacer

[0027] 120 ~ the third dielectric layer of the spacer

[0028] 122, 322 ~ Depression

[0029] 122'~Modified concavity

[0030] 123 ~ Passage Area

[0031] 124 ~ Doped region

[0032] 124', 124a', 124b', 124c' – Residual portions of the doped region

[0033] 126, 126a, 126b, 126c – Source / Drain Structures

[0034] 128, 128a, 128b, 128c – First region of the source / drain structure

[0035] 130, 130a, 130b, 130c – Second region of the source / drain structure

[0036] 132, 132a, 132b, 132c – Third region of the source / drain structure

[0037] D, D1, D', D1' ~ Depth

[0038] 200, 200a ~ Semiconductor Structure

[0039] 202~Substrate

[0040] 203, 203b ~ Fin structure

[0041] 203', 203b' ~ etched fin structures

[0042] 204 Gate Structure

[0043] 205 ~ Isolation Structure

[0044] 206 ~ Gate Dielectric Layer

[0045] 208 ~ Gate electrode layer

[0046] 212 ~ Hard mask layer or hard mask structure

[0047] 214, 215, 215b – Spacers

[0048] 216, 217 – First dielectric layer of spacers

[0049] 218, 219 – Second dielectric layer of spacers

[0050] 220, 221 – Third dielectric layer of spacers

[0051] 222, 222b ~ Depression

[0052] 222'~Modified concavity

[0053] 224, 224a' ~ Doped Region

[0054] 224', 224b' ~ Residual portions of the doped region

[0055] 226, 226a, 226b, 326 – Source / Drain Structures

[0056] 228, 228a, 228b, 328 – First region of source / drain structure

[0057] 230, 230a, 230b, 330 – Second region of the source / drain structure

[0058] 232, 232a, 232b, 332 – Third region of the source / drain structure

[0059] 234 ~ Contact Etching Stop Layer

[0060] 236 - Interlayer Dielectric Layer

[0061] 238 ~ Metal gate structure

[0062] 240 ~ Gate Dielectric Layer

[0063] 242 ~ Work Function Metal Layer

[0064] 244 ~ Gate electrode layer

[0065] 246 ~ Contact

[0066] 324 ~ Doped layer

[0067] 324' ~ Residual portion of the doped layer Detailed Implementation

[0068] The following discloses many different implementations or examples of different feature components of the embodiments of the present invention. Specific elements and their arrangements are described below to illustrate the embodiments of the present invention. Of course, these embodiments are merely illustrative and should not be construed as limiting the scope of the embodiments of the present invention. For example, the specification mentions that a first feature component is formed on a second feature component, which includes embodiments where the first and second feature components are in direct contact, and also includes embodiments where there are other feature components between the first and second feature components, that is, the first and second feature components are not in direct contact. Furthermore, the embodiments of the present invention may repeat reference numerals and / or letters in various examples. The above repetition is for the purpose of brevity and clarity, and is not intended to limit the relationship between the various embodiments and / or configurations discussed.

[0069] Furthermore, spatially related terms may be used, such as "below," "below," "lower," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more elements or features in the illustrations and to one or more other elements or features. These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the figures. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn. It should be understood that in other embodiments, additional steps may be present before, during, or after the method, and some of the described steps may be replaced or omitted.

[0070] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure may include a gate structure formed on a substrate and a recess formed in the substrate adjacent to the gate structure. After forming the recess, a source / drain structure may be formed in the recess. Furthermore, two etching processes can be performed to form the recess, and the contour of the formed recess can be more easily controlled according to the design, thus improving the performance of the source / drain structure formed in the recess.

[0071] Figures 1A to 1E Cross-sectional schematic diagrams of various stages in manufacturing the semiconductor structure 100 are shown according to some embodiments. For example... Figure 1A As shown, according to some embodiments, a gate structure 104 is formed on a substrate 102.

[0072] The substrate 102 may be a semiconductor wafer (e.g., a silicon wafer). Alternatively or additionally, the substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0073] In some embodiments, substrate 102 includes structures such as doped regions, isolation features, interlayer dielectric (ILD) layers, and / or conductive features. Furthermore, substrate 102 may also include one or more material layers to be patterned. For example, the material layers may include silicon layers, dielectric layers, and / or doped polysilicon layers.

[0074] The gate structure 104 may be a dummy gate structure, which may be subsequently replaced by a metal gate structure. In some embodiments, the gate structure 104 includes a gate dielectric layer 106, a gate electrode layer 108 formed on the gate dielectric layer 106, and a hard mask layer 112 formed on the gate electrode layer 108.

[0075] In some embodiments, the gate dielectric layer 106 is formed of silicon oxide. In some embodiments, the gate dielectric layer 106 is formed of a high-k dielectric material, such as metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, or oxynitrides of metals. For example, high-k dielectric materials include, but are not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, titanium oxide, aluminum oxide, HfO2-Al2O3 alloys, or other suitable dielectric materials.

[0076] In some embodiments, the gate electrode layer 108 is formed of polysilicon. In some embodiments, the hard mask layer 112 is formed of silicon nitride. The hard mask layer 112 can be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), but other deposition processes may also be used in some other embodiments.

[0077] According to some embodiments, after forming the gate structure 104, spacers 114 are formed on the sidewalls of the gate structure 104 (e.g., ...). Figure 1A (As shown). In some embodiments, spacer 114 includes a first dielectric layer 116, a second dielectric layer 118, and a third dielectric layer 120. In some embodiments, the first dielectric layer 116 and the third dielectric layer 120 are oxide layers, and the second dielectric layer 118 is a nitride layer.

[0078] Next, according to some embodiments, such as Figure 1B As shown, a recess 122 is formed in a substrate 102 adjacent to the gate structure 104. In some embodiments, the substrate 102 is etched using a fluorine-based etchant in a dry etching process to form the recess 122. In some embodiments, the fluorine-based etchant used as the etchant includes BF2, CH2F2, or similar etchants. In some embodiments, fluorine residues are formed on the sidewalls and top surface of the recess 122. In some embodiments, the etchant further includes Cl2. In some embodiments, the step of forming the recess 122 further includes using He, Ar, or a combination thereof.

[0079] like Figure 1B As shown, the recess 122 formed by etching the substrate 102 can have a narrower bottom width and a wider top width. In other words, the lateral distance between the channel region 123 and the top of the recess 122 is smaller than the lateral distance between the channel region 123 and the bottom of the recess 122.

[0080] The aforementioned channel region 123 can be defined as the region in the substrate 102 directly below the gate structure 104. The lateral distance between the channel region 123 and the top of the recess 122 can be defined as the lateral distance between the edge of the channel region 123 and the recess 122 on the top surface of the substrate 102. Furthermore, the lateral distance between the channel region 123 and the bottom of the recess 122 can be defined as the average lateral distance between the channel region 123 and the bottom quarter of the recess 122. The bottom quarter of the recess 122 can be defined as the lowest quarter portion of the recess 122, which may have a depth D1 (e.g., ...). Figure 1B As shown in the figure, the depth D1 is approximately 1 / 4 of the total depth D of the entire depression 122.

[0081] In some embodiments, the difference between the lateral distance between the channel region 123 and the top of the recess 122 and the lateral distance between the channel region 123 and the bottom of the recess 122 is greater than about 3 nm.

[0082] According to some embodiments, such as Figure 1C As shown, after the recess 122 is formed, a doped region 124 is formed around the recess 122. In some embodiments, dopant is applied to the recess 122 via a planting process to form the doped region 124 on the sidewalls and bottom surface of the recess 122. In some embodiments, the dopant includes As, P, Sb, B, or similar dopant. In some embodiments, the doped region 124 is an arsenic-doped region.

[0083] In some embodiments, the dopant dose of the doped region 124 is approximately 1 x 10⁻⁶. 13 atoms / cm 2 Up to 1x10 16 atoms / cm 2 The dopant dosage in doped region 124 can be controlled to be sufficiently large so that doped region 124 can be etched more thoroughly in subsequent processes. However, the dopant dosage in doped region 124 should not be too large, otherwise the dopant may diffuse to other parts of the structure (e.g., channel region 123).

[0084] A dopant (e.g., As) may be doped from the top side of the substrate 102 to the portion below the recess 122 to form a doped region 124. In some embodiments, the bottom width of the doped region 124 is greater than the bottom width of the recess 122. In some embodiments, the distance between the top portion of the doped region 124 and the channel region 123 is substantially the same as the distance between the bottom portion of the doped region 124 and the channel region 123.

[0085] Next, according to some embodiments, such as Figure 1DAs shown, each doped region 124 is at least partially removed to form the modified recess 122'. In some embodiments, a chlorine-based etchant is used in a dry etching process to etch the doped regions 124 to form the modified recess 122'. Compared to Figure 1B The formation steps of the recess 122 shown, by first forming a doped region 124 and then partially removing the doped region 124 to form a modified recess 122', allow for easier control over the shape of the formed recess 122' according to the design. The formed modified recess 122' can have a relatively large bottom width, thus improving the performance of the source / drain structure subsequently formed in the modified recess 122' (which will be explained in detail later).

[0086] According to some embodiments, by partially removing the doped region 124, Figure 1D The modified depression 122' shown is larger than Figure 1B The recess 122 is shown. In some embodiments, the bottom width of the modified recess 122' is greater than the bottom width of the recess 122. In other words, the shape of the recess 122 is changed to form the modified recess 122', which has a wider width at its bottom. Therefore, according to some embodiments, the channel region 123 and Figure 1D The lateral distance between the bottoms of the modified recess 122' shown is less than that between the channel area 123 and... Figure 1B The lateral distance between the bottoms of the recesses 122 shown. The lateral distance between the channel region 123 and the bottom of the modified recess 122' can be defined as the average lateral distance between the channel region 123 and 1 / 4 of the bottom of the modified recess 122', the bottom of the modified recess 122' may have a depth D1', the depth D1' being approximately 1 / 4 of the total depth D' of the recess 122'.

[0087] In some embodiments, the lateral distance between the channel region 123 and the top of the modified recess 122' is less than the lateral distance between the channel region 123 and the bottom of the modified recess 122'. In some embodiments, the difference between the lateral distance between the channel region 123 and the top of the modified recess 122' and the lateral distance between the channel region 123 and the bottom of the modified recess 122' is about 1 nm to 2 nm. The lateral distance between the channel region 123 and the top of the modified recess 122' can be defined as the lateral distance between the edge of the channel region 123 and the modified recess 122' on the top surface of the substrate 102.

[0088] In some embodiments, the doped region 124 is an arsenic-doped region, which can be etched using a dry etching process. In some embodiments, the arsenic-doped region 124 is etched using a chlorine-based etchant, where the Cl in the etchant reacts with the substrate 102 to form silicon-chlorine bonds (Si-Cl bonding). Due to the charge imbalance caused by As in the doped region 124, the silicon-chlorine bonds can be broken quickly. Therefore, the etching reactivity of the substrate 102 can be improved. Furthermore, due to the presence of As in the doped region 124, the conformity of the formed modified recess 122' can also be improved, and thus the shape of the formed modified recess 122' can be more easily controlled. In addition, even if some chlorine residue remains on the modified recess 122', the performance of the source / drain structure formed in the modified recess 122' in subsequent processes will not be weakened by the chlorine residue.

[0089] Furthermore, as mentioned above, when etching the substrate 102 to form the recess 122, the formed recess 122 typically has a narrower bottom width (compared to its top width). In some embodiments, an arsenic-doped region 124 is formed after the recess 122 is formed, and the arsenic-doped region 124 is etched to form a modified recess 122' with a designed shape, because the etching of the arsenic-doped region 124 can have a higher etching rate (compared to the original undoped substrate 102) and is easier to control.

[0090] As mentioned above, due to the formation of the recess 122, some fluorine residue may remain on the top surface of the recess 122. In some embodiments, these fluorine residues are also removed when the doped region 124 is partially removed. Therefore, contamination caused by fluorine residues can be reduced.

[0091] like Figure 1D As shown, after the modified recess 122' is formed, some residual portions 124' of the doped regions remain on the sidewalls of the modified recess 122' and below the bottom surface of the modified recess 122'. In some embodiments, the thickness of the residual portions 124' of the doped regions gradually increases from the top to the bottom of the modified recess 122'. The residual portions 124' of the doped regions can be used as a masking layer to prevent atoms in the source / drain structure formed in the modified recess 122' in subsequent processes from diffusing into the channel region 123 (which will be described in detail below).

[0092] In some embodiments, the residual portion 124' of the doped region is annealed. More specifically, according to some embodiments, the residual portion 124' of the doped region is annealed to transform the amorphous structure into a crystalline structure. In some embodiments, the annealing process is an in-situ annealing process, which is performed in the same chamber as the subsequent processes used to form the source / drain structure. In some embodiments, the annealing process is performed at a temperature of about 600°C to 900°C for about 100 to 1000 seconds. The annealing process can stabilize the dopant distribution in the residual portion 124' of the doped region. Furthermore, the above temperature needs to be high enough to reduce the resistance of the residual portion 124' of the doped region so that it can be subsequently used as part of the source / drain structure.

[0093] Next, according to some embodiments, such as Figure 1E As shown, a source / drain structure 126 is formed in the modified recess 122'. In some embodiments, the residual portion 124' of the doped region (e.g., as shown) Figure 1D (As shown) the crystallization annealing process and the source / drain structure 126 (e.g., as shown) Figure 1E The formation steps (shown) are performed within the same cavity. As mentioned earlier, the modified recess 122' has a relatively large bottom width, and therefore the source / drain structure 126 formed in the modified recess 122' also has a large bottom width. Therefore, the distance between the channel region 123 at the top and the source / drain structure 126, and the distance between the channel region 123 at the bottom and the source / drain structure 126, are approximately equal or have a relatively small difference (compared to the recess 122), thereby improving the current efficiency of the formed semiconductor structure.

[0094] More specifically, the distance between the channel region 123 and the top of the source / drain structure 126 is approximately equal to the distance between the channel region 123 and the top of the aforementioned modified recess 122', and the distance between the channel region 123 and the bottom of the source / drain structure 126 is approximately equal to the distance between the channel region 123 and the bottom of the aforementioned modified recess 122'.

[0095] In some embodiments, the source / drain structure 126 is a raised source / drain structure with a height of approximately 3 nm to 10 nm. The height of the raised source / drain structure can be defined as the height measured from the top of the raised source / drain structure to the top surface of the substrate 102.

[0096] In some embodiments, the source / drain structure 126 includes a first region 128, a second region 130 on the first region 128, and a third region 132 on the second region 130. Furthermore, the residual portion 124' of the doped region can also be considered part of the source / drain structure 126.

[0097] In some embodiments, the first region 128, the second region 130, and the third region 132 each include a dopant (e.g., phosphorus (P), boron (B), arsenic (As), antimony (Sb), or a similar dopant). In some embodiments, the first region 128, the second region 130, and the third region 132 are all phosphorus-doped regions. In some embodiments, epitaxial growth is performed in an epitaxial growth cavity to sequentially form the first region 128, the second region 130, and the third region 132.

[0098] In some embodiments, the first region 128 is formed of phosphorus-doped silicon (P-doped Si), arsenic-doped silicon phosphide (As-doped SiP), or phosphorus-doped silicon arsenide (P-doped SiAs). In some embodiments, a SiP layer is epitaxially grown on the residual portion 124' of the doped region to form the first region 128. According to some embodiments, after the SiP layer is formed, some arsenic in the residual portion 124' of the doped region diffuses into the outer region of the first region 128, such that the outer region of the first region 128 includes arsenic, but the inner region of the first region 128 does not contain arsenic. The outer region of the first region 128 can be defined as the side that is in direct contact with the residual portion 124' of the doped region. On the other hand, the inner region of the first region 128 can be defined as the side that is in direct contact with the second region 130.

[0099] In some embodiments, the phosphorus concentration in the first region 128 is approximately 1 x 10⁻⁶. 19 Up to 1x10 21 atoms / cm 3 In some embodiments, a SiP layer is epitaxially grown on the first region 128 to form the second region 130. In some embodiments, the phosphorus concentration in the second region 130 is greater than the phosphorus concentration in the first region 128. In some embodiments, the phosphorus concentration in the second region 130 is approximately 1 x 10⁻⁶. 20 Up to 5x10 21 atoms / cm 3 In some embodiments, the subsequently formed contact (not shown) Figure 1E (China) Direct contact with Zone 2, 130.

[0100] In some embodiments, a material layer is epitaxially grown on the second region 130 to form the third region 132. According to some embodiments, such as... Figure 1EAs shown, the top surface of the second region 130 is completely covered by the third region 132. The third region 132 can be considered a capping layer, which can be configured to prevent out-diffusion of the second region 130. More specifically, the third region 132 can be formed to prevent high-concentration dopants (e.g., phosphorus) in the second region 130 from diffusing to other regions of the semiconductor structure. In some embodiments, the third region 132 is formed of silicon, phosphorus-doped silicon-germanium (P-doped SiGe), or silicon phosphide. In some embodiments, the phosphorus concentration in the third region 132 is lower than the phosphorus concentration in the second region 130. In some embodiments, the phosphorus concentration in the third region 132 is about 1 x 10⁻⁶. 20 atoms / cm 3 Up to 3x10 21 atoms / cm 3 .

[0101] As described above, the residual portion 124' of the doped region can be used as a shielding layer to prevent dopants in the source / drain structure 126 from diffusing into the channel region 123 below the gate structure 104. For example, the source / drain structure 126, which may be formed of highly doped SiP, is surrounded by the residual portion 124' of the doped region. Therefore, the residual portion 124' of the doped region can physically block or at least slow down the diffusion of phosphorus atoms into the channel region 123. Furthermore, since the diffusivity of arsenic atoms is lower than that of phosphorus atoms, the function of the channel region 123 may not be weakened by the diffusion of arsenic atoms in the residual portion 124' of the doped region.

[0102] In some embodiments, the thickness of the residual portion 124' of the doped region gradually increases from the top to the bottom of the source / drain structure 126. In some embodiments, the bottom of the source / drain structure 126 is completely covered or surrounded by the residual portion 124' of the doped region. The residual portion 124' of the doped region below the source / drain structure 126 prevents dopants or contaminants in the substrate 102 below the source / drain structure 126 from diffusing into the source / drain structure 126.

[0103] As described above, the semiconductor structure 100 includes a source / drain structure 126 adjacent to the gate structure 104. The source / drain structure 126 is formed in an enlarged modified recess 122' (the modified recess 122' has a larger width at the bottom). Therefore, the bottom of the source / drain structure 126 formed in the modified recess 122' can be closer to the channel region 123 below the gate structure 104, thereby improving the current efficiency of the formed semiconductor structure 100.

[0104] Figure 2A schematic cross-sectional view of semiconductor structure 100a is shown according to some embodiments. Semiconductor structure 100a may be similar to or the same as the aforementioned semiconductor structure 100, except that the residual portion of the doped region of semiconductor structure 100a remains only at the bottom of the source / drain structure. Some processes and materials used to form semiconductor structure 100a may be similar to or the same as those used to form semiconductor structure 100, and will not be repeated here.

[0105] For example, a process similar to that shown in Figures 1A to 1E can be performed. More specifically, a fluorine-based etchant can be used to form a recess (e.g., recess 122) in the substrate 102 adjacent to the gate structure 104. Figure 1B As shown), a doped region (e.g., doped region 124) can be formed in the recess (as shown). Figure 1C (As shown). Next, a chlorine-based etchant can be used to etch the doped region to form a modified recess, and a source / drain structure 126a is formed in the modified recess. Furthermore, according to some embodiments, such as Figure 2 As shown, the residual portion 124a' of the doped region is located below the source / drain structure 126a.

[0106] like Figure 2 As shown, with Figure 1E Unlike the residual portion 124' of the doped region shown, the residual portion 124a' of the doped region in semiconductor structure 100a remains at the bottom of source / drain structure 126a but not on the sidewalls of source / drain structure 126a. That is, according to some embodiments, the doped region formed around the sidewalls of the original recess (e.g., recess 122) is completely removed, thus the formed source / drain structure 126a can have a larger size. Furthermore, the residual portion 124a' of the doped region can be used as a shielding layer below the source / drain structure 126a to prevent dopants (e.g., dopants in well regions) in the underlying substrate 102 from diffusing into the source / drain structure 126a. For example, a P-type well region can be formed in substrate 102, and a dopant (e.g., B or Sb) can be doped into the P-type well region. The residual portion 124a' of the doped region can prevent the diffusion of dopants (e.g., B) in the P-type well region into the source / drain structure 126a and prevent the diffusion of dopants (e.g., P) in the source / drain structure 126a into the P-type well region.

[0107] In some embodiments, the source / drain structure 126a includes a first region 128a, a second region 130a, and a third region 132a. In some embodiments, the bottom surface of the first region 128a directly contacts the residual portion 124a' of the doped region. The processes and materials used to form the first region 128a, the second region 130a, and the third region 132a may be the same as those used to form the first region 128a, the second region 130a, and the third region 132a, and will not be repeated here. For example, the first region 128a may also have a region including As, which can diffuse from the doped region 124a' below the source / drain structure 126a to the As-containing region of the first region 128a.

[0108] Figure 3 A schematic cross-sectional view of semiconductor structure 100b is shown according to some embodiments. Semiconductor structure 100b may be similar to or the same as the aforementioned semiconductor structure 100, except that the residual portion of the doped region of semiconductor structure 100b extends further below the spacer 114. Some processes and materials used to form semiconductor structure 100b may be similar to or the same as those used to form semiconductor structure 100, and will not be described again here.

[0109] For example, fluorine-based etchants can be used. Figure 1A and 1B The process shown in the figure is to form a recess (e.g., recess 122) in the substrate 102 adjacent to the gate structure 104. Figure 1B (As shown). Next, a doped region can be formed in the depression. Unlike Figure 1C The doped region 124 shown, according to some embodiments, extends further below the spacer 114 in the semiconductor structure 100b (e.g., Figure 3 (As shown). After forming the doped region, the doped region can be etched using a chlorine-based etchant to form a modified recess, and a source / drain structure 126b can be formed in the modified recess surrounding the residual portion 124b' of the doped region.

[0110] like Figure 3 As shown, different Figure 1E The residual portion 124' of the doped region shown extends further below the spacer 114 into the sidewall of the source / drain structure 126b in the semiconductor structure 100b. That is, according to some embodiments, the doped region formed around the sidewall of the original recess (e.g., recess 122) is relatively thick, thus the formed source / drain structure 126b can have a larger size relative to the source / drain structure 126.

[0111] Similar to the source / drain structure 126, the source / drain structure 126b may also include a first region 128b, a second region 130b, and a third region 132b, and its process and materials may be the same as those used to form the first region 128, the second region 130, and the third region 132b, which will not be described again here.

[0112] Figure 4 A cross-sectional schematic diagram of semiconductor structure 100c is shown according to some embodiments. Semiconductor structure 100c may be similar to or the same as the aforementioned semiconductor structure 100b, except that the bottom of the source / drain structure 126c of semiconductor structure 100c is wider than the top of the source / drain structure 126c. Some processes and materials used to form semiconductor structure 100c may be similar to or the same as those used to form semiconductor structures 100, 100a, and 100b, and will not be described again here.

[0113] More specifically, when the doped region formed in the original recess is etched to form the modified recess, the bottom of the modified recess is wider than the top. Therefore, the bottom of the source / drain structure 126c formed in the modified recess is also wider than the top. Furthermore, similar to the semiconductor structure 100b, the residual portion 124c' of the doped region also extends below the spacer 114 formed on the sidewall of the gate structure 104.

[0114] Similar to the source / drain structure 126, the source / drain structure 126c may also include a first region 128c, a second region 130c, and a third region 132c, and its process and materials may be the same as those used to form the first region 128, the second region 130, and the third region 132, which will not be repeated here.

[0115] It should be noted that, although not explicitly shown in Figures 1A to 4 In this design, semiconductor structures 100, 100a, 100b, and 100c can be fin field-effect transistor (FinFET) structures. That is, substrate 102 can include fin structures and a gate structure 104 formed on the fin structures, and source / drain structures 126, 126a, 126b, and 126c can be formed within the fin structures. According to some embodiments, figures 5A to 5H show perspective views of various stages in the fabrication of semiconductor structure 200. Semiconductor structure 200 can be similar to the aforementioned semiconductor structures, except that the fin structures in semiconductor structure 200 are shown and labeled in the perspective views. Some processes and materials used to form semiconductor structure 200 can be similar to or the same as those used to form the aforementioned semiconductor structures 100, 100a, 100b, and 100c, and will not be repeated here.

[0116] In some embodiments, the semiconductor structure 200 is an N-type fin field-effect transistor structure. According to some embodiments, such as... Figure 5A As shown, a fin structure 203 is formed from a substrate 202. The substrate 202 may be similar to or the same as the substrate 102. In some embodiments, the fin structure 203 has a narrower top and a wider bottom, and thus has sloping sidewalls. In some embodiments, the sloping sidewalls of the fin structure 203 extend along a first direction, and the angle between the first direction and the top (or bottom) surface of the substrate 202 is about 82° to 88°.

[0117] According to some embodiments, after the fin structure 203 is formed, an isolation structure 205 is formed on the substrate 202, and the fin structure 203 is surrounded by the isolation structure 205 (e.g., Figure 5A (As shown).

[0118] An insulating layer may be deposited on the substrate 202 and etched to form an isolation structure 205. In some embodiments, the isolation structure 205 is formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low dielectric constant dielectric materials.

[0119] Next, according to some embodiments, such as Figure 5B As shown, a gate structure 204 is formed across the fin structure 203. The gate structure 204 may include a gate dielectric layer 206, a gate electrode layer 208, and a hard mask layer 212, which may be similar to or the same as the aforementioned gate dielectric layer 106, gate electrode layer 108, and hard mask layer 112.

[0120] According to some embodiments, after forming the gate structure 204, spacers 214 are formed on the sidewalls of the gate structure 204, and spacers 215 are formed on the sidewalls of the fin structure 203 (e.g., ...). Figure 5C (As shown). In some embodiments, spacer 214 includes a first dielectric layer 216, a second dielectric layer 218, and a third dielectric layer 220, and spacer 215 includes a first dielectric layer 217, a second dielectric layer 219, and a third dielectric layer 221. The materials used to form spacers 214 and 215 may be similar to or the same as the material used to form the aforementioned spacer 114, and will not be described again here.

[0121] According to some embodiments, after the spacers 214 and 215 are formed, the portion of the fin structure 203 not covered by the gate structure 204 is etched to form a recessed fin structure 203', and the recess 222 is formed between the spacers 215 (e.g., Figure 5D (As shown). The process used to form the depression 222 may be similar to or the same as that described above for forming the depression 122 (e.g. Figure 1BThe process is shown in the figure.

[0122] In some embodiments, a fluorine-based etchant is used to etch the fin structure 203 to form a recess 222 on the etched fin structure 203'. As mentioned above, the fin structure 203 may have a narrower top and a wider bottom, making it more difficult to remove the lower part of the fin structure 203. Therefore, the formed recess 222 may have a narrower bottom. That is, the distance between the bottommost portion of the recess 222 and the channel region (similar to channel region 123) below the gate structure 204 may be relatively large.

[0123] Therefore, according to some embodiments, such as Figure 5E As shown, a dopant (e.g., As) is implanted from the recess 222 to form a doped region 224. The process used to form the doped region 224 may be similar to or the same as the process used to form the doped region 124 described above, and will not be repeated here.

[0124] According to some embodiments, such as Figure 5F As shown, after forming the doped region 224, a process similar to that used to form the modified recess 122' is performed (e.g. Figure 1D Another etching process (shown) is used to form the modified recess 222'. In some embodiments, similar to Figure 1D As shown, the modified recess 222' is surrounded by the residual portion 224' of the doped region. Next, the residual portion 224' of the doped region is annealed. As mentioned above, the above annealing process can be an in-situ annealing process, which is performed in the same cavity as the subsequent process used to form the source / drain structure.

[0125] Next, according to some embodiments, such as Figure 5G As shown, a source / drain structure 226 is formed in the modified recess 222'. The process used to form the source / drain structure 226 may be similar to or the same as that used to form the source / drain structure 126 (e.g., Figure 1E The process shown (as illustrated) will not be repeated here. Figure 5G As shown, the source / drain structure 226 includes a first region 228, a second region 230, and a third region 232, which may be the same as the first region 128, the second region 130, and the third region 132.

[0126] According to some embodiments, such as Figure 5H As shown, after the source / drain structure 226 is formed, a contact etch stop layer (CESL) 234 is conformally formed on the substrate 102 to cover the source / drain structure 236, and an interlayer dielectric layer 236 is formed on the contact etch stop layer 234.

[0127] In some embodiments, the contact etch stop layer 234 is formed of silicon nitride, silicon oxynitride, and / or other suitable materials. The contact etch stop layer 234 may be formed using plasma-assisted chemical vapor deposition (PACVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or other suitable processes. The interlayer dielectric layer 236 may comprise multilayers formed of various materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable low-dielectric-constant dielectric materials). The interlayer dielectric layer 236 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0128] After the contact etch stop layer 234 and the interlayer dielectric layer 236 are formed, a polishing process can be performed until the top surface of the gate structure 204 is exposed. In some embodiments, a chemical mechanical polishing (CMP) process can be performed.

[0129] Next, according to some embodiments, such as Figure 5H As shown, a metal gate structure 238 replaces the gate structure 204. In some embodiments, the metal gate structure 238 includes a gate dielectric layer 240, a work function metal layer 242, and a gate electrode layer 244. In some embodiments, the gate dielectric layer 240 is formed of a high dielectric constant dielectric material, such as: metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, or metal oxynitride. For example, high dielectric constant dielectric materials include, but are not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, titanium oxide, aluminum oxide, HfO2-Al2O3 alloy, or other suitable dielectric materials.

[0130] According to some embodiments, a work function metal layer 242 is formed on top of the gate dielectric layer 240. The work function metal layer 242 can be customized to have an appropriate work function. In some embodiments, the gate electrode layer 244 is formed of a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, or other suitable materials.

[0131] According to some embodiments, such as Figure 5HAs shown, after forming the metal gate structure 238, a contact 246 is formed on the source / drain structure 236 and extends through the interlayer dielectric layer 236. Furthermore, according to some embodiments, the contact 246 extends through the third region 232 of the source / drain structure 236 and directly contacts the second region 230 of the source / drain structure 236. In some other embodiments (not shown in the figures), the contact 246 terminates on the third region 232 of the source / drain structure 236 and does not extend through the third region 232; therefore, the contact 246 does not directly contact the second region 230 of the source / drain structure 236.

[0132] In some embodiments, contact 246 comprises aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, nickel, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. In some embodiments, contact 246 comprises a titanium nitride layer and tungsten formed on the titanium nitride layer.

[0133] Contact 246 may also include a liner and / or a barrier layer. For example, a liner (not shown in the figure) may be formed on the sidewalls and bottom of the contact trench. The liner may be formed of silicon nitride, but any other suitable dielectric material may be used as an alternative. The liner may be formed using a plasma-assisted chemical vapor deposition process, but other suitable processes (e.g., physical vapor deposition or thermal processes) may be used as alternatives. A barrier layer (not shown in the figure) may be formed on the liner (if a liner is formed) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using chemical vapor deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted physical vapor deposition, atomic layer deposition, or any other suitable deposition process. The barrier layer may be formed of tantalum nitride, but other materials may be used, such as tantalum, titanium, titanium nitride, or similar materials.

[0134] Figure 6 A perspective view of a semiconductor structure 200a is shown according to some embodiments. The semiconductor structure 200a may be similar to or identical to the aforementioned semiconductor structure 200, except that the residual portion 224a' of the doped region of the semiconductor structure 200a extends below the spacer 215. Some processes and materials used to form the semiconductor structure 200a may be similar to or identical to those used to form the semiconductor structure 200, and will not be repeated here.

[0135] like Figure 6 As shown, different Figure 5HThe residual portion 224' of the doped region shown in the figure extends further below the spacer 215 in the semiconductor structure 200a. That is, the residual portion 224a' of the doped region extends further into the isolation structure 205. In some embodiments, the residual portion 224a' of the doped region also extends into the fin structure below the spacer 214 (not shown in the figure). As mentioned above, the residual portion 224a' of the doped region can be used as a shielding layer to prevent dopants in the source / drain structure 226a from entering the channel region below the metal gate structure 238.

[0136] Although semiconductor structures 200 and 200a have contact etch stop layers 234 (such as...) Figure 5H as well as Figure 6 (as shown), but in some embodiments, a contact etch stop layer 234 may or may not be formed as appropriate.

[0137] Figures 7A to 7C illustrate perspective views of various stages in the fabrication of semiconductor structure 200b according to some embodiments. Semiconductor structure 200b may be similar to the aforementioned semiconductor structures 200 and 200a, except that the fin structures in semiconductor structure 200b are only partially etched and thus have a greater height. Some processes and materials used to form semiconductor structure 200b may be similar to or the same as those used to form semiconductor structures 200 and 200a, and will not be repeated here.

[0138] Can proceed to 5A Figure 5C The process described herein will not be repeated here. More specifically, according to some embodiments, a fin structure 203b is formed on the substrate 202, and an isolation structure 205 is formed around the fin structure 203b. Next, according to some embodiments, a gate structure 204 (including a gate dielectric layer 206, a gate electrode layer 208, and a hard mask structure 212) is formed across the fin structure 203b, and spacers 214 (including a first dielectric layer 216, a second dielectric layer 218, and a third dielectric layer 220) are formed on the sidewalls of the gate structure 204.

[0139] Next, according to some embodiments, such as Figure 7A As shown, spacers 215b are formed on the bottom of the sidewall of the fin structure 203b. Similar to... Figure 5C The spacer 215 shown is etched into the top of the spacer to form spacer 215b. In some embodiments, spacer 215b also includes a first dielectric layer 217, a second dielectric layer 219, and a third dielectric layer 221.

[0140] Next, according to some embodiments, such as Figure 7BAs shown, the fin structure 203b is etched to form the etched fin structure 203b', and a recess 222b similar to the aforementioned recess 122 is formed. In some embodiments, the bottom portion of the recess 222b is higher than the top surface of the spacer 215b. The process used to etch the fin structure 203b may be similar to or the same as the process used to etch the fin structure 203 described above, and will not be repeated here.

[0141] According to some embodiments, such as Figure 7C As shown, after forming the etched fin structure 203b', the processes shown in Figures 5D to 5H can be performed to form the semiconductor structure 200b. More specifically, according to some embodiments, a doped region is formed around the recess 222b, and the doped region is etched to form the modified recess and the residual portion 224b' of the doped region. Next, according to some embodiments, such as Figure 7C As shown, the residual portion 224b' of the doped region is annealed, and a source / drain structure 226b is formed in the modified recess.

[0142] like Figure 7C As shown, the source / drain structure 226b includes a first region 228b, a second region 230b, and a third region 232b, which may be similar to the aforementioned first region 228, second region 230, and third region 232, except that the source / drain structure 226b is formed around the etched fin structure 203b'.

[0143] According to some embodiments, such as Figure 7C As shown, after forming the source / drain structure 226b, a contact etch stop layer 234 and an interlayer dielectric layer 236 are formed, and the gate structure 204 is replaced by a metal gate structure 238. Similarly, the metal gate structure 238 includes a gate dielectric layer 240, a work function metal layer 242, and a gate electrode layer 244. According to some embodiments, after forming the metal gate structure 238, a contact 246 is formed on the source / drain structure 236b and extends through the interlayer dielectric layer 236. Furthermore, according to some embodiments, the contact 246 extends through the third region 232b of the source / drain structure 236b and directly contacts the second region 230b of the source / drain structure 236b. According to some embodiments, figures 8A to 8D show cross-sectional schematic diagrams of various stages in fabricating the semiconductor structure 300. The semiconductor structure 300 may be similar to the semiconductor structure 100, except that the doped regions of the semiconductor structure 300 are deposited onto the recess rather than being doped from the recess into the substrate.

[0144] More specifically, according to some embodiments, such as Figure 8AAs shown, the recess 322 is formed in the substrate 102 and adjacent to the spacer 114 formed on the sidewall of the gate structure 104. According to some embodiments, the substrate 102 is etched using a fluorine-based etchant to form the recess 322. According to some embodiments, such as... Figure 8B As shown, after forming the recess 322, a doped layer 324 is formed to cover the recess 322. In some embodiments, the doped layer 324 is a SiAs layer. In some embodiments, the thickness of the doped layer 324 may be from about 30 nm to 130 nm. The doped layer 324 needs to be thick enough so that the subsequently formed modified recess can have a large bottom width. The doped layer 324 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes.

[0145] Next, according to some embodiments, such as Figure 8C As shown, the doped layer 324 is partially removed to form the modified recess 322' and the remaining portion 324' of the doped layer. Next, according to some embodiments, such as... Figure 8D As shown, a source / drain structure 326 is formed in the modified recess 322'.

[0146] Specifically, similar to the aforementioned doped region 124, the removal of the doped layer 324 is easier to control. Therefore, the shape of the modified recess 322' formed by partially removing the doped layer 324 is easier to control. Consequently, the shape of the source / drain structure 326 formed in the modified recess 322' is easier to control, and the performance of the semiconductor structure 300 including the source / drain structure 326 can be improved. Furthermore, the residual portion 324' of the doped layer surrounds the source / drain structure 326, thus preventing dopant diffusion from the source / drain structure 326 into the channel region below the gate structure 104.

[0147] As mentioned earlier, the source / drain structures 126, 126a, 126b, 126c, 226, 226a, 226b, and 326 are formed in modified recesses, and the modified recesses are formed by etching the doped regions / doped layers. Therefore, the shapes of the source / drain structures 126, 126a, 126b, 126c, 226, 226a, 226b, and 326 can be more easily controlled. For example, the source / drain structures can have a relatively large bottom width, thus improving the current efficiency of the source / drain structures. Therefore, the threshold voltage and subthreshold slope can be reduced. In particular, forming a recess with a wide bottom width is more difficult for fin field-effect transistor structures such as semiconductor structures 200, 200a, and 200b compared to planar structures, especially when the fins have sloping sidewalls. Therefore, by forming doped regions and partially removing them to form modified recesses, the shape of the source / drain structure can be more easily controlled and the performance of the semiconductor structure can be improved.

[0148] Furthermore, the top shapes of the formed source / drain structures 126, 126a, 126b, 126c, 226, 226a, 226b, and 326 can be designed to reduce problems such as the short channel effect and drain-induced barrier lowering (DIBL).

[0149] Furthermore, the original recesses formed by fluorine-based etching may have fluorine residues remaining on the recesses. According to some embodiments, the etching process used to form the modified recesses can remove these residues. In some embodiments, the residual portion of the doped region beneath the source / drain structure is used as a masking layer, so that contaminants beneath the source / drain structure do not enter the source / drain structure in subsequent processes. Additionally, the residual portion of the doped region around the sidewalls of the source / drain structure can be used as a masking layer to prevent dopants in the source / drain structure from entering the channel region in subsequent processes.

[0150] Embodiments of forming a semiconductor structure are provided. The semiconductor structure may include source / drain structures formed in a modified recess and adjacent to a gate structure. An original recess may be formed first, and a doped layer / doped region may be formed within the recess. Next, the doped layer / doped region may be partially removed to form the modified recess. Because the modified recess is formed by etching the doped layer / doped region, the shape of the modified recess can be more easily controlled, and the source / drain structures formed in the modified recess also have the designed modified shape, thus improving the performance of the semiconductor structure including the source / drain structures.

[0151] Some embodiments provide methods for forming semiconductor structures. These methods include forming a gate structure on a substrate and forming a recess in the substrate adjacent to the gate structure. The methods also include forming doped regions on the sidewalls and bottom surface of the recess and partially removing the doped regions to change the shape of the recess. The methods further include forming source / drain structures on the remaining portion of the doped regions.

[0152] In some embodiments, a doped region is formed by implanting arsenic (As) into the recessed sidewalls and bottom surface.

[0153] In some embodiments, the arsenic in the residual portion of the doped region diffuses further into the source / drain structure.

[0154] In some embodiments, a fluorine-based etchant is used to etch the substrate to form a recess.

[0155] In some embodiments, the residual portion of the pre-annealed doped region is used to form the source / drain structure.

[0156] In some embodiments, a source / drain structure is formed in the cavity, and the residual portion of the in-situ annealed doped region is also present in the same cavity.

[0157] In some embodiments, the doped region is a SiAs layer formed on the sidewalls and bottom surface of the depression by a chemical vapor deposition process.

[0158] In some embodiments, the residual portion of the doped region directly contacts the sidewalls and bottom surface of the source / drain structure.

[0159] Some embodiments provide methods for forming semiconductor structures. These methods include forming a fin structure with sloping sidewalls on a substrate and forming a gate structure on the fin structure. The methods also include etching the fin structure to form a recess and implanting arsenic around the recess to form a doped region. The methods further include etching the doped region to partially remove the doped region and forming a source / drain structure on the remaining portion of the doped region.

[0160] In some embodiments, a fluorine-based etchant is used to etch the fin structure to form a recess.

[0161] In some embodiments, the annealing step is performed on the residual portion of the pre-annealed doped region that forms the source / drain structure, at a temperature of about 600°C to 900°C.

[0162] In some embodiments, a chlorine-based etchant is used to etch the doped region to enlarge the depression.

[0163] In some embodiments, the source / drain structure includes a first region, a second region formed on the first region, and a third region formed on the second region, wherein the phosphorus concentration in the second region is greater than the phosphorus concentration in the first region, and arsenic in the doped region diffuses into the first region.

[0164] In some embodiments, the doped region surrounds the sidewalls and bottom surface of the source / drain structure.

[0165] In some embodiments, the angle between the inclined sidewall and the bottom surface of the substrate is approximately 82 to 88 degrees.

[0166] Some embodiments provide a semiconductor structure. This semiconductor structure includes a fin structure formed on a substrate and having sloping sidewalls, and a gate structure spanning the fin structure. The semiconductor structure also includes a source / drain structure formed within the fin structure. Furthermore, the source / drain structure includes a first region, a second region formed on the first region, and a third region formed on the second region. Additionally, the phosphorus concentration in the second region is greater than the phosphorus concentration in the first region, and the phosphorus concentration in the second region is greater than the phosphorus concentration in the third region. The semiconductor structure also includes an arsenic-doped region formed beneath the source / drain structure and in direct contact with the first region.

[0167] In some embodiments, the outer region of the first region includes arsenic.

[0168] In some embodiments, the arsenic-doped region directly contacts the sidewalls and bottom surface of the source / drain structure.

[0169] In some embodiments, the bottom width of the source / drain structure is greater than the top width of the source / drain structure, and the angle between one of these inclined sidewalls and the bottom surface of the substrate is about 82 to 88 degrees.

[0170] In some embodiments, the semiconductor structure further includes a contact that passes through the third region of the source / drain structure and directly contacts the second region of the source / drain structure.

[0171] The aforementioned fins can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography with a self-aligned process, which can result in a pattern with a smaller pitch, for example, than that obtained using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins.

[0172] The foregoing description outlines the feature components of many embodiments, enabling those skilled in the art to better understand the corresponding detailed description. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive concept and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive concept and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: A gate structure is formed on an isolation structure of a substrate; A recess is formed in the substrate and adjacent to the gate structure; A doped region is formed on one sidewall and one bottom surface of the depression; Partially remove the doped region to change the shape of the depression; Annealing a residual portion of the doped region; as well as After annealing the residual portion of the doped region, a source / drain structure is formed on the residual portion of the doped region, wherein the residual portion of the doped region separates the source / drain structure from the isolation structure. The source / drain structure is formed in a cavity, and the residual portion of the doped region is annealed in situ in the cavity.

2. The method of forming a semiconductor structure as claimed in claim 1, wherein the doped region is formed by implanting arsenic into the sidewalls and bottom surface of the recess.

3. The method of forming a semiconductor structure as claimed in claim 2, wherein the arsenic in the residual portion of the doped region diffuses into the source / drain structure.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein the substrate is etched using a fluorine-based etchant to form the recess.

5. The method of forming a semiconductor structure as claimed in claim 1, wherein the doped region is a SiAs layer formed on the sidewall and bottom surface of the recess via a chemical vapor deposition process.

6. The method of forming a semiconductor structure as claimed in claim 1, wherein the residual portion of the doped region directly contacts a sidewall and a bottom surface of the source / drain structure.

7. The method of forming a semiconductor structure as claimed in claim 1, wherein the source / drain structure is buried in the doped region.

8. The method for forming a semiconductor structure as described in claim 1, further comprising: A fin structure is formed from this substrate. The gate structure is formed across the fin structure, and the recess is formed in the fin structure.

9. A method for forming a semiconductor structure, comprising: A fin structure with an inclined sidewall is formed on a substrate and surrounded by an isolation structure; A gate structure is formed on the fin structure; The fin structure was etched to create a recess; Arsenic was implanted around the depression to form a doped region; The doped region is etched to partially remove the doped region; as well as A source / drain structure is formed on a residual portion of the doped region, wherein the residual portion of the doped region separates the source / drain structure from the isolation structure.

10. The method of forming a semiconductor structure as claimed in claim 9, wherein the fin structure is etched using a fluorine-based etchant to form the recess.

11. The method of forming a semiconductor structure as described in claim 9, further comprising: The remaining portion of the doped region is annealed before the source / drain structure is formed, wherein the annealing is performed at a temperature of 600°C to 900°C.

12. The method of forming a semiconductor structure as claimed in claim 11, wherein the doped region is etched using a chlorine-based etchant to enlarge the recess.

13. The method of forming a semiconductor structure as claimed in claim 9, wherein the source / drain structure comprises: First District; A second region, formed above the first region, wherein the phosphorus concentration in the second region is greater than the phosphorus concentration in the first region; and A third zone, formed above the second zone, Arsenic in the doped region diffuses into the first region.

14. The method of forming a semiconductor structure as claimed in claim 9, wherein the doped region surrounds one sidewall and a bottom surface of the source / drain structure.

15. The method of forming a semiconductor structure as claimed in claim 9, wherein the angle between the inclined sidewall and a bottom surface of the substrate is 82 degrees to 88 degrees.

16. A method for forming a semiconductor structure, comprising: A fin structure is formed on a substrate and surrounded by an isolation structure; A gate structure is formed across the fin structure to define a channel region within the fin structure; The fin structure is etched to form a depression; Arsenic was implanted around the depression to form a doped region; The doped region is partially etched to form a modified depression; as well as A source / drain structure is formed in the modified recess, wherein the doped region separates the source / drain structure from the isolation structure. The lateral distance between the channel area and the bottom of the altered depression is less than the lateral distance between the channel area and the bottom of the depression.

17. The method of forming a semiconductor structure as described in claim 16, further comprising: The doped region is annealed before the source / drain structure is formed.

18. The method of forming a semiconductor structure as claimed in claim 16, wherein the source / drain structure comprises: First District; A second region is formed on top of the first region, wherein the phosphorus concentration in the second region is greater than the phosphorus concentration in the first region; as well as A third region is formed above the second region, wherein the phosphorus concentration in the second region is greater than the phosphorus concentration in the third region.

19. The method of forming a semiconductor structure as claimed in claim 18, wherein the arsenic in the doped region diffuses into the first region.

20. The method of forming a semiconductor structure as described in claim 19, further comprising: A contact is formed that passes through the third region of the source / drain structure and directly contacts the second region of the source / drain structure.

21. A semiconductor structure, comprising: A fin structure protrudes from a substrate; An isolation structure is formed around the fin structure; A gate structure is formed across the fin structure; An arsenic-doped region is formed in the fin structure, wherein the two sidewalls of the arsenic-doped region extend upward and meet at the highest point of the arsenic-doped region. as well as A source / drain structure is formed on the arsenic-doped region, wherein the bottom of the arsenic-doped region is lower than the bottom of the source / drain structure, and the arsenic-doped region separates the source / drain structure from the isolation structure, wherein the source / drain structure covers the two sidewalls of the arsenic-doped region, and the bottom surface of the arsenic-doped region is higher than the top surface of the isolation structure.

22. The semiconductor structure of claim 21, wherein a bottom surface of the isolation structure is lower than the bottommost part of the arsenic-doped region.

23. The semiconductor structure of claim 21, wherein the source / drain structure further comprises: A first region is formed on top of this arsenic-doped region; A second region, formed above the first region, wherein the phosphorus concentration in the second region is greater than the phosphorus concentration in the first region; and A third region is formed above the second region, wherein the phosphorus concentration in the second region is greater than the phosphorus concentration in the third region.

24. The semiconductor structure of claim 23, wherein an outer region of the first region comprises arsenic.

25. The semiconductor structure of claim 23, further comprising: Upon contact, it passes through the third region of the source / drain structure and directly contacts the second region of the source / drain structure.

26. A semiconductor structure comprising: A fin structure protrudes from a substrate; An isolation structure is formed around the fin structure; A gate structure is formed to span the fin structure and extend over the isolation structure; A source / drain structure is formed on this fin structure; as well as An arsenic-doped region is sandwiched between the bottom of the fin structure and the source / drain structure and separates the source / drain structure from the isolation structure. The two sidewalls of the arsenic-doped region extend upward and meet at the highest point of the arsenic-doped region. The source / drain structure covers the two sidewalls of the arsenic-doped region, and the bottom surface of the arsenic-doped region is higher than the top surface of the isolation structure.

27. The semiconductor structure of claim 26, further comprising: Multiple spacers are formed on the sidewalls of the source / drain structure. The spacer is in direct contact with the arsenic-doped region.

28. The semiconductor structure of claim 26, further comprising: Multiple spacers are formed on the sidewalls of the source / drain structure. One top of the arsenic-doped region is higher than one top of the spacer.

29. The semiconductor structure of claim 28, wherein a bottom of the arsenic-doped region is lower than the top of the plurality of spacers.

30. A semiconductor structure comprising: A gate structure is formed on a channel region and an isolation structure of a substrate; An arsenic-doped region is formed in the substrate and adjacent to the channel region, wherein the two sidewalls of the arsenic-doped region extend upward and meet at the highest point of the arsenic-doped region. as well as A source / drain structure is formed on the arsenic-doped region, wherein the arsenic-doped region separates the source / drain structure from the isolation structure. The bottom of the source / drain structure directly contacts the arsenic-doped region, the source / drain structure covers the two sidewalls of the arsenic-doped region, and the bottom surface of the arsenic-doped region is higher than the top surface of the isolation structure.

31. The semiconductor structure of claim 30, wherein the arsenic-doped region has a curved bottom surface.

32. The semiconductor structure of claim 30, further comprising: A spacer is formed on one sidewall of the gate structure, wherein the sidewall of the spacer is in direct contact with the arsenic-doped region.

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