Power packaging with multiple molding compounds

Abstract

A semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first portion of the lead frame, and a second power semiconductor device mounted on a second portion of the lead frame. The first power semiconductor device is encapsulated by a first molding compound. The second power semiconductor device is encapsulated by a second molding compound. The first molding compound and the second molding compound are substantially separated from each other. The lead frame includes an intermediate portion arranged between the first portion and the second portion. The intermediate portion is not covered by the first molding compound or by the second molding compound.

Description

Technical Field

[0001] The present disclosure relates generally to the art of semiconductor device packaging, and more particularly to aspects of packaging power semiconductor devices that provide product-to-system improvements and high power dissipation capabilities. Background Art

[0002] Semiconductor device manufacturers are constantly striving to increase the performance of their products while reducing their manufacturing and system integration costs. The performance of semiconductor devices depends on the heat dissipation capabilities provided by the packaging. In addition, it is desirable to have a package that is easy to implement in a system with high thermal robustness at low cost. Summary of the invention

[0003] One aspect of the present disclosure relates to a semiconductor device package. The semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first portion of the lead frame, and a second power semiconductor device mounted on a second portion of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separated from each other. The lead frame includes an intermediate portion arranged between the first portion and the second portion, the intermediate portion not being covered by the first mold compound or by the second mold compound.

[0004] One aspect of the present disclosure relates to a power semiconductor system. The power semiconductor system includes a semiconductor device package, which includes a lead frame, a first power semiconductor device mounted on a first portion of the lead frame, and a second power semiconductor device mounted on a second portion of the lead frame. The first power semiconductor device is encapsulated by a first molding compound. The second power semiconductor device is encapsulated by a second molding compound. The first molding compound and the second molding compound are substantially separated from each other. The lead frame includes an intermediate portion arranged between the first portion and the second portion, the intermediate portion not being covered by the first molding compound or by the second molding compound. The power semiconductor system further includes at least one heat sink thermally and mechanically coupled to the first molding compound and the second molding compound.

[0005] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device package. The method includes mounting a first power semiconductor device on a first portion of a lead frame and mounting a second power semiconductor device on a second portion of the lead frame. Encapsulating the first power semiconductor device with a first molding compound. Encapsulating the second power semiconductor device with a second molding compound. The first molding compound and the second molding compound are substantially separated from each other. The lead frame includes an intermediate portion disposed between the first portion and the second portion, the intermediate portion not being covered by the first molding compound or by the second molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the various aspects and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the various aspects and are used together with the description to explain the principles of the various aspects. It will be easy to recognize many of the other aspects and the expected advantages of the various aspects because they become better understood by reference to the detailed description below. The elements of the accompanying drawings are not necessarily in proportion to each other. Similar reference symbols can designate corresponding similar parts. It is to be understood that the features of the various examples of the embodiments described below can be combined with each other unless otherwise specifically noted.

[0007] Figure 1A is a cross-sectional view of an example of a semiconductor device package 100 according to various embodiments.

[0008] Figure 1B is a top view of a semiconductor device package 100 prior to encapsulation according to various embodiments.

[0009] Figure 2 is a cross-sectional view of an example of a semiconductor device package 200 according to various embodiments.

[0010] Figure 3A is a cross-sectional view of an example of a semiconductor device package 300 according to various embodiments.

[0011] Figure 3B is a top view of a semiconductor device package 300 prior to encapsulation according to various embodiments.

[0012] Figure 4 is a cross-sectional view of an example of a semiconductor device package 400 according to various embodiments.

[0013] Figure 5 is a perspective top side view of an array of semiconductor device packages 500 each including first and second package bodies at a stage of the manufacturing process prior to lead separation.

[0014] Figure 6 yes Figure 5 FIG. 5 is a perspective top side view of an array of semiconductor device packages 500 at a stage in the manufacturing process before encapsulating first and second power semiconductor devices in first and second molding compounds, respectively.

[0015] Figure 7 After the packet is encapsulated, Figure 6 FIG. 7 is a cross-sectional view of an example of a semiconductor device package 700 taken along line AA.

[0016] Fig. 8A is a perspective view of a lead frame at a stage in the manufacturing process before first and second power semiconductor devices are mounted on the lead frame.

[0017] Figure 8Bis a perspective view of an example of a semiconductor device package 800 including first and second package bodies.

[0018] Figure 8C is another perspective view of semiconductor device package 800 .

[0019] Fig.8D is another perspective view of a partial semiconductor device package 800 showing the interior of the package body through the cutaway molding compound.

[0020] Fig.9A is a partial (one package body) perspective view of an example of a semiconductor device package 900 including a lead frame exposed at the bottom of the semiconductor device package.

[0021] Fig. 9B is a perspective view of a semiconductor device package 900 ′, which corresponds to the semiconductor device package 900 having a thermal interface material (TIM) applied to an exposed surface of a lead frame.

[0022] Fig. 9C yes Fig. 9B FIG. 9 is a cross-sectional view of an example of a semiconductor device package 900 ′.

[0023] Fig. 10A is a perspective top side view of a lead frame 1020 with cutouts for use as a hybrid lead frame at a stage in the manufacturing process before first and second power semiconductor devices are mounted on the lead frame.

[0024] Fig. 10B is a top side view of an example of a power semiconductor device pad and a power semiconductor device mounted thereon, which is configured to be inserted into Fig. 10A The lead frame is cut out.

[0025] Fig. 10C yes Fig. 10B A perspective bottom side view of a power semiconductor device pad.

[0026] Fig. 10D is a partial perspective top side view of an array of semiconductor device packages 1000 at a stage in the manufacturing process prior to encapsulating first and second power semiconductor devices in first and second molding compounds, respectively.

[0027] Fig.10E is a perspective top side view of a semiconductor device package 1000 showing the interior of one package body through a cut-away molding compound.

[0028] Fig.10F is a perspective bottom side view of a semiconductor device package 1000 showing the lead frame exposed from the first and / or second molding compound.

[0029] Fig.11Ais a perspective view of a semiconductor device package 1100 having first and second package bodies bent relative to each other.

[0030] Fig. 11B is a perspective view of a semiconductor device package 1100 showing the interior of a package body through a cut-away molding compound.

[0031] Fig. 12A is a perspective view of a semiconductor device package 1200 implementing a 3-phase bridge circuit, in which the number of package bodies is six.

[0032] Fig. 12B yes Fig. 12A Another perspective view of a semiconductor device package 1200 with a package body cut away.

[0033] Fig.13 is a cross-sectional view of an example of a power system 1300 having a common heat sink thermally and mechanically coupled to a first package body and a second package body of a semiconductor device package.

[0034] Fig.14A is a perspective view of a semiconductor device package 1400 having two package bodies.

[0035] Fig. 14B A first package body and a second package body having a relative bending relationship Fig.14A 1400 is a perspective view of a semiconductor device package 1400.

[0036] Fig.15A is a perspective view of a semiconductor device package 1500 having six package bodies.

[0037] Fig. 15B A package having first and second package bodies bent relative to each other Fig.15A 15 is a perspective view of a semiconductor device package 1500.

[0038] Fig.16 is thermally and mechanically coupled to Fig. 15B A perspective view of an example of a power system 1600 of a semiconductor device package with a common heat sink.

[0039] Fig.17 For example, Figures 12A-12B 15A-15B are circuit diagrams of a three-phase bridge 1700 implemented in the semiconductor device package of FIG. 15A-15B.

[0040] Fig.18 is a flow chart illustrating stages of an exemplary method of manufacturing a semiconductor device package according to the present disclosure. DETAILED DESCRIPTION

[0041] In the detailed description that follows, reference is made to the accompanying drawings that form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced. As used in this specification, the terms "combined", "attached", "connected", "mounted", "coupled" and / or "electrically connected / coupled" are not meant to imply that elements or layers must be directly in contact together; elements that are "interposed", "attached", "connected", "mounted", "coupled" and / or "electrically connected / coupled", respectively. However, in accordance with the present disclosure, the above-mentioned terms may also optionally have the specific meaning that elements or layers are directly in contact together, i.e. no intervening elements or layers are provided between the elements that are "combined", "attached", "connected", "mounted", "coupled" and / or "electrically connected / coupled", respectively.

[0042] In addition, the word "on..." used in connection with a portion, element, or material layer formed or located "on" a surface may be used herein to mean that the portion, element, or material layer is "directly" located (e.g., placed, formed, deposited, etc.) on the implied surface, such as in direct contact with the implied surface. The word "on..." used in connection with a portion, element, or material layer formed or located "on" a surface may be used herein to mean that the portion, element, or material layer is "indirectly" located (e.g., placed, formed, deposited, etc.) on the implied surface, with one or more additional portions, elements, or layers disposed between the implied surface and the portion, element, or material layer.

[0043] The semiconductor device package described herein includes at least two molding compounds. Each molding compound can form a package body of the semiconductor device package. Each molding compound can include a power semiconductor device. Each power semiconductor device can include one or more power semiconductor chips. The semiconductor power chip (e.g., one or more transistors, such as one or more transistors of any of the types described below) can be monolithically integrated.

[0044] More specifically, the power semiconductor chip can be configured, for example, as a power MISFET (Metal Insulator Semiconductor Field Effect Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Gate Field Effect Transistor), a HEMT (High Electron Mobility Transistor), a power bipolar transistor or a power diode (such as, for example, a PIN diode or a Schottky diode).

[0045] (Multiple) power semiconductor chips may, for example, have a vertical structure, that is, (multiple) semiconductor chips may be manufactured in such a way that current can flow in a direction perpendicular to the main surface of (multiple) semiconductor chips. A semiconductor chip having a vertical structure has electrodes on its two main surfaces (that is, on its top and bottom sides). As an example, in a vertical device, the source contact electrode and the gate contact electrode of a power MISFET or a power MOSFET or a power JFET or a HEMT may be located on one main surface, while the drain contact electrode of a power MISFET or a power MOSFET or a power JFET or a power HEMT may be arranged on the other main surface. Similarly, in a bipolar transistor vertical device, the emitter contact electrode and the gate contact electrode of a power IGBT may be located on one main surface, while the collector contact electrode of a power IGBT may be arranged on the other main surface. In the case of a power diode, the anode contact electrode may be located on one main surface, while the cathode contact electrode of the power diode may be arranged on the other main surface. In addition, it is also possible that the drain (collector) contact electrode and the gate contact electrode are located on one main surface, while the source (emitter) contact electrode is located on the other main surface.

[0046] In addition, a semiconductor device package may be provided that includes (multiple) semiconductor chips having a horizontal structure. A semiconductor chip having a horizontal structure has a chip electrode only on one of its two main surfaces (e.g., its active surface). Logic integrated circuit chips and power semiconductor chips (e.g., power MISFET or power MOSFET or power JFET power HEMT) may have a horizontal structure.

[0047] The semiconductor chip may be made of a specific semiconductor material (such as, for example, Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc.), and may further contain inorganic and / or organic materials that are not semiconductors. In particular, the semiconductor chip is made of a plurality of layers of the above materials, and may, for example, involve a gallium nitride on silicon chip or a gallium nitride on silicon carbide chip. The semiconductor chip may be of different types and may be manufactured by different technologies.

[0048] The semiconductor chip may have an electrode (chip pad) that allows electrical contact with the integrated circuit included in the semiconductor chip. The electrode may include one or more metal layers of the semiconductor material applied to the semiconductor chip. The metal layer can be manufactured using any desired geometry and any desired material composition. The metal layer can, for example, be in the form of a layer or land covering the area. As an example, any desired metal (e.g., Cu, Ni, NiSn, Au, Ag, Pt, Pd, In, Sn) that can form a solder bond or a diffusion solder bond and an alloy of one or more of these metals can be used as the material. The metal layer does not need to be uniform or made of only one material, that is, various compositions and concentrations of the material contained in the metal layer are possible.

[0049] The semiconductor device package described herein includes a conductive lead frame. The lead frame can be encapsulated in a first molding compound forming a first package body and a second molding compound forming a second package body. The lead frame can include a single (i.e., not formed by multiple pieces bonded together) middle portion that is not covered by the first molding compound or by the second molding compound.

[0050] The lead frame may form part of a structured metal sheet.The structured metal sheet may be made of any metal or metal alloy, such as copper or a copper alloy.

[0051] Each package body may include a power semiconductor device encapsulated in a molding compound. The molding compound may each form a portion of the periphery of the corresponding package body, ie, may at least partially define the shape of the semiconductor package body.

[0052] The molding compound is made of at least one encapsulating material. The encapsulating material may be an electrically insulating material. The encapsulating material may include or be a thermosetting material or a thermoplastic material. The thermosetting material may be made, for example, on the basis of an epoxy resin, a silicone resin or an acrylic resin. The thermoplastic material may, for example, include one or more materials selected from the group of polyetherimide (PEI), polyethersulfone (PES), polyphenylene sulfide (PPS), polyamide-imide (PAI) and polyethylene terephthalate (PET). Thermoplastic materials melt by applying pressure and heat during molding or lamination and harden (reversibly) when cooled and the pressure is released.

[0053] The encapsulating material may include or be a polymer material, such as a duroplastic polymer material. The encapsulating material may include or be at least one of a filled or unfilled mold material, a filled or unfilled thermoplastic material, a filled or unfilled thermosetting material, a filled or unfilled laminate, a fiber-reinforced laminate, a fiber-reinforced polymer laminate, and a fiber-reinforced polymer laminate with filler particles.

[0054] The encapsulation material is a mold material. The encapsulation material can be applied to the power semiconductor device (e.g., semiconductor chip) and the lead frame by molding. The molding compound can be formed using various techniques such as, for example, compression molding, injection molding, powder molding, liquid molding, transfer molding, or film assisted molding (FAM).

[0055] A variety of different types of electronic power devices and / or power systems can be configured to use semiconductor device packages as described herein. As an example, electronic power devices and / or power systems according to the present disclosure can constitute, for example, engine control units (ECUs), power supplies, DC-DC voltage converters, AC-DC voltage converters, power amplifiers, and many other devices.

[0056] In general, any power device and / or power system including at least two package bodies including at least one semiconductor power device or chip having high thermal power loss and / or relatively small footprint for dissipating thermal power may benefit from the disclosure herein. As an example, a power device and / or power system having a thermal power loss equal to or greater than, for example, 1 W, 10 W, 20 W, 50 W, 100 W, 200 W, 300 W, 400 W, 500 W, or 1000 W in operation and a footprint equal to or less than, for example, 200 mm 2 、150mm 2 , 100mm 2 , 50mm 2 , 25mm 2 , 10mm 2 , 5mm 2 , 3mm 2 , or 1mm 2 Semiconductor power chips with reduced footprint for thermal power dissipation may use multi-body power packages as described herein for improved handling during product to system assembly and thermal behavior and power dissipation during operation.

[0057] Figure 1A A cross-sectional view showing an example of a semiconductor device package 100 and Figure 1BFIG. 1 shows a top view of a semiconductor device package 100 before packaging. The semiconductor device package 100 includes a first molding compound 114 and a second molding compound 124 (in Figure 1B ). The first power semiconductor device 112 is encapsulated by a first molding compound 114 that may form a first package body 110. The second power semiconductor device 122 is encapsulated by a second molding compound 124 that may form a second package body 120. The first molding compound 114 and the second molding compound 124 are substantially separated from each other. Throughout the present disclosure, the term “substantially separated” may, for example, mean that there may be no connection of encapsulation material between the first molding compound 114 and the second molding compound 124 or there may only be an insignificant connection of encapsulation material between the first molding compound 114 and the second molding compound 124 that is not rigid and / or inflexible and / or bulky enough to transfer mechanical properties (such as, for example, mechanical stress from one molding compound 114, 124 to the other molding compound 124, 114). In other words, the first and second molding compounds 114, 124 are mechanically decoupled from each other with respect to any stress transfer coupling via the encapsulation material.

[0058] The first power semiconductor device 112 is mounted on a first portion of a lead frame 130 and the second power semiconductor device 122 is mounted on a second portion of the lead frame 130. The lead frame 130 mechanically and electrically connects the first molding compound 114 and the second molding compound 124. More specifically, the first portion of the lead frame 130 may be cast in the first molding compound 114 and the second portion of the lead frame 130 may be cast in the second molding compound 124.

[0059] The lead frame 130 may have a first main surface 130A and a second main surface 130B opposite to the first main surface 130A. The first power semiconductor device 112 and the second power semiconductor device 122 may be mounted on the same main surface of the lead frame 130, for example, on the first main surface 130A.

[0060] The lead frame 130 is encapsulated by the first molding material 114 and by the second molding material 124. A middle portion 132 of the lead frame 130 disposed between the first portion and the second portion may be exposed from the first molding material 114 and from the second molding material 124. More specifically, a first surface 130A of the middle portion 132 of the lead frame 130 and / or a second surface 130B of the middle portion 132 of the lead frame 130 may be revealed by both the first and second molding materials 114, 124 (i.e., exposed from both the first and second molding materials 114, 124).

[0061] It is noted that the middle portion 132 is an integral part (it is a single component) of the lead frame 130. That is, the middle portion 132 does not provide a joining joint (e.g., a welded joint, a soldered joint, an adhesive joint, etc.) through which the lead frame 130 will be made of more than one part. More specifically, although the first molding compound 114 defining the first package body 110 and the second molding compound 124 defining the second package body 120 are separate from each other, the single lead frame 130 can be a one-piece part that is inherently part of both package bodies 110, 120.

[0062] In addition, the middle portion 132 of the lead frame 130 can have an inherent structural stability sufficient to hold the first package body 110 and the second package body 120 in place, even without being supported by other holding means. That is, rather than being a flexible package carrier (such as, for example, a flexible PCB), the lead frame 130 and in particular the middle portion 132 thereof can provide a hardness and / or rigidity sufficient to control the positional relationship between the first molding compound 114 and the second molding compound 124 without any further holding or supporting means. In this regard, the semiconductor device package 100 can be viewed as a single semiconductor package having a spacing 140 (such as, for example, a continuous spacing) between the first molding compound 114 and the second package 124, which exposes at least one major surface 130A, 130B of the lead frame 130 and separates the first molding compound 114 from the second molding compound 124 (or in other words separates the first package body 110 from the second package body 120). The middle portion 132 of the lead frame may form a power lead connecting a plurality (eg, two here) of molding compounds 114 , 124 (or package bodies 110 , 120 ).

[0063] The middle portion 132 of the lead frame 130 may be plastically deformable by bending in order to allow the first molding compound 114 and the second molding compound 124 to be brought into a determined spatial relationship towards each other (not shown in FIG. 1 ).

[0064] In various embodiments, the leadframe 130 may also be a hybrid carrier consisting of, for example, a leadframe and any other substrate, as described in more detail further below.

[0065] In some embodiments, the lead frame 130 may have a constant thickness along its extension, for example, in particular the thickness of the middle portion 132 may be the same as the thickness in the portion of the lead frame 130 encapsulated by the first molding compound 114 and / or the second molding compound 124. In other embodiments, the lead frame 130 may have a different thickness along its extension, as described in more detail further below.

[0066] The subdivision of a large package body into a multi-body package design as disclosed herein may be beneficial in the following aspects: First, the larger the area size (or diagonal length) of the molding compound (package body), the more mechanical stress generated in the package caused by the CTE (thermal expansion coefficient) mismatch of the various materials of the package (e.g., carrier, encapsulation material, chip material). Therefore, it may be beneficial to subdivide a large molding compound (package body) into multiple smaller molding compounds (package bodies) in avoiding harmful effects based on CTE mismatch (e.g., package warpage, degradation of thermal contact to a heat sink, reliability under large temperature cycles). In addition, the separation of the first and second molding compounds from each other allows separation in consideration of the thermal load experienced by the molding compounds. As an example, temperature-sensitive components (such as, for example, logic integrated circuits (ICs) or sensors and / or actuators) can be placed in a molding compound with a lower thermal load or peak temperature than another molding compound that accommodates more temperature-resistant components (such as, for example, power switches).

[0067] Figure 2 A cross-sectional view of an example of a semiconductor device package 200 is shown. The semiconductor device package 200 is similar to the semiconductor device package 100, except that the second surface 130B of the lead frame 130 may remain completely exposed by the first molding compound 114 of the first package body 110 and by the second molding compound 124 of the second package body 120 or at least partially within the outline of the molding compounds 114, 124. Other features are disclosed in conjunction with the semiconductor device package 100, and reference is made to its description to avoid repetition.

[0068] Figure 3A A cross-sectional view of an example of a semiconductor device package 300 is shown, and Figure 3B A top view of a semiconductor device package 300 before encapsulation is shown. The semiconductor device package 300 may be similar or identical to the semiconductor device package 100, except that the lead frame 130 is a hybrid carrier, also denoted as a hybrid lead frame 330 hereinafter. The hybrid lead frame 330 may include a common frame structure 330_1, 330_2, 330_3 and two power semiconductor device pads 332_1, 332_2. The common frame structures 330_1, 330_2, 330_3 are lead frames. The middle portion 132 of the lead frame 130 (here the hybrid lead frame 330) is formed by the common frame structure 330_2. In general, at least one opening 330_1 may be provided in the common frame structures 330_1, 330_2, 330_3 and at least one power semiconductor device pad 332_1 may be inserted into this opening. In other words, although one of the package bodies 110, 120 may have a common frame structure as in Figure 1A , 1B The design shown in FIG. 1 , but other package bodies 120, 110 may be configured according to Figure 3A ,3B To design.

[0069] The first power semiconductor device pad 332_1 and the second power semiconductor device pad 332_2 may each be selected from the group consisting of, for example, an insulated metal substrate (IMS), a metal substrate (such as, for example, a metal plate (e.g., a copper plate), a metal composite plate (e.g., a copper composite plate)), a ceramic-based substrate (particularly a direct bonded copper (DBC) substrate, a ceramic thick film coated substrate), an active metal brazing (AMB) substrate, or a printed circuit board (PCB). The first and second power semiconductor device pads 332_1, 332_2 may be formed as inlays to fit into first and second cutouts or openings 335_1, 335_2 in a common frame structure 330_1, 330_2, 330_3. The first and second power semiconductor device pads 332_1 , 332_2 may have higher thermal and / or electrical conductivity properties (ie lower thermal resistance and / or lower electrical resistance) than a common frame structure 330_1 , 330_2 , 330_3 (eg a lead frame) to provide a high level of heat dissipation and / or electrical conductivity.

[0070] As in Figure 3A and 3B As shown in FIG. 1 , the first and second power semiconductor device pads 332_1 and 332_2 may be completely encapsulated by the first molding compound 114 and the second molding compound 124, respectively. That is, except for the area on which the first and second power semiconductor devices 112 and 122 are bonded, the entire periphery including the side surfaces of the first and second power semiconductor device pads 332_1 and 332_2 may be covered by the encapsulation material. Figure 3B The first molding compound 114 and the second molding compound 124 are shown by dashed lines.

[0071] Figure 4 A cross-sectional view of an example of a semiconductor device package 400 is shown. The semiconductor device package 400 may be similar or identical to the semiconductor device package 300, except that the bottom surfaces of the common frame structures 330_1, 330_2, 330_3 and / or the bottom surfaces of the first and second power semiconductor device pads 332_1, 332_2 are completely exposed by the first and second molding materials 114, 124, respectively, or are at least partially within the contours of the molding materials 114, 124. Thus, similar to Figure 2 The exposed second surface 130B of the lead frame 130 in the embodiment of the present invention can achieve direct thermal and electrical contact to the bottom surfaces of the first and second power semiconductor device pads 332_1, 332_2, and if desired, also to the bottom surfaces of the common frame structure 330_1, 330_2, 330_3. In addition, although one of the package bodies 110, 120 may have a Figure 2The design shown in FIG. 1 , but other package bodies 120, 110 may be configured according to Figure 4 To design.

[0072] The common frame structure 330_1, 330_2, 330_3 may be made of the same material as the first and second power semiconductor device pads 332_1, 332_2 or may be made of a material different from the first and second power semiconductor device pads 332_1, 332_2. The first power semiconductor device pad 332_1 may be made of the same material as the second power semiconductor device pad 332_2 or may be made of a material different from the second power semiconductor device pad 332_2. In addition, the thickness of the common frame structure 330_1, 330_2, 330_3 may be the same as the thickness of the first and second power semiconductor device pads 332_1, 332_2 or may be greater than or less than the thickness of the first and second power semiconductor device pads 332_1, 332_2. It is noted that the thickness of all parts is measured in the direction from the upper surface (e.g., the first surface 130A of the lead frame 130) to the lower surface (e.g., the second surface 130B of the lead frame 130) of the corresponding part.

[0073] The thickness of the lead frame 130 and / or the hybrid lead frame 330 (particularly the common frame structures 330_1, 330_2, 330_3 and / or the first and second power semiconductor device pads 332_1, 332_2) can, for example, be equal to or greater than or less than 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.2 mm, 1.4 mm, 1.6 mm, 1.8 mm, 2.0 mm, 2.2 mm, 2.4 mm, 2.6 mm, 2.8 mm, or 3.0 mm. For example, in a hybrid leadframe 330 or in a leadframe 130 with different thicknesses (e.g., a so-called dual-gauge leadframe), the thickness of the first and second power semiconductor device pads 332_1, 332_2 may be greater than the thickness of one or more of the portions of the common frame structure 330_1, 330_2, 330_3, 330_1, wherein the ratio of the thicknesses may be, for example, equal to or greater than a factor of 1.2, 1.4, 1.6, 1.8, 2.0, 2.5, 3.0 or more. The area size of the first and second power semiconductor device pads 332_1, 332_2 may be, for example, equal to or greater than or less than the values ​​stated above for the occupied area of ​​the power semiconductor chip.

[0074] Figure 5 1 is a perspective top side view of an array of semiconductor device packages 500 each including first and second package bodies 110 and 120, respectively. Figure 5As shown in FIG. 5 , the package bodies 110 , 120 of each semiconductor device package 500 are separated by a gap 140 . A middle portion 132 of the lead frame 130 is exposed from the first and second molding materials 114 , 124 within the gap 140 .

[0075] The lead frame 130 may further include a first end portion 134 protruding from the first molding material 114 and a second end portion 136 protruding from the second molding material 124. In addition, leads 135 and / or 137 may protrude from the first molding material 114 and the second molding material 124, respectively.

[0076] Adjacent semiconductor device packages 500 may be connected to each other via tie bars 510. The tie bars 510 may also connect the first end portion 134 to a longitudinal frame bar 522 of a continuous lead frame 520 and the tie bars 510 may be used to connect the second end portion 136 to another longitudinal frame bar 524 of the continuous lead frame 520. Individual semiconductor device packages 500 are separated from the continuous lead frame 520 during the manufacturing process by cutting the tie bars 520 between the first end portion 134 and the longitudinal frame bar 522, the tie bars 510 between the second end portion 136 and the longitudinal frame bar 524, and the tie bars 510 between adjacent semiconductor device packages 500. In addition, the semiconductor device package 500 may have any of the features explained in conjunction with the semiconductor device packages 100-400 illustrated in FIGS. 1-4, and vice versa.

[0077] Figure 6 yes Figure 5 1 is a top view of an array of semiconductor device packages 500 at a stage in the manufacturing process before encapsulating the first and second power semiconductor devices 112, 122 in the first and second molding compounds 114 and 124, respectively. In this example, the lead frame 130 corresponds to, for example, Figure 1A , 1B 2 and the lead frame 130 shown in FIG.

[0078] exist Figure 6In the example shown in , the first power semiconductor device 112 includes a plurality of semiconductor power chips 610, 612 and the second power semiconductor device 122 may include a plurality of power semiconductor chips 620, 622. The power semiconductor chips 610, 612 and the power semiconductor chips 620, 622 may, for example, be mounted directly on the lead frame 130. In addition, the first power semiconductor device 112 and / or the second power semiconductor device 122 may include a driver and / or control function and one or more power semiconductor chips. For example, the semiconductor chips 610, 620 may include a control electrode (e.g., gate) driver circuit, and the semiconductor chips 612, 622 may be power semiconductor chips, as described above. In addition, a stacked chip arrangement (not shown) is also feasible, such as a power chip on a power chip or a driver chip on a power chip, and the like.

[0079] Figure 7 The diagram shows that after the packet is encapsulated, Figure 6 A cross-sectional view of an example of a semiconductor device package 500 taken along line AA of FIG. Figure 7 Obviously, the middle portion 132 of the lead frame 130 may be connected to the power semiconductor device 612 by electrical connection elements 710 such as, for example, bonding wires. Similar connections may be provided between the power semiconductor chips 612 and 610 and between the semiconductor chip 610 and the leads 137 .

[0080] Fig. 8A is a perspective view of a continuous lead frame 520 for the lead frame 130 at a stage in the manufacturing process before mounting the first and second power semiconductor devices 112 , 122 to the lead frame 130 .

[0081] Figure 8B 1 is a perspective view of an example of a semiconductor device package 800 including a first package body 110 and a second package body 120. The semiconductor device package 800 has been separated from the continuous lead frame 520. Figure 8BAs shown in the figure, the leads 135, 137 and the first and second end portions 134, 136 of the lead frame 130 can be bent, for example, at an angle of about 90°. In addition, the middle portion 132 of the lead frame 130 can include a cutting line that defines a tab (e.g., a bent-out flap 132_1). The bent-out flap 132_1 is bent from the plane of the lead frame 130 to extend, for example, in a plane perpendicular to the plane of the lead frame 130. The bent-out flap 132_1 of the middle portion 132 of the lead frame 130 can be provided with a through hole. It is noted that the leads 135 and / or 137 can also protrude from the first molding compound 114 and the second molding compound 124 at the opposite package body side (i.e., adjacent to the middle portion 132 of the lead frame 130). In this and other cases, it is possible that the leads 135 and 137 are unitary (i.e., integrally formed as part of the intermediate portion 132 of the lead frame 130). Such a design allows the connectivity and / or functionality (e.g., control and / or sensing functionality) associated with the leads 135 and 137 in the respective package bodies 110, 120 to be combined.

[0082] Figure 8C is a perspective view of semiconductor device package 800 illustrating the bottom of the package. Obviously, semiconductor device package 800 may be constructed according to semiconductor device package 100, ie, lead frame 130 may be covered by first and second molding compounds 114, 124 at both first and second surfaces 130A, 130B.

[0083] Fig.8D is a perspective view of a semiconductor device package 800 showing the interior of a package body through cutaway first and second molding compounds 114 , 124 .

[0084] Fig.9A 9 is a partial perspective bottom side view of an example of a semiconductor device package 900. Only one package body 120 with a molding compound 124 is depicted. Fig.9A Obviously, in this case, the lead frame 130 is exposed at the bottom of the semiconductor device package 900. Therefore, Figure 2 The semiconductor device package 900 is designed based on the semiconductor device package 200 of FIG. In addition, similar or identical features as those in the semiconductor device packages 700 and 800 are provided in the semiconductor device package 900 , and reference is made to the corresponding disclosure to avoid repetition.

[0085] Fig. 9BThe semiconductor device package 900 ′ is shown to be the same as the semiconductor device package 900 ′, except that a thermal interface material (TIM) 910 may be applied to the exposed second major surface 130B of the lead frame 130 . The TIM 910 may, for example, partially or completely cover the bottom of each package body 112 , 122 . The TIM 910 may provide electrical insulation of the second surface 130B of the lead frame 130 exposed from the first and second molding materials 114 , 124 . In addition, if the second surface 130B of the lead frame 130 is to be covered by an encapsulation material (such as in Figure 8C ), the TIM 910 may provide a lower thermal resistance than the first and second molding materials 114 , 124 .

[0086] Fig. 9C yes Fig. 9B FIG. 9 is a partial cross-sectional view of a semiconductor device package 900 ′. Fig. 9C Electrical connection elements (eg bonding wires) 710 are shown interconnecting, for example, the first power semiconductor chip 610 and the second power semiconductor chip 620 .

[0087] Fig. 10A 1 is a top view of a continuous lead frame 1020 used as a hybrid lead frame. The continuous lead frame 1020 can be used with Fig. 8A The continuous lead frame 520 is the same or similar to the lead frame 520, except that the lead frame has the same Figure 3A , 3B The cutout 1030 corresponds to the openings (cutouts) 335_1 and 335_2 of the hybrid lead frame 330 of FIG. 4 .

[0088] Fig. 10B 1 is a top view of an example of a power semiconductor device pad 1332 and a power semiconductor device 1100 mounted thereon. As an example, the power semiconductor device 1100 may be a first power semiconductor device 112 including, for example, power semiconductor chips 610 , 612 , or may be a second power semiconductor device 122 including, for example, power semiconductor chips 620 , 622 .

[0089] Fig. 10C 13 is a perspective bottom side view of a power semiconductor device pad 1332. The power semiconductor device pad 1332 may be, for example, formed by combining Figure 3A , 3B 4 and 5. Fig. 10C In the example shown in , the power semiconductor device pad 1332 may be a direct bonded copper (DBC) substrate, for example, may include a bottom copper layer 1332_1 , a top copper layer 1332_3 , and a ceramic material layer 1332_2 sandwiched between the two copper layers 1332_1 and 1332_3 .

[0090] Fig. 10D FIG. 1 is a partial perspective top-side view of an array of semiconductor device packages 1000 at a stage of the manufacturing process prior to packaging. Fig. 10D , the power semiconductor device pad 1332 has been inserted into the cutout 1030 of the continuous lead frame 1020. The other features of the hybrid continuous lead frame 1020 are similar to the continuous lead frame 520, and reference is made to the above disclosure to avoid repetition.

[0091] Fig.10E and 10F Top and bottom perspective views of the semiconductor device package 1000 are illustrated, respectively. Fig.10E The interior of the first package body is shown, which is similar to Fig.8D The first package body 110 is shown in FIG.

[0092] Fig.10F In the semiconductor device package 1000 shown in the figure, the bottom side of the power semiconductor device pad 1332 (eg, the bottom copper layer 1332_1) may be exposed, while the portion of the lead frame 130 (eg, the bottom copper layer 1332_1) defining the cutout 1030 may be exposed. Figure 3A , 3B and 4: the openings 335_1, 335_2) may be covered by an encapsulation material, for example. The exposed power semiconductor device pad 1332 (eg, exposed DBC) (which may also be applied to the Figure 3A , 3B This concept of the hybrid leadframe 330 illustrated in FIGS. 4 and 5 allows for high heat dissipation capabilities while ensuring high mechanical robustness of the first and second package bodies 110 , 120 .

[0093] Fig.11A and 11B A perspective view of a semiconductor device package 1100 is shown having a first package body 110 and a second package body 120 bent toward each other at a predetermined angle (e.g., opposite to each other). In various embodiments, the first and second package bodies are "reversely bent", i.e., the bottom sides of the package bodies 110, 120 are bent toward each other. All package bodies 110, 120 of the semiconductor device packages described herein can be brought into this positional relationship.

[0094] In all semiconductor device packages, the first power semiconductor device 112 may include NS1 power switches and the second power semiconductor device 122 may include NS2 power switches. NS1 and NS2 are integers equal to or greater than 1. That is, each package body 110, 120 may include, for example, 1, 2, 3, ..., power switches.

[0095] In addition, as an example in Fig. 12A and 12BAs illustrated in , the semiconductor device package disclosed herein may have a first molding compound (eg, first package body 110 ) of number 1, 2, 3, . . . and may have a molding compound (eg, second package body 120 ) of number 1, 2, 3, . . . Fig. 12A and 12B The semiconductor device package 1200 is shown to include three first molding compounds (first package bodies 110 ) and three second molding compounds (second package bodies 120 ). Generally speaking, the semiconductor device package disclosed herein may include NB number of molding compounds (or package bodies), where NB is an integer equal to or greater than 2.

[0096] The three first molding materials 114 (package body 110) and the three second molding materials 124 (package body 120) are each interconnected to each other through an interconnection portion 1135 of the lead frame 130. The interconnection portion 1135 may have the same material as the middle portion 132 of the lead frame 130 and have the same mechanical properties as the middle portion 132. However, the interconnection portion 1135 is connected between the first molding materials 114 (first package body 110) that are coplanar with each other, or between the second molding materials 124 (second package body 120) that are also coplanar with each other, but not between the first and second molding materials (first and second package bodies 110, 120) that can be bent into planes that are, for example, inclined or parallel but away from each other.

[0097] In general, the multi-package body semiconductor device package disclosed herein can implement a variety of different power devices. In various embodiments, a semiconductor device package having two molding compounds 114, 124 (package bodies, such as a first package body 110 and a second package body 120) can include a half-bridge circuit, wherein the first molding compound 114 (first package body 110) accommodates a low-side (LS) switch of the half-bridge circuit and the second molding compound 124 (second package body 120) accommodates a high-side (HS) switch of the half-bridge circuit, or vice versa.

[0098] If the semiconductor device package includes four molding compounds 114, 124 (or package bodies), i.e., NB=4, the semiconductor device package may, for example, include a two-phase bridge circuit, wherein each of the two first molding compounds 114 (first package bodies 110) accommodates a low-side switch of the two-phase bridge circuit and each of the two second molding compounds 124 (second package bodies 120) accommodates a high-side switch of the two-phase bridge circuit, or vice versa. Similarly, if the semiconductor device package includes six molding compounds 114, 124 (package bodies 110, 120), i.e., NB=6 (as in, for example, Fig. 12A , 12B), the semiconductor device package may include a three-phase bridge circuit, wherein each of the three first molding materials 114 (first package body 110) accommodates a low-side switch of the three-phase bridge circuit and each of the three second molding materials 124 (second package body 120) accommodates a high-side switch of the three-phase bridge circuit, or vice versa.

[0099] In addition, in all semiconductor device packages disclosed herein, the first and second end portions 134, 136 protruding from the first and second molding materials 114, 124, respectively, can form load external terminals of the semiconductor device package (i.e., terminals connected to the load electrodes of the power transistors included in the first or second power semiconductor devices 112, 122), and the leads 135, 137 can form control and / or sensing terminals of the semiconductor device package, i.e., external terminals connected to the gate electrodes or voltage and / or temperature sensing electrodes of the power transistors included in the first or second power semiconductor devices 112, 124.

[0100] The first power semiconductor device 112 and the second power semiconductor device 122 of the semiconductor device package disclosed herein may have the same function or may have different functions.

[0101] In addition, depending on the application of the semiconductor device package described herein, the semiconductor device package described herein can be operated (e.g., switched) from, for example, 2V or equal to, greater than, or less than, for example, 12V, 48V, 100V, 500V, 1.0kV, 1.2kV, 1.5kV, 2.0kV, 2.5kV, or even up to 6.5kV.

[0102] Fig.13 1 is a cross-sectional view of an example of a power system 1300. The power system 1300 includes, for example, a semiconductor device package according to one or more of the multi-body semiconductor device packages described above. That is, the semiconductor device package includes a first package body 110 having a first power semiconductor device encapsulated in a first molding compound 114 and a second package body 120 including a second power semiconductor device encapsulated in a second molding compound 124. The semiconductor device package further includes a lead frame 130 configured to mechanically and electrically connect the first package body 110 and the second package body 120, wherein the first power semiconductor device and the second power semiconductor device are mounted on the lead frame 130. As explained above, the lead frame 130 may have a middle portion 132 bent at an angle of, for example, about 180°. The power system 1300 further includes at least one heat sink, for example, a common heat sink 1310 thermally and mechanically coupled to the first molding compound 114 (first package body 110) and the second molding compound 124 (second package body 120).

[0103] More specifically, the (e.g., shared) heat sink 1310 may include a board having a first surface 1310A and a second surface 1310B opposite the first surface 1310A. The first molding compound 114 (first package body 110) may be thermally and mechanically coupled to the first surface 1310A of the board and the second molding compound 124 (second package body 120) may be thermally and mechanically coupled to the second surface 1310B of the board. As described above, the thermal coupling may be provided by direct abutment of the bottom side material (e.g., lead frame, encapsulation material, or TIM) of the semiconductor device package to the first and second surfaces 1310A, 1310B of the shared heat sink 1310. In particular, it is possible to not have to use additional materials (e.g., thermal grease or any other thermal bonding material) between the semiconductor device package and the shared heat sink 1310 during assembly of the power system 1300.

[0104] The semiconductor device package of the power system 1300 may be, for example, a two-body package, a three-body package, a four-body package, a five-body package, a six-body package, etc. As an example, the semiconductor device package may include a half-bridge circuit, a two-phase bridge circuit, or a three-phase bridge circuit. Fig.13 As shown in FIG. 1 , a screw clamp 1320 may be used to press the first and second package bodies 110, 120 onto the heat sink 1310. The screw clamp 1320 may, for example, include a clamping bracket 1322 surrounding the first and second molding compounds 114, 124 (package bodies 110, 120) and a plurality of fixing screws 1324 for pressing the clamping bracket 1322 together.

[0105] As in Fig.13 As shown in FIG. 1 , the first and second end portions 134, 136 of the lead frame 130 may be used as external terminals of the semiconductor device package. In addition, a gate driver PCB 1330 is shown for providing gate control signals and / or voltage or temperature sensing signals.

[0106] Fig.14A and 14B 1 is a perspective view of a semiconductor device package 1400 having a first molding compound 114 (first package body 110) and a second molding compound 124 (second package body 120). The semiconductor device package 1400 has similar features as described above, and reference is made to the above disclosure to avoid repetition. In particular, Fig.14A and 14B It is apparent that the first and second package bodies 110 , 120 may be standard package bodies such as, for example, a TO247 package which, except for the lead frame 130 and its single middle portion 132 , is conventional technology.

[0107] The middle portion 132 (e.g., power lead) of the lead frame 130 may have an annular central region 132_5. The annular central region 132_5 may define a through hole in the middle portion 132 of the lead frame. The annular central region 132_5 of the middle portion 132 of the lead frame 130 may serve as a (common) external terminal of the semiconductor device package 1400. The semiconductor device package 1400 may implement, for example, a half-bridge circuit.

[0108] Fig.15A and 15B A perspective view of a semiconductor device package 1500 having, for example, six molding compounds (package bodies) is shown, wherein three of the six molding compounds (package bodies) are first molding compounds 114 (first package bodies 110) and the remaining three are second molding compounds 124 (second package bodies 120). Again, each package body 110, 120 may be, for example, a standard package body, such as, for example, a TO247 package.

[0109] The middle portion 132 of the leadframe 130 may include at least three separate connections 132a, 132b, and 132c. Each of these connections is singular (necessary to form an integral whole) and connects the molding compound 114 (first package body 110) to the second molding compound 124 (second package body 120).

[0110] Fig.16 A perspective view of an example of a power system 1600 is shown. The power system 1600 may be similar to the power system 1300, except that the semiconductor device package 1500 is used. Therefore, reference is made to the above description to avoid reiteration. Similar to the power system 1300, a (common) heat sink 1310 with a plate is used for heat dissipation and the package body 110, 120 is reversely bent and abuts the plate. It is noted that in the power system 1600, each individual molding compound 114, 124 (package body 110, 120) is provided with a through hole that allows the molding compound 114, 124 (package body 110, 120) to be fixed (e.g., screwed) to the board. In addition, throughout the present disclosure, instead of the common heat sink 1310, multiple heat sinks (e.g., one for each molding compound 114, 124 (package body 110, 120) or one for each pair of molding compounds 114, 124 (package body 110, 120)) may be provided.

[0111] Fig.17 1 is a circuit diagram of a three-phase bridge circuit 1700. Such a three-phase bridge circuit 1700 can be used, for example, in Figures 12A-12B and implemented in the semiconductor device package shown in 15A-15B.

[0112] The three-phase bridge circuit includes three half-bridges. The first half-bridge includes a low-side switch LS1 and a high-side switch HS1 connected in series between a negative power supply voltage (e.g., ground: GND) 1701 and a positive power supply voltage (e.g., battery: BAT) 1702. The second half-bridge includes a low-side switch LS2 and a high-side switch HS2 connected in series between the negative power supply voltage 1701 and the positive power supply voltage 1702. The third half-bridge includes a low-side switch LS3 and a high-side switch HS3 connected in series between the negative power supply voltage 1701 and the positive power supply voltage 1702. The control electrodes (e.g., gate electrodes) of the low-side switches LS1, LS2, and LS3 are connected to nodes 1703, 1704, and 1705, respectively. The control electrodes (e.g., gate electrodes) of the high-side switches HS1, HS2, and HS3 are connected to nodes 1707, 1708, and 1709, respectively.

[0113] The connections between the low side switch LS1 and the high side switch HS1 of the first, second and third half bridges are connected to a node 1412, a node 1413 and a node 1414, respectively.

[0114] exist Fig.17 In the example shown in FIG. 1 , the low-side switches LS1 , LS2 , LS3 and the high-side switches HS1 , HS2 , HS3 are implemented by MOSFETs, for example. Fig.17 In , D denotes drain and S denotes source. However, other types of switches and other polarities are also possible. As an example, it is also possible to implement the low-side switches LS1, LS2, LS3 and the high-side switches HS1, HS2, HS3, for example, by IGBTs. In this case, the circuit diagram would be similar to Fig.17 , except that the IGBT replaces the MOSFET. Then, the emitter will replace the source S and the collector will replace the drain D. In addition, the two-phase bridge circuit only includes the first and second half-bridges LS1, HS1, LS2, HS2, and the half-bridge circuit only includes the first half-bridge LS1, HS1.

[0115] If you can Fig.17 As can be understood by comparing the circuit diagram with the semiconductor device package disclosed herein, it appears that the (multiple) first molding materials 114 ((multiple) first package bodies 110) correspond to, for example, (multiple) LS switches, and the (multiple) second molding materials 124 ((multiple) second package bodies 120) correspond to, for example, (multiple) HS switches.

[0116] Fig.18 is a flow chart illustrating stages of an exemplary method of manufacturing a semiconductor device package according to the present disclosure.

[0117] At S1 , a first power semiconductor device is mounted on a first portion of a lead frame.

[0118] At S2, a second power semiconductor device is mounted on the second portion of the lead frame. In S1 and S2, any mounting technique may be used, such as, for example, soldering, adhesive gluing, sintering, and the like.

[0119] At S3 , the first power semiconductor device is encapsulated with a first molding compound.

[0120] At S4 , the second power semiconductor device is encapsulated with a second molding compound, the first molding compound and the second molding compound being substantially separated from each other, wherein the lead frame includes a middle portion arranged between the first portion and the second portion, the middle portion not being covered by the first molding compound or by the second molding compound.

[0121] The method may further include separating leads of the lead frame to singulate the semiconductor device package outside the lead frame.

[0122] Throughout this disclosure, the first molding compound can be the same encapsulation material as the second molding compound or can be an encapsulation material different from the second molding compound. Further, throughout this disclosure, the first molding compound and the second molding compound can be formed (e.g., molded, laminated, etc.) in one manufacturing process or in separate manufacturing processes (e.g., in one or more molding and / or lamination processes).

[0123] The method may further include bending a middle portion of the lead frame to fold the first molding compound (first package body) back onto the second molding compound (second package body).

[0124] The following examples relate to further aspects of the present disclosure:

[0125] Example 1 is a semiconductor device package, which includes a lead frame; a first power semiconductor device mounted on a first portion of the lead frame; a second power semiconductor device mounted on a second portion of the lead frame; the first power semiconductor device is encapsulated by a first molding compound; the second power semiconductor device is encapsulated by a second molding compound; wherein the first molding compound and the second molding compound are substantially separated from each other, and the lead frame includes an intermediate portion arranged between the first portion and the second portion, and the intermediate portion is not covered by the first molding compound or by the second molding compound.

[0126] In Example 2, the subject matter of Example 1 can optionally include wherein the first portion of the lead frame is cast in a first molding compound and the second portion of the lead frame is cast in a second molding compound.

[0127] In Example 3, the subject matter of Example 1 or 2 can optionally include wherein the lead frame is a unitary component.

[0128] In Example 4, the subject matter of any of Examples 1 to 3 can optionally include wherein the intermediate portion of the lead frame has an inherent structural stability sufficient to maintain the first molding compound in position relative to the second molding compound.

[0129] In Example 5, the subject matter of any one of Examples 1 to 4 can optionally include wherein the middle portion of the lead frame is plastically deformable by bending to allow the first molding compound and the second molding compound to be brought into a position relative to each other.

[0130] In Example 6, the subject matter of any one of Examples 1 to 5 can optionally include wherein the intermediate portion of the lead frame includes a cut line defining a tongue-shaped tab.

[0131] In Example 7, the subject matter of any one of Examples 1 to 6 can optionally include wherein the middle portion of the lead frame is provided with a through hole.

[0132] In Example 8, the subject matter of any one of Examples 1 to 7 can optionally include wherein the first portion of the lead frame includes a cutout, and a device pad inserted into the cutout, wherein the first power semiconductor device is mounted on the device pad.

[0133] In Example 9, the subject matter of any one of Examples 1 to 8 can optionally include wherein the first power semiconductor device is mounted on a first surface of a first portion of a lead frame, and a second surface of the first portion of the lead frame opposite to the first surface is exposed from the first molding compound.

[0134] In Example 10, the subject matter of any one of Examples 1 to 9 can optionally include wherein the lead frame further includes at least one of a first end portion protruding from the first molding compound and a second end portion protruding from the second molding compound.

[0135] In Example 11, the subject matter of any of Examples 1 to 10 can optionally include a half-bridge circuit, wherein the first molding compound accommodates a low-side switch of the half-bridge circuit and the second molding compound accommodates a high-side switch of the half-bridge circuit.

[0136] In Example 12, the subject matter of any one of Examples 1 to 11 can optionally include a number NB of first and second molding compounds, where NB is an integer equal to or greater than 3.

[0137] In Example 13, the subject matter of Example 12 can optionally include at least one of a two-phase bridge circuit in which NB is equal to or greater than 4 and a three-phase bridge circuit in which NB is equal to or greater than 6.

[0138] Example 14 is a power system, which includes a semiconductor device package, which includes a lead frame; a first power semiconductor device mounted on a first portion of the lead frame; a second power semiconductor device mounted on a second portion of the lead frame; the first power semiconductor device is encapsulated by a first molding compound; the second power semiconductor device is encapsulated by a second molding compound; wherein the first molding compound and the second molding compound are substantially separated from each other, and the lead frame includes an intermediate portion arranged between the first portion and the second portion, the intermediate portion not being covered by the first molding compound or by the second molding compound; and a heat sink thermally and mechanically coupled to the first molding compound and the second molding compound.

[0139] In Example 15, the subject matter of Example 14 can optionally include wherein the heat sink comprises a plate having a first surface and a second surface opposite the first surface, the first molding compound is thermally and mechanically coupled to the first surface, and the second molding compound is thermally and mechanically coupled to the second surface.

[0140] In Example 16, the subject matter of Example 14 or 15 can optionally include at least one of a half-bridge circuit, a two-phase bridge circuit, and a three-phase bridge circuit.

[0141] Example 17 is a method for manufacturing a semiconductor device package, comprising mounting a first power semiconductor device on a first portion of a lead frame; mounting a second power semiconductor device on a second portion of the lead frame; encapsulating the first power semiconductor device with a first molding compound; encapsulating the second power semiconductor device with a second molding compound, the first molding compound and the second molding compound being substantially separated from each other, and wherein the lead frame comprises an intermediate portion arranged between the first portion and the second portion, the intermediate portion being not covered by the first molding compound or by the second molding compound.

[0142] In Example 18, the subject matter of Example 17 can optionally include wherein encapsulating the first power semiconductor device includes casting a first portion of the leadframe in a first molding compound; and encapsulating the second power semiconductor device includes casting a second portion of the leadframe in a second molding compound.

[0143] In Example 19, the subject matter of Example 17 or 18 can optionally include cutting leads of the lead frame to singulate the semiconductor device package outside the lead frame after encapsulation.

[0144] In Example 20, the subject matter of any one of Examples 17 to 19 can optionally include bending a middle portion of the lead frame to fold the first molding compound back onto the second molding compound.

[0145] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will recognize that multiple alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any modifications or variations of the specific embodiments discussed herein.

Claims

1. A semiconductor device package, comprising: Metal lead frame; a first power semiconductor device mounted directly to a first metal portion of the metal lead frame; a second power semiconductor device mounted directly to a second metal portion of the metal lead frame; wherein the first power semiconductor device is encapsulated by a first molding compound; wherein the second power semiconductor device is encapsulated by a second molding compound; wherein the first molding compound and the second molding compound are substantially separated from each other, wherein the metal lead frame comprises an intermediate metal portion arranged between a first metal portion and a second metal portion, The intermediate metal portion is not covered by the first molding compound or the second molding compound. 2 . The semiconductor device package according to claim 1 , wherein the first metal portion of the metal lead frame is cast in a first molding compound and the second metal portion of the metal lead frame is cast in a second molding compound.

3. The semiconductor device package according to claim 1, wherein the metal lead frame is a single member, and wherein the first metal portion, the second metal portion, and the intermediate metal portion are all integrally necessary portions of the single member.

4. The semiconductor device package of claim 1, wherein the intermediate metal portion of the metal leadframe has an inherent structural stability sufficient to hold the first molding compound in place relative to the second molding compound.

5. The semiconductor device package according to claim 1, wherein the intermediate metal portion of the metal lead frame is bent so that the first molding compound and the second molding compound are located opposite to each other. 6 . The semiconductor device package of claim 1 , wherein the intermediate metal portion of the metal lead frame includes a cut line defining a tongue-shaped tab.

7. The semiconductor device package according to claim 1, wherein the intermediate metal portion of the metal lead frame is provided with a through hole.

8. The semiconductor device package according to claim 1, wherein the first metal portion of the metal lead frame comprises: incision; as well as The device pads inserted into the cutouts, The first power semiconductor device is directly mounted to the device pad.

9. The semiconductor device package of claim 1, wherein the first power semiconductor device is directly mounted to a first surface of a first metal portion of a metal lead frame, and wherein a second surface of the first metal portion of the metal lead frame opposite to the first surface is exposed from the first molding compound. 10 . The semiconductor device package according to claim 1 , wherein the metal lead frame further comprises at least one of a first end portion protruding from the first molding compound and a second end portion protruding from the second molding compound. 11 . The semiconductor device package of claim 1 , further comprising a half-bridge circuit, wherein the first molding compound accommodates a low-side switch of the half-bridge circuit and the second molding compound accommodates a high-side switch of the half-bridge circuit.

12. A power system comprising: A semiconductor device package, comprising: Metal lead frame; a first power semiconductor device mounted directly to a first metal portion of the metal lead frame; and a second power semiconductor device mounted directly to the second metal portion of the metal lead frame, wherein the first power semiconductor device is encapsulated by a first molding compound; wherein the second power semiconductor device is encapsulated by a second molding compound; wherein the first molding compound and the second molding compound are substantially separated from each other, wherein the metal lead frame comprises an intermediate metal portion arranged between the first metal portion and the second metal portion, wherein the intermediate metal portion is not covered by the first molding compound or by the second molding compound; and A heat sink is in contact with the first molding compound and the second molding compound. 13 . The power system of claim 12 , wherein the heat sink comprises a plate having a first surface and a second surface opposite the first surface, wherein the first molding compound contacts the first surface, and wherein the second molding compound contacts the second surface.

14. The power system according to claim 12, further comprising: At least one of a half-bridge circuit, a two-phase bridge circuit, and a three-phase bridge circuit.

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