System and method for efficient virtual tagging cache implementation

Abstract

The present disclosure provides a multiprocessor system including: a plurality of nodes and at least one memory, each node including at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being dedicated to at least one of the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the plurality of first caches, wherein at least one of the plurality of first cache lines includes a first associative pointer pointing to a location of one of the plurality of second cache lines, and wherein at least one of the plurality of second cache lines includes a second associative pointer pointing to a location of one of the plurality of first cache lines. The present disclosure also provides a data management method and a computer-readable storage medium for a system.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] U.S. Provisional Application No. 62 / 588,720, filed with the U.S. Patent and Trademark Office on November 20, 2017, is incorporated herein by reference in its entirety. Technical Field

[0003] At least some example embodiments of the inventive concepts relate generally to methods and systems for accessing data in a computer memory device, and more particularly, to mechanisms and techniques for implementing a coherent cache hierarchy. Background Art

[0004] Today's processors are often equipped with caches that can store copies of data and copies of instructions stored in some high-capacity memory. A popular example of such high-capacity memory today is dynamic random access memory (DRAM). In this article, the term "memory" will be used to collectively refer to all existing and future memory implementations. Cache memory, or simply "cache", is usually built with a much smaller and faster memory than other memory implementations, and can then only keep a copy of a small portion of the data stored in the main memory or auxiliary storage device at any given time. Today, caches are often implemented using SRAM, and large caches can be implemented using DRAM. The caches described herein can be implemented using any existing and future memory technology.

[0005] Typically, the memory system of a computer system includes a series of caches, with larger and slower caches (referred to herein as higher-level caches) close to the main memory and smaller and faster caches (referred to herein as lower-level caches) close to the processor. This configuration is often referred to as a cache hierarchy, memory hierarchy, or memory system. Each level in the cache hierarchy is called a cache level. Figure 1 is a block diagram showing a portion of a computer system. Figure 1 In the example shown, the computer system is a multiprocessor system in which each CPU 101 is assigned its own first level private cache 102 (L1 cache). Figure 2A more detailed example of CPU 101 and L1 cache 102 is described. A private cache is a cache in which space for data cells can only respond to activity of the CPU local to the cache (or a CPU located in the same node as the cache, where the cache is private to that node). In this example, the second level cache 103 is shared by all CPUs 101 and can contain data and instructions accessed by all CPUs 101. Because space for data cells can be made responsive to activity of any CPU 101, cache 103 is a global cache. Furthermore, cache 103 is a shared cache in that each data cell can only exist in one shared copy (whereas each private cache can have its own replica). Memory 105 also stores instructions and data accessed by all CPUs 101. Physical addresses (or PA for short) are typically used to access (main) memory 105, while addresses generated by CPU 101 are typically virtual addresses. For example Figure 1 The system shown, a computer system with multiple CPUs and multiple dedicated caches, requires an efficient mechanism to find a requested data unit in one of the caches and to keep multiple copies of the data stored in different nodes consistent.

[0006] In addition to the main memory and cache memory, such a computer system typically includes one or more auxiliary storage devices. These auxiliary storage devices may include one or more of a hard disk drive, an optical drive, a flash drive, etc., collectively represented here by disk 104. Disk or auxiliary storage 104 can store several orders of magnitude more data than memory 105, but cannot be directly accessed using physical addresses. If CPU 101 wants to access data stored on disk 104, the virtual memory system ( Figure 1 105) moves large blocks of data (often called pages) from disk 104 to memory 105 and creates translations from the virtual addresses corresponding to the pages to the physical addresses. Special types of translation caches ( Figure 1 The virtual memory system (not shown) (commonly referred to as a "translation look-aside buffer" or TLB for short) caches translation mappings from virtual pages to physical pages. The virtual memory system can be viewed as a cache system that stores a portion of the data located on disk 104 in memory 105.

[0007] Figure 2 is a block diagram used to explain an example cache hierarchy for a computer system. Figure 2 Shown from Figure 11 , and a more detailed view of the cache organization of the CPU 101. The CPU 101 is shown to include multiple cache-like structures, such as an instruction TLB (ITLB, 201) and a data TLB (DTLDB, 205), and a CPU core 202. The level 1 cache 102 is shown to include an instruction cache 200 and a data cache 206 inserted between the CPU 101 and the level 2 (and possibly higher level) cache 207. Figure 2 Also shown is a high capacity memory 208 connected to the cache hierarchy. Figure 2 The computer system in is shown as a uniprocessor (ie, single processor) system. Figure 2 The computer system in may be part of a multiprocessor system.

[0008] When CPU 101 requests data that is present in the cache (referred to as a cache hit), the request can be serviced much faster than an access to data that is not present in the cache (referred to as a cache miss). Typically, an application running on CPU 101 that experiences fewer cache misses will execute faster and consume less energy than the same application that experiences more cache misses (assuming the two versions of the application have similar properties). Therefore, considerable effort has been invested in techniques for avoiding cache misses, and implementations have been designed that can make cache hits and cache misses efficient in terms of access latency and the energy consumed by these memory transactions.

[0009] In order to understand how to develop solutions to this cache hit / miss problem, some understanding of cache organization and terminology will be useful. Typically, data is installed into the cache in fixed blocks that are larger than the word size of the processor, called cache lines. Common cache line sizes today are, for example, 32, 64, and 128 bytes, but as will be appreciated by those skilled in the art, there are larger and smaller cache line sizes for various cache implementations. For some cache implementations, the cache line size may also be variable.

[0010] A common way to organize data placement in memory 208 is in a way that each data word is statically mapped to reside in a specific cache line. Each cache typically has an index function that identifies the portion of the cache where each cache line can reside, which is called a group. A group can contain space for holding one or more cache lines at the same time. The number of cache lines that a group can hold is called its associativity. Typically, the associativity of all groups in a cache is the same. Such caches are typically called set associative caches. Associativity can also vary between groups. Each space in a group that can hold a cache line is called a way.

[0011] In order to determine the identity of each cache line stored in each group, the cache lines in the cache each have some identifier associated with them. A common example of such an identifier is an address tag. When looking up a particular cache line in a cache, its address can be used to determine the group of cache in which it may reside. The address tag of the cache line of the corresponding group is compared to the tag portion of the address used to identify the cache line (see, for example, in Figure 3 and ATAGs) depicted in and described below to determine whether the desired cache line resides in the cache, and if so, which way it resides, that is, which space it resides in the group that can hold the cache line.

[0012] Typically, each cache has a built-in strategy to determine which cache lines to keep in a group and which cache lines to evict (also called replacements) to make room for new cache lines to be introduced into the group, which is called a replacement policy. The cache lines that are replaced are called victim cache lines or replaced cache lines. Popular replacement policies used in conjunction with cache memories include (but are not limited to) least recently used (LRU), pseudo-LRU, and random replacement policies.

[0013] An inclusive cache hierarchy requires that a copy of a data block (e.g., a cache line) present in one cache level, such as the L1 cache, also be present in higher cache levels (here, higher refers to cache levels with a number higher than 1), such as in the L2 and L3 caches. An exclusive cache hierarchy only has one copy of a data block (e.g., a cache line) present in the entire cache hierarchy, while a non-inclusive hierarchy may have a mix of the two strategies. In both exclusive and non-inclusive cache hierarchies, a cache line is typically installed in the next higher cache level upon eviction from a given cache level.

[0014] Keeping this background of caches and cache lines in mind, the discussion now continues by describing the methods used to identify caches such as Figure 1 and Figure 2 A conventional technique for specifying a cache location within a cache hierarchy as shown. Figure 3 is a block diagram for explaining a conventional implementation of a two-level cache hierarchy including a set associative cache and a set associative data translation lookaside buffer (TLB). Figure 3An example of the organization of a computer system node including a CPU 301, a DTLB 303, an L1 cache 307, and an L2 cache 311 is shown. The CPU 301 generates a memory request including a virtual address 302 (VADDR), which is used to perform an associative lookup in the DTLB 303. In this example, the virtual address 302 is divided into three parts: P_OFFSET (page offset, e.g., composed of low-order bits), a tag, and an index. The index portion of the virtual address 302 is used to identify a group within the DTLB 303 where the address translation can be stored.

[0015] The DTLB 303 used in this example is shown to have a bidirectional associative organization, which shows two entries of the identified group. Each entry consists of an address tag (ATAG) 304 and a physical page frame (PPF) 305. The tag portion of the virtual address 302 is compared with the ATAG 304 of each entry of the identified group. Logic 318 determines whether there is a match for any entry, and if so, controls MUX 306 to select the corresponding PPF 305. The physical address PADDR 316 is composed by concatenating the PPF 305 selected by MUX 306 with the P_OFFSET portion of the virtual address 302. Alternatively, if none of the entries of the identified group matches the tag portion of the virtual address 302, a TLB fill operation is performed and the required translation entries are introduced into the DTLB 303.

[0016] PADDR 316 is used to perform a lookup in L1 cache 307. More specifically, the index portion of PADDR 316 is used to identify a group that can store a cache line containing the requested data. (It should be noted that the L1 index may contain different bits than the DTLB index). The depicted L1 cache 307 has a bidirectional associative organization with two entries in the identified group. Each entry consists of an address tag (ATAG) 308 and data 309 of the corresponding cache line. The tag portion of PADDR 316 is compared with the ATAG of each entry of the identified group. Logic 319 determines whether there is a match for any entry and controls MUX 310 to select the corresponding data. If none of the entries match (indicated by L1 miss 317), a lookup is required in L2 cache 311. Although the division of PADDR 316 into index and tag portions for L2 cache lookups may be different from the divisions made for L1 cache lookups, the remaining steps for L2 cache lookups are generally similar to the steps performed for lookups in L1 caches. If a miss in the L2 cache is determined, a new lookup in a higher level cache or access to memory may be required. It may be noted that if the index portion of PADDR 316 used by the L1 cache consists entirely of P_OFFSET bits, accesses to the L1 cache 307 may begin before the PPF information from MUX 306 is available. This is often referred to as a virtually indexed physically tagged (VIPT) cache.

[0017] Those skilled in the art will understand that each has Figure 3 Multiple "nodes" of a memory hierarchy similar to the memory hierarchy shown in FIG. 1 can be connected together to form a coherent multiprocessor system. Figure 1 Another example of a multiprocessor is shown in , where each CPU has its own private L1 cache. This further complicates the task of locating where the requested data resides, since it is no longer sufficient to always search for the data in the next higher cache level. Mechanisms are needed for searching the caches of other nodes and for keeping multiple copies of datums stored in different nodes consistent. Typically, a global cache coherence protocol will be implemented to keep the data values ​​of each cache line consistent. Such a protocol will send coherence messages (sometimes called coherence requests) to the different caches. For example, Figure 1 and Figure 2 The L1 cache may receive a read request or an invalidate request from the coherence protocol. Such a coherence request typically carries a physical address identifying the requested cache line.

[0018] Figure 5is a block diagram showing three options for implementing caching. Figure 5 Three high-level cache implementation options are shown. The functionality for looking up data in the L1 cache 307 is depicted by a physically indexed physically tagged (PIPT) cache 500. A portion of a virtual address VA 502 is used to perform a lookup in a TLB 503 to obtain a physical page frame (PPF), which is used in part to form an index 504 for accessing the L1 cache 505. Some other portion of the PPF is compared to the physical address tags PAT of the set in the L1 cache 505 identified by the index 504 (a bidirectional associative cache is shown). The result of the comparison is used to select data associated with the virtual address (VA) 502 accessed by the CPU core 501.

[0019] The VIPT cache 510 can provide faster access times to data associated with a virtual address 512 generated by the CPU core because it uses only the virtual address bits to form its index 514. The lookup in the TLB 513 (for finding the corresponding physical page frame PPF) can be performed in parallel with reading out two physical address tags (PAT) from the indexed group in the L1 cache 515. Because the TLB access is performed in parallel with the PAT lookup, the way associated with the virtual address 512 can be accessed faster than in the VIPT cache 500. In order to make the VIPT cache 510 practical, there are usually size restrictions imposed on such caches. The combination of the cache size and its associativity must be such that no bits of the index 514 should be translated when the TLB 513 translates the virtual address 512 into a physical address. For example, if the page size of the computer system is 4K bytes, the bits used for the indexing function can only be the lower 12 bits of the virtual address.

[0020] Figure 5 The top-most cache 520 shown in is a virtually indexed virtual tag (VIVT) cache. The top-most cache 520 uses only the bits of the virtual address 522 for its index bits 524 and address bits 523 to compare with the index address tags of the L1 cache 525. Subsequently, the address tags stored in the L1 cache 525 are virtual address tags (VAT) that store the virtual address bits. The VIVT cache 520 has multiple advantages over the other two caches. First, accessing the L1 520 does not require TLB translation, which saves energy for L1 hits, which are currently the most common access type in the memory hierarchy. Second, it can be accessed faster than the PIPT cache 500 because its index bits 524 do not require a TLB lookup. Finally, it has no size limit.

[0021] However, the existence of the VIVT cache brings new problems that need to be solved. First, different virtual addresses can be used to reference the same physical cache line. If multiple virtual copies are stored for the same physical cache line, this will lead to the synonym problem of the VIVT cache. This problem is usually handled by a mandatory mechanism that ensures that two or more synonym cache lines cannot reside in the VIVT cache at the same time. Second, the same virtual address used by different processes can refer to different physical cache lines. This is called the confusion problem. If the virtual address 522 generated by the CPU core 521 includes some process identifiers (commonly called address space identifiers), the confusion problem can be handled. When (for example Figure 1 A third problem is introduced when there are multiple dedicated caches in a multi-core system (as shown). L2 and higher-level caches are typically of the PIPT type and are addressed using physical addresses. Therefore, any communication between these L2 caches and the L1 cache typically carries a physical address. Examples of such communications include (but are not limited to) coherence requests generated by the coherence protocol, and so-called back-invalidate requests caused by certain inclusion properties imposed between the L1 cache and the L2 cache and higher-level caches. While both PIPT caches and VIPT caches can perform cache lookups based on physical addresses and find the cache line targeted by such external requests, VIVT caches cannot be accessed using physical addresses.

[0022] Figure 4 is a block diagram illustrating an example implementation of a tag-less cache. As background information, Figure 4 A possible implementation of a sparsely tagged cache is depicted. Such a cache may rely on location information LI (sometimes called a cache line pointer (CP)) corresponding to the requested cache line of the matching cache table entry CTE (sometimes called a region location) to indicate in which cache the requested cache line resides, and at which location within that cache. This will cause some systems to perform a direct cache lookup in the appropriate cache. For example, in Figure 4 In the system shown (which may be a node in a multiprocessor system), the location information may distinguish between the L1 cache and the L2 cache. It may also be possible to distinguish between other caches ( Figure 4 (not shown) to distinguish between. Figure 4An sparsely tagged node is shown that can be connected to other nodes in a multiprocessor system having a two-level cache hierarchy of set associative caches and a CPU (which can contain one or more traditional caches, described here as L0), where the CPU 401 generates an address (ADDR) 402. Figure 4 Also shown is a set associative CLB of a two-level cache location buffer (CLB) (sometimes also referred to as a metadata cache - MD cache) hierarchy, where a first-level CLB CLB1 410 and a second-level CLB CLB2 420 are indexed by ADDR. As used in the present disclosure, the term "CLB1" may refer to a first-level CLB and the term "CLB2" may refer to a second-level CLB. Each entry in CLB1 410 includes at least an address tag (AT) 411 and a cache location table (CLT) 412. It may store additional information, such as region information (RI) 413. CLT 412 stores location information (LI) of cache lines of a corresponding region (also referred to as a micro-page). Figure 4 Four LIs per region are shown as an example. Empirical studies by the inventors have shown that 8 to 16 LIs per region (i.e., 8 to 16 data units (cache lines) per region) are cost-effective and efficient. The location information encodes the location of the corresponding cache line that can be found in a multiprocessor system. For example, the location information may include an identification of a cache in which the data unit can be found. The location information may also include the location where the data unit can be found within the cache. Alternatively, the location information may include an identification of a node in which the data unit can be found, or some symbols that provide information about its location, such as the symbol "MEM" indicating that the data unit can be found in a memory. In at least some cases, the symbol "unknown" may indicate that the location of the corresponding data unit is not recorded in the CLT corresponding to the region.

[0023] MUX 416 selects the CLT having AT 411 that matches the tag portion of ADDR 402, and MUX 415 selects the LI 414 corresponding to the requested cache line based on the L-OFFSET portion of ADDR 402. If the cache tag stored in the selected LI corresponds to L2 cache 440, an address 417 for accessing the requested data unit in L2 cache 440 is formed using the index portion of address 402 and a portion of location information 414. In the example of a set associative L2 cache 440, this portion contains information corresponding to the associated way in which the requested data unit is stored. If the cache tag stored in the selected LI corresponds to L1 cache 430, an address 418 for accessing the requested data unit in L1 cache 430 is formed in a similar manner.

[0024] exist Figure 4 In the example shown in , each entry in L1 cache 430 and L2 cache 440 has a back pointer (BP) (432 and 442, respectively) associated with its cache line (DATA) (431 and 441, respectively). In this example, the BP pointers point to their respective associated CTEs in CLB2 420. Each CTE in CLB2 420 contains an address tag (AT) 421, a CLT 422, and a CLB1 pointer (CIP) 423. If a CLB2 entry has a corresponding CLT residing on CLB1 410, its CIP will point to the entry. In this case, CLB1 410 will contain the latest information for the region. In this case, the CLE in CLB1 is called an active CLB entry, while the CLB entry for the region in CLB2 420 contains a passive entry. If CLB1 410 contains an active entry for a region, CLB2 420 will be required to contain a passive entry for the region.

[0025] When no matching CTE is found in CLB1 410, the corresponding CTE may be looked up in CLB2 420 and copied to CLB1, and the old entry in CLB1 is copied to CLB2 420, which is referred to as overflow and fill or simply overflow / fill ( Figure 4 Overflow and fill in the cache). For example, overflow is also performed when a traditional inclusive cache evicts a data unit to the next level to make room for a new data unit, which can be brought in (filled) from the next cache level. Similar overflow / fill activities will be performed between different CLB levels, where CLB entries are moved between CLB levels because the CLB levels form an inclusive hierarchy. The directory DIR can be located at the root of the CLB hierarchy and use the highest level CLB for overflow / fill.

[0026] Access to the requested data unit may be initiated in parallel with the overflow / fill activity.

[0027] The contents of the CLBs of the multi-level CLB implementation may be consistent with the locations of the data units of the multi-level cache system they manage. Data units moved in the cache hierarchy (including but not limited to movements caused by requests for data units from the CPU, evictions of data units, prefetch activities, and coherency activities) result in updates to their corresponding location information in one or more CLBs. For example, in Figure 4In the example, evicting a data unit 441 from cache 440 may include the following steps: following its associated BP 442 pointer to find its corresponding CTE (which is in CLB2 420 in this example) and updating its corresponding location information to point to the new location of the data unit (e.g., storing the MEM symbol). And, if the CIP pointer of the CLE corresponding to CLB2 is valid, following the CIP to find its corresponding CTE in CLB1 410 and updating its location information associated with the cache line. If there is a valid CIP pointer, the entry in CLB2 may not be updated. For example, the CLT may be updated so that only the active CLT is updated.

[0028] As will be appreciated from the foregoing description, use of the above-mentioned sparsely tagged cache system (i.e., a cache system in which data units stored in the cache do not have address tags associated therewith) will result in many different types of transactions occurring when the CPU 401 requests various cache lines located in different storage devices. Figure 4 The node depicted in FIG. 1 may be a subsystem (or node) of a larger multiprocessor system composed of multiple such cache nodes. Keeping the data in the caches of multiple nodes consistent requires a cache consistency protocol, such as implementing snooping or directory-based consistency. The consistency protocol sends a consistency request to the cache. Figure 4 Node depicted (external request). These requests typically go first to CLB2 420, which can determine that the cache system does not have the requested cache line (CLB2 miss or CLB2 hits an entry with an inactive CIP and the location information of the requested cache line maintains a numerical memory mode). If so, no further action is required regarding the data caches L1 and L2 (called consistency filtering), but the corresponding LI in the active CLT still needs to be updated to track the new location associated with the data unit. Otherwise, the CLB2 lookup can provide the requested location information (CLB2 hits and the location information of the requested cache line maintains the location where the cache line is stored), or it can determine that CLB1 410 stores the associated location information (CLB2 hits and a valid CIP). In the latter case, a lookup is required in CLB1 410 to determine the location of the requested cache line or the cache line does not reside in the cache subsystem. (The corresponding location information in CLB1 contains the memory mode). Depending on the nature of the coherence request, such as an invalidation request, a read request, or an exclusive read request, the coherence protocol will perform some operations on the requested data unit and may change its state. It may also be necessary to update the corresponding LI in the active CLT to track the new location associated with the data unit.

[0029] Although Figure 4 The node shown in FIG. 1 is composed of two cache levels, but those skilled in the art will appreciate that other numbers of levels may be used to assemble the node, and that the node may contain more than one CPU. In addition, the number of cache levels in a node and the number of CLB levels do not need to be the same.

[0030] Summarize the above Figure 3 and Figure 5 , those skilled in the art will appreciate that current implementations of cache hierarchies may require many associative lookups in the TLB and at different cache levels before the location of the requested cache line can be determined. In addition, each translation entry and cached cache line requires an accompanying address tag, and a plurality of these tags need to be compared with a portion of the address of each of these levels. In general, this implementation may cost a considerable amount of money in terms of dynamic energy for each associative lookup. It also requires a large amount of static energy and memory capacity to store the additional tag information required to perform the comparison. In addition, a multiprocessor comprising multiple CPUs or multiple nodes, each with its own dedicated cache hierarchy, requires an additional costly search mechanism to locate data residing in a dedicated cache, and a costly consistency activity is required to keep the replicas of the same data in the dedicated cache consistent.

[0031] Therefore, it may be desirable to provide systems and methods that avoid the above-mentioned problems and disadvantages associated with TLB lookups for data and instructions. For example, it may be advantageous if data and instructions in a lower level cache (e.g., an L1 cache) can be accessed using virtual addresses rather than physical addresses. Further implementation efficiencies can be achieved if the address tags for data and instructions in the lower level caches include virtual address tags. In this way, the additional delay and energy consumption imposed by the TLB can be completely avoided for L1 hits, which are by far the most common type of memory access to the memory hierarchy. In order to achieve this, a solution is needed for how physically tagged L2 and higher level caches interact with the virtually tagged L1 cache. Summary of the invention

[0032] According to at least one example embodiment of the inventive concept, cache lines are stored in a dedicated cache in a node of a multiprocessor system, each node containing at least one processor (CPU), and at least one cache dedicated to the node. According to one embodiment, a core in a node can access a node-specific cache using a virtual address, which is referred to as a virtual cache. The core and requests issued from other cores in the system can access another cache in the system using a physical address, which is referred to as a physical cache. In order to solve the translation problem that usually exists in such a virtually accessed cache, each cache line position in the virtual cache stores a cache line pointer (CP) associated with its cache line, wherein the pointer identifies a cache line position in the physical cache. Similarly, each cache line position in the physical cache stores a cache line pointer (CP) associated with its cache line. The cache line position in the physical cache pointed to by the cache line pointer of the cache line position in the virtual cache will have a cache line pointer pointing to the cache line position in the virtual cache.

[0033] According to at least some example embodiments conceived in the present invention, a multiprocessor system includes a plurality of nodes and at least one memory, each node including at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being dedicated to at least one node among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the plurality of first cache lines includes a first associated pointer pointing to a location of one of the plurality of second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.

[0034] According to at least some example embodiments conceived in the present invention, a data management method for a system, the system comprising at least one node, the at least one node comprising a processor allocated with a first cache, a second cache and a memory, the first cache storing a plurality of first cache lines and being dedicated to the at least one node, and the second cache storing a plurality of second cache lines and being at a higher level than the first cache, the data management method comprising: storing a first associative pointer pointing to a location of one of the plurality of second cache lines in one of the plurality of first cache lines; and storing a second associative pointer pointing to a location of the first cache line in the plurality of second cache lines pointed to by the first associative pointer.

[0035] According to at least some example embodiments of the present inventive concepts, a non-transitory computer-readable storage medium including computer-executable instructions, when the instructions are executed by at least one processor assigned with a virtual tagged cache, a physically tagged cache and a memory, causes the at least one processor to perform operations including the following steps: storing a first associative pointer pointing to a location of one of a plurality of second cache lines stored in the physically tagged cache in one of a plurality of first cache lines in the virtually tagged cache; and storing a second associative pointer pointing to a location of one of the plurality of first cache lines in one of the plurality of second cache lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other features and advantages of the exemplary embodiments of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings. The accompanying drawings are intended to describe exemplary embodiments of the present invention and should not be interpreted as limiting the intended scope of the claims. Unless explicitly stated, the accompanying drawings should not be considered to be drawn to scale.

[0037] Figure 1 is a block diagram illustrating a portion of a computer system.

[0038] Figure 2 is a block diagram used to explain an example cache hierarchy for a computer system.

[0039] Figure 3 is a block diagram for explaining a conventional implementation of a two-level cache hierarchy including a set associative cache and a set associative data translation lookaside buffer (TLB).

[0040] Figure 4 is a block diagram illustrating an example implementation of a sparsely tagged cache.

[0041] Figure 5 is a block diagram showing three options for implementing caching.

[0042] Figure 6 is a block diagram for explaining an implementation of a two-level cache hierarchy, wherein a first level is a virtually indexed virtually tagged cache and a second level is a physically indexed physically tagged cache according to at least some example embodiments of the inventive concepts.

[0043] Figure 7 is a block diagram for explaining an implementation of a three-level cache hierarchy according to at least some example embodiments of the present invention, wherein the first level is a virtually indexed, virtually tagged VIVT cache, and the second and third levels are less-tagged physically indexed, no tag PINT caches.

[0044] Figure 8 is a block diagram for explaining an implementation of a three-level cache hierarchy according to at least some example embodiments of the present invention, wherein the first level is an untagged VINT cache with few tags of virtual indexes, and the second and third levels are untagged PINT caches with few tags of physical indexes. DETAILED DESCRIPTION

[0045] As in accordance with the tradition of the field of the present invention, the embodiment is described in terms of functional blocks, units and / or modules and shown in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. Moreover, without departing from the scope of the present invention, each block, unit and / or module of the embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules.

[0046] A general problem with interfacing and interacting between a virtual tagged cache and a physically tagged cache (hereinafter referred to simply as a virtual cache and a physical cache) is that they do not speak the same "language", but rather the virtual cache and the physical cache call the same cache line by its virtual name or physical name, respectively. Performing a full translation between the virtual and physical address spaces requires new complex and expensive hardware each time there is an interaction between the virtual cache and the physical cache.

[0047] Figure 6 1 is a block diagram for explaining an embodiment of a two-level cache hierarchy according to at least some example embodiments of the inventive concept, wherein the first level is a virtual index virtual tagged (VIVT) cache and the second level is a physical index physical tagged (PIPT) cache. According to at least some example embodiments of the inventive concept, Figure 6 The example shown in provides a simple and fast mechanism to support interaction between virtual cache and physical cache. It should be noted that in Figure 5When comparing the standard virtually indexed virtual tagged (VIVT) cache and the physically indexed physically tagged (PIPT) cache depicted in FIG. 6 , the cache line location 627 in the L1-VIVT cache 625 and the cache line location 607 in the L2-PIPT cache 605 have been extended with a new cache line pointer (CP) field.

[0048] exist Figure 6 At the bottom is the virtual cache 625, which can provide fast and energy-efficient access using the virtual address 622 generated by the CPU core 621, because both its index bits 624 and its VAT comparison bits 623 make up the virtual address bits. It can quickly determine whether the requested cache line resides in its cache 625, and if so, returns the requested data to the CPU core 621.

[0049] If it is determined that the requested cache line does not exist in the virtual cache 625, a victim cache line location is selected. In this example, it is assumed that the rightmost cache line location 627 of the selected group in the L1 cache is selected (determined by the index bits 624) and its cache line is evicted. At the same time, the requested virtual address is sent to a virtual-to-physical address translator 640, such as a translation lookaside buffer (TLB), to generate a physical address L2 request 602 that can be used to search for the requested cache line in the L2 cache (and higher-level caches). According to at least some example embodiments of the present inventive concepts, the virtual-to-physical address translator 640 can be a virtual-to-physical address translator (e.g., TLB) assigned to the CPU core 621.

[0050] The L2 request 602 also carries the victim cache line location, i.e., the rightmost cache line location 627 of the selected group of the L1 cache. The cache index and cache way of the victim cache line location can be used to encode the location information. However, assuming that some of the address bits used as index bits 624 for the L1 cache will not change when translating addresses between virtual addresses and physical addresses, the location information only needs to contain the index portion that cannot be determined from the physical address, i.e., if the page size of the system is 4Kbyte, the 12 lowest address bits do not need to be included. If the L1 cache 625 is direct mapped (i.e., each group has only one cache line location), the victim cache line location carried by the L2 request 602 only needs to identify the selected group and does not need to identify any way.

[0051] A lookup in the L2 cache is performed to select the set where the requested cache line should reside (if it is there) by selecting index bits 604 from the physical address of the L2 request 602. In this example, a comparison between the PAT of the selected set of the L2 cache and the address bits 603 determines that the requested cache line resides in the leftmost cache line position 607 of the set. This position is referred to herein as the "hit cache line position".

[0052] Now the following steps will be taken: (1) the CP of the victim cache line location is stored in the CP of the hit cache line location in cache 605; (2) the physical cache 605 returns the cache line to the CPU core 621 and returns it to the L1 virtual cache 625 and writes the cache line to the victim cache line location in the L1 virtual cache 625; and (3) the CP of the hit cache line location is stored in the CP of the victim cache line location. In summary, after the requested cache line has been filled from the L2 cache to the L1 cache, the cache line location in the L2 cache that provides the data will store a CP pointer pointing to the cache line location in the L1 cache where the cache line is installed (e.g., stored), and the cache line location in the L1 cache where the cache line is installed (e.g., stored) will store a CP pointer pointing to the cache line location in the L2 cache where the data is provided. In this way, the corresponding cache line locations in the L1 cache and the L2 cache will store crossed CP pointers pointing to each other.

[0053] According to at least one example embodiment of the inventive concept, in Figure 6 , and the physical L2 cache 605. This means that if a cache line resides at a location in the L1 cache, the cache line must have a corresponding location that resides in the L2 cache. According to at least one example embodiment of the inventive concept, the L1 cache is a write-through type (e.g., a write-through cache), i.e., when a cache line in the L1 cache is being written, a corresponding cache line in the L2 cache (identified by the CP of the cache line being written in the L1 cache) is also written. According to at least one example embodiment of the inventive concept, the L1 cache is a write-invalidate type (e.g., a write-invalidate cache), i.e., a cache line residing in the L1 cache (and subsequently also in the L2 cache) is invalidated, rather than updated, with respect to writes performed on the cache line and the corresponding cache line in the L2 cache. For both cache types, a cache line in the L1 cache never stores dirty data that is different from the corresponding cache line in the L2 cache.

[0054] However, according to at least one example embodiment of the inventive concept, the L1 cache is a write-back type (e.g., a write-back cache), that is, a cache line in the L1 cache can be modified without modifying its corresponding cache line in the L2 cache. Therefore, the cache line in the L1 cache will become dirty. According to at least one example embodiment of the inventive concept, when a dirty cache line is evicted from the L1 cache, the corresponding cache line in the L2 cache is updated. According to at least one example embodiment of the inventive concept, the CP storing the cache line location of the dirty cache line is used to find the appropriate cache line in the L2 cache for updating. According to at least one example embodiment of the inventive concept, the CP of the corresponding cache line in the L2 cache changes its state to reflect that it is unreadable when the CP in its corresponding L1 cache line becomes dirty. According to at least one example embodiment of the inventive concept, the CP of the corresponding cache line in the L2 cache updates its CP when its corresponding clean (i.e., not dirty) cache line is cleared from the L1 cache.

[0055] Figure 6 The L2-PIPT cache in may receive an external request 608, for example, a read request or an invalidation request generated by a cache coherence protocol. This means that a cache line residing in the L2-PIPT cache and / or the L1-VIVT cache needs to be read or invalidated. According to at least one example embodiment of the present invention, the external request 608 carries a physical address that can be used to perform a lookup on the L2-PIPT cache, but is not directly used to perform a lookup in the L1-VIVT cache. Instead, the corresponding cache line is first searched in the L2-PIPT cache, where, for example, it is determined that the requested cache line is located in the leftmost cache line position 607 of the selected group. If the CP of the leftmost cache line position 607 contains a valid pointer, the CP can be used to determine the location of the cache line in the LI-VIVT cache. According to at least one example embodiment of the present invention, if the external request 608 is an invalidation request, the identified cache line positions are all invalidated, and if the external request 608 is a read request, at least one of the identified cache line positions is read.

[0056] According to at least one example embodiment of the inventive concept, if the CP of the cache line location identified in the L2-PIPT cache can determine that the cache line location identified in the L1-VIVT cache is dirty, then in response to the external read request, the cache line location identified in the L1-VIVT cache will be read, otherwise the cache line location identified in the L2-PIPT cache will be read. It is understood by those skilled in the art that there are many other alternative ways to encode and determine that the cache line in the L1-VIVT cache is dirty, including (but not limited to) storing a dedicated cache line state in the selected L2-PIPT cache line location.

[0057] According to at least one example embodiment of the inventive concept, if the CP of the cache line location identified in the L2-PIPT cache can determine that the cache line location identified in the L1-VIVT cache is writable, then in response to the external read request, the cache line location identified in the L1-VIVT cache will be read, otherwise the cache line location identified in the L2-PIPT cache will be read. Those skilled in the art will understand that there are many alternative ways to encode and determine that the cache line in the L1-VIVT cache is writable, including (but not limited to) storing a dedicated cache line state in the selected L2-PIPT cache line location.

[0058] Those skilled in the art will appreciate that there are many possible alternative configurations for the L1 cache, for which Figure 6 The above translation scheme explained will be beneficial. For example, the L1 cache can be a Virtual Index Physical Tagged (VIPT) cache 510, which has such a size / associativity that some of its index bits will be translated based on the translation from virtual address to physical address. Such a configuration will also benefit from the mechanism explained above, because it cannot be determined by the physical address which index is selected in the VIPT cache. It is understood by those skilled in the art that for Figure 6 The explained mechanism is broadly applicable to any low-level cache for which the cache line location of a cache line cannot be determined by an address (physical, virtual or other) provided by some access request to the cache.

[0059] Following are some steps taken in response to some requests according to at least some example embodiments of the inventive concepts.

[0060] According to at least some example embodiments of the inventive concepts, in response to a read request for data identified by a virtual address VA1 that misses in the L1-VIVT cache and hits in the L2-PIPT cache, the following steps are taken:

[0061] 1) VA1 is used to select a set within the L1 cache 625 .

[0062] 2) Compare the VAT of the selected group with certain bits 623 of VA1.

[0063] 3) Comparison determines that the data does not exist in the VIVT cache 625.

[0064] 4) Select the victim cache line location 627.

[0065] 5) Evict the previous cache line stored at that location.

[0066] 6) Perform translation from VA1 to PA1.

[0067] 7) PA1 is used to access L2-PIPT cache 605 .

[0068] 8) Determine that the requested data resides in the hit cache line location 607 .

[0069] 9) Update the CP of the hit cache line location 607 to hold a pointer to the victim cache line location 627.

[0070] 10) Return the requested data to the CPU core 621.

[0071] 11) Update the CP of victim cache line location 627 to hold a pointer to cache line location 607.

[0072] According to at least some example embodiments of the inventive concepts, in response to a read request for data identified by virtual address VA1 that misses in the L1-VIVT cache and misses in the L2-PIPT cache, some additional steps are taken.

[0073] Steps 1-7 will be performed as described above.

[0074] At step 8, it will be determined that the requested data does not exist in the L2-PIPT cache, and additional steps will be included to send a request to the "higher level cache" and select an L2 victim location. Once the data is returned from the "higher level cache", the L2 victim location will take the only hit cache location, and steps 9-11 will continue.

[0075] According to at least some example embodiments of the inventive concepts, in response to evicting a dirty victim cache line from a victim location in an L1-VIVT cache, the following steps will be taken.

[0076] 1) The target location in the L2 cache of the dirty cache line is identified as the location pointed to by the CP of the victim cache line.

[0077] 2) The dirty cache line is sent to the target location in the L2 cache.

[0078] 3) Change the CP of the target location to reflect the fact that the L1 cache no longer contains the dirty victim cache line.

[0079] According to at least some example embodiments of the inventive concepts, when a coherent read request for a physical address PA1 is received through an external request 608, the following steps are taken:

[0080] 1) Determine whether the cache line corresponding to PA1 resides in the L2 cache 605, and identify the cache line location 607 to hold the cache line.

[0081] 2) Determine that the cache line stored in cache line location 607 cannot be used to reply to the request. This may be because, for example, the CP of cache line location 607 encodes that the corresponding cache line location in L1 cache 625 has a dirty cache line, stores a writable cache line (which may have become dirty in this cycle), or has some other reason that makes the cache line in L2 cache 605 unusable for certain coherency requests.

[0082] 3) Read the cache line location 627 in the L1 cache 625 pointed to by the CP and return its data as a response to the coherency request.

[0083] 4) The cache line in L1 cache 625 is demoted to no longer be writable.

[0084] 5) The CP of cache line location 607 in L2 cache 605 is changed to reflect that the cache line in L1 cache 625 is no longer writable or dirty.

[0085] According to at least some example embodiments of the inventive concepts, in response to receiving a consistency invalidation request for the physical address PA1 via the external request 608, the following steps are taken:

[0086] 1) Determine whether the cache line corresponding to PA1 resides in the L2 cache 605, and identify the cache line location 607 to hold the cache line.

[0087] 2) The cache line stored in cache line location 607 is invalidated.

[0088] 3) Check the CP of the cache line location 607 to determine whether there is a corresponding cache line stored in the L1 cache 625 (eg, determine whether the CP of the cache line location 607 is valid).

[0089] 4) The cache line location in the L1 cache 625 pointed to by the CP is invalidated and marked as not readable or writable to the CPU core 621 .

[0090] 5) A confirmation message may be sent as a response to the consistency request.

[0091] Figure 7 is a block diagram for explaining an implementation of a three-level cache hierarchy according to at least some example embodiments of the present invention, wherein the first level is a virtually indexed virtually tagged VIVT cache, and the second and third levels are less tagged physically indexed untagged PINT caches. Figure 7 A system constructed in part from a so-called tag-less cache is shown. A tag-less cache does not store address tags associated with its cache line location. Instead, a special metadata cache hierarchy tracks the location of the system cache lines by storing cache line pointers. Detailed examples of tag-less caches according to at least some example embodiments of the present inventive concepts may be found in Figure 4 Found in. Figure 7 Only the lowest level metadata cache (MD cache) 740 is shown. The MD cache 740 is organized similarly to a conventional cache, e.g. Figure 5 Any cache configuration in may be used in one or more example embodiments of the inventive concept. It may be set associative, skewed associative, fully associative, or any other common cache structure. When an address (e.g., Figure 7 722 shown in FIG. 1 ), it will determine whether the metadata corresponding to the address is contained in its MD cache 740. According to at least one example embodiment of the inventive concept, the metadata of the MD cache 740 is organized into regions, each of which has an address tag ( Figure 7 740). The region may consist of, for example, 16 cache lines, but any number of cache lines is possible. In a VAT match, the region location is identified by an associative lookup in the MD cache 740. The region information stored in the identified region location contains information related to its corresponding cache line. For example, it may store a cache line pointer (CP in the figure) for each of the corresponding cache lines. The CP may, for example, consist of a cache ID (e.g., cache level) and information of an associated way within the cache where each corresponding cache line can be found. It may also store a partial index for looking up in the corresponding cache. The metadata location may also store information applicable to all of its associated cache lines. It may, for example, store physical address information ( Figure 7Other region-wide information stored in a region may include permission bits and certain partial index information applicable to all cache lines of the region.

[0092] Cache line request 728 may, for example, perform a lookup in MD cache 740 and determine its corresponding CP (741). The CP information may be sufficient to find the corresponding cache line in a cache line location in L2 cache 745 or L3 cache 750. If these caches are physically indexed, the PA information from the identified region location may be used to form index information 742 or 752.

[0093] Figure 7 A logic diagram is shown of how to find the corresponding cache line location in the L2 cache 745 and the L3 cache 750. First, the cache ID information of the CP is compared with "L2" in the comparison 747. If there is a match, the way of the CP is used to select the cache line location in the L2 cache 745. If there is a match of cache ID="L3" in the comparison 757, the cache line location corresponding to the way information of the CP is used instead to find the corresponding cache line. Those skilled in the art will understand that knowing the cache ID, way information, and index information of the requested cache line enables direct access to the cache without the need for the comparison 747 or the multiplexer 746, which is shown only as a logic example. Those skilled in the art will also understand that the L2 cache 745 and the L3 cache 750 can be implemented using ordinary memory arrays, such as SRAM, DRAM, NVM, or any other memory technology. Due to Figure 7 The L2 cache 745 and L3 cache 750 in do not contain any tags and are physically addressed, which we refer to as physically indexed, untagged (PINT).

[0094] Figure 7 The "PINT L2 and higher level cache" stores CP information associated with each of its cache line locations. Figure 6 Similar to the system shown, corresponding cache line locations in L1 cache 725 and L2 cache 745 will store cross-CP pointers pointing to each other. Receiving an external request 760 will cause a lookup through MD cache 740 to identify the corresponding cache line location in L2 cache 745, which identifies the corresponding CP and PA. Figure 6The steps of initializing the cross-CP pointer and replying to external requests and evicting cache lines from the L1 cache are also applicable to how the L2 cache 745 and the L1 cache 725 interact to implement such activities. According to at least one example embodiment of the inventive concept, the partial index information stored as part of the CP of the L2 cache 605 and pointing to the corresponding cache line in the L1-VIVT 625 may be stored as a portion of the CP of the L2 cache 605 instead. Figure 7 A portion of a corresponding region in the MD cache 740 in the depicted system. According to at least one example embodiment of the inventive concept, if it can be determined that all cache lines of a region always have the same partial index information for indexing to the L1-VIVT cache 725, then the partial region information can be stored as region-wide information in the corresponding region location, which is more efficient than storing the index information for each cache line separately. According to at least one example embodiment of the inventive concept, the L1-VIVT cache 725 is direct mapped, and there is no need to store way information in the CP of the L2 cache 745. For this configuration, it may be sufficient to implement the CP in the L2 cache 745 as a single valid bit indicating whether a corresponding cache line exists in the L1 cache 725. In this configuration, the region-wide index information stored in the MD cache 740 can be used to find the corresponding cache line location in the L1 cache 725.

[0095] Figure 8 is a block diagram for explaining the implementation of a three-level cache hierarchy according to at least some example embodiments of the present invention, wherein the first level is an untagged VINT cache with few tags of virtual indexes, and the second and third levels are untagged PINT caches with few tags of physical indexes. Figure 8 Similar to Figure 7 , which depicts the same "PINTL2 and higher cache". However, the L1 cache 825 is a less-tagged cache, a virtually indexed, untagged (VINT) cache. The CP of the MD cache 840 has been extended here to store the location information 823 of the L1 cache 825. Subsequently, the VAT tag is not included in the L1 cache 825. Instead, the extended location information 823 of the MD cache 840 is used to select the corresponding cache line of the L1-VINT. According to at least one example embodiment of the present inventive concept, the LI-VINT is direct-mapped, which is why the location information 823 of the L1 cache can be limited to a single bit.

[0096] According to at least one example embodiment of the inventive concept, a virtual address is used to access Figure 7 and Figure 8In that case, virtual-to-physical translation is required along the path of requests 728 and 828 from the L1-VIVT cache and the L1-VINT cache.

[0097] According to at least one example embodiment of the inventive concept, a virtual address is used to access Figure 7 and Figure 8 In that case, physical to virtual translation is required along the path of external requests 760 and 860.

[0098] According to at least one example embodiment of the inventive concept, the virtual addresses from the L1-VIVT cache and the L1-VINT cache are used to access the cache memory along the 728 and 828 paths. Figure 7 and Figure 8 MD cache of the present invention, and the external requests 760 and 860 carry information identifying the location of the region within the MD cache 740 and 840 associated with the requested cache line. According to at least one example embodiment of the inventive concept, similar to Figure 4 The structure of CLB2 420 is used to translate the physical address carried by the external request into a CLB1 pointer (CIP 423 ), which identifies the cache location entry CLE (also called region location) within CLB1 corresponding to MD caches 740 and 840 .

[0099] To overcome some of the artifacts of direct-mapped VIVT caches or VIVT caches with low associativity, especially considering the possible use of SMT cores, the L1 cache can be partially indexed by a scrambled index. Its index [15-12] consists of an XOR function between some address bits and some ASID bits. In this way, two identical programs running simultaneously on SMT threads (e.g., SPEC rates) are less likely to thrash the cache. Furthermore, two threads from the same process are less likely to thrash each other, even if their parallel runtime systems allocate dedicated stacks / heaps with power-of-two alignment (as was the case with some early multithreaded runtime systems). There are many choices for the scrambled index function. It could be an XOR function between some ASID bits, some higher address bits, and some lower address bits, for example,

[0100] INDEX[15-12]=VA[15-12]XOR VA{21,22,25,27}XOR ASID[3-0].

[0101] The use of such garbled index bits forces the use of 4 additional L1VAT tag bits for cache 725, since there is no longer a 1:1 mapping between INDEX[15-12] and VA[15-12].

[0102] A new field SI(4)-(Gibberish Index) in the MD cache can store a gibberish INDEX[15-12] for each region to allow external requests to access data in the L1 cache.

[0103] Combination Figure 6 The steps described may be performed in various orders, and some steps may be performed in parallel or sequentially. These method embodiments, system embodiments, and other embodiments described above may provide various beneficial results. For example, detailed simulation studies that have been performed according to one or more example embodiments of the present invention have shown that cache implementations associated with one or more example embodiments of the present invention may save a significant amount of energy compared to conventional cache systems, and may also result in caches having significantly shorter access times.

[0104] Although for clarity, much of the description herein generally describes techniques for locating a cache line and returning it to a requesting CPU, it will be apparent to those skilled in the art that there are a variety of ways to select a requested word contained in a cache line and return it to a CPU.

[0105] For clarity, most of the descriptions of the processing of data in the cache hierarchy herein describe an exclusive cache hierarchy. It will be appreciated by those skilled in the art that one or more example embodiments of the inventive concept can be extended to also cover inclusive memory hierarchies and non-exclusive memory hierarchies.

[0106] Although one or more exemplary embodiments of the inventive concept described above may be related to a single processor system and a multi-processor system, for example, Figure 1 and Figure 2 Although the system shown and described above is shown, one or more exemplary embodiments of the inventive concept are primarily shown in conjunction with a single processor system. However, those skilled in the art will appreciate that one or more exemplary embodiments of the inventive concept shown in conjunction with a single processor system are not limited to such implementations. For example, although for simplicity, Figures 6 to 8 A single CPU is shown, according to at least some example embodiments of the present inventive concepts Figures 6 to 8 Any or all of the portions of the computer system shown in may be part of a multi-processor system.

[0107] Although described above in the context of certain example computer architectures, caches exist in Figures 6 to 8The example computer system shown in and many other settings outside, and those skilled in the art will appreciate that at least some of the example embodiments of the above-described inventive concept in the context of a computer system may also be applied to such other contexts. An example of such use is a virtual memory system that caches data from a slow, high-capacity memory (e.g., a disk or FLASH memory) into a faster and smaller high-capacity memory that can be implemented using dynamic RAM. Other examples of caching in a computer system include (but are not limited to) a disk cache, a web cache, and a name cache. The organization and caching mechanism of such a cache may be different from the cache discussed above, for example, there are variations in the size of the group, the implementation of the group, and the associativity. Regardless of the implementation of the caching mechanism itself, at least some of the example embodiments of the present invention concept are equally applicable to implementing various caching schemes.

[0108] The methods or flow charts provided in the present application may be implemented in a computer program, software or firmware clearly embodied in a computer-readable storage medium for execution by a general-purpose computer or processor.

[0109] Thus having described the exemplary embodiments of the inventive concept, it will be apparent that the exemplary embodiments of the inventive concept may be modified in a variety of ways. These changes should not be regarded as departing from the intended spirit and scope of the exemplary embodiments of the inventive concept, and all such modifications apparent to those skilled in the art are intended to be included within the scope of the appended claims.

Claims

1. A multiprocessor system for supporting interaction between a virtual cache and a physical cache, comprising: A plurality of nodes and at least one memory, each node comprising at least one processor, the at least one processor comprising a first processor; a first cache configured to store a plurality of first cache lines, the first cache being dedicated to at least one node of the plurality of nodes; as well as a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one first cache line of the plurality of first cache lines comprises a first associated pointer pointing to a location of a second cache line of the plurality of second cache lines in the second cache, wherein at least one of the plurality of second cache lines comprises a second associated pointer pointing to a location of a first cache line of the plurality of first cache lines in the first cache, and wherein a data request in response to the first processor of the at least one node results in a cache miss in the first cache because data requested by the data request is not included in any first cache line in the first cache, and a cache hit in the second cache because the data is included in at least one second cache line in the second cache, The first processor is configured to: generating a new cache line, the new cache line holding the data and the pointer, storing the new cache line in the first cache as one of the plurality of first cache lines, The pointer of the new cache line points to the location of the second cache line storing the data.

2. The multiprocessor system according to claim 1, wherein: the first cache being a virtually tagged cache, Each of the plurality of first cache lines includes a virtual tag, The second cache is a physically tagged cache, and Each of the plurality of second cache lines includes a physical tag.

3. The multiprocessor system according to claim 1, wherein: The first cache is a write-through cache such that first data written to a first cache line among the plurality of first cache lines of the first cache is also written to a second cache line among the plurality of second cache lines of the second cache, and The first cache line into which the first data is written includes a pointer pointing to a location of the second cache line into which the first data is written in the second cache.

4. The multiprocessor system according to claim 1, wherein: The first cache is a write-invalidate cache such that in response to a first cache line among the plurality of first cache lines of the first cache being invalidated, a corresponding second cache line among the plurality of second cache lines of the second cache is also invalidated, and The invalidated first cache line includes a pointer pointing to a location of the invalidated corresponding second cache line in the second cache.

5. The multiprocessor system according to claim 1, wherein: The first cache is a write-back cache such that, in response to a first cache line among the plurality of first cache lines being written to and becoming dirty, a second cache line among the plurality of second cache lines pointed to by a pointer included in the dirty first cache line is written to and becomes dirty. is updated when the dirty first cache line is evicted, or The state of the first cache line is changed to reflect that it is dirty and cannot be read.

6. A data management method for a system, for supporting interaction between a virtual cache and a physical cache, the system comprising at least one node, the at least one node comprising a processor to which a first cache, a second cache, and a memory are allocated, the first cache storing a plurality of first cache lines and being dedicated to the at least one node, and the second cache storing a plurality of second cache lines and being at a higher level than the first cache, the data management method comprising: storing a first associated pointer pointing to a location of a second cache line among the plurality of second cache lines in the second cache in a first cache line among the plurality of first cache lines; storing a second associative pointer pointing to a location in the first cache of the first cache line storing the first associative pointer in a second cache line located at the location pointed to by the first associative pointer; sending a request for data from the processor to the first cache and the second cache; and In response to The requested data results in a cache miss in the first cache because the requested data is not included in any first cache line in the first cache, and the requested data resulting in a cache hit in the second cache because the requested data is included in at least one second cache line in the second cache, creating a new cache line holding the requested data and pointer, and storing the new cache line in the first cache as one of the plurality of first cache lines, The pointer of the new cache line points to the location of the second cache line storing the data.

7. The data management method according to claim 6, further comprising: In response to first data being written into a first cache line among the plurality of first cache lines of the first cache, the first data is also written into a second cache line among the plurality of second cache lines of the second cache, The first cache line into which the first data is written includes a pointer pointing to a location of the second cache line into which the first data is written in the second cache.

8. The data management method according to claim 6, further comprising: In response to a first cache line among the plurality of first cache lines of the first cache being invalidated, a corresponding second cache line among the plurality of second cache lines of the second cache is also invalidated, The invalidated first cache line includes a pointer pointing to a location of the invalidated corresponding second cache line in the second cache.

9. The data management method according to claim 6, further comprising: In response to a first cache line in the plurality of first cache lines being written to and becoming dirty, changing a state to reflect that the dirty first cache line is unreadable, The state is a state of a second cache line pointed to by a pointer included in the dirty first cache line among the plurality of second cache lines.

10. The data management method according to claim 6, further comprising: receiving external requests generated by a cache coherence protocol; performing a lookup in the second cache and selecting a second cache line from the plurality of second cache lines; as well as A first cache line pointed to by a pointer included in the selected second cache line is accessed.

11. The data management method according to claim 10, further comprising: When the external request is an invalidation request, both the accessed first cache line and the selected second cache line are invalidated.

12. The data management method according to claim 10, further comprising: When the external request is a read request, data stored in at least one of the accessed first cache line and the selected second cache line is read.

13. The data management method according to claim 6, wherein: The processor is also assigned a virtual to physical address translator, the first cache is a virtually tagged cache, and the second cache is a physically tagged cache, and the method further comprises: performing a lookup of the first cache based on a virtual address included in a data request generated from the processor; When data misses in the first cache, selecting one of the plurality of first cache lines as a victim cache line, and generating a physical address from the virtual-to-physical address translator based on the data request; and A lookup of the second cache is performed based on the physical address.

14. The data management method according to claim 13, wherein: The physical address includes the location of the victim cache line.

15. A non-transitory computer-readable storage medium comprising computer-executable instructions, which, when executed by at least one processor assigned with a virtually tagged cache comprising a plurality of first cache lines, a physically tagged cache comprising a plurality of second cache lines, and a memory, causes the at least one processor to perform a method for supporting interaction between the virtually tagged cache and the physically tagged cache, the method comprising: storing a first associative pointer in a first cache line among the plurality of first cache lines, the first associative pointer pointing to a location of a second cache line among the plurality of second cache lines in the physically tagged cache; storing a second association pointer in a second cache line located at the location pointed to by the first association pointer, the second association pointer pointing to the location of the first cache line storing the first association pointer in the virtually tagged cache; sending a request for data from the processor to the virtually tagged cache and the physically tagged cache; and In response to The requested data results in a cache miss in the virtually tagged cache because the requested data is not included in any first cache line in the virtually tagged cache, and the requested data resulting in a cache hit in the physically tagged cache because the requested data is included in at least one second cache line in the physically tagged cache, creating a new cache line holding the requested data and pointer, and storing the new cache line as one of the plurality of first cache lines in the virtually tagged cache, The pointer of the new cache line points to the location of the second cache line storing the data.

16. The non-transitory computer-readable storage medium of claim 15, wherein: The method further comprises: In response to first data being written to a first cache line among the plurality of first cache lines of the virtually tagged cache, also writing the first data to a second cache line among the plurality of second cache lines of the physically tagged cache, The first cache line into which the first data is written includes a pointer pointing to a location of the second cache line into which the first data is written in the physically tagged cache.

17. The non-transitory computer-readable storage medium of claim 15, wherein: The method further comprises: In response to a first cache line among the plurality of first cache lines of the virtually tagged cache being invalidated, a corresponding second cache line among the plurality of second cache lines of the physically tagged cache is also invalidated, The invalidated first cache line includes a pointer to a location of the invalidated corresponding second cache line in the physically tagged cache.

18. The non-transitory computer-readable storage medium of claim 15, wherein: The method further comprises: In response to a first cache line in the plurality of first cache lines being written to and becoming dirty, changing a state to reflect that the dirty first cache line is unreadable, The state is a state of a second cache line pointed to by a pointer included in the dirty first cache line among the plurality of second cache lines.

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