Semiconductor device structure and its formation method

Abstract

A semiconductor device structure and a method for forming the same are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure on a semiconductor substrate. The method includes forming a first spacer element on the sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming a second spacer element on the sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is higher than the first spacer element. The method includes epitaxially growing semiconductor material on the first fin structure, the second fin structure, and the third fin structure, then forming a merged semiconductor element on the first fin structure and the second fin structure, and forming an isolated semiconductor element on the third fin structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device structure and a method for forming the same, and more particularly to a semiconductor device structure having a fin field effect transistor (FinFET) and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design of ICs have created generations of ICs, each with smaller and more complex circuits than the previous generation.

[0003] In the course of integrated circuit (IC) evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing manufacturing efficiency and reducing associated costs.

[0004] However, such developments have increased the complexity of integrated circuit (IC) processing and manufacturing. As component feature sizes continue to shrink, processes continue to become more difficult to perform. Therefore, it has become a challenge to form reliable semiconductor devices at increasingly smaller sizes. Summary of the invention

[0005] Some embodiments of the present invention provide a method for forming a semiconductor device structure, the method comprising forming a first fin structure, a second fin structure, and a third fin structure on a semiconductor substrate; forming a plurality of first spacer elements on a plurality of sidewalls of the first fin structure and the second fin structure; partially removing the first fin structure and the second fin structure after forming the first spacer elements; forming a plurality of second spacer elements on a plurality of sidewalls of the third fin structure, wherein each second spacer element is higher than each first spacer element; partially removing the third fin structure after forming the second spacer elements; and epitaxially growing a semiconductor material on the first fin structure, the second fin structure, and the third fin structure after partially removing the first fin structure, the second fin structure, and the third fin structure, thereby forming a merged semiconductor element on the first fin structure and the second fin structure, and forming an isolated semiconductor element on the third fin structure.

[0006] Some embodiments of the present invention provide a method for forming a semiconductor device structure, which includes forming a first fin structure, a second fin structure, and a third fin structure on a semiconductor substrate; forming a plurality of spacer elements on the sidewalls of the third fin structure; recessing the third fin structure; recessing the first fin structure and the second fin structure so that a plurality of top surfaces of the first fin structure and the second fin structure are located below the top surface of the third fin structure; and after recessing the first fin structure, the second fin structure, and the third fin structure, epitaxially growing a semiconductor material on the first fin structure, the second fin structure, and the third fin structure, thereby forming a merged semiconductor element on the first fin structure and the second fin structure, and forming an isolated semiconductor element on the third fin structure.

[0007] Some embodiments of the present invention provide a semiconductor device structure, which includes a semiconductor substrate, a first fin structure, a second fin structure, a third fin structure, a plurality of first spacer elements, a plurality of second spacer elements, a merged semiconductor element, and an isolated semiconductor element. The first fin structure, the second fin structure, and the third fin structure are located on the semiconductor substrate. The first spacer element is located on the sidewall of the first fin structure and on the sidewall of the second fin structure. The second spacer element is located on the sidewall of the third fin structure, wherein each second spacer element is higher than each first spacer element. The merged semiconductor element is located on the first fin structure and the second fin structure. The isolated semiconductor element is located on the third fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the content of the embodiments of the present invention. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0009] Figure 1 is a schematic top view of a semiconductor device structure according to some embodiments.

[0010] Figure 2 is a perspective diagram of a stage in a process of forming a semiconductor device structure according to some embodiments.

[0011] Figure 3A to Figure 3J is a schematic cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0012] Figure 4A to Figure 4E is a schematic cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0013] Figure 5 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0014] Figure 6 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0015] Description of reference numerals:

[0016] 10~1st zone;

[0017] 20~Second Zone;

[0018] 100~Semiconductor substrate;

[0019] 102A, 102A', 102A", 102B, 102B', 102B", 102C, 102C', 102D,

[0020] 102D'~Fin structure;

[0021] 104~Isolation components;

[0022] 106~gate dielectric layer;

[0023] 108A, 108B~gate electrodes;

[0024] 110~ patterned hard mask element;

[0025] 112~spacer layer;

[0026] 114, 120, 402 ~ shielding element;

[0027] 116, 116', 121, 121'-spacer elements;

[0028] 118, 124 ~ concave;

[0029] 126A, 126B ~ inner part;

[0030] 128A, 128B ~ external part;

[0031] 129A, 129B ~ surrounding part;

[0032] 130~Integrated semiconductor components;

[0033] 132~Isolating semiconductor components;

[0034] 502~Insulation layer;

[0035] H 1 , H 2 , H 3 、h 1 、h 2 、h 3 、h 4 ~height;

[0036] II, JJ~ line;

[0037] W 1 , W 2 ~width. DETAILED DESCRIPTION

[0038] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present invention may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0039] In addition, spatially relative terms may be used herein, such as "under," "beneath," "below," "above," "above," and other similar terms may be used herein to describe the relationship between an element or component as shown in the figures and other elements or components. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device can be rotated to other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein can also be interpreted based on the rotated orientation.

[0040] Some embodiments of the present invention are described below. Additional operating steps may be provided before, between, and / or after the various stages described in these embodiments. For different embodiments, some of the stages described herein may be replaced or eliminated. Additional components may be added to the semiconductor device structure. For different embodiments, some of the components described herein may be replaced or eliminated. Although in the discussion of some embodiments, some operating steps are performed in a specific order, these operating steps may be performed in other logical orders.

[0041] Some embodiments of the present invention may relate to a fin field effect transistor (FinFET) structure having a fin. The fin may be patterned by any suitable method. For example, the fin may be patterned using one or more photolithography processes, such as a double-patterning or multi-patterning process. In general, the double- or multi-patterning process is combined with photolithography and a self-aligned process so that the pitch of the pattern produced is, for example, smaller than the pitch obtained by a single direct photolithography process in other cases. For example, in some embodiments, a sacrificial layer is formed on a substrate and a photolithography process is used to pattern the sacrificial layer. Spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. However, the fin may also be formed using one or more other applicable processes.

[0042] Figure 1 1 is a schematic top view of a semiconductor device structure according to some embodiments. In some embodiments, the semiconductor device structure includes a first region 10 and a second region 20. The second region 20 may be a memory cell region including a plurality of memory devices. In some embodiments, the second region 20 includes a plurality of static random-access memory (SRAM) devices. The first region 10 may be a pickup region including a plurality of devices. These devices may be electrically connected to the memory devices in the second region 20. The first region 10 and the second region 20 may each include a plurality of fin field effect transistors (FinFETs).

[0043] Figure 2 is a perspective view of a stage of a process for forming a semiconductor device structure according to some embodiments. Figure 2 One FinFET in the first region 10 and one FinFET in the second region are presented.

[0044] Figure 3A to Figure 3J is a cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 3A As shown, a semiconductor substrate 100 is received or provided. Some parts of the first region 10 and the second region 20 are shown in the figure. In some embodiments, as Figure 3A The first zone 10 shown corresponds to the Figure 2 The cross-sectional view of line II is as follows: Figure 3A The second zone 20 shown corresponds to the Figure 2 A cross-sectional view of line JJ.

[0045] In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the semiconductor substrate 100 includes silicon or other elemental semiconductor materials, such as germanium. The semiconductor substrate 100 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or any combination thereof. In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator (SOI) substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other applicable methods, or any combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multilayer structure. For example, the semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.

[0046] According to some embodiments, Figure 3A and Figure 2 As shown, a plurality of recesses (or trenches) are formed in the semiconductor substrate 100. In this way, a plurality of fin structures including fin structures 102A, 102B, 102C, and 102D are formed or defined between the recesses. In some embodiments, the recesses are formed using one or more photolithography and etching processes. In some embodiments, the fin structures 102A, 102B, 102C, and 102D directly contact the semiconductor substrate 100. Figure 3A As shown, each fin structure 102A, 102B, 102C, and 102D has a height H 1 . Height H 1 It may be in the range of about 50 nanometers to about 60 nanometers.

[0047] However, the embodiments of the present invention have many variations and / or modifications. In some other embodiments, the fin structures 102A, 102B, 102C, and 102D do not directly contact the semiconductor substrate 100. One or more material layers may be formed between the semiconductor substrate 100 and the fin structures 102A, 102B, 102C, and 102D. For example, a dielectric layer may be formed therebetween.

[0048] According to some embodiments, Figure 3A and Figure 2As shown, an isolation feature 104 is formed in the recess to surround the lower end portions of the fin structures 102A, 102B, 102C, and 102D. The isolation feature 104 is used to define and electrically isolate a plurality of device elements formed in and / or on the semiconductor substrate 100. In some embodiments, the isolation feature 104 includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or any combination thereof.

[0049] In some embodiments, each isolation component 104 has a multi-layer structure. In some embodiments, the isolation component 104 is made of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low dielectric constant material, one or more other suitable materials, or any combination thereof. In some embodiments, a shallow trench isolation (STI) liner (not shown) is formed to reduce crystallization defects at the interface between the semiconductor substrate 100 and the isolation component 104. Similarly, the shallow trench isolation (STI) liner can also be used to reduce crystallization defects at the interface between the isolation component 104 and the fin structures 102A, 102B, 102C and 102D.

[0050] In some embodiments, a dielectric material layer is deposited on the semiconductor substrate 100. The dielectric material layer covers the fin structures 102A, 102B, 102C, and 102D, and fills the recesses between the fin structures. In some embodiments, the dielectric material layer is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a spin-on process, one or more other applicable processes, or any combination thereof. In some embodiments, a planarization process is used to thin the dielectric material layer downward until the fin structures 102A, 102B, 102C, and 102D or the hard mask elements used to define the fin structures are exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other applicable processes, or any combination thereof. Afterwards, the dielectric material layer is etched back, so that the fin structures 102A, 102B, 102C, and 102D after the etching process protrude from the top surface of the remaining dielectric material layer. Figure 3A and Figure 2 As shown, the remaining portions of the dielectric material layer form isolation features 104 .

[0051] Then, according to some embodiments, Figure 2 As shown, a plurality of gate stacks are formed on the semiconductor substrate 100 to partially cover the fin structures 102A, 102B, 102C and 102D. Figure 2 As shown, a first gate stack and a second gate stack including gate electrodes 108A and 108B and a gate dielectric layer 106 are formed. The first gate stack partially covers the fin structures 102A and 102B. The second gate stack partially covers the fin structures 102C and 102D.

[0052] In some embodiments, a gate dielectric layer 106 and a gate electrode layer are deposited over the isolation feature 104 and the fin structures 102A, 102B, 102C, and 102D. In some embodiments, the gate dielectric layer 106 may include or be made of silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant, one or more other suitable dielectric materials, or any combination thereof. Examples of high dielectric constant materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high dielectric constant materials, or any combination thereof. In some embodiments, the gate dielectric layer 106 is a dummy gate dielectric layer and is subsequently removed. The dummy gate dielectric layer 106 is, for example, a silicon oxide layer.

[0053] In some embodiments, the gate dielectric layer 106 is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a physical vapor deposition (PVD) process, one or more other suitable processes, or any combination thereof.

[0054] In some embodiments, the gate electrode layer is a dummy gate electrode layer and includes or is made of a semiconductor material, such as polysilicon. For example, the dummy gate electrode layer is deposited using a chemical vapor deposition (CVD) process or other suitable processes.

[0055] Then, according to some embodiments, Figure 2 As shown, a patterned hard mask element 110 is formed on the gate electrode layer. The patterned hard mask element 110 is used to pattern the gate electrode layer and the gate dielectric layer 106 into one or more gate stacks. Then, according to some embodiments, Figure 2 As shown, the gate electrode layer and the gate dielectric layer 106 are etched to form a gate stack by using the patterned hard mask element 110 as an etching mask.

[0056] According to some embodiments, Figure 3BAs shown, a spacer layer 112 is deposited over the fin structures 102A, 102B, 102C, and 102D. The spacer layer 112 extends over the isolation feature 104. The spacer layer 112 also extends over the sidewalls and top surfaces of the fin structures 102A, 102B, 102C, and 102D. In some embodiments, the spacer layer 112 extends over the sidewalls and top surfaces of the gate stack. The spacer layer 112 may be made of or include one or more dielectric materials. Examples of dielectric materials include silicon nitride, silicon oxynitride, silicon carbide, silicon oxide, silicon oxycarbide, one or more other suitable dielectric materials, or any combination thereof. The spacer layer 112 may be deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, one or more other suitable processes, or any combination thereof.

[0057] According to some embodiments, Figure 3C As shown, a mask element 114 is formed to cover a portion of the spacer layer 112 located above the fin structures 102A and 102B. The mask element 114 is used as an etching mask during a subsequent etching process to form the spacer element on the sidewalls of the fin structures 102C and 102D. In some embodiments, the mask element 114 and the spacer layer 112 are made of different materials. In some embodiments, a patterned photoresist layer is used to define the mask element 114. In some other embodiments, the mask element 114 includes a patterned photoresist layer.

[0058] In some embodiments, the mask element 114 is a blanket layer covering the fin structures 102A and 102B. However, embodiments of the present invention may be derived from many variations and / or modifications. In some other embodiments, the mask element 114 is a conformal layer covering the sidewalls and top surfaces of the fin structures 102A and 102B.

[0059] Then, according to some embodiments, Figure 3C As shown, the spacer layer 112 not covered by the mask element 114 is partially removed. As a result, some remaining portions of the spacer layer 112 form spacer elements 116 on the sidewalls of the fin structures 102C and 102D. Some other remaining portions of the spacer layer 112 can form gate spacer elements on the sidewalls of the gate stack not covered by the mask element 114. For example, the gate spacer elements are formed on the sidewalls of the gate electrode 108B. In some embodiments, an etching process is used to partially remove the spacer layer 112 to form the spacer elements 116. The etching process can be an anisotropic etching process.

[0060] In some embodiments, the etching process used to form the spacer elements 116 is a plasma-involved dry etching process. A mixture of gases may be used to generate the plasma. The mixture of gases may include CH 4 , HBr, O 2 , one or more other suitable gases, or any combination of the foregoing.

[0061] According to some embodiments, Figure 3D As shown, the fin structures 102C and 102D are partially removed. In this way, recessed (or thinned) fin structures 102C' and 102D' are formed. In some embodiments, an etching process is used to partially remove the fin structures 102C and 102D. In some embodiments, the etching process used to partially remove the fin structures 102C and 102D is a plasma dry etching process. A mixture of gases may be used to generate plasma. The mixture of gases may include HBr, O 2 , one or more other suitable gases, or any combination of the foregoing.

[0062] The etchant used in the etching process may also partially or slightly remove the spacer element 116. Therefore, according to some embodiments, Figure 3D As shown, a spacer element 116' is formed that is lower than the spacer element 116. In some embodiments, a recess 118 surrounded by the spacer element 116' is formed on the fin structures 102C' and 102D'.

[0063] According to some embodiments, Figure 3E As shown, the mask element 114 is removed and a mask element 120 is formed to cover the spacer element 116' and the fin structures 102C' and 102D'. Figure 3E As shown, a portion of the spacer layer 112 covering the fin structures 102A and 102B is not covered by the mask element 120 and is exposed. The material and formation method of the mask element 120 may be the same as or similar to the material and formation method of the mask element 114.

[0064] According to some embodiments, Figure 3F As shown, the spacer layer 112 not covered by the mask element 120 is partially removed. As a result, some remaining portions of the spacer layer 112 form spacer elements 121 on the sidewalls of the fin structures 102A and 102B. In some embodiments, each spacer element 121 is shorter than each spacer element 116'. Some other remaining portions of the spacer layer 112 can form spacer elements on the sidewalls of the gate stack not covered by the mask element 120. For example, the spacer elements are formed on the sidewalls of the gate stack. Figure 2In some embodiments, an etching process is used to partially remove the spacer layer 112 to form the spacer element 121. The etching process may be an anisotropic etching process.

[0065] In some embodiments, the etching process used to form the spacer element 121 is similar to the etching process of Figure 3C The etching process used to form the spacer element 116 may be the same or similar. In some embodiments, the etching time used to form the spacer element 121 is longer than the etching time used to form the spacer element 116. Figure 3F As shown, each spacer element 121 is shorter than each spacer element 116 or 116'. The etching time for forming the spacer element 121 is in the range of about 30 seconds to about 60 seconds. The etching time for forming the spacer element 116 is in the range of about 20 seconds to about 40 seconds.

[0066] According to some embodiments, Figure 3G As shown, the fin structures 102A and 102B are partially removed. As a result, recessed (or thinned) fin structures 102A' and 102B' are formed. In some embodiments, an etching process is used to partially remove the fin structures 102A and 102B. The etchant used in the etching process can also partially or slightly remove the spacer element 121. Therefore, according to some embodiments, Figure 3G As shown, a spacer element 121' is formed which is lower than the spacer element 121. In some embodiments, a recess 124 surrounded by the spacer element 121' is formed on the fin structures 102A' and 102B'.

[0067] In some embodiments, the etching process for partially removing the fin structures 102A and 102B is similar to the etching process described above. Figure 3C to Figure 3D The etching process for partially removing the fin structures 102C and 102D may be the same or similar. In some embodiments, the etching time for partially removing the fin structures 102A and 102B is longer than the etching time for partially removing the fin structures 102C and 102D. Figure 3G As shown, each fin structure 102A' and 102B' is shorter than each fin structure 102C' and 102D'. The etching time for forming the (recessed) fin structures 102A' and 102B' is in the range of about 30 seconds to about 60 seconds. The etching time for forming the (recessed) fin structures 102C' and 102D' is in the range of about 20 seconds to about 50 seconds.

[0068] Many variations and / or modifications may be derived from the embodiments of the present invention. In some other embodiments, the spacer element 121 is completely removed during or after forming the fin structures 102A' and 102B'. In these cases, the spacer element 121' is not formed.

[0069] According to some embodiments, Figure 3H As shown, the mask element 120 is removed. As a result, the fin structures 102A', 102B', 102C' and 102D' and the spacer elements 121' and 116' are exposed. In some embodiments, each fin structure 102C' and 102D' is higher than each fin structure 102A' and 102B'. Figure 3H As shown, the top surface of the fin structure 102C' or 102D' is higher than the top surfaces of the fin structures 102A' and 102B'.

[0070] In some embodiments, such as Figure 3H As shown, the top surfaces of the fin structures 102A' and 102B' are lower than the top surface of the isolation feature 104 by a height h. 1 . Height h 1 The height h may be in the range of about 1 nanometer to about 10 nanometers. In some embodiments, the top surfaces of the fin structures 102C' and 102D' are higher than the top surface of the isolation feature 104 by a height h 2 . Height h 2 It may be in the range of about 5 nanometers to about 15 nanometers.

[0071] In some embodiments, each spacer element 116' is taller than each spacer element 121'. Figure 3H As shown, one or each spacer element 121 ′ has a height h 3 , one or each spacer element 116' has a height h 4 . Height h 3 can be in the range of about 2 nanometers to about 15 nanometers. In some embodiments, the spacer element 121' is completely removed. In these cases, the height h 3 is 0. Height h 4 It can be in the range of about 10 nanometers to about 30 nanometers. In some embodiments, the height h 3 With height h 4 The height ratio (h 3 / h 4 ) is in the range of about 0 to about 0.5. In some cases, if the height ratio (h 3 / h 4 ) is greater than about 0.5, then the height h 3 It may be too high, which may have a negative impact on the subsequent epitaxial growth of the merged semiconductor structure.

[0072] According to some embodiments, Fig. 3I As shown, one or more semiconductor materials are epitaxially grown on the fin structures 102A', 102B', 102C' and 102D'. In this way, a merged semiconductor element 130 is formed on the fin structures 102A' and 102B'. The merged semiconductor element 130 has a first portion connected to the fin structure 102A' and a second portion connected to the fin structure 102B'. An isolation semiconductor element 132 is formed on the fin structures 102C' and 102D', respectively. The merged semiconductor element 130 can be used as a source / drain structure of a transistor. The isolation semiconductor elements 132 separated from each other and separated by a distance can be used as source / drain structures of different transistors. In some embodiments, the merged semiconductor element 130 and the isolation semiconductor element 132 are formed simultaneously.

[0073] In some embodiments, such as Fig. 3I As shown, the merged semiconductor element 130 is wider and taller than the individual isolated semiconductor elements 132. Fig. 3I As shown, the merged semiconductor element 130 has a width W 1 , each isolated semiconductor element 132 has a width W 2 Width W 1 Greater than width W 2 Therefore, the combined semiconductor element 130 has a larger area than the isolated semiconductor element 132. Therefore, the resistance between the combined semiconductor element 130 and the conductive contact formed thereon can be reduced, which significantly improves the electrical characteristics of the semiconductor device structure.

[0074] like Fig. 3I As shown, the combined semiconductor element 130 has a height H 2 , and each isolation semiconductor element 132 has a height H 3 In some embodiments, the height H 2 Greater than height H 3 In some embodiments, Figure 3A As shown, each fin structure 102A, 102B, 102C and 102D originally has a height H 1 In some embodiments, the height H 2 Greater than height H 1 In some embodiments, the height H 3 Less than height H 1 In some other embodiments, the height H 3 Substantially equal to height H 1 .

[0075] The height H of the combined semiconductor element 130 2The height H of the isolation semiconductor element 132 is in the range of about 55 nanometers to about 70 nanometers. 3 In some embodiments, the height H is in the range of about 40 nanometers to about 60 nanometers. 3 Relative to height H 2 The height ratio (H 3 / H 2 ) is in the range of about 0.7 to about 0.9. In some cases, if the height ratio (H 3 / H 2 ) is less than about 0.7, the height difference between the merged semiconductor element 130 and the isolated semiconductor element 132 may be too large. This may have a negative impact on the subsequent formation of the conductive contact. In some other cases, if the height ratio (H 3 / H 2 ) is greater than about 0.9, the isolated semiconductor element 132 may contact the adjacent isolated semiconductor element 132 to form a merged semiconductor element. As a result, the device in the second region 20 may not provide the expected function.

[0076] In some embodiments, the growth of the merged semiconductor element 130 and the isolated semiconductor element 132 is performed simultaneously. In some other embodiments, the growth of the merged semiconductor element 130 and the isolated semiconductor element 132 is performed separately in different processes.

[0077] In some embodiments, because each spacer element 121' has a smaller height and the spacer element 116' has a larger height, the epitaxial growth of semiconductor material on the fin structures 102A' and 102B' is less confined than the epitaxial growth of semiconductor material on the fin structures 102C' and 102D' and surrounded by the spacer elements 116'. Therefore, the epitaxially grown semiconductor material on the fin structures 102A' and 102B' can touch each other and together form the merged semiconductor element 130. Since the spacer element 116' has a larger height compared to the spacer element 121', the epitaxially grown semiconductor material on the fin structures 102C' and 102D' is confined. Therefore, the epitaxially grown semiconductor material on the fin structures 102C' and 102D' does not touch each other. In this way, the isolated semiconductor elements 132 on the fin structures 102C' and 102D' are prevented from touching each other. In some embodiments, based on some design reasons, the isolation semiconductor elements 132 are designed to be separated from each other.

[0078] In some embodiments, the merged semiconductor element 130 and the isolated semiconductor element 132 are made of p-type semiconductor material. For example, the merged semiconductor element 130 and the isolated semiconductor element 132 may include epitaxially grown silicon germanium. In some other embodiments, the merged semiconductor element 130 and the isolated semiconductor element 132 are made of n-type semiconductor material. The merged semiconductor element 130 and the isolated semiconductor element 132 may include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown silicon phosphide (SiP), or other suitable epitaxially grown semiconductor materials.

[0079] In some embodiments, the combined semiconductor element 130 and the isolated semiconductor element 132 are formed using a selective epitaxial growth (SEG), a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (CVD) process, and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, one or more other suitable processes, or any combination thereof. The combined semiconductor element 130 and the isolated semiconductor element 132 may be formed using a gas or liquid precursor.

[0080] In some embodiments, the merged semiconductor element 130 and the isolated semiconductor element 132 are grown in the same process chamber. The merged semiconductor element 130 and the isolated semiconductor element 132 may be formed using an in-situ epitaxial growth process.

[0081] The embodiments of the present invention have many variations and / or modifications. In some other embodiments, the integrated semiconductor element 130 and the isolated semiconductor element 132 are grown in different process chambers.

[0082] In some embodiments, the merged semiconductor element 130 and the isolated semiconductor element 132 include dopants. For example, the merged semiconductor element 130 and the isolated semiconductor element 132 are p-type doped, and the dopants include boron, gallium, or a combination thereof. In some embodiments, multiple implantation processes are performed to dope the merged semiconductor element 130 and the isolated semiconductor element 132. In some embodiments, the merged semiconductor element 130 and the isolated semiconductor element 132 are not doped during the growth of the merged semiconductor element 130 and the isolated semiconductor element 132. After the epitaxial growth, the merged semiconductor element 130 and the isolated semiconductor element 132 are doped in a subsequent process.

[0083] In some embodiments, doping is performed using an ion implantation process, a plasma immersion ion implantation process, a gas source and / or solid source diffusion process, one or more other suitable processes, or any combination thereof. In some embodiments, the combined semiconductor element 130 and the isolated semiconductor element 132 are further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

[0084] In some embodiments, the merged semiconductor element 130 and the isolated semiconductor element 132 are doped in-situ during the growth of the merged semiconductor element 130 and the isolated semiconductor element 132. In some embodiments, a first semiconductor-containing gas is introduced into the process chamber to epitaxially grow the inner portion 126A of the merged semiconductor element 130 and the inner portion 126B of the isolated semiconductor element 132. Thereafter, a second semiconductor-containing gas is introduced into the same process chamber to epitaxially grow the outer portion 128A of the merged semiconductor element 130 and the outer portion 128B of the isolated semiconductor element 132. Fig. 3I As shown, outer portion 128A surrounds inner portion 126A, and outer portion 128B surrounds outer portion 126B.

[0085] In some embodiments, the first semiconductor-containing gas and the second semiconductor-containing gas each contain silicon and germanium. In some embodiments, one or both of the first semiconductor-containing gas and the second semiconductor-containing gas contain a dopant. In some embodiments, the second semiconductor-containing gas and the first semiconductor-containing gas have different doping concentrations. In some embodiments, the second semiconductor-containing gas has a higher doping concentration than the first semiconductor-containing gas.

[0086] In some embodiments, outer portion 128B of each isolated semiconductor element 132 has a higher doping concentration than inner portion 126B. In some embodiments, outer portion 128A of merged semiconductor element 130 has a higher doping concentration than inner portion 126A. In some embodiments, inner portion 126A and inner portion 126B have the same doping concentration. In some embodiments, outer portion 128A and outer portion 128B have the same doping concentration. Inner portion 126A and / or inner portion 126B have a doping concentration of about 10 20 atoms / cm 3 ) to about 10 21 atoms / cm 3 The outer portion 128A and / or the outer portion 128B has a doping concentration of about 10 21 atoms / cm 3 to about 10 22atoms / cm 3 within the range.

[0087] In some embodiments, during the growth of the merged semiconductor element 130, the semiconductor materials grown on the adjacent semiconductor fins touch each other and form a plane that allows the semiconductor material to continue to grow at a higher rate than the growth rate of the semiconductor material on the inner portion 126B of the isolated semiconductor element 132. As a result, the outer portion 128A of the merged semiconductor element 130 is larger than the outer portion 128B of the isolated semiconductor element 132. The volume ratio of the outer portion of the merged semiconductor element 130 to the inner portion is greater than the volume ratio of the outer portion of the isolated semiconductor element 132 to the inner portion. The outer portion 128A accounts for a first fraction of the merged semiconductor element 130. The outer portion 128B accounts for a second fraction of the isolated semiconductor element 132. In some embodiments, the first fraction is greater than the second fraction. In some embodiments, the outer portion 128A of the merged semiconductor element 130 is larger than each inner portion 126A. In some embodiments, the outer portion 128B of the isolated semiconductor element 132 is smaller than the inner portion 126B. As described above, the outer portion has a higher doping concentration than the inner portion. Therefore, the merged semiconductor element 130 having a larger outer portion may have a higher conductivity than the isolated semiconductor element 132 .

[0088] According to some embodiments, Figure 3J As shown, a surrounding portion 129A of the merged semiconductor element 130 and a surrounding portion 129B of the isolated semiconductor element 132 are formed. In some embodiments, the surrounding portions 129A and 129B surround the outer portions 128A and 128B, respectively. In some embodiments, the surrounding portion 129A has a lower doping concentration than the outer portion 128A. In some embodiments, the surrounding portion 129B has a lower doping concentration than the outer portion 128B. In some embodiments, the surrounding portions 129A and 129B are formed simultaneously. In some embodiments, the surrounding portions 129A and 129B are formed in-situ in the same process chamber in which the outer portions 128A and 128B are formed.

[0089] In some embodiments, Figure 3A to Figure 3J As shown, two mask elements including mask elements 114 and 120 are used to form spacer elements 121' and 116'. However, the embodiments of the present invention have many variations and / or modifications. In some other embodiments, only one mask element is used to form spacer elements with different heights.

[0090] Figure 4A to Figure 4E is a schematic cross-sectional view of multiple stages of a process for forming a semiconductor device structure according to some embodiments. Figure 4Aas shown, forming or receiving the same or similar Figure 3B The structure shown.

[0091] Then, according to some embodiments, Figure 4B As shown, perform the same or similar Figure 3C to Figure 3D The etching process shown in FIG. 1 is repeated, but the mask element 114 is not formed. In this way, the spacer element 116' is formed, and the fin structure is partially removed to form the Figure 4B Fin structures 102A", 102B", 102C', and 102D' are shown. Spacer elements 116' extend along sidewalls of the fin structures 102A", 102B", 102C', and 102D'.

[0092] Then, according to some embodiments, Figure 4B As shown, a mask element 402 is formed to cover the fin structures 102C' and 102D' and the spacer element 116' surrounding the fin structures 102C' and 102D'. Figure 4B As shown, the fin structures 102A" and 102B" not covered by the mask element 402 and the spacer elements 116' surrounding the fin structures 102A" and 102B" are exposed. Figure 3D The materials and methods of forming the mask element 114 shown may be the same or similar.

[0093] According to some embodiments, Figure 4C As shown, the spacer elements 116' not covered by the mask element 402 are partially removed. As a result, spacer elements 121 shorter than the spacer elements 116' are formed on the sidewalls of the fin structures 102A" and 102B". In some embodiments, each spacer element 121 is shorter than each spacer element 116'. In some embodiments, an etching process is used to partially remove the spacer layer 116' not covered by the mask element 402 to form the spacer elements 121. This etching process can be an anisotropic etching process.

[0094] According to some embodiments, Figure 4D As shown, the fin structures 102A" and 102B" are partially removed. As a result, recessed (or thinned) fin structures 102A' and 102B' are formed. In some embodiments, an etching process is used to partially remove the fin structures 102A" and 102B". The etchant used in the etching process can also partially or slightly remove the spacer element 121. Therefore, according to some embodiments, Figure 4D As shown, a spacer element 121' is formed which is lower than the spacer element 121. In some embodiments, a recess 124 surrounded by the spacer element 121' is formed on the fin structures 102A' and 102B'.

[0095] Many variations and / or modifications may be derived from the embodiments of the present invention. In some other embodiments, the spacer element 121 is completely removed during or after forming the fin structures 102A' and 102B'. In these cases, the spacer element 121' is not formed.

[0096] According to some embodiments, Figure 4E As shown, the mask element 402 is removed. As a result, the fin structures 102A', 102B', 102C' and 102D' and the spacer elements 121' and 116' are exposed. In some embodiments, each fin structure 102C' and 102D' is higher than each fin structure 102A' and 102B'. Figure 4E As shown, the top surface of the fin structure 102C' or 102D' is higher than the top surfaces of the fin structures 102A' and 102B'. In some embodiments, each spacer element 116' is higher than each spacer element 121'.

[0097] According to some embodiments, Figure 4E As shown, one or more semiconductor materials are epitaxially grown on the fin structures 102A', 102B', 102C' and 102D'. Fig. 3I In the embodiment shown, a merged semiconductor element 130 is formed on the fin structures 102A' and 102B'. An isolated semiconductor element 132 is formed on the fin structures 102C' and 102D', respectively. The merged semiconductor element 130 can be used as a source / drain structure of a transistor. The isolated semiconductor elements 132 separated from each other and spaced a distance apart can be used as source / drain structures of different transistors. Then, according to some embodiments, similar to Figure 3J The embodiment shown, as Figure 4E As shown, surrounding portions 129A and 129B are formed.

[0098] The embodiments of the present invention have many variations and / or modifications. In some other embodiments, the fin structures 102A, 102B, 102C, and 102D do not directly contact the semiconductor substrate 100 . Figure 5 5 is a cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, the semiconductor substrate 100 and the fin structures 102A, 102B, 102C, and 102D are separated by an insulating layer 502. The insulating layer 502 may include or be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or any combination thereof. In these cases, the fin structures 102A, 102B, 102C, and 102D may be formed by patterning a semiconductor layer originally formed on the insulating layer 502.

[0099] As mentioned above, in some embodiments, the spacer element 121 ′ is not formed. Figure 6 FIG. 1 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. Figure 6 As shown, the spacer layer 112 located on the sidewalls of the fin structures 102A' and 102B' is completely removed. Figure 6 As shown, the merged semiconductor element 130 may directly contact and extend from the isolation feature 104 .

[0100] The embodiment of the present invention forms spacer elements with different heights on the sidewalls of different fin structures. Because the spacer elements have different heights, the subsequent epitaxial growth of semiconductor materials on multiple fin structures can be limited to different degrees. In this way, a merged semiconductor element and a non-merged semiconductor element are formed in a single epitaxial growth process. The cost and time of production are significantly improved.

[0101] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure on a semiconductor substrate. The method also includes forming a first spacer element on the sidewalls of the first fin structure and the second fin structure. The method also includes partially removing the first fin structure and the second fin structure after forming the first spacer element. Moreover, the method includes forming a second spacer element on the sidewall of the third fin structure, and each second spacer element is higher than each first spacer element. The method includes partially removing the third fin structure after forming the second spacer element. After partially removing the first fin structure, the second fin structure, and the third fin structure, the method also includes epitaxially growing semiconductor material on the first fin structure, the second fin structure, and the third fin structure. In this way, a merged semiconductor element is formed on the first fin structure and the second fin structure, and an isolated semiconductor element is formed on the third fin structure.

[0102] In one embodiment, forming a first spacer element and a second spacer element includes: forming a spacer layer over the first fin structure, the second fin structure, and the third fin structure; removing a first portion of the spacer layer, wherein a first remaining portion of the spacer layer forms the first spacer element; and removing a second portion of the spacer layer, wherein a second remaining portion of the spacer layer forms the second spacer element.

[0103] In one embodiment, forming the first spacer element and the second spacer element further includes: before removing the second portion of the spacer layer, forming a first mask element to cover a first portion of the spacer layer located above the first fin structure and the second fin structure; after forming the second spacer element, removing the first mask element; forming a second mask element to cover the second spacer element and the third fin structure; and after forming the first spacer element, removing the second mask element.

[0104] In one embodiment, forming a first spacer element and a second spacer element includes: forming a spacer layer over a first fin structure, a second fin structure, and a third fin structure; partially removing the spacer layer so that a first remaining portion of the spacer layer forms the second spacer element, and a second remaining portion of the spacer layer forms the third spacer element over sidewalls of the first fin structure and the second fin structure; forming a mask element to cover the second spacer element and the third fin structure; and after forming the mask element, partially removing the third spacer element, wherein a third remaining portion of the third spacer element forms the first spacer element.

[0105] In one embodiment, the second spacer element is formed before the first spacer element.

[0106] In one embodiment, epitaxially growing a semiconductor material includes: using a first semiconductor-containing gas to epitaxially grow an inner portion of a merged semiconductor element and an inner portion of an isolated semiconductor element; and using a second semiconductor-containing gas to epitaxially grow an outer portion of the merged semiconductor element and an outer portion of the isolated semiconductor element, wherein the second semiconductor-containing gas has a higher doping concentration than the first semiconductor-containing gas.

[0107] In one embodiment, the outer portion of the merged semiconductor element is larger than the outer portion of the isolated semiconductor element.

[0108] In one embodiment, the merged semiconductor device and the isolated semiconductor device are formed simultaneously.

[0109] In one embodiment, the formation method further includes forming an isolation component to surround lower end portions of the first fin structure, the second fin structure, and the third fin structure, wherein: after partially removing the first fin structure and the second fin structure, top surfaces of the first fin structure and the second fin structure are located below the top surface of the isolation component, and after partially removing the third fin structure, the top surface of the third fin structure is located above the top surface of the isolation component.

[0110] In one embodiment, the formation method further includes: before forming the first spacer element and the second spacer element, forming a first gate stack partially covering the first fin structure and the second fin structure; and before forming the first spacer element and the second spacer element, forming a second gate stack partially covering the third fin structure.

[0111] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure on a semiconductor substrate. The method also includes forming a spacer element on the sidewall of the third fin structure. The method also includes recessing the third fin structure, and recessing the first fin structure and the second fin structure, so that the top surfaces of the first fin structure and the second fin structure are located below the top surface of the third fin structure. Furthermore, the method includes epitaxially growing semiconductor material on the first fin structure, the second fin structure, and the third fin structure after recessing the first fin structure, the second fin structure, and the third fin structure. In this way, a merged semiconductor element is formed on the first fin structure and the second fin structure, and an isolated semiconductor element is formed on the third fin structure.

[0112] In one embodiment, forming a spacer element includes: forming a spacer layer over a first fin structure, a second fin structure, and a third fin structure; and removing a portion of the spacer layer located on a sidewall of the third fin structure so that a remaining portion of the spacer layer located on the sidewall of the third fin structure forms a spacer element.

[0113] In one embodiment, the formation method further includes: forming a first mask element to cover a first portion of the spacer layer located above the first fin structure and the second fin structure; after forming the spacer element, removing the first mask element; forming a second mask element to cover the spacer element and the third fin structure; after forming the second mask element, removing at least a portion of the spacer layer located above the sidewalls of the first fin structure and the second fin structure; and removing the second mask element.

[0114] In one embodiment, the spacer layer located on the sidewalls of the first fin structure and the sidewalls of the second fin structure is completely removed.

[0115] In one embodiment, epitaxially growing a semiconductor material includes: using a first semiconductor-containing gas to epitaxially grow an inner portion of a merged semiconductor element and an inner portion of an isolated semiconductor element; and using a second semiconductor-containing gas to epitaxially grow an outer portion of the merged semiconductor element and an outer portion of the isolated semiconductor element, wherein the second semiconductor-containing gas has a higher doping concentration than the first semiconductor-containing gas.

[0116] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure, a second fin structure, and a third fin structure located on the semiconductor substrate. The semiconductor device structure also includes a first spacer element located on a sidewall of the first fin structure and on a sidewall of the second fin structure. The semiconductor device structure also includes a second spacer element located on a sidewall of the third fin structure. Each second spacer element is higher than each first spacer element. Furthermore, the semiconductor device structure includes a merged semiconductor element located on the first fin structure and the second fin structure. The semiconductor device structure also includes an isolated semiconductor element located on the third fin structure.

[0117] In one embodiment, the merged semiconductor element has a first height, the isolated semiconductor element has a second height, and a ratio of the second height to the first height is in a range of about 0.7 to about 0.9.

[0118] In one embodiment, a top surface of the third fin structure is higher than a top surface of the first fin structure.

[0119] In one embodiment, the isolated semiconductor element includes a first portion located on a third fin structure and a second portion surrounding the first portion, and the second portion of the isolated semiconductor element has a higher doping concentration than the first portion of the isolated semiconductor element. The merged semiconductor element includes a third portion located on the first fin structure, a fourth portion located on the second fin structure, and a fifth portion surrounding the third portion and the fourth portion, and the fifth portion of the merged semiconductor element has a higher doping concentration than the third portion or the fourth portion of the merged semiconductor element.

[0120] In one embodiment, the fifth portion accounts for a first fraction of the combined semiconductor element, the second portion accounts for a second fraction of the isolated semiconductor element, and the first fraction is greater than the second fraction.

[0121] The above summarizes the components of several embodiments so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as defined by the claims.

Claims

1. A method for forming a semiconductor device structure, comprising: Forming a first fin structure, a second fin structure, and a third fin structure on a semiconductor substrate; forming a plurality of first spacer elements over a plurality of sidewalls of the first fin structure and the second fin structure; After forming the first spacer elements, partially removing the first fin structure and the second fin structure; forming a plurality of second spacer elements on a plurality of sidewalls of the third fin structure, wherein each of the second spacer elements is higher than each of the first spacer elements, and the second spacer elements are formed before forming the first spacer elements; After forming the second spacer elements, partially removing the third fin structure; and After partially removing the first fin structure, the second fin structure, and the third fin structure, a semiconductor material is epitaxially grown on the first fin structure, the second fin structure, and the third fin structure to form a merged semiconductor element on the first fin structure and the second fin structure, and to form an isolated semiconductor element on the third fin structure.

2. The method of claim 1 , wherein forming the first spacer elements and the second spacer elements comprises: forming a spacer layer on the first fin structure, the second fin structure, and the third fin structure; removing a first portion of the spacer layer, wherein a first remaining portion of the spacer layer forms the first spacer elements; as well as A second portion of the spacer layer is removed, wherein a second remaining portion of the spacer layer forms the second spacer elements.

3. The method of forming as claimed in claim 2, wherein forming the first spacer elements and the second spacer elements further comprises: Before removing the second portion of the spacer layer, forming a first mask element to cover a first portion of the spacer layer located above the first fin structure and the second fin structure; After forming the second spacer elements, removing the first mask element; forming a second mask element to cover the second spacer elements and the third fin structure; as well as After forming the first spacer elements, the second mask element is removed.

4. The method of claim 1 , wherein forming the first spacer elements and the second spacer elements comprises: forming a spacer layer on the first fin structure, the second fin structure, and the third fin structure; Partially removing the spacer layer so that a first remaining portion of the spacer layer forms the second spacer elements and a second remaining portion of the spacer layer forms a plurality of third spacer elements on the sidewalls of the first fin structure and the second fin structure; forming a mask element to cover the second spacer elements and the third fin structure; and After forming the mask element, the third spacer elements are partially removed, wherein a third remaining portion of the third spacer elements forms the first spacer elements.

5. The method of claim 1 , wherein epitaxially growing the semiconductor material comprises: epitaxially growing an inner portion of the merged semiconductor element and an inner portion of the isolated semiconductor element using a first semiconductor-containing gas; as well as An outer portion of the merged semiconductor element and an outer portion of the isolated semiconductor element are epitaxially grown using a second semiconductor-containing gas, wherein the second semiconductor-containing gas has a higher dopant concentration than the first semiconductor-containing gas. 6 . The method of claim 5 , wherein the outer portion of the merged semiconductor element is larger than the outer portion of the isolated semiconductor element. 7 . The method of claim 1 , wherein the merged semiconductor element and the isolated semiconductor element are formed simultaneously.

8. The method of forming as claimed in claim 1 , further comprising forming an isolation member to surround lower end portions of the first fin structure, the second fin structure, and the third fin structure, wherein: After partially removing the first fin structure and the second fin structure, top surfaces of the first fin structure and the second fin structure are located below a top surface of the isolation component; as well as After partially removing the third fin structure, a top surface of the third fin structure is located above the top surface of the isolation feature.

9. The forming method according to claim 1, further comprising: Before forming the first spacer elements and the second spacer elements, forming a first gate stack partially covering the first fin structure and the second fin structure; as well as Before forming the first spacer elements and the second spacer elements, a second gate stack is formed partially covering the third fin structure.

10. A method for forming a semiconductor device structure, comprising: Forming a first fin structure, a second fin structure and a third fin structure on a semiconductor substrate; forming a plurality of spacer elements over a plurality of sidewalls of the third fin structure; recessing the third fin structure; Recessing the first fin structure and the second fin structure so that top surfaces of the first fin structure and the second fin structure are located below a top surface of the third fin structure; After the first fin structure, the second fin structure, and the third fin structure are recessed, a semiconductor material is epitaxially grown on the first fin structure, the second fin structure, and the third fin structure, so that a merged semiconductor element is formed on the first fin structure and the second fin structure, and an isolated semiconductor element is formed on the third fin structure, wherein the epitaxial growth of the semiconductor material includes: epitaxially growing an inner portion of the merged semiconductor element and an inner portion of the isolated semiconductor element using a first semiconductor-containing gas; as well as An outer portion of the merged semiconductor element and an outer portion of the isolated semiconductor element are epitaxially grown using a second semiconductor-containing gas, wherein the second semiconductor-containing gas has a higher dopant concentration than the first semiconductor-containing gas.

11. The forming method as claimed in claim 10, wherein forming the spacer elements comprises: forming a spacer layer on the first fin structure, the second fin structure, and the third fin structure; as well as A portion of the spacer layer located above the sidewalls of the third fin structure is removed so that a remaining portion of the spacer layer located above the sidewalls of the third fin structure forms the spacer elements.

12. The forming method according to claim 11, further comprising: forming a first mask element to cover a first portion of the spacer layer located above the first fin structure and the second fin structure; After forming the spacer elements, removing the first mask element; forming a second mask element to cover the spacer elements and the third fin structure; After forming the second mask element, removing at least a portion of the spacer layer located on a plurality of sidewalls of the first fin structure and the second fin structure; as well as The second mask element is removed. 13 . The forming method according to claim 12 , wherein the spacer layer located on the sidewalls of the first fin structure and the second fin structure is completely removed. 14 . The forming method according to claim 12 , wherein the spacer layer on the sidewalls of the first fin structure and the second fin structure is partially removed.

15. A method for forming a semiconductor device structure, comprising: forming a first fin structure and a second fin structure on a semiconductor substrate; forming a spacer layer on a sidewall of the first fin structure and a sidewall of the second fin structure; partially removing the spacer layer to form a first spacer element on the sidewall of the second fin structure; recessing the second fin structure; partially removing the spacer layer to form a second spacer element on the sidewall of the first fin structure; After recessing the second fin structure, recessing the first fin structure so that the second fin structure is higher than the first fin structure; as well as A semiconductor material is epitaxially grown on the first fin structure and the second fin structure to form a first semiconductor element and a second semiconductor element on the first fin structure and the second fin structure respectively after the second fin structure is recessed. 16 . The method of claim 15 , wherein after recessing the first fin structure, the first spacer element is taller than the second spacer element. 17 . The method of claim 16 , wherein the first spacer element is formed before the second spacer element is formed.

18. The method of forming as claimed in claim 15, further comprising forming an isolation member surrounding lower end portions of the first fin structure and the second fin structure, wherein: After recessing the second fin structure, a top surface of the second fin structure is above a top surface of the isolation feature; as well as After recessing the first fin structure, a top surface of the first fin structure is located below the top surface of the isolation feature.

19. The method of claim 15, wherein epitaxially growing the semiconductor material comprises: epitaxially growing an inner portion of the first semiconductor element and an inner portion of the second semiconductor element using a first semiconductor-containing gas; as well as An outer portion of the first semiconductor element and an outer portion of the second semiconductor element are epitaxially grown using a second semiconductor-containing gas, wherein the second semiconductor-containing gas has a higher dopant concentration than the first semiconductor-containing gas. 20 . The method of claim 19 , wherein the outer portion of the first semiconductor element is larger than the outer portion of the second semiconductor element.

21. A semiconductor device structure, comprising: a semiconductor substrate; A first fin structure, a second fin structure, and a third fin structure are located on the semiconductor substrate; A plurality of first spacer elements are located on a plurality of sidewalls of the first fin structure and a plurality of sidewalls of the second fin structure; a plurality of second spacer elements disposed on a plurality of sidewalls of the third fin structure, wherein each second spacer element is higher than each first spacer element; a merged semiconductor element located on the first fin structure and the second fin structure; an isolation semiconductor element, located on the third fin structure; as well as An isolation component is located on the semiconductor substrate and at least partially surrounds the first fin structure, the second fin structure, and the third fin structure, wherein a top surface of the first fin structure is located below a top surface of the isolation component, and a top surface of the third fin structure is located above the top surface of the isolation component. 22 . The semiconductor device structure of claim 21 , wherein the merged semiconductor element has a first height, the isolated semiconductor element has a second height, and a ratio of the second height to the first height is in a range of 0.7 to 0.

9. 23 . The semiconductor device structure of claim 21 , wherein the top surface of the third fin structure is higher than the top surface of the first fin structure.

24. The semiconductor device structure of claim 21, wherein: The isolation semiconductor element comprises a first portion located on the third fin structure and a second portion surrounding the first portion; The second portion of the isolated semiconductor element has a higher doping concentration than the first portion of the isolated semiconductor element; The merged semiconductor device includes a third portion located on the first fin structure, a fourth portion located on the second fin structure, and a fifth portion surrounding the third portion and the fourth portion; as well as The fifth portion of the merged semiconductor element has a higher doping concentration than the third portion or the fourth portion of the merged semiconductor element. 25 . The semiconductor device structure of claim 24 , wherein the fifth portion accounts for a first fraction of the combined semiconductor element, the second portion accounts for a second fraction of the isolated semiconductor element, and the first fraction is greater than the second fraction.

26. The semiconductor device structure of claim 21, wherein the merged semiconductor element is closer to the semiconductor substrate than the isolated semiconductor element. 27 . The semiconductor device structure of claim 21 , wherein the second spacer elements extend across an interface between the isolation semiconductor element and the third fin structure.

28. The semiconductor device structure of claim 21, wherein the merged semiconductor element is separated from the isolation feature by the first spacer elements.

29. The semiconductor device structure of claim 21, wherein the top surface of the first fin structure is separated from the top surface of the isolation component by a first distance, the top surface of the third fin structure is separated from the top surface of the isolation component by a second distance, and the second distance is greater than the first distance.

30. The semiconductor device structure of claim 21, wherein the first spacer elements are separated from the second spacer elements.

31. A semiconductor device structure comprising: a semiconductor substrate; A first fin structure, a second fin structure, and a third fin structure are located on the semiconductor substrate; A plurality of spacer elements are located on a plurality of sidewalls of the third fin structure, wherein a top of the first fin structure is closer to the semiconductor substrate than tops of the spacer elements; a merged epitaxial structure located on the first fin structure and the second fin structure; as well as An isolated epitaxial structure is located on the third fin structure, wherein compared with the isolated epitaxial structure, the merged epitaxial structure is closer to the semiconductor substrate. 32 . The semiconductor device structure of claim 31 , further comprising an isolation component disposed on the semiconductor substrate and at least partially surrounding the first fin structure, the second fin structure, and the third fin structure.

33. The semiconductor device structure of claim 32, wherein the merged epitaxial structure is in direct contact with the isolation feature, and the isolation epitaxial structure is separated from the isolation feature by the spacer elements.

34. The semiconductor device structure of claim 32, further comprising a plurality of second spacer elements, the second spacer elements being disposed between the merged epitaxial structure and the isolation feature, and each second spacer element being shorter than each spacer element.

35. The semiconductor device structure of claim 31, wherein the merged epitaxial structure is taller than the isolated epitaxial structure.

36. A semiconductor device structure comprising: a semiconductor substrate; A first fin structure and a second fin structure are located on the semiconductor substrate, wherein a top surface of the first fin structure is closer to the semiconductor substrate than a top surface of the second fin structure; a first epitaxial structure located on the first fin structure; as well as A second epitaxial structure is located on the second fin structure, wherein the first epitaxial structure is wider than the second epitaxial structure, the first epitaxial structure has a first height, the second epitaxial structure has a second height, and the ratio of the second height to the first height is in the range of 0.7 to 0.

9.

37. The semiconductor device structure of claim 36, wherein the first epitaxial structure is taller than the second epitaxial structure.

38. The semiconductor device structure of claim 36, further comprising: a first spacer element, located below the first epitaxial structure and in contact with the first epitaxial structure; as well as A second spacer element is located below the second epitaxial structure and directly contacts the second epitaxial structure.

39. The semiconductor device structure of claim 38, wherein the second spacer element is taller than the first spacer element. 40 . The semiconductor device structure of claim 36 , further comprising an isolation component located on the semiconductor substrate and at least partially surrounding the first fin structure and the second fin structure, wherein the first epitaxial structure is in direct contact with the isolation component.

Images