Continuous gate and fin spacers for advanced integrated circuit structure fabrication

Abstract

Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and more particularly in the field of 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent to a sidewall of a lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer being continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed on November 30, 2017, entitled “ADVANCED INTEGRATED CIRCUITSTRUCTURE FABRICATION,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and in particular, 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. Background Art

[0004] Over the past few decades, feature scaling in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased within the limited footprint of semiconductor chips. For example, shrinking transistor size allows for the integration of increased numbers of memory or logic devices on a chip, leading to the manufacture of products with higher capacity. However, the drive for ever-larger capacity is not without its challenges. The need to optimize the performance of each device has become increasingly important.

[0005] Variability in conventional and currently known manufacturing processes may limit the possibility of further scaling them to the 10 nm node or sub-10 nm node range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into current manufacturing processes, or their replacement by other current manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A cross-sectional view of the starting structure is shown after deposition of a hard mask material layer formed on an inter-layer dielectric (ILD) layer, but before patterning thereof.

[0007] Figure 1B shows the hard mask layer after patterning by halving the pitch. Figure 1A Cross-sectional view of the structure.

[0008] Figure 2A is a schematic diagram of a pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0009] Figure 2B A cross-sectional view of a semiconductor fin fabricated using a pitch quartering method according to an embodiment of the present disclosure is shown.

[0010] Figure 3ASchematic diagram of a fused fin pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0011] Figure 3B A cross-sectional view of a semiconductor fin fabricated using a fused fin pitch quartering approach according to an embodiment of the present disclosure is shown.

[0012] Figures 4A-4C Depicted are cross-sectional views representing various operations in a method of fabricating a plurality of semiconductor fins, in accordance with an embodiment of the present disclosure.

[0013] Figure 5A A cross-sectional view of a pair of semiconductor fins separated by a triple-layer trench isolation structure according to an embodiment of the present disclosure is shown.

[0014] Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another triple-layer trench isolation structure according to another embodiment of the present disclosure is shown.

[0015] Figures 6A-6D Cross-sectional views illustrating various operations in fabricating a triple-layer trench isolation structure according to an embodiment of the present disclosure are shown.

[0016] Figures 7A-7E Angled three-dimensional cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present disclosure.

[0017] Figures 8A-8F The flowchart of various operations in the method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0018] Figure 9A An embodiment of the present disclosure is shown for an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0019] Figure 9B The invention shows an integrated circuit structure including an epitaxial source or drain region and a multi-layer trench isolation structure according to an embodiment of the present invention. Figure 7E Cross-sectional view taken along the b-b' axis.

[0020] Figure 10 A cross-sectional view of an integrated circuit structure cut at a source or drain position according to an embodiment of the present disclosure is shown.

[0021] Figure 11 A cross-sectional view of another integrated circuit structure cut at a source or drain position according to an embodiment of the present disclosure is shown.

[0022] Figures 12A-12D Depicted are cross-sectional views taken at a source or drain location and representing various operations in a method of fabricating an integrated circuit structure, in accordance with an embodiment of the present disclosure.

[0023] Figure 13A and Figure 13B illustratively, plan views representing various operations in a method of patterning fins with multiple gate spacers to form local isolation structures, in accordance with an embodiment of the present disclosure.

[0024] Figures 14A-14D illustratively, plan views representing various operations in a method of patterning a fin having a single gate spacer to form a local isolation structure, in accordance with another embodiment of the present disclosure.

[0025] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multiple gate spacers for local isolation according to an embodiment of the present disclosure is shown.

[0026] Figure 16A A cross-sectional view of an integrated circuit structure with a fin having a single gate spacer for local isolation according to another embodiment of the present disclosure is shown.

[0027] Figure 16B A cross-sectional view showing where a fin isolation structure may be formed to replace a gate electrode according to an embodiment of the present disclosure is shown.

[0028] Figures 17A-17C Various depth possibilities are shown for fin cuts made using fin trim isolation according to embodiments of the present disclosure.

[0029] Figure 18 A plan view and corresponding cross-sectional view taken along the aa' axis showing possible options for depth of localized locations of a fin cutout within a fin as compared to the depth of wider locations according to an embodiment of the present disclosure are shown.

[0030] Figure 19A and Figure 19B Cross-sectional views are depicted of various operations in a method of selecting a fin end stressor location at an end of a fin having a wide cutout, in accordance with an embodiment of the present disclosure.

[0031] Figure 20A and Figure 20B Cross-sectional views illustrating various operations in a method of selecting a fin end stressor location at an end of a fin having a partial notch, in accordance with an embodiment of the present disclosure.

[0032] Figures 21A-21MCross-sectional views are illustrated of various operations in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs, in accordance with an embodiment of the present disclosure.

[0033] Figures 22A-22D A cross-sectional view illustrating an exemplary structure of a PMOS fin end stressor dielectric plug according to an embodiment of the present disclosure is shown.

[0034] Figure 23A A cross-sectional view of another semiconductor structure having fin tip stress-inducing features according to another embodiment of the present disclosure is shown.

[0035] Figure 23B A cross-sectional view of another semiconductor structure having fin tip stress-inducing features according to another embodiment of the present disclosure is shown.

[0036] Figure 24A An oblique view of a fin with uniaxial tensile stress is shown, according to an embodiment of the present disclosure.

[0037] Figure 24B An oblique view of a fin with uniaxial compressive stress is shown according to an embodiment of the present disclosure.

[0038] Figure 25A and Figure 25B An illustration of a plan view representing various operations in a method of patterning a fin with a single gate spacer to form a local isolation structure at a select gate line cut location is shown, in accordance with an embodiment of the present disclosure.

[0039] Figures 26A-26C The embodiment according to the present disclosure is shown Figure 25B Cross-sectional views of various possibilities for dielectric plugs with multi-notch and fin trim isolation (FTI), local fin notch locations, and multi-notch-only locations for various regions of the structure.

[0040] Figure 27A A plan view and corresponding cross-sectional views of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer of the gate line according to an embodiment of the present disclosure are shown.

[0041] Figure 27B A plan view and corresponding cross-sectional views are shown of an integrated circuit structure having a gate line cutout with a dielectric plug extending beyond the gate line's dielectric spacer according to another embodiment of the present disclosure.

[0042] Figures 28A-28FCross-sectional views are shown of various operations in a method of fabricating an integrated circuit structure having a gate line cutout with a dielectric plug having an upper portion extending out of a dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line in accordance with another embodiment of the present disclosure.

[0043] Figures 29A-29C A plan view and corresponding cross-sectional views are shown of an integrated circuit structure having residual dummy gate material at a portion of a bottom portion of a permanent gate stack according to an embodiment of the present disclosure.

[0044] Figures 30A-30D Cross-sectional views are illustrated of various operations in a method of fabricating an integrated circuit structure having residual dummy gate material at a portion of a bottom portion of a permanent gate stack in accordance with another embodiment of the present disclosure.

[0045] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is shown.

[0046] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is shown.

[0047] Figure 32A A plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0048] Figure 32B The embodiment according to the present disclosure is shown Figure 32A Cross-sectional view taken along the a-a' axis.

[0049] Figure 33A A cross-sectional view of an NMOS device pair and a PMOS device pair according to an embodiment of the present disclosure is shown. The NMOS device pair has differentiated voltage thresholds based on modulated doping, and the PMOS device pair has differentiated voltage thresholds based on modulated doping.

[0050] Figure 33B A cross-sectional view of an NMOS device pair and a PMOS device pair according to another embodiment of the present disclosure is shown. The NMOS device pair has differentiated voltage thresholds based on differentiated gate electrode structures, and the PMOS device pair has differentiated voltage thresholds based on differentiated gate electrode structures.

[0051] Figure 34ACross-sectional views of three NMOS devices and three PMOS devices according to an embodiment of the present disclosure are shown, where the three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0052] Figure 34B A cross-sectional view of three NMOS devices and three PMOS devices according to another embodiment of the present disclosure is shown, wherein the three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0053] Figures 35A-35D Cross-sectional views illustrating various operations in a method of fabricating an NMOS device having differentiated voltage thresholds based on differentiated gate electrode structures, in accordance with an embodiment of the present disclosure.

[0054] Figures 36A-36D Cross-sectional views illustrating various operations in a method of fabricating a PMOS device having differentiated voltage thresholds based on differentiated gate electrode structures, in accordance with an embodiment of the present disclosure.

[0055] Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is shown.

[0056] Figures 38A-38H Cross-sectional views are illustrated of various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow in accordance with an embodiment of the present disclosure.

[0057] Figures 39A-39H Depicted are cross-sectional views representing various operations in a method of fabricating a bisulicide based integrated circuit, in accordance with an embodiment of the present disclosure.

[0058] Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to an embodiment of the present disclosure is shown.

[0059] Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device according to another embodiment of the present disclosure is shown.

[0060] Figure 41A A cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to an embodiment of the present disclosure is shown.

[0061] Figure 41BA cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region according to an embodiment of the present disclosure is shown.

[0062] Figure 42 A plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0063] Figures 43A-43C The flowchart of various operations in the method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 42 Cross-sectional view taken along the a-a' axis.

[0064] Figure 44 The embodiment of the present disclosure shows an integrated circuit structure along the Figure 42 Cross-sectional view taken along the b-b' axis.

[0065] Figure 45A and Figure 45B A plan view and corresponding cross-sectional views are respectively shown of an integrated circuit structure including a trench contact plug having a hard mask material thereon according to an embodiment of the present disclosure.

[0066] Figures 46A-46D Depicted are cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including a trench contact plug having a hard mask material thereon, in accordance with an embodiment of the present disclosure.

[0067] Figure 47A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Figure 47B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0068] Figure 48A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0069] Figures 49A-49D Cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present disclosure.

[0070] Figure 50 A plan view and corresponding cross-sectional views of an integrated circuit structure having a trench contact including an overlying insulating cap layer according to an embodiment of the present disclosure are shown.

[0071] Figures 51A-51F Cross-sectional views of various integrated circuit structures are shown, each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer, according to embodiments of the present disclosure.

[0072] Figure 52A A plan view of another semiconductor device having a gate contact via disposed above an active portion of a gate according to another embodiment of the present disclosure is shown.

[0073] Figure 52B A plan view of another semiconductor device having trench contact vias coupling pairs of trench contacts according to another embodiment of the present disclosure is shown.

[0074] Figures 53A-53E Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure with a gate stack having an overlying insulating cap layer are illustrated in accordance with an embodiment of the present disclosure.

[0075] Figure 54 FIG. 4 is a schematic diagram of a pitch quartering method for manufacturing trenches of an interconnect structure according to an embodiment of the present disclosure.

[0076] Figure 55A A cross-sectional view of a metallization layer fabricated using a pitch-quartering scheme according to an embodiment of the present disclosure is shown.

[0077] Figure 55B A cross-sectional view of a metallization layer fabricated using a pitch-halving scheme over a metallization layer fabricated using a pitch-quartering scheme is shown in accordance with an embodiment of the present disclosure.

[0078] Figure 56A A cross-sectional view of an integrated circuit structure is shown in which a metallization layer having one metal line composition is over a metallization layer having a different metal line composition according to an embodiment of the present disclosure.

[0079] Figure 56B A cross-sectional view of an integrated circuit structure is shown in which a metallization layer having one metal line composition is coupled to a metallization layer having a different metal line composition according to an embodiment of the present disclosure.

[0080] Figures 57A-57C Cross-sectional views of individual interconnect lines with various liner and conductive cap structure arrangements are shown, according to embodiments of the present disclosure.

[0081] Figure 58 A cross-sectional view of an integrated circuit structure is shown in which four metallization layers having one metal line composition and pitch are above two metallization layers having a different metal line composition and smaller pitch, according to an embodiment of the present disclosure.

[0082] Figures 59A-59DCross-sectional views of various interconnect and via arrangements with a bottom conductive layer are shown according to embodiments of the present disclosure.

[0083] Figures 60A-60D A cross-sectional view illustrating a structural arrangement for a recessed line topography of a BEOL metallization layer according to an embodiment of the present disclosure is shown.

[0084] Figures 61A-61D A cross-sectional view illustrating a structural arrangement for a step-line topography of a BEOL metallization layer according to an embodiment of the present disclosure is shown.

[0085] Figure 62A A plan view and corresponding cross-sectional views taken along the aa′ axis of the plan view of a metallization layer according to an embodiment of the present disclosure are shown.

[0086] Figure 62B A cross-sectional view of a wire end or plug is shown according to an embodiment of the present disclosure.

[0087] Figure 62C Another cross-sectional view of a wire end or plug is shown according to an embodiment of the present disclosure.

[0088] Figures 63A-63F Shown are plan views and corresponding cross-sectional views illustrating various operations in a plug finishing scheme according to an embodiment of the present disclosure.

[0089] Figure 64A A cross-sectional view of a conductive wire plug having a seam therein is shown according to an embodiment of the present disclosure.

[0090] Figure 64B A cross-sectional view of a stack of metallization layers including conductive line plugs at underlying metal line locations according to an embodiment of the present disclosure is shown.

[0091] Figure 65 A first view of a cell layout for a memory cell is shown.

[0092] Figure 66 A first view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0093] Figure 67 A second view of the cell layout for a memory cell is shown.

[0094] Figure 68 A second view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the disclosure is shown.

[0095] Figure 69 A third view of the cell layout for a memory cell is shown.

[0096] Figure 70 A third view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0097] Figure 71A and Figure 71B A bit cell layout and a schematic diagram for a six-transistor (6T) static random access memory (SRAM) according to an embodiment of the present disclosure are respectively shown.

[0098] Figure 72 Cross-sectional views of two different layouts for the same standard cell are shown according to embodiments of the present disclosure.

[0099] Figure 73 Shown are plan views of four different cell arrangements indicating even (E) or odd (O) designations according to embodiments of the present disclosure.

[0100] Figure 74 A plan view of a block-level multi-grid according to an embodiment of the present disclosure is shown.

[0101] Figure 75 Exemplary acceptable (pass) layouts based on standard cells with different versions according to embodiments of the present disclosure are shown.

[0102] Figure 76 Exemplary unacceptable (failed) layouts based on standard cells with different versions according to an embodiment of the present disclosure are shown.

[0103] Figure 77 Another exemplary acceptable (pass) layout based on standard cells with different versions according to an embodiment of the present disclosure is shown.

[0104] Figure 78 A partially cut plan view and corresponding cross-sectional views of a fin-based thin film resistor structure according to an embodiment of the present disclosure are shown, wherein the cross-sectional view is taken along the aa′ axis of the partially cut plan view.

[0105] Figures 79-83 Depicted are plan views and corresponding cross-sectional views representing various operations in a method of fabricating a fin-based thin film resistor structure, in accordance with an embodiment of the present disclosure.

[0106] Figure 84 Shown are plan views of fin-based thin film resistor structures with various exemplary locations for anode or cathode electrode contacts according to embodiments of the present disclosure.

[0107] Figures 85A-85D Plan views illustrating various fin geometries for fabricating fin-based precision resistors according to embodiments of the present disclosure.

[0108] Figure 86 A cross-sectional view of a photolithography mask structure according to an embodiment of the present disclosure is shown.

[0109] Figure 87 A computing device according to one embodiment of the present disclosure is shown.

[0110] Figure 88 An interposer including one or more embodiments of the present disclosure is shown.

[0111] Figure 89 is an isometric view of a mobile computing platform according to an embodiment of the present disclosure that employs an IC manufactured according to one or more processes described herein or includes one or more features described herein.

[0112] Figure 90 A cross-sectional view of a flip-chip mounted die is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] Advanced integrated circuit structure fabrication is described. In the following description, numerous specific details, such as specific integration and material systems, are set forth to provide a deeper understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. Furthermore, it should be appreciated that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0114] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, no intention is to be bound by any expressed or implied theory presented in the preceding technical field, background, summary, or the following detailed description.

[0115] This description includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0116] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0117] The term "comprising" is open ended. As used in the appended claims, the term does not exclude additional structures or operations.

[0118] "Configured to." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In this context, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform one or more of those tasks during operation. Thus, even when the specified unit or component is not currently in operation (e.g., not turned on or active), the unit or component may be said to be configured to perform a task. Reciting a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 USC §112, sixth paragraph, for that unit or component.

[0119] "First," "second," etc. As used herein, these terms serve as labels for the nouns that follow them and do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0120] "Coupled"—The following description refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

[0121] In addition, certain terms are used in the following description for reference purposes only and are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the accompanying drawings to which reference is provided. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of a portion of a component within a consistent but arbitrary frame of reference that can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar import.

[0122] "Inhibit"—As used in this application, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent the result, consequence, or future state. Additionally, "inhibit" may refer to reducing or diminishing a consequence, manifestation, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or condition, it does not necessarily completely prevent or eliminate the result or condition.

[0123] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operations, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0124] The embodiments described herein may relate to back-end-of-the-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using lines, such as one or more metallization layers, on a wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0125] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although exemplary processing schemes may be illustrated using FEOL processing scenarios, such approaches may also be applicable to BEOL processing. Similarly, although exemplary processing schemes may be illustrated using BEOL processing scenarios, such approaches may also be applicable to FEOL processing.

[0126] Pitch division processing and patterning schemes can be implemented to implement the embodiments described herein, or can be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch halving, pitch quartering, etc. The pitch division scheme can be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or predominantly unidirectional) with a predefined pitch. Pitch division processing is then implemented as a technique to increase line density.

[0127] In an embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a close-pitch grid structure. In one such embodiment, the close pitch cannot be achieved directly by the selected lithography. For example, a pattern based on the selected lithography can be formed first, but the pitch can be halved using spacer mask patterning, as is known in the art. Further, the initial pitch can be quartered by a second round of spacer mask patterning. Thus, the grid-like pattern described herein can have metal lines, ILD lines, or hard mask lines that are spaced at a substantially uniform pitch and have a substantially uniform width. For example, in some embodiments, the pitch variation will be within ten percent and the width variation will be within ten percent, and in some embodiments, the pitch variation will be within five percent and the width variation will be within five percent. The pattern can be manufactured by halving the pitch or quartering the pitch, or other pitch division methods. In an embodiment, the grid is not necessarily a single pitch.

[0128] In a first example, pitch halving may be implemented to double the line density of the fabricated grid structure. Figure 1A A cross-sectional view of the starting structure is shown after deposition of a hard mask material layer formed on an inter-layer dielectric (ILD) layer, but before patterning thereof. Figure 1B shows the hard mask layer after patterning by halving the pitch. Figure 1A Cross-sectional view of the structure.

[0129] refer to Figure 1A , a starting structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102. A patterned mask 106 is disposed over the hard mask material layer 104. The patterned mask 106 has spacers 108 formed on the hard mask material layer 104 along the sidewalls of the features (lines) thereof.

[0130] refer to Figure 1B , the hard mask material layer 104 is patterned in a pitch-halving manner. Specifically, the patterned mask 106 is first removed. The resulting pattern of the spacer 108 has doubled the density of the mask 106 or halved the pitch or features of the mask 106. For example, the pattern of the spacer 108 is transferred to the hard mask material layer 104 by an etching process to form a patterned hard mask 110, as shown in FIG. Figure 1B In one such embodiment, the patterned hard mask 110 is formed to have a grid pattern having unidirectional lines. The grid pattern of the patterned hard mask 110 can be a closely spaced grid pattern. For example, closely spaced spacing may not be directly achievable by the selected photolithography technique. Further, although not shown, the initial spacing can be quartered by a second round of spacer mask patterning. Thus, Figure 1BThe grid-like pattern of the patterned hard mask 110 may have hard mask lines spaced at a constant pitch relative to each other and having a constant width. The dimensions achieved may be much smaller than the critical dimension of the employed photolithography technology.

[0131] Thus, for the front-end of line (FEOL) or back-end of line (BEOL) or both, the uniformly thick film can be patterned using lithography and etching processes, which can involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It will be appreciated that other pitch division schemes can also be implemented. In any case, in an embodiment, a gridded layout can be manufactured by a selected lithographic method, such as 193nm immersion lithography (193i). Pitch division can be implemented to increase the density of lines in the gridded layout by a factor of n. The formation of a gridded layout using 193i lithography plus "n" times the pitch division can be designated as 193i+P / n pitch division. In one such embodiment, 193nm immersion scaling can be continued for many generations using cost-effective pitch division.

[0132] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to shrink. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0133] However, scaling multi-gate transistors is not without consequences. As the dimensions of these fundamental building blocks of microelectronic circuits decrease and as the absolute number of fundamental building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

[0134] According to one or more embodiments of the present disclosure, a pitch-quartering approach is implemented for patterning a semiconductor layer to form a semiconductor fin. In one or more embodiments, a fused fin pitch-quartering approach is implemented.

[0135] Figure 2A FIG. 2 is a schematic diagram of a pitch quartering method 200 for fabricating semiconductor fins according to an embodiment of the present disclosure. Figure 2B A cross-sectional view of a semiconductor fin fabricated using a pitch quartering method according to an embodiment of the present disclosure is shown.

[0136] refer to Figure 2A, in operation (a), a photoresist layer (PR) is patterned to form a photoresist feature 202. The photoresist feature 202 can be patterned using a standard photolithography process technique such as 193 immersion lithography. In operation (b), a material layer such as an insulating layer or a dielectric hard mask layer is patterned using the photoresist feature 202 to form a first backbone (BB1) feature 204. A first spacer (SP1) feature 206 is then formed adjacent to a sidewall of the first backbone feature 204. In operation (c), the first backbone feature 204 is removed to leave only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206', as shown. Figure 2A . Depending on the desired spacing and size of the BB2 features (208, described below), this thinning can be performed (as shown) before or after the removal of BB1 (feature 204). In operation (d), the first spacer features 206 or the thinned first spacer features 206' are used to pattern a material layer such as an insulating layer or a dielectric hard mask layer to form a second backbone (BB2) feature 208. A second spacer (SP2) feature 210 is then formed adjacent to the sidewalls of the second backbone feature 208. In operation (e), the second backbone feature 208 is removed to leave only the second spacer features 210. The remaining second spacer features 210 can then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins having a size that is one-quarter the spacing relative to the initially patterned photoresist features 202. As an example, reference Figure 2B , using the second spacer features 210 as a mask for patterning (eg, dry or plasma etch patterning) to form a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer. Figure 2B In the example shown, the plurality of semiconductor fins 250 all have substantially the same pitch and spacing.

[0137] It will be appreciated that the spacing between the initially patterned photoresist features can be modified to alter the structural outcome of the pitch quartering process. In this example, Figure 3A is a schematic diagram of a fused fin pitch quartering approach 300 for fabricating semiconductor fins according to an embodiment of the present disclosure. Figure 3B A cross-sectional view of a semiconductor fin fabricated using a fused fin pitch quartering approach according to an embodiment of the present disclosure is shown.

[0138] refer to Figure 3A, in operation (a), a photoresist layer (PR) is patterned to form photoresist features 302. The photoresist features 302 can be patterned using standard photolithographic processing techniques such as 193 immersion lithography, but with spacings (e.g., spacings referred to as sub-design rule spaces) that may ultimately conflict with the design rules required to produce uniformly spaced multiple patterns. In operation (b), a material layer such as an insulating layer or a dielectric hard mask layer is patterned using the photoresist features 302 to form a first backbone (BB1) feature 304. A first spacer (SP1) feature 306 is then formed adjacent to the sidewalls of the first backbone feature 304. However, in contrast to Figure 2A In contrast to the embodiment shown in FIG, some of the adjacent first spacer features 306 are fused spacer features due to the closer photoresist features 302. In operation (c), the first backbone features 304 are removed to leave only the first spacer features 306. Before or after removing the first backbone features 304, some of the first spacer features 306 may be thinned to form thinned first spacer features 306', as shown in FIG. Figure 3A In operation (d), a material layer such as an insulating layer or a dielectric hard mask layer is patterned using the first spacer feature 306 and the thinned first spacer feature 306' to form a second backbone (BB2) feature 308. A second spacer (SP2) feature 310 is then formed adjacent to the sidewalls of the second backbone feature 308. However, where the BB2 feature 308 is a fused feature, for example, Figure 3A No second spacer is formed at the center BB2 feature 308 of the photoresist. In operation (e), the second backbone feature 308 is removed to leave only the second spacer feature 310. The remaining second spacer features 310 can then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins having a size that is one-quarter the pitch relative to the initially patterned photoresist features 302.

[0139] As an example, refer to Figure 3B , a plurality of semiconductor fins 350, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 310 as a mask for patterning (eg, dry or plasma etch patterning). Figure 3B In the example of FIG. 3 , the plurality of semiconductor fins 350 have varying pitches and spacings. Such a fused fin spacer patterning approach can be implemented to substantially eliminate the presence of fins in certain locations of the pattern of the plurality of fins. Thus, fusing the first spacer features 306 in certain locations allows for the fabrication of six or four fins based on two first backbone features 304, which typically results in eight fins, such as those in the embodiment of FIG. Figure 2A and Figure 2BIn one example, the fins have a tighter spacing in the board than would normally be allowed by creating the fins at uniform spacing and then cutting away the unneeded fins, although the latter approach may still be implemented according to embodiments described herein.

[0140] In an exemplary embodiment, reference Figure 3B , an integrated circuit structure, a first plurality of semiconductor fins 352 has a longest dimension along a first direction (y, into the page). Adjacent individual semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount (S1) in a second direction (x) that is orthogonal to the first direction. A second plurality of semiconductor fins 354 has a longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart from each other by a first amount (S1) in the second direction. The nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are respectively spaced apart from each other by a second amount (S2) in the second direction x. In an embodiment, the second amount S2 is greater than the first amount S1, but less than twice the first amount S1. In another embodiment, the second amount S2 is more than twice the first amount S1.

[0141] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with the underlying single crystal silicon substrate. In one embodiment, the individual fins in the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 have sidewalls that taper outwardly from a top to a bottom of the individual fins in the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 along the second direction x. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0142] In another exemplary embodiment, referring to Figure 3A and Figure 3BA method of fabricating an integrated circuit structure includes forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). A primary spacer structure 306 is formed adjacent to sidewalls of the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). The primary spacer structure 306 is fused between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed, and first, second, third, and fourth secondary backbone structures 308 are provided. The second and third secondary backbone structures (e.g., the middle pair of secondary backbone structures 308) are fused. Secondary spacer structures 310 are formed adjacent to sidewalls of the first, second, third, and fourth secondary backbone structures 308. The first, second, third, and fourth secondary backbone structures 308 are then removed. The semiconductor material is then patterned using the secondary spacer structure 310 to form semiconductor fins 350 in the semiconductor material.

[0143] In one embodiment, the first and second primary backbone structures 304 (left BB1) are patterned with sub-design rule spacing between the first and second primary backbone structures 304 (right BB1). In one embodiment, the semiconductor material comprises silicon. In one embodiment, individual semiconductor fins in the semiconductor fins 350 have sidewalls that taper outwardly from a top to a bottom of the individual semiconductor fins in the semiconductor fins 350 along a second direction x. In one embodiment, the semiconductor fins 350 are continuous with the underlying single crystal silicon substrate. In one embodiment, patterning the semiconductor material with the secondary spacer structures 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, wherein adjacent individual semiconductor fins in the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x that is orthogonal to the first direction y. A second plurality of semiconductor fins 354 are formed having a longest dimension along the first direction y, wherein adjacent individual semiconductor fins in the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount S1 in the second direction x. The nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are respectively spaced apart from each other by a second amount S2 in the second direction x. In an embodiment, the second amount S2 is greater than the first amount S1. In one such embodiment, the second amount S2 is less than two times the first amount S1. In another such embodiment, the second amount S2 is greater than two times the first amount S1 but less than three times the first amount S1. In an embodiment, as Figure 3B As shown in , the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0144] In another aspect, it should be appreciated that fin trimming processes, where fin removal is performed as an alternative to fused fins, can trim (remove) the fins during hard mask patterning or by physically removing the fins. As an example of the latter approach, Figures 4A-4C Depicted are cross-sectional views representing various operations in a method of fabricating a plurality of semiconductor fins, in accordance with an embodiment of the present disclosure.

[0145] refer to Figure 4A , a patterned hard mask layer 402 is formed over a semiconductor layer 464 such as a bulk single crystal silicon layer. Figure 4B , and then forming fins 406 in the semiconductor layer 404 by, for example, a dry or plasma etching process. Figure 4C , for example, selected fins 406 are removed using a masking and etching process. In the illustrated example, one of the fins 406 is removed and a residual fin stump 408 may be left behind. In such a "fin trim last" approach, the hard mask 402 as a whole is patterned to provide a grid structure without removing or modifying individual features. The total number of fins is not modified until after the fins are fabricated.

[0146] In another aspect, multi-layer trench isolation regions, which may be referred to as shallow trench isolation (STI) structures, may be implemented between semiconductor fins. In an embodiment, a multi-layer STI structure is formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0147] It may be desirable to use bulk silicon for fin-based or tri-gate transistors. However, there is concern that the area below the active silicon fin portion of the device (the sub-fin) (e.g., the gate control region, or HSi) is eliminated or not gate controlled. As a result, if the source or drain region is at or below the HSi point, then there may be leakage paths through the sub-fin region. It is likely that leakage paths in the sub-fin region should be controlled for the device to operate properly.

[0148] One approach to addressing the above issues involves using a well implantation operation in which the sub-fin region is heavily doped (e.g., much greater than 2E18 / cm 3 ), which cuts off sub-fin leakage, but also results in significant doping in the fin. Adding a halo implant further increases the fin doping so that the ends of the line fins are doped at high levels (e.g., greater than about 1E18 / cm 3 ).

[0149] Another approach involves providing doping through sub-fin doping without having to deliver the same level of doping to the HSi portion of the fin. The process can involve selectively doping the sub-fin region of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer by, for example, outdiffusion of a tri-gate doped glass sub-fin. For example, selectively doping the sub-fin region of a tri-gate or FinFET transistor can mitigate sub-fin leakage while keeping the fin doping low. Incorporating solid-state dopant sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor process flow (after recessing from the fin sidewalls) delivers well doping to the sub-fins while keeping the main body of the fin relatively undoped.

[0150] Thus, the process scheme can include using a solid source doping layer (e.g., boron-doped oxide) deposited on the fin after fin etching. Later, after trench filling and polishing, the doping layer is recessed together with the trench filling material to define the fin height (HSi) for the device. This operation removes the doping layer from the fin sidewalls above HSi. As a result, the doping layer only exists along the fin sidewalls in the sub-fin area, which ensures precise control of doping placement. After the drive-in anneal, the high doping is confined to the sub-fin area and quickly transitions to low doping in the adjacent area of ​​the fin above HSi (thus forming the channel region of the transistor). Typically, borosilicate glass (BSG) is implemented for NMOS fin doping, while phosphosilicate (PSG) or arsenic silicate glass (AsSG) layers are implemented for PMOS fin doping. In one example, this P-type solid dopant source layer is a BSG layer with a boron concentration in the range of approximately 0.1-10 weight %. In another example, the N-type solid dopant source layer is a PSG layer or an AsSG layer having a phosphorus or arsenic concentration in the range of approximately 0.1-10 wt %. A silicon nitride cap layer may be included on the doped layer, and then a silicon dioxide or silicon oxide filler material may be included on the silicon nitride cap layer.

[0151] According to another embodiment of the present disclosure, for relatively thin fins (e.g., fins having a width of less than about 20 nanometers), the sub-fin leakage is sufficiently low, wherein an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filler material is included on the silicon nitride cap layer. It should be appreciated that doping of the sub-fin region, such as halo doping, can also be implemented using such a structure.

[0152] Figure 5A A cross-sectional view of a pair of semiconductor fins separated by a triple-layer trench isolation structure according to an embodiment of the present disclosure is shown.

[0153] refer to Figure 5AThe integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (H Si ). First insulating layer 504 is directly on the sidewalls of lower fin portion 502A of fin 502. Second insulating layer 506 is directly on first insulating layer 504, which is directly on the sidewalls of lower fin portion 502A of fin 502. Dielectric filler material 508 is directly and laterally adjacent to second insulating layer 506 directly on first insulating layer 504, which is directly on the sidewalls of lower fin portion 502A of fin 502.

[0154] In an embodiment, first insulating layer 504 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, first insulating layer 504 comprises silicon and oxygen and no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, first insulating layer 504 has a thickness in the range of 0.5-2 nanometers.

[0155] In an embodiment, the second insulating layer 506 includes silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 506 has a thickness in the range of 2-5 nanometers.

[0156] In an embodiment, dielectric fill material 508 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, a gate electrode is ultimately formed on top of and laterally adjacent to the sidewalls of upper fin portion 502B of fin 502 .

[0157] It should be appreciated that during processing, the upper fin portion of the semiconductor fin may be corroded or consumed. Furthermore, the trench isolation structures between the fins may also be corroded to have a non-planar topography, or may be formed to have a non-planar topography during fabrication. As an example, Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another triple-layer trench isolation structure according to another embodiment of the present disclosure is shown.

[0158] refer to Figure 5BThe integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 in the region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, has a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 in the region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. First insulating layer 574 has a first end 574A that is substantially coplanar with shoulder feature 554 of first fin 552, and first insulating layer 574 also has a second end 574B that is substantially coplanar with shoulder feature 564 of second fin 562. Second insulating layer 576 is directly on first insulating layer 574, which is directly on the sidewalls of lower fin portion 552A of first fin 552 and directly on the sidewalls of lower fin portion 562A of second fin 562.

[0159] The dielectric fill material 578 is laterally adjacent to the second insulating layer 576 directly on the first insulating layer 574, which is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. In an embodiment, the dielectric fill material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric fill material 578 is below at least one of the shoulder features 554 of the first fin 552 and below at least one of the shoulder features 564 of the second fin 562, as shown. Figure 5B shown.

[0160] In an embodiment, the first insulating layer 574 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, the first insulating layer 574 comprises silicon and oxygen, and is free of other atomic species at an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 574 has a thickness in the range of 0.5-2 nanometers.

[0161] In an embodiment, the second insulating layer 576 includes silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 576 has a thickness in the range of 2-5 nanometers.

[0162] In one embodiment, dielectric fill material 578 includes silicon and oxygen, such as an insulating layer of silicon oxide or silicon dioxide. In one embodiment, a gate electrode is ultimately formed on top of and laterally adjacent to the sidewalls of upper fin portion 552B of first fin 552, and on top of and laterally adjacent to the sidewalls of upper fin portion 562B of second fin 562. The gate electrode also forms on dielectric fill material 578 between first fin 552 and second fin 562.

[0163] Figures 6A-6D Cross-sectional views illustrating various operations in fabricating a triple-layer trench isolation structure according to an embodiment of the present disclosure are shown.

[0164] refer to Figure 6A , a method of manufacturing an integrated circuit structure includes forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on the fin 602 and conforms to the fin 602, such as Figure 6B In an embodiment, the first insulating layer 604 includes silicon and oxygen, and no other atomic species at an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0165] refer to Figure 6C , the second insulating layer 606 is formed directly on the first insulating layer 604 and conforms to the first insulating layer 604. In an embodiment, the second insulating layer 606 includes silicon and nitrogen. The dielectric filler material 608 is formed directly on the second insulating layer 606, such as Figure 6D shown.

[0166] In an embodiment, the method further involves recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 to provide a dielectric fill material 608 with an exposed upper fin portion 602A (eg, Figure 5A and Figure 5B The resulting structure can be as shown in FIG. Figure 5A or Figure 5B In one embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching process or a dry etching process.

[0167] In one embodiment, first insulating layer 604 is formed using a chemical vapor deposition process. In one embodiment, second insulating layer 606 is formed using a chemical vapor deposition process. In one embodiment, dielectric fill material 608 is formed using a spin-on process. In one such embodiment, dielectric fill material 608 is a spin-on material and is exposed to a steam treatment, for example, before or after a recess etch process, to provide a cured material comprising silicon and oxygen. In one embodiment, a gate electrode is ultimately formed on top of and laterally adjacent to the sidewalls of the upper fin portion of fin 602.

[0168] In another aspect, the gate sidewall spacer material may remain over certain trench isolation regions to protect the trench isolation regions from corrosion during subsequent processing operations. Figures 7A-7E Angled three-dimensional cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present disclosure.

[0169] refer to Figure 7A , a method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to a sidewall of the lower fin portion 702A of the fin 702. A gate structure 706 is formed over the upper fin portion 702B and over the insulating structure 704. In an embodiment, the gate structure is a placeholder or dummy gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed to be conformal to the upper fin portion 702B of the fin 702, to the gate structure 706, and to the insulating structure 704.

[0170] refer to Figure 7B , a hard mask material 710 is formed over the dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0171] refer to Figure 7C , the hard mask material 710 is recessed to form a recessed hard mask material 712 and expose a portion of the dielectric material 708 that conforms to the upper fin portion 702B of the fin 702 and to the gate structure 706. The recessed hard mask material 712 covers the portion of the dielectric material 708 that conforms to the insulating structure 704. In one embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0172] refer to Figure 7D, the dielectric material 708 is anisotropically etched to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as a dielectric spacer 714A), along portions of the sidewalls of the upper fin portion 702B of the fin 702, and over the insulating structure 704.

[0173] refer to Figure 7E ,from Figure 7D The recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In an embodiment, further processing includes forming an embedded source or drain structure on an opposite side of the gate structure 706, as described in more detail below.

[0174] Reference again Figure 7E In an embodiment, an integrated circuit structure 700 includes a first fin (left 702), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure also includes a second fin (right 702), such as a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is directly adjacent to a sidewall of the lower fin portion 702A of the first fin and directly adjacent to a sidewall of the lower fin portion 702A of the second fin. A gate electrode 706 is above the upper fin portion 702B of the first fin (left 702), above the upper fin portion 702B of the second fin (right 702), and above the first portion 704A of the insulating structure 704. A first dielectric spacer 714A is along the sidewalls of the upper fin portion 702B of the first fin (left 702), and a second dielectric spacer 702C is along the sidewalls of the upper fin portion 702B of the second fin (right 702). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B over a second portion 704B of the insulating structure 704 between the first fin (left 702) and the second fin (right 702).

[0175] In an embodiment, the first and second dielectric spacers 714B and 714C include silicon and nitrogen, such as a stoichiometric Si 3 N 4 silicon nitride material, a silicon-rich silicon nitride material, or a silicon-poor silicon nitride material.

[0176] In an embodiment, the integrated circuit structure 700 further includes an embedded source or drain structure on opposite sides of the gate electrode 706, the embedded source or drain structure having a bottom surface below the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, and the source or drain structure having a top surface above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, as described below in conjunction with Figure 9B In an embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filling material directly on the second insulating layer laterally, as described below in conjunction with Figure 9B As stated.

[0177] Figures 8A-8F The flowchart of various operations in the method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0178] refer to Figure 8A The method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion ( Figure 8A 702B. The insulating structure 704 is formed directly adjacent to the sidewalls of the lower fin portion 702A of the fin 702. A pair of gate structures 706 are formed above the upper fin portion 702B and above the insulating structure 704. It should be appreciated that Figures 8A-8F The perspective view shown in FIG is slightly projected to show portions of the gate structure 706 and the insulating structure in front of (outside of) the upper fin portion 702B, where the upper fin portion extends slightly into the page. In an embodiment, the gate structure 706 is a placeholder or dummy gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0179] refer to Figure 8B , which corresponds to the combination Figure 7A The process operations depicted, dielectric material 708 is formed to conform to upper fin portion 702B of fin 702 , to conform to gate structure 706 , and to conform to exposed portions of insulating structure 704 .

[0180] refer to Figure 8C , which corresponds to the combination Figure 7B 1. The process operation depicted, hard mask material 710 is formed over dielectric material 708. In an embodiment, hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0181] refer to Figure 8D , which corresponds to the combination Figure 7C The process described recesses the hard mask material 710 to form a recessed hard mask material 712 and exposes a portion of the dielectric material 708 that conforms to the upper fin portion 702B of the fin 702 and to the gate structure 706. The recessed hard mask material 712 covers the portion of the dielectric material 708 that conforms to the insulating structure 704. In one embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0182] refer to Figure 8E , which corresponds to the combination Figure 7D The process operates to anisotropically etch the dielectric material 708 to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as portion 714A), along portions of the sidewalls of the upper fin portion 702B of the fin 702 , and over the insulating structure 704 .

[0183] refer to Figure 8F , which corresponds to the combination Figure 7E The process operation described, from Figure 8E The recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and the processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In an embodiment, further processing includes forming an embedded source or drain structure on an opposite side of the gate structure 706, as described in more detail below.

[0184] Reference again Figure 8F In an embodiment, the integrated circuit structure 700 includes a fin 702, such as a silicon fin, having a lower fin portion ( Figure 8F 706) and the upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewalls of the lower fin portion of the fin 702. The first gate electrode (left 706) is above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. The second gate electrode (right 706) is above the upper fin portion 702B and above the second portion 704A' of the insulating structure 704. A first dielectric spacer (right 714A of left 706) is along the sidewalls of the first gate electrode (left 706), and a second dielectric spacer (left 714A of right 706) is along the sidewalls of the second gate electrode (right 706), the second dielectric spacer being continuous with the first dielectric spacer over a third portion 704A" of the insulating structure 704 between the first gate electrode (left 706) and the second gate electrode (right 706).

[0185] Figure 9A An embodiment of the present disclosure is shown for an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis. Figure 9B The invention shows an integrated circuit structure including an epitaxial source or drain region and a multi-layer trench isolation structure according to an embodiment of the present invention. Figure 7E Cross-sectional view taken along the b-b' axis.

[0186] refer to Figure 9A and Figure 9B In an embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on opposite sides of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below a top surface 990 of the first and second dielectric spacers 714B and 714C along sidewalls of the upper fin portions 702B of the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above a top surface of the first and second dielectric spacers 714B and 714C along sidewalls of the upper fin portions 702B of the first and second fins 702.

[0187] In an embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926 such as Figure 9A In one embodiment where the permanent gate structure 920 is above the insulating structure 704, the permanent gate structure 920 is formed on a residual polysilicon portion 930, which may be a remnant of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0188] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric filler material 906 directly on the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric filler material 906 includes silicon and oxygen.

[0189] In another aspect, epitaxial embedded source or drain regions are implemented as source or drain structures for semiconductor fins. As an example, Figure 10 A cross-sectional view of an integrated circuit structure cut at a source or drain position according to an embodiment of the present disclosure is shown.

[0190] refer to Figure 10The integrated circuit structure 1000 includes a P-type device, such as a P-type metal oxide semiconductor (PMOS) device, and an N-type device, such as an N-type metal oxide semiconductor (PMOS) device.

[0191] Figure 10 The PMOS device includes a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain locations, the upper portion of the fins 1002 has been removed, and the same or different semiconductor material is grown to form a source or drain structure 1004. It should be appreciated that the source or drain structure 1004 will appear identical in a cross-sectional view taken on either side of the gate electrode; for example, it will appear substantially identical on the source side as on the drain side. In an embodiment, as described, the source or drain structure 1004 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as shown, the source or drain structure 1004 has strong faceting. In an embodiment, a conductive contact 1008 is formed over the source or drain structure 1004. However, in one such embodiment, the strong faceting and relatively wide growth of the source or drain structure 1004 inhibits good coverage of the conductive contact 1008, at least to some extent.

[0192] Figure 10 The NMOS device includes a second plurality of semiconductor fins 1052, such as silicon fins formed from the bulk silicon substrate 1001. At the source or drain location, the upper portion of the fin 1052 has been removed and the same or different semiconductor material has been grown to form a source or drain structure 1054. It should be appreciated that the source or drain structure 1054 will appear the same in a cross-sectional view taken on either side of the gate electrode, for example, they will appear substantially the same on the source side as on the drain side. In an embodiment, as described above, the source or drain structure 1054 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as shown, the source or drain structure 1054 has a weaker facet relative to the source or drain structure 1004. In an embodiment, a conductive contact 1058 is formed above the source or drain structure 1054. In one such embodiment, having weaker faceting and the resulting narrower growth of the source or drain structure 1054 (compared to the source or drain structure 1004 ) enhances good coverage of the conductive contact 1058 .

[0193] The shape of the source or drain structure of the PMOS device can be changed to improve the contact area with the overlying contact portion. For example, Figure 11 A cross-sectional view of another integrated circuit structure cut at a source or drain position according to an embodiment of the present disclosure is shown.

[0194] refer to Figure 11 , the integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is on a first side of a first gate electrode (which may be formed above an upper fin portion such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 at a second side of such first gate electrode opposite the first side. In an embodiment, the first epitaxial source or drain structure 1104 and the second epitaxial source or drain structure include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick profile, such as Figure 11 The first conductive electrode 1108 is on the first epitaxial source or drain structure 1104 .

[0195] Reference again Figure 11 In one embodiment, the integrated circuit structure 1100 further includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is on a first side of a second gate electrode (which may be formed above an upper fin portion, such as a channel portion of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 at a second side of the second gate electrode, opposite the first side. In one embodiment, the third epitaxial source or drain structure 1154 and the fourth epitaxial source or drain structure include silicon and have a profile substantially the same as the profile 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is above the third epitaxial source or drain structure 1154.

[0196] In an embodiment, the first epitaxial source or drain structure 1104 has weaker faceting. In an embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers.

[0197] In an embodiment, the first epitaxial source or drain structure 1104 has a germanium concentration gradient from approximately 20% at a bottom 1104A of the first epitaxial source or drain structure 1104 to approximately 45% germanium at a top 1104B of the first epitaxial source or drain structure 1104. In an embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

[0198] Figures 12A-12D Cross-sectional views taken at a source or drain location and representing various operations in fabricating an integrated circuit structure are shown in accordance with an embodiment of the present disclosure.

[0199] refer to Figure 12A , a method of manufacturing an integrated circuit structure includes forming a fin, such as a silicon fin formed from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In an embodiment, although not shown, a gate electrode is formed over a portion of the upper fin portion 1202B of the fin 1202 at a location into the page. Such a gate electrode has a first side opposite a second side and defines a source or drain location on the first and second sides. For example, for illustrative purposes, Figures 12A-12D The cross-sectional position of the view is taken at one of the source or drain positions at one of the sides of the gate electrode.

[0200] refer to Figure 12B , the source or drain location of the fin 1202 is recessed to form a recessed fin portion 1206. The recessed source or drain location of the fin 1202 can be on one side of the gate electrode and on a second side of the gate electrode. Figure 12A and Figure 12B In both embodiments, the dielectric spacer 1204 is formed along a sidewall of a portion of the fin 1202 , such as on one side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below a top surface 1204A of the dielectric spacer 1204 .

[0201] refer to Figure 12C , an epitaxial source or drain structure 1208 is formed on the recessed fin 1206, for example, so that it can be formed on one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 that is on a second side of such gate electrode. In an embodiment, the epitaxial source or drain structure 1208 includes silicon and germanium and has a matchstick profile, such as Figure 12CIn an embodiment, the dielectric spacer 1204 is included along a lower portion 1208A of a sidewall of the epitaxial source or drain structure 1208, as shown.

[0202] refer to Figure 12D , a conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive fill material 1201B. In one embodiment, the conductive electrode 1210 follows the contour of the epitaxial source or drain structure 1208, as shown. In other embodiments, the upper portion of the epitaxial source or drain structure 1208 is etched during the fabrication of the conductive electrode 1210.

[0203] In another aspect, fin trim isolation (FTI) and single gate spacing for isolated fins are described. Non-planar transistors utilizing fins of semiconductor material protruding from the surface of the substrate employ a gate electrode that wraps around two, three, or even all sides of the fin (i.e., dual-gate, triple-gate, nanowire transistors). Typically, source and drain regions are then formed in the fin on either side of the gate electrode, or formed as a regrown portion of the fin. In order to isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or space can be formed between two adjacent fins. Such an isolation gap typically requires some kind of masking etch. Once isolated, the gate stack is then typically patterned over the individual fins using some kind of masking etch (e.g., line etching or opening etching, depending on the specific embodiment).

[0204] A potential issue with the fin isolation technology described above is that the gate is not self-aligned to the end of the fin, and the alignment of the gate stack pattern with the semiconductor fin pattern relies on the overlap of the two patterns. As a result, lithographic overlay tolerances are added to the sizing of the semiconductor fin and the isolation gap, where the fin requires a greater length and the isolation gap is larger than the isolation gap for a given level of transistor functionality. Therefore, device architectures and manufacturing techniques that reduce this oversizing offer highly beneficial improvements in transistor density.

[0205] Another potential issue with the fin isolation technology described above is that the stress in the semiconductor fin required to improve carrier mobility can be lost from the channel region of the transistor, where excessive fin surface is left unconstrained during fabrication, allowing fin strain to relax. Therefore, device architectures and fabrication techniques that maintain higher levels of desired fin stress offer advantageous improvements in non-planar transistor performance.

[0206] According to embodiments of the present disclosure, through-gate fin isolation architectures and techniques are described herein. In the illustrated exemplary embodiments, non-planar transistors in a microelectronic device such as an integrated circuit (IC) are isolated from each other in a manner that is self-aligned to the gate electrodes of the transistors. Although embodiments of the present disclosure are applicable to virtually any IC employing non-planar transistors, exemplary ICs include, but are not limited to, microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0207] In an embodiment, two ends of adjacent semiconductor fins are electrically isolated from each other using an isolation region, with only one patterned mask level being used to position the isolation region relative to the gate electrode. In an embodiment, a single mask is used to form multiple sacrificial placeholder strips of fixed spacing, a first subset of the placeholder strips defining the position or size of the isolation region, and a second subset of the placeholder strips defining the position or size of the gate electrode. In certain embodiments, the first subset of the placeholder strips is removed, and isolation cuts are made into the semiconductor fin in the openings obtained by removing the first subset, while the second subset of the placeholder strips is ultimately replaced with a non-sacrificial gate electrode stack. Because the subset of placeholders used for gate electrode replacement is used to form the isolation region, the method and resulting architecture are referred to herein as "through-gate" isolation. For example, one or more through-gate isolation embodiments described herein can achieve higher transistor density and higher levels of favorable transistor channel stress.

[0208] With the isolation defined after the gate electrode is placed or defined, greater transistor density can be achieved because the fin isolation size setting and placement can be performed perfectly with the gate electrode on the field so that the gate electrode and the isolation region are integer multiples of the minimum feature spacing of a single masking level. In other embodiments where the semiconductor fin has a lattice mismatch with the substrate on which the fin is disposed, a greater degree of strain is maintained by defining the isolation after the gate electrode is placed or defined. For such embodiments, other features of the transistor formed before defining the ends of the fin (e.g., the gate electrode and added source or drain material) help to mechanically maintain the fin strain after the isolation cut is made into the fin.

[0209] To provide further context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are separated from their adjacent cells by two or more dummy gates, with the dummy gates having buried fins. The cells are isolated by etching fins underneath the two or more dummy gates, which connect one cell to another. Scaling could be significantly beneficial if the number of dummy gates separating adjacent cells could be reduced from two or more to one. As described above, one approach requires two or more dummy gates. The fins under the two or more dummy gates are etched during fin patterning. A potential problem with this approach is that the dummy gates consume space on the chip that could be used for cells. In an embodiment, the approach described herein makes it possible to separate adjacent cells using only a single dummy gate.

[0210] In an embodiment, the fin trim isolation approach is implemented as a self-aligned patterning scheme. Here, the fin beneath a single gate is etched away. Adjacent cells can then be separated by a single dummy gate. Advantages of this approach can include saving space on the chip and allowing for greater computing power per given area. This approach can also allow fin trimming to be performed at sub-fin pitch distances.

[0211] Figure 13A and Figure 13B illustratively, plan views representing various operations in a method of patterning fins with multiple gate spacers to form local isolation structures, in accordance with an embodiment of the present disclosure.

[0212] refer to Figure 13A , a plurality of fins 1302 are shown having a length along a first direction 1304. A grid 1306 is shown along a second direction 1308 orthogonal to the first direction 1304, with spaces 1307 between the grids, defining locations for ultimately forming a plurality of gate lines.

[0213] refer to Figure 13B A portion of the plurality of fins 1302 is cut (e.g., removed by an etching process) to leave a fin 1310 having a cutout 1312 therein. Consequently, the isolation structure ultimately formed in the cutout 1312 has dimensions exceeding those of a single gate line, for example, the dimensions of three gate lines 1306. Consequently, the gate structure ultimately formed along the location of the gate lines 1306 will be formed at least partially over the isolation structure formed in the cutout 1312. Thus, the cutout 1312 is a relatively wide fin cutout.

[0214] Figures 14A-14D illustratively, plan views representing various operations in a method of patterning a fin having a single gate spacer to form a local isolation structure, in accordance with another embodiment of the present disclosure.

[0215] refer to Figure 14A The method of fabricating an integrated circuit structure includes forming a plurality of fins 1402, wherein individual fins in the plurality of fins 1402 have a longest dimension along a first direction 1404. A plurality of gate structures 1406 are formed over the plurality of fins 1402, wherein individual gate structures in the gate structures 1406 have a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In one embodiment, the gate structures 1406 are sacrificial or dummy gate lines, for example, fabricated from polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0216] refer to Figure 14B , a dielectric material structure 1410 is formed between adjacent gate structures in the plurality of gate structures 1406 .

[0217] refer to Figure 14C , removing portion 1412 of one of the plurality of gate structures 1406 to expose portion 1414 of each of the plurality of fins 1402. In an embodiment, removing portion 1412 of one of the plurality of gate structures 1406 involves using a lithographic window 1416 that is wider than width 1418 of portion 1412 of one of the plurality of gate structures 1406.

[0218] refer to Figure 14D , removing the exposed portion 1414 of each of the plurality of fins 1402 to form the kerf region 1420. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed using a dry or plasma etching process. In an embodiment, removing the exposed portion 1414 of each of the plurality of fins 1402 involves etching to a depth that is less than the height of the plurality of fins 1402. In one such embodiment, the depth is greater than the depth of the source or drain region in the plurality of fins 1402. In an embodiment, the depth is deeper than the depth of the active portion of the plurality of fins 1402 to provide an isolation margin. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially without etching the source or drain region (e.g., epitaxial source or drain region) of the plurality of fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without laterally etching, or substantially laterally etching, source or drain regions (eg, epitaxial source or drain regions) of the plurality of fins 1402 .

[0219] In an embodiment, the cutout region 1420 is ultimately filled with an insulating layer, for example, in the location of the removed portion 1414 of each of the plurality of fins 1402. An exemplary insulating layer or "multi-cutout" or "plug" structure is described below. However, in other embodiments, the cutout region 1420 is only partially filled with an insulating layer, and then a conductive structure is formed therein. The conductive structure can be used as a local interconnect. In an embodiment, before the cutout region 1420 is filled with an insulating layer or with an insulating layer that accommodates a local interconnect structure, dopants can be implanted or delivered from a solid source dopant layer through the cutout region 1420 into the locally cutout portions of one or more fins.

[0220] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multiple gate spacers for local isolation according to an embodiment of the present disclosure is shown.

[0221] refer to Figure 15 , the silicon fin 1502 has a first fin portion 1504 laterally adjacent to a second fin portion 1506. The first fin portion 1504 is separated from the second fin portion 1506 by a wider cutout 1508, such as in combination with Figure 13A and Figure 13B As shown, the wider cutout 1508 has a width X. A dielectric fill material 1510 is formed in the wider cutout 1508 and electrically isolates the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are formed over the silicon fin 1502, wherein each of the gate lines may include a gate dielectric and gate electrode stack 1514, a dielectric cap layer 1516, and sidewall spacers 1518. Two gate lines (the two gate lines 1512 on the left) occupy the wider cutout 1508, effectively separating the first fin portion 1504 from the second fin portion 1506 by two dummy gates or passive gates.

[0222] In contrast, the fin sections can be separated by a single gate distance. As an example, Figure 16A A cross-sectional view of an integrated circuit structure having a fin with a single gate spacer for local isolation according to another embodiment of the present disclosure is shown.

[0223] refer to Figure 16A , the silicon fin 1602 has a first fin portion 1604 laterally adjacent to a second fin portion 1606. The first fin portion 1604 is separated from the second fin portion 1606 by a narrow cut 1608, for example, Figures 14A-14D As shown, the narrower cutout 1608 has a width Y, where Y is less than Figure 15X. Dielectric fill material 1610 is formed in the narrower cut 1608 and electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are above the silicon fin 1602, wherein each of the gate lines may include a gate dielectric and gate electrode stack 1614, a dielectric cap layer 1616, and sidewall spacers 1618. The dielectric fill material 1610 takes the position where the single gate line was previously located, so that the first fin portion 1604 is separated from the second fin portion 1606 by a single "plugged" gate line. In one embodiment, residual spacer material 1620 remains on the sidewalls at the location of the removed gate line portion, as shown. It should be recognized that other areas of the fin 1602 can be isolated from each other by two or more inactive gate lines (region 1622 with three inactive gate lines) manufactured by an earlier, wider fin cut process, as described below.

[0224] Reference again Figure 16A Integrated circuit structure 1600 includes a fin 1602, such as a silicon fin. Fin 1602 has a longest dimension along a first direction 1650. Isolation structure 1610 separates a first upper portion 1604 of fin 1602 from a second upper portion 1606 of fin 1602 along first direction 1650. Isolation structure 1610 has a center 1611 along first direction 1650.

[0225] A first gate structure 1612A is over the first upper portion 1604 of the fin 1602, with the first gate structure 1612A having a longest dimension along a second direction 1652 (e.g., into the page) that is orthogonal to the first direction 1650. A center 1613A of the first gate structure 1612A is spaced apart from a center 1611 of the isolation structure 1610 along the first direction 1650. A second gate structure 1612B is over the first upper portion 1604 of the fin, with the second gate structure 1612B having a longest dimension along the second direction 1652. A center 1613B of the second gate structure 1612B is spaced apart from a center 1613A of the first gate structure 1612A along the first direction 1650. A third gate structure 1612C is over the second upper portion 1606 of the fin 1602, with the third gate structure 1612C having a longest dimension along the second direction 1652. A center 1613C of the third gate structure 1612C is spaced apart from a center 1611 of the isolation structure 1610 along the first direction 1650. In an embodiment, the isolation structure 1610 has a top that is substantially coplanar with a top of the first gate structure 1612A, a top of the second gate structure 1612B, and a top of the third gate structure 1612C, as shown.

[0226] In an embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between sidewalls of a high-k gate dielectric layer 1662, as shown for the exemplary third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewalls of the high-k gate dielectric layer 1662.

[0227] In one embodiment, integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of fin 1602, between first gate structure 1612A and isolation structure 1610. A second epitaxial semiconductor region 1664B is on the first upper portion 1604 of fin 1602, between first gate structure 1612A and second gate structure 1612B. A third epitaxial semiconductor region 1664C is on the second upper portion 1606 of fin 1602, between third gate structure 1612C and isolation structure 1610. In one embodiment, first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon and germanium. In another embodiment, first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon.

[0228] In one embodiment, isolation structure 1610 induces stress on first upper portion 1604 of fin 1602 and second upper portion 1606 of fin 1602. In one embodiment, the stress is compressive. In another embodiment, the stress is tensile. In other embodiments, isolation structure 1610 is partially filled with an insulating layer, and then a conductive structure is formed therein. The conductive structure can be used as a local interconnect. In one embodiment, dopants are implanted or delivered from a solid source dopant layer into the locally cutout portion of one or more fins before forming isolation structure 1610 using an insulating layer or an insulating layer that accommodates a local interconnect structure.

[0229] In another aspect, it is recognized that instead of having an active gate electrode at a localized location of the fin cut or at a wider location of the fin cut, an isolation structure, such as the isolation structure 1610 described above, can be formed. Furthermore, the depth of such localized or wider locations of the fin cut can be formed to vary relative to one another within the fin. In a first example, Figure 16B A cross-sectional view showing where a fin isolation structure may be formed to replace a gate electrode according to an embodiment of the present disclosure is shown.

[0230] refer to Figure 16B, a fin 1680, such as a silicon fin, is formed over a substrate 1682 and may be continuous with the substrate 1682. The fin 1680 has a fin end or wide fin cutout 1684, which may be formed, for example, during fin patterning in a fin trim finish approach such as described above. The fin 1680 also has a partial cutout 1686, where portions of the fin 1680 have been removed, for example, using a fin trim isolation approach in which a dummy gate is replaced with a dielectric plug, as described above. An active gate electrode 1688 is formed over the fin and, for purposes of illustration, is shown slightly in front of the fin 1680 with the fin 1680 in the background, with the dashed lines representing the area covered in the front view. A dielectric plug 1690 may be formed at the fin end or wide fin cutout 1684, in lieu of using an active gate at such a location. Additionally, or alternatively, a dielectric plug 1692 may be formed at the localized notch 1686 to replace the use of an active gate at such a location. It should be appreciated that an epitaxial source or drain region 1694 is also shown at the location of the fin 1680 between the active gate electrode 1688 and the plug 1690 or 1692. Furthermore, in an embodiment, the surface roughness of the end of the fin at the localized notch 1686 is rougher than that of the end of the fin at the wider notch location, as shown in FIG. Figure 16B shown.

[0231] Figures 17A-17C Various depth possibilities for fin cuts made using fin trim isolation according to embodiments of the present disclosure are shown.

[0232] refer to Figure 17A , a semiconductor fin 1700, such as a silicon fin, is formed above and may be continuous with an underlying substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B, as defined by the height of the insulating structure 1704 relative to the fin 1700. A local fin isolation cut 1706A separates the fin 1700 into a first fin portion 1710 and a second fin portion 1712. Figure 17A In the example shown along the aa′ axis, the depth of the local fin isolation cut 1706A is the full depth of the fin 1700 to the substrate 1702 .

[0233] refer to Figure 17B In the second example, as shown along the aa′ axis, the depth of the local fin isolation cut 1706B is deeper than the entire depth of the fin 1700 to the substrate 1702 . That is, the cut 1706B extends into the underlying substrate 1702 .

[0234] refer to Figure 17CIn the third example, as shown along the aa' axis, the depth of the local fin isolation cut 1706C is less than the entire depth of the fin 1700, but deeper than the upper surface of the isolation structure 1704. Figure 17C In the fourth example, as shown along the aa′ axis, the depth of the partial fin isolation cut 1706D is less than the entire depth of the fin 1700 and is at a level that is substantially coplanar with the upper surface of the isolation structure 1704 .

[0235] Figure 18 A plan view and corresponding cross-sectional view taken along the aa' axis showing possible options for depth of localized locations of a fin cutout within a fin as compared to the depth of wider locations according to an embodiment of the present disclosure are shown.

[0236] refer to Figure 18 , first and second semiconductor fins 1800 and 1802, such as silicon fins, have upper fin portions 1800B and 1802B extending above an insulating structure 1804. Both fins 1800 and 1802 have a fin end or wide fin cut 1806, such as the cut 1806 that may be formed during fin patterning, such as in the fin trim last approach described above. Both fins 1800 and 1802 also have a local cut 1808, where a portion of the fin 1800 or 1802 is removed, such as using a fin trim isolation approach in which a dummy gate is replaced with a dielectric plug, as described above. In an embodiment, the surface roughness of the ends of the fins 1800 and 1802 at the local cut 1808 is rougher than the end of the fin at the location of 1806, such as Figure 18 shown.

[0237] refer to Figure 18 , the lower fin portions 1800A and 1802A can be seen below the level of the insulating structure 1804. Also seen in the cross-sectional view is the remnant 1810 of the fin that was removed at the last fin trimming process prior to forming the insulating structure 1804, as described above. Although shown as protruding above the substrate, the remnant 1810 can also be at the level of the substrate or into the substrate, as shown by the additional exemplary wide cut depth 1820. It should be recognized that the wide cut 1806 of the fins 1800 and 1802 can also be at the level described for the cut depth 1820, an example of which is shown. The local cut 1808 can have the same depth as described for Figures 17A-17C The described depths correspond to exemplary depths, as shown.

[0238] Common Reference Figure 16A 、 Figure 16B 、 Figures 17A-17C and Figure 18According to an embodiment of the present disclosure, an integrated circuit structure includes a fin, the fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. The gate structure includes a gate electrode located above a top of a region of the first portion of the fin and laterally adjacent to a sidewall of the region. The gate structure has a width along the first direction, and a center of the gate structure is spaced apart from a center of the first isolation structure by a spacing along the first direction. A second isolation structure is above a second end of the first portion of the fin, the second end being opposite to the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness that is less than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced apart from the center of the gate structure by a spacing along the first direction.

[0239] In one embodiment, the first end of the first portion of the fin has a fan-shaped morphology, such as Figure 16B In one embodiment, the first epitaxial semiconductor region is on a first portion of the fin between the gate structure and the first isolation structure. The second epitaxial semiconductor region is on a first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, and the width along the second direction is wider than the width of the first portion of the fin below the gate structure along the second direction, for example, as combined Figure 11 and Figure 12D The epitaxial features shown, for example, in Figure 11 and Figure 12D The perspective view is shown having a width greater than the portion of the fin where the epitaxial feature is grown. In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along sidewalls of the gate electrode.

[0240] Common Reference Figure 16A 、 Figure 16B 、 Figures 17A-17C and Figure 18According to another embodiment of the present disclosure, an integrated circuit structure includes a fin, the fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the direction. The first end of the first portion of the fin has a depth. The gate structure includes a gate electrode that is above the top of a region of the first portion of the fin and laterally adjacent to the sidewalls of the region. A second isolation structure is above a second end of the first portion of the fin, the second end being opposite the first end. The second end of the first portion of the fin has a depth that is different from the depth of the first end of the first portion of the fin.

[0241] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a spacing along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by the spacing along the direction.

[0242] Common Reference Figure 16A 、 Figure 16B 、 Figures 17A-17C and Figure 18 According to another embodiment of the present disclosure, an integrated circuit structure includes a first fin comprising silicon, the first fin having a top and sidewalls, wherein the top has a longest dimension along a direction, and a discontinuity separates a first end of a first portion of the first fin from a first end of a second portion of the fin along the direction. The first portion of the first fin has a second end opposite the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure also includes a second fin comprising silicon, the second fin having a top and sidewalls, wherein the top has a longest dimension along the direction. The integrated circuit structure also includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, wherein the top has a longest dimension along the direction, and the top is not coplanar with the depth of the first end of the first portion of the fin.

[0243] In one embodiment, the first end of the first portion of the fin has a depth that is lower than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the depth of the first end of the first portion of the fin. In one embodiment, the first end of the first portion of the fin has a depth that is higher than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the top of the remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the top of the remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth greater than the top of the residual fin portion.

[0244] In another aspect, the dielectric plug formed in the location of the localized fin cutout or wide fin cutout can be tuned to provide a specific stress to the fin or fin portion. In such an embodiment, the dielectric plug can be referred to as a fin end stressor.

[0245] One or more embodiments relate to the manufacture of fin-based semiconductor devices. Performance improvements to such devices can be made by inducing channel stress from a multi-plug fill process. Embodiments may include inducing mechanical stress in a metal oxide semiconductor field effect transistor (MOSFET) channel using material properties in a multi-plug fill process. As a result, the induced stress can improve the mobility and drive current of the transistor. In addition, the plug filling method described herein can allow for the elimination of any seam or pore formation during deposition.

[0246] To provide context, manipulating the unique material properties of the plug fill adjacent to the fin can induce stress within the channel. According to one or more embodiments, by adjusting the composition, deposition, and post-processing conditions of the plug fill material, the stress in the channel is modulated to benefit both NMOS and PMOS transistors. In addition, such a plug can be deeper in the fin substrate than other common stressor technologies such as epitaxial source or drain. The nature of the plug fill that achieves this effect also eliminates seams or voids during deposition and mitigates certain defect modes during processing.

[0247] To provide more context, currently, there is no artificial stress engineering for gate (multi) plugs. Stress enhancement from traditional stressors such as epitaxial source or drain, dummy multi-gate removal, stress liners, etc. unfortunately tends to decrease as device pitch decreases. To address one or more of the above issues, according to one or more embodiments of the present disclosure, additional stressors are incorporated into the transistor structure. Another possible benefit of this process may be the elimination of seams or pores within the plug, which are common with other chemical vapor deposition methods.

[0248] Figure 19A and Figure 19B Illustrations of cross-sectional views of various operations in a method of selecting a fin end stressor location at the end of a fin having a wide kerf, for example, as part of the fin trimming final process described above, in accordance with an embodiment of the present disclosure.

[0249] refer to Figure 19A , a fin 1900, such as a silicon fin, is formed over and may be continuous with a substrate 1902. The fin 1900 has a fin end or wide fin cutout 1904, which may be formed during fin patterning, such as in the final fin trimming method described above. An active gate electrode location 1908 and a dummy gate electrode location 1908 are formed over the fin 1900 and, for purposes of illustration, are shown slightly in front of the fin 1900, with the fin 1900 in the background, with the dotted lines representing the covered areas in the front view. It should be appreciated that an epitaxial source or drain region 1910 is also shown at the location of the fin 1900 between the gate locations 1906 and 1908. In addition, an interlayer dielectric material 1912 is included at the location of the fin 1900 between the gate locations 1906 and 1908.

[0250] refer to Figure 19B , the gate placeholder structure or dummy gate location 1908 is removed to expose the fin tip and wide fin cutout 1904. This removal creates an opening 1920 where a dielectric plug, such as a fin tip stressor dielectric plug, may ultimately be formed.

[0251] Figure 20A and Figure 20B Cross-sectional views are depicted of various operations in a method of selecting a fin end stress location at a fin end having a partial notch, as part of a fin trim isolation process, such as described above, in accordance with an embodiment of the present disclosure.

[0252] refer to Figure 20A, a fin 2000, such as a silicon fin, is formed above and may be continuous with a substrate 2002. The fin 2000 has a localized cutout 2004 where portions of the fin 2000 are removed, for example, using a fin trim isolation method in which a dummy gate is removed and the fin is etched in a localized location, as described above. An active gate electrode location 2006 and a dummy gate electrode location 2008 are formed above the fin 2000 and, for purposes of illustration, are shown slightly in front of the fin 2000 with the fin 2000 in the background, with the dotted lines representing the covered areas in the front view. It should be appreciated that an epitaxial source or drain region 2010 is also shown at the location of the fin 2000 between the gate locations 2006 and 2008. In addition, an interlayer dielectric material 2012 is included at the location of the fin 2000 between the gate locations 2006 and 2008.

[0253] refer to Figure 20B , the gate placeholder structure or dummy gate electrode location 2008 is removed to expose the fin tip with a partial notch 2004. This removal creates an opening 2020 where a dielectric plug, such as a fin tip stressor dielectric plug, may ultimately be formed.

[0254] Figures 21A-21M Cross-sectional views are illustrated of various operations in a method of fabricating an integrated circuit structure with differentiated fin end dielectric plugs, in accordance with an embodiment of the present disclosure.

[0255] refer to Figure 21A , the starting structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the starting structure 2100 includes a first fin 2102, such as a first silicon fin, which is formed above the substrate 2104 and can be continuous with the substrate 2104. The first fin 2102 has a fin end 2106, which can be formed by a local or wide fin cut. The first active gate electrode location 2108 and the first dummy gate electrode location 2110 are formed above the first fin 2102 and, for illustrative purposes, are shown slightly in front of the first fin 2102, with the first fin 2102 in the background, where the dotted line represents the area covered in the front view. An epitaxial N-type source or drain region 2112, such as an epitaxial silicon source or drain structure, is also shown at the location of the first fin 2102 between the gate locations 2108 and 2110. Additionally, an interlayer dielectric material 2114 is included at the location of the first fin 2102 between gate locations 2108 and 2110 .

[0256] The PMOS region of the starting structure 2100 includes a second fin 2122, such as a second silicon fin, formed above and may be continuous with the substrate 2104. The second fin 2122 has a fin end 2126, which may be formed by a partial or wide fin cut. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed above the second fin 2122 and, for illustrative purposes, are shown slightly in front of the second fin 2122, with the second fin 2122 in the background, with the dotted line representing the area covered in the front view. An epitaxial P-type source or drain region 2132, such as an epitaxial silicon germanium source or drain structure, is also shown at the location of the second fin 2122 between the gate locations 2128 and 2130. In addition, an interlayer dielectric material 2134 is included at the location of the second fin 2122 between the gate locations 2128 and 2130.

[0257] refer to Figure 21B , the first and second dummy gate electrodes at locations 2110 and 2130, respectively, are removed. During the removal, the fin end 2106 of the first fin 2102 and the fin end 2126 of the second fin 2122 are exposed. This removal also creates openings 2116 and 2136, respectively, where dielectric plugs, such as fin end stressor dielectric plugs, may ultimately be formed.

[0258] refer to Figure 21C , material lining 2140 with Figure 21B In an embodiment, the material liner layer includes silicon and nitrogen, such as a silicon nitride material liner layer.

[0259] refer to Figure 21D , a protective cap layer 2142 such as a metal nitride layer is formed on Figure 21C structure.

[0260] refer to Figure 21E , a hard mask material 2144 such as a carbon-based hard mask material is formed on Figure 21D A photolithographic mask or mask stack 2146 is formed over the hard mask material 2144 .

[0261] refer to Figure 21F ,from Figure 21E The structure of FIG. 21 removes portions of the hard mask material 2144 in the PMOS region and portions of the protective cap layer 2142. The photolithography mask or mask stack 2146 is also removed.

[0262] refer to Figure 21G , the second material lining 2148 and Figure 21FIn one embodiment, the second material liner layer includes silicon and nitrogen, such as a second silicon nitride material liner layer. In one embodiment, the second material liner layer 2148 has different stress states to adjust the stress in the exposed plug.

[0263] refer to Figure 21H A second hard mask material 2150, such as a second carbon-based hard mask material, is formed on Figure 21G 21. The MOSFET is formed over the structure and then recessed into the opening 2136 in the PMOS region of the structure.

[0264] refer to Figure 21I ,from Figure 21H The second material liner 2148 is etched away from the structure to remove the second material liner 2148 from the NMOS region and to recess the second material liner 2148 in the PMOS region of the structure.

[0265] refer to Figure 21J ,from Figure 21I The structure of FIG. 21 removes hard mask material 2144, protective cap layer 2142, and second hard mask material 2150. This removal leaves two different fill structures for opening 2116 compared to opening 2136, respectively.

[0266] refer to Figure 21K , the insulating filling material 2152 is formed in Figure 21J Insulating fill material 2152 is formed in openings 2116 and 2136 of the structure and is planarized. In an embodiment, insulating fill material 2152 is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

[0267] refer to Figure 21L , the insulating filling material 2152 is recessed into Figure 21K 2136 of the structure to form a recessed insulating fill material 2154. In one embodiment, a steam oxidation process is performed as part of the recessing process, or after the recessing process, to cure the recessed insulating fill material 2154. In one such embodiment, the recessed insulating fill material 2154 shrinks, thereby inducing tensile stress on the fins 2102 and 2122. However, there is less tensile stress-inducing material in the PMOS region than in the NMOS region.

[0268] refer to Figure 21M , the third material lining 2156 is Figure 21L In one embodiment, the third material liner 2156 includes silicon and nitrogen, such as a third silicon nitride material liner. In one embodiment, the third material liner 2156 prevents the recessed insulating filling material 2154 from being etched away during subsequent source or drain contact etching.

[0269] Figures 22A-22D A cross-sectional view illustrating an exemplary structure of a PMOS fin end stressor dielectric plug according to an embodiment of the present disclosure is shown.

[0270] refer to Figure 22A , an opening 2136 over the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to a lower portion of material liner 2140 but is recessed relative to an upper portion of material liner 2140. A recessed insulating fill material 2154 is within second material liner 2148 and has an upper surface coplanar with an upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and is on both the upper surface of insulating fill material 2154 and the upper surface of second material liner 2148. Third material liner 2156 has a seam 2157, for example, as an artifact of the deposition process used to form third material liner 2156.

[0271] refer to Figure 22B , an opening 2136 in the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to the lower portion of material liner 2140 but is recessed relative to the upper portion of material liner 2140. A recessed insulating filler material 2154 is within second material liner 2148 and has an upper surface coplanar with the upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and is on the upper surface of insulating filler material 2154 and the upper surface of second material liner 2148. Third material liner 2156 has no seam.

[0272] refer to Figure 22C , an opening 2136 over the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to the lower portion of material liner 2140 but is recessed relative to the upper portion of material liner 2140. A recessed insulating fill material 2154 is within and above second material liner 2148 and has an upper surface above the upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and on the upper surface of insulating fill material 2154. Third material liner 2156 is shown as having no seam, but in other embodiments, third material liner 2156 has a seam.

[0273] refer to Figure 22D, an opening 2136 over the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but is recessed relative to the upper portion of the material liner 2140. A recessed insulating fill material 2154 is within the second material liner 2148 and has an upper surface that is recessed below the upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140 and is on the upper surface of the insulating fill material 2154 and the upper surface of the second material liner 2148. The third material liner 2156 is shown as having no seam, but in other embodiments, the third material liner 2156 has a seam.

[0274] Common Reference Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figures 21A-21M as well as Figures 22A-22D According to an embodiment of the present disclosure, an integrated circuit structure includes a fin, such as silicon, having a top and sidewalls. The top has a longest dimension along a direction. A first isolation structure is above the first end of the fin. The gate structure includes a gate electrode that is above the top of a region of the fin and laterally adjacent to the sidewall of the region. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is above the second end of the fin, the second end being opposite to the first end. The second isolation structure is spaced apart from the gate structure along the direction. Both the first isolation structure and the second isolation structure include a first dielectric material (e.g., a material liner 2140) that laterally surrounds a recessed second dielectric material (e.g., a second material liner 2148) that is different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., a recessed insulating fill material 2154) that is different from the first and second dielectric materials.

[0275] In one embodiment, both the first and second isolation structures further include a fourth dielectric material (e.g., third material liner 2156) laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on an upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a substantially vertical central seam. In another such embodiment, the fourth dielectric material has no seam.

[0276] In one embodiment, the third dielectric material has an upper surface that is coplanar with an upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is below an upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is above an upper surface of the second dielectric material, and the third dielectric material is further above an upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0277] In one embodiment, the first isolation structure has a width along the direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In one such embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a spacing along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by the spacing along the direction. In one embodiment, both the first and second isolation structures are in corresponding trenches in the interlayer dielectric layer.

[0278] In one such embodiment, the first source or drain region is between the gate structure and the first isolation structure. The second source or drain region is between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further comprises a high-k dielectric layer between the gate electrode and the fin and along the sidewalls of the gate electrode.

[0279] In another aspect, the depth of individual dielectric plugs can vary within a semiconductor structure or within an architecture formed on a common substrate. As an example, Figure 23A FIG2 shows a cross-sectional view of another semiconductor structure having a fin end stress-inducing feature according to another embodiment of the present disclosure. Figure 23A , including a shallow dielectric plug 2308A and a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as shown, shallow dielectric plug 2308C is at a depth approximately equal to the depth of semiconductor fin 2302 within substrate 2304, while deep dielectric plug pair 2308B and 2308C is at a depth less than the depth of semiconductor fin 2302 within substrate 2304.

[0280] Reference again Figure 23ASuch an arrangement can achieve stress amplification on fin trim isolation (FTI) devices in trenches etched deeper into the substrate 2304 to provide isolation between adjacent fins 2302. This approach can be implemented to increase the density of transistors on a chip. In an embodiment, the stress effects induced on the transistor from the plug fill are amplified in the FTI transistor because the stress transfer occurs both in the fin and in the substrate or just below the transistor.

[0281] In another aspect, the width or amount of the tensile stress-inducing oxide layer included in the dielectric plug can vary within the semiconductor structure or within an architecture formed on a common substrate, for example, depending on whether the device is a PMOS device or an NMOS device. As an example, Figure 23B FIG2 shows a cross-sectional view of another semiconductor structure having a fin end stress-inducing feature according to another embodiment of the present disclosure. Figure 23B In certain embodiments, an NMOS device includes relatively more tensile stress inducing oxide layer 2350 than a corresponding PMOS device.

[0282] Reference again Figure 23B In an embodiment, differentiated plug filling is implemented to induce appropriate stress in NMOS and PMOS. For example, NMOS plugs 2308D and 2308E have a tensile stress-inducing oxide layer 2350 with a larger volume and a larger width than PMOS plugs 2308F and 2308G. The plug filling can be patterned to induce different stresses in NMOS and PMOS devices. For example, a PMOS device can be opened using photolithographic patterning (e.g., widening the dielectric plug trench for the PMOS device), at which time different filling options can be performed to differentiate the plug filling in the NMOS device relative to the plug filling in the PMOS device. In an exemplary embodiment, reducing the volume of the flowable oxide in the plug on the PMOS device can reduce the induced tensile stress. In one such embodiment, the compressive stress may be primarily from, for example, compressively stressed source and drain regions. In other embodiments, the use of different plug liners or different filling materials provides adjustable stress control.

[0283] As described above, it is recognized that the multi-plug stress effect can benefit both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to an embodiment of the present disclosure, the semiconductor fin is a uniaxially stressed semiconductor fin. The uniaxially stressed semiconductor fin can be stressed in a uniaxial direction using tensile stress or using compressive stress. For example, according to one or more embodiments of the present disclosure, Figure 24A shows an oblique view of the fin with tensile uniaxial stress, while Figure 24B An oblique view of the fin with compressive uniaxial stress is shown.

[0284] refer to Figure 24A , semiconductor fin 2400 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in semiconductor fin 2400 on either side of the channel region (C). The discrete channel regions of semiconductor fin 2400 have a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing away from each other and toward ends 2402 and 2404).

[0285] refer to Figure 24B , semiconductor fin 2450 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in semiconductor fin 2450 on either side of the channel region (C). The discrete channel regions of semiconductor fin 2450 have a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (arrows pointing toward each other and from ends 2452 and 2454). Therefore, the embodiments described herein can be implemented to improve transistor mobility and drive current, thereby allowing faster execution of circuits and chips.

[0286] In another aspect, there may be a relationship between the locations where gate line cuts (multi-cuts) are made and the locations where fin trim isolation (FTI) local fin cuts are made. In an embodiment, FTI local cuts are made only in the locations where the multi-cuts are made. However, in one such embodiment, FTI cuts are not necessarily made at every location where the multi-cuts are made.

[0287] Figure 25A and Figure 25B An illustration of a plan view representing various operations in a method of patterning a fin with a single gate spacer to form a local isolation structure in a select gate line cut location is shown, in accordance with an embodiment of the present disclosure.

[0288] refer to Figure 25A The method of fabricating an integrated circuit structure includes forming a plurality of fins 2502, wherein individual fins in the plurality of fins 2502 have a longest dimension along a first direction 2504. A plurality of gate structures 2506 are formed over the plurality of fins 2502, wherein individual fins in the gate structures 2506 have a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In one embodiment, the gate structures 2506 are sacrificial or dummy gate lines, for example, fabricated from polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0289] Reference again Figure 25AA dielectric material structure 2510 is formed between adjacent gate structures in the plurality of gate structures 2506. Portions 2512 and 2513 of two gate structures in the plurality of gate structures 2506 are removed to expose portions of each of the plurality of fins 2502. In an embodiment, removing portions 2512 and 2513 of two gate structures in the plurality of gate structures 2506 involves using a lithography window that is wider than the width of each of portions 2512 and 2513 of gate structures 2506. The exposed portion of each of the plurality of fins 2502 at location 2512 is removed to form a kerf region 2520. In an embodiment, the exposed portion of each of the plurality of fins 2502 is removed using a dry or plasma etch process. However, the exposed portion of each of the plurality of fins 2502 at location 2513 is masked from removal. In an embodiment, region 2512 / 2520 represents both a multi-kerf and an FTI local fin kerf. However, location 2513 represents only a multi-kerf.

[0290] refer to Figure 25B The multi-cut and FTI local fin cut locations 2512 / 2520 and multi-cut location 2513 are filled with an insulating structure such as a dielectric plug 2530. Exemplary insulating structures or "multi-cut" or "plug" structures are described below.

[0291] Figures 26A-26C The embodiment according to the present disclosure is shown Figure 25B Cross-sectional views of various possibilities for dielectric plugs with multi-cut and FTI local fin cut locations and multi-cut only locations for various regions of the structure.

[0292] refer to Figure 26A ,along Figure 25B The aa′ axis of the structure of FIG shows a cross-sectional view of a portion 2600A of the dielectric plug 2530 at location 2513 . The portion 2600A of the dielectric plug 2530 is shown on the uncut fin 2502 and between the dielectric material structures 2510 .

[0293] refer to Figure 26B ,along Figure 25B The bb' axis of the structure of FIG shows a cross-sectional view of a portion 2600B of the dielectric plug 2530 at a location 2512. The portion 2600B of the dielectric plug 2530 is shown over the cut-fin location 2520 and between the dielectric material structures 2510.

[0294] refer to Figure 26C ,along Figure 25B2 shows a cross-sectional view of a portion 2600C of the dielectric plug 2530 at position 2512 along the c-c' axis of the structure. The portion 2600C of the dielectric plug 2530 is shown on the trench isolation structure 2602 between the fins 2502 and between the dielectric material structure 2510. In the embodiment, examples of which are described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating fill material 2602C on the second insulating layer 2602B.

[0295] Common Reference Figure 25A 、 Figure 25B and Figures 26A-26C According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit structure includes forming a plurality of fins, individual fins of the plurality of fins being along a first direction. A plurality of gate structures are formed on the plurality of fins, individual gate structures of the gate structures being along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent gate structures of the plurality of gate structures. A portion of a first gate structure of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins. A portion of a second gate structure of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed in the location of the removed first portion of the plurality of fins. A second insulating structure is formed in the location of the removed portion of the second of the plurality of gate structures.

[0296] In one embodiment, removing portions of the first and second gate structures in the plurality of gate structures involves using a lithographic window that is wider than a width of each of the portions of the first and second gate structures in the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth that is less than a height of the plurality of fins. In one such embodiment, the depth is greater than a depth of a source or drain region in the plurality of fins. In one embodiment, the plurality of fins comprises silicon fins and is continuous with a portion of an underlying silicon substrate.

[0297] Common Reference Figure 16A 、 Figure 25A 、 Figure 25B and Figures 26A-26CAccording to another embodiment of the present disclosure, an integrated circuit structure includes a fin, the fin including silicon, the fin having a longest dimension along a first direction. An isolation structure is above an upper portion of the fin, the isolation structure having a center along the first direction. A first gate structure is above an upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a spacing along the first direction. A second gate structure is above an upper portion of the fin, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by the spacing along the first direction. A third gate structure is above an upper portion of the fin on a side of the isolation structure opposite to the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by the spacing along the first direction.

[0298] In one embodiment, each of the first, second, and third gate structures includes a gate electrode on and between sidewalls of the high-k gate dielectric layer. In one such embodiment, each of the first, second, and third gate structures further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0299] In one embodiment, the first epitaxial semiconductor region is located on an upper portion of the fin between the first gate structure and the isolation structure. The second epitaxial semiconductor region is located on an upper portion of the fin between the first gate structure and the second gate structure. The third epitaxial semiconductor region is located on an upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0300] Common Reference Figure 16A 、 Figure 25A 、 Figure 25B and Figures 26A-26CAccording to another embodiment of the present disclosure, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is on the STI structure, and the isolation structure has a center along the first direction. A first gate structure is on the STI structure, and the first gate structure has a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a spacing along the first direction. A second gate structure is on the STI structure, and the second gate structure has a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by the spacing along the first direction. A third gate structure is on the STI structure, on a side of the isolation structure opposite to the first and second gate structures, and the third gate structure has a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by the spacing along the first direction.

[0301] In one embodiment, each of the first, second, and third gate structures includes a gate electrode on and between sidewalls of the high-k gate dielectric layer. In one such embodiment, each of the first, second, and third gate structures further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, the semiconductor fin pair is a silicon fin pair.

[0302] In another aspect, whether with multiple cuts and FTI local fin cuts or with just multiple cuts, the insulating structure or dielectric plug used to fill the cut locations can extend laterally into or even beyond the dielectric spacer of the corresponding cut gate line.

[0303] In the first example where the trench contact shape is not affected by the multi-cut dielectric plug, Figure 27A A plan view and corresponding cross-sectional views of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer of the gate line according to an embodiment of the present disclosure are shown.

[0304] refer to Figure 27AIntegrated circuit structure 2700A includes a first silicon fin 2702 having its longest dimension along a first direction 2703. A second silicon fin 2704 has its longest dimension along the first direction 2703. An insulator material 2706 is disposed between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is disposed above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, which is orthogonal to the first direction 2703. Gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. Gate line 2708 has a discontinuity 2710 above the insulator material 2706 and between the first end 2708C and the second end 2708D of gate line 2708. Discontinuity 2710 is filled with a dielectric plug 2712.

[0305] A trench contact 2714 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709 at a first side 2708A of the gate line 2708. The trench contact 2714 is continuous over the insulator material 2706 at a location 2715 laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is laterally interposed between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712 that is thinner than a width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0306] In one embodiment, a second trench contact 2718 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709 at a second side 2708B of the gate line 2708. The second trench contact 2718 is continuous over the insulator material 2706 at a location 2719 laterally adjacent to the dielectric plug 2712. In one such embodiment, a second dielectric spacer 2720 is laterally interposed between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712 that is thinner than a width laterally adjacent to the second side 2708B of the gate line 2708.

[0307] In one embodiment, gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, dielectric plug 2712 includes the same material as dielectric spacer 2714, but is separate from dielectric spacer 2714. In one embodiment, dielectric plug 2712 includes a different material than dielectric spacer 2714.

[0308] In a second example where the trench contact shape is influenced by a multi-cut dielectric plug, Figure 27B A plan view and corresponding cross-sectional views are shown of an integrated circuit structure having a gate line cutout with a dielectric plug extending beyond the gate line's dielectric spacer according to another embodiment of the present disclosure.

[0309] refer to Figure 27B Integrated circuit structure 2700B includes a first silicon fin 2752 having its longest dimension along a first direction 2753. A second silicon fin 2754 has its longest dimension along the first direction 2753. An insulator material 2756 is disposed between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is disposed above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759, which is orthogonal to the first direction 2753. Gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. Gate line 2758 has a discontinuity 2760 above the insulator material 2756 and between the first end 2758C and the second end 2758D of gate line 2758. Discontinuity 2760 is filled with a dielectric plug 2762.

[0310] A trench contact 2764 is located above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759 at a first side 2758A of the gate line 2758. The trench contact 2764 is continuous over the insulator material 2756 at a location 2765 laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is laterally interposed between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 extends along the first side 2758A of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762 that is thinner than a width (W2) laterally adjacent to the dielectric spacer 2766.

[0311] In one embodiment, a second trench contact 2768 is disposed over the first silicon fin 2752 and over the second silicon fin 2754 along a second direction 2759 at a second side 2758B of the gate line 2758. The second trench contact 2768 is continuous over the insulator material 2756 at a location 2769 laterally adjacent to the dielectric plug 2762. In one such embodiment, a second dielectric spacer 2770 is laterally interposed between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 extends along the second side 2758B of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. The second trench contact 2768 has a thinner width laterally adjacent to the dielectric plug 2762 than the second dielectric spacer 2770 laterally adjacent to the dielectric plug 2762.

[0312] In one embodiment, gate line 2758 includes a high-k dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, dielectric plug 2762 includes the same material as dielectric spacer 2764 but is separate from dielectric spacer 2764. In one embodiment, dielectric plug 2762 includes a different material than dielectric spacer 2764.

[0313] In a third example where the dielectric plug for a multi-cut location tapers from the top of the plug to the bottom of the plug, Figures 28A-28F Cross-sectional views are shown of various operations in a method of fabricating an integrated circuit structure having a gate line cutout with a dielectric plug having an upper portion extending out of a dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line in accordance with another embodiment of the present disclosure.

[0314] refer to Figure 28A , a plurality of gate lines 2802 are formed over a structure 2804, such as over trench isolation structures between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, for example, having a dummy gate electrode 2806 and a dielectric cap 2808. Portions of such sacrificial or dummy gate lines can be replaced later in a replacement gate process, for example, after the dielectric plug is formed as described below. Dielectric spacers 2810 are formed along the sidewalls of the gate lines 2802. A dielectric material 2812, such as a dielectric interlayer, is between the gate lines 2802. A mask 2814 is formed and photolithographically patterned to expose a portion of one of the gate lines 2802.

[0315] refer to Figure 28B, with mask 2814 in place, an etching process is used to remove center gate line 2802. Mask 2814 is then removed. In an embodiment, the etching process erodes the portion of dielectric spacer 2810 of gate line 2802 that was removed, thereby forming a reduced dielectric spacer 2816. Additionally, upper portions of dielectric material 2812 exposed by mask 2814 are eroded during the etching process, thereby forming eroded dielectric material portions 2818. In certain embodiments, residual dummy gate material 2820, such as residual polysilicon, remains in the structure as an artifact of the incomplete etching process.

[0316] refer to Figure 28C , the hard mask 2822 is formed on Figure 28B The hard mask 2822 can be Figure 28B The upper portion of the structure is conformal, particularly conformal to the etched dielectric material portion 2818.

[0317] refer to Figure 28D The remaining dummy gate material 2820 is removed, for example, using an etching process that can be chemically similar to the etching process used to remove the center gate line in the gate lines 2802. In an embodiment, the hard mask 2822 protects the etched dielectric material portion 2818 from further etching during the removal of the remaining dummy gate material 2820.

[0318] refer to Figure 28E , removing hard mask 2822. In one embodiment, hard mask 2822 is removed without or substantially without further etching of etched dielectric material portion 2818.

[0319] refer to Figure 28F , the dielectric plug 2830 is formed in Figure 28E The upper portion of the dielectric plug 2830 is above the etched dielectric material portion 2818, for example, effectively extending beyond the initial spacer 2810. The lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, effectively entering but not extending beyond the initial spacer 2810. As a result, the dielectric plug 2830 has a tapered profile, such as Figure 28F It should be appreciated that dielectric plug 2830 may be fabricated from the materials and processes described above for other multi-notch or FTI plugs or fin end stressors.

[0320] In another aspect, a portion of the placeholder gate structure or dummy gate structure may remain above the trench isolation region below the permanent gate structure to serve as a protective structure to prevent the trench isolation region from being corroded during the replacement gate process. Figures 29A-29CA plan view and corresponding cross-sectional views are shown of an integrated circuit structure having residual dummy gate material at a portion of a bottom portion of a permanent gate stack according to an embodiment of the present disclosure.

[0321] refer to Figures 29A-29C The integrated circuit structure includes a fin 2902, such as a silicon fin, protruding from a semiconductor substrate 2904. Fin 2902 has a lower fin portion 2902B and an upper fin portion 2902A. Upper fin portion 2902A has a top portion 2902C and sidewalls 2902D. An isolation structure 2906 surrounds lower fin portion 2902B. Isolation structure 2906 includes an insulating material 2906C having a top surface 2907. Semiconductor material 2908 is disposed on a portion of top surface 2907 of insulating material 2906C. Semiconductor material 2908 is separated from fin 2902.

[0322] A gate dielectric layer 2910 is over a top portion 2902C of the upper fin portion 2902A and laterally adjacent to sidewalls 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further over the semiconductor material 2908 over a portion of a top surface 2907 of the insulating material 2906C. An intervening additional gate dielectric layer 2911, such as an oxidized portion of the fin 2902, may be between the gate dielectric layer 2910 over the top portion 2902C of the upper fin portion 2902A and laterally adjacent to sidewalls 2902D of the upper fin portion 2902A. A gate electrode 2912 is over the gate dielectric layer 2910 over the top portion 2902C of the upper fin portion 2902A and laterally adjacent to sidewalls 2902D of the upper fin portion 2902A. Gate electrode 2912 is further over gate dielectric layer 2910 on semiconductor material 2908 on a portion of top surface 2907 of insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of gate electrode 2912, and a second source or drain region 2918 is adjacent to a second side of gate electrode 2912, the second side being opposite the first side. In the embodiment, examples of which are described above, isolation structure 2906 includes first insulating layer 2906A, second insulating layer 2906B, and insulating material 2906C.

[0323] In one embodiment, semiconductor material 2908 on a portion of top surface 2907 of insulating material 2906C is or includes polysilicon. In one embodiment, top surface 2907 of insulating material 2906C has a concave depression, and as shown, semiconductor material 2908 is within the concave depression. In one embodiment, isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A / 2906B) along the bottom and sidewalls of insulating material 2906C. In one such embodiment, a portion of the second insulating material (2906A or 2906B or both 2906A / 2906B) along the sidewalls of insulating material 2906C has a top surface that is above the uppermost surface of insulating material 2906, as shown. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A / 2906B) is higher than or coplanar with the uppermost surface of semiconductor material 2908.

[0324] In one embodiment, the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view perspective, the location of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along a first side of the gate electrode 2912. The second dielectric spacer 2922 is along a second side of the gate electrode 2912. In one such embodiment, the gate dielectric layer 2910 also extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as shown in FIG. Figure 29B shown.

[0325] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 also includes a conductive fill metal layer 2912B over the work function layer 2912A. In one such embodiment, the conductive fill metal layer 2912B includes tungsten. In a specific embodiment, the conductive fill metal layer 2912B includes 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, an insulating cap 2924 is on the gate electrode 2912 and may extend over the gate dielectric layer 2910, as shown in FIG. Figure 29B shown.

[0326] Figures 30A-30D 1 illustrates cross-sectional views of various operations in a method of fabricating an integrated circuit structure having residual dummy gate material at a portion of a bottom portion of a permanent gate stack in accordance with another embodiment of the present disclosure. Figure 29C The a-a' axis portion of the structure.

[0327] refer to Figure 30A The method of fabricating an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. Fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. Upper fin portion 3000B has a top portion 3000C and sidewalls 3000D. An isolation structure 3004 surrounds lower fin portion 3000A. Isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A placeholder gate electrode 3006 is above top portion 3000C of upper fin portion 3000B and laterally adjacent to sidewalls 3000D of upper fin portion 3000B. Placeholder gate electrode 3006 comprises a semiconductor material.

[0328] Although from Figure 30A The angles are not shown (but Figure 29C ), a first source or drain region may be formed adjacent to a first side of the placeholder gate electrode 3006, and a second source or drain region may be formed adjacent to a second side of the placeholder gate electrode 3006, the second side being opposite the first side. Furthermore, gate dielectric spacers may be formed along sidewalls of the placeholder gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the placeholder gate electrode 3006.

[0329] In one embodiment, placeholder gate electrode 3006 is or includes polysilicon. In one embodiment, top surface 3005 of insulating material 3004C of isolation structure 3004 has a concave depression, as shown. A portion of placeholder gate electrode 3006 is within the concave depression. In one embodiment, isolation structure 3004 includes a second insulating material (3004A or 3004B or both 3004A / 3004B) along the bottom and sidewalls of insulating material 3004C, as shown. In one such embodiment, portions of the second insulating material (3004A or 3004B or both 3004A / 3004B) along the sidewalls of insulating material 3004C have a top surface above at least a portion of top surface 3005 of insulating material 3004C. In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A / 3004B) is above the lowest surface of a portion of placeholder gate electrode 3006.

[0330] refer to Figure 30B , for example, along Figure 30AThe placeholder gate electrode 3006 is etched from the top 3000C and sidewalls 3000D of the upper fin portion 3000B in a direction 3008. The etching process may be referred to as a replacement gate process. In an embodiment, the etching or replacement gate process is not completed and leaves a portion 3012 of the placeholder gate electrode 3006 on at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0331] refer to Figure 30A and Figure 30B In one embodiment, the oxidized portion 3010 of the upper fin portion 3000B formed before forming the placeholder gate electrode 3006 is retained during the etching process, as shown. However, in another embodiment, a placeholder gate dielectric layer is formed before forming the placeholder gate electrode 3006 and is removed after etching the placeholder gate electrode.

[0332] refer to Figure 30C , a gate dielectric layer 3014 is formed over a top portion 3000C of the upper fin portion 3000B and laterally adjacent to sidewalls 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed over the oxidized portion 3010 of the upper fin portion 3000B over the top portion 3000C of the upper fin portion 3000B and laterally adjacent to sidewalls 3000D of the upper fin portion 3000B, as shown. In another embodiment, where the oxidized portion 3010 of the upper fin portion 3000B is removed after etching the placeholder gate electrode, the gate dielectric layer 3014 is formed directly over the upper fin portion 3000B, over the top portion 3000C of the upper fin portion 3000B, and laterally adjacent to sidewalls 3000D of the upper fin portion 3000B. In either case, in an embodiment, a gate dielectric layer 3014 is further formed on the portion 3012 of the placeholder gate electrode 3006 on the portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004 .

[0333] refer to Figure 30D A permanent gate electrode 3016 is formed over the gate dielectric layer 3014 over a top portion 3000C of the upper fin portion 3000B and laterally adjacent to a sidewall 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further formed over the gate dielectric layer 3014 over a portion 3012 of the placeholder gate electrode 3006 over a portion of the top surface 3005 of the insulating material 3004C.

[0334] In one embodiment, forming the permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A includes titanium and nitrogen. In another such embodiment, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 also includes forming a conductive fill metal layer 3016B formed over the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, an insulating gate cap layer 3018 is formed over the permanent gate electrode 3016.

[0335] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer for a gate electrode in a gate dielectric structure. In other embodiments, a partially or fully crystalline high-k layer for a gate electrode is included in the gate dielectric structure. In one embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0336] In embodiments, this document describes ways to increase the charge in the device channel and improve subthreshold behavior by employing ferroelectric or antiferroelectric gate oxides. Ferroelectric and antiferroelectric gate oxides can increase the channel charge to achieve higher currents and also enable steeper turn-on behavior.

[0337] To provide context, ferroelectric and antiferroelectric (FE or AFE) materials based on hafnium or zirconium (Hf or Zr) are typically much thinner than ferroelectric materials such as lead zirconium titanate (PZT), making them compatible with highly scaled logic technologies. FE or AFE materials have two characteristics that improve the performance of logic transistors: (1) higher charge in the channel due to FE or AFE polarization, and (2) steeper turn-on behavior due to sharp FE or AFE transitions. These properties improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0338] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is shown.

[0339] refer to Figure 31A, integrated circuit structure 3100 includes a gate structure 3102 above a substrate 3104. In one embodiment, gate structure 3102 is above or on a semiconductor channel structure 3106 comprising a single crystalline material, such as single crystal silicon. Gate structure 3102 includes a gate dielectric above semiconductor channel structure 3106 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode includes a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Conductive layer 3102B includes a metal and can be a barrier layer, a work function layer, or a template layer that enhances the crystallinity of the FE or AFE layer. One or more gate fill layers 3102C are on or above conductive layer 3102B. Source region 3108 and drain region 3110 are on opposite sides of gate structure 3102. A source or drain contact 3112 is electrically connected to the source region 3108 and the drain region 3110 at location 3149 and is separated from the gate structure 3102 by an interlayer dielectric layer 3114 or a gate dielectric spacer 3116. Figure 31A In the example of FIG, source region 3108 and drain region 3110 are regions of substrate 3104. In an embodiment, source or drain contact 3112 includes barrier layer 3112A and conductive trench fill material 3112B. In an embodiment, ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along dielectric spacer 3116, as shown in FIG. Figure 31A shown.

[0340] In an embodiment, and as applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, having a Zr:Hr ratio of 50:50 or more Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0341] In an embodiment, and as applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, having a Zr:Hr ratio of 80:20 or having more Zr, even up to 100% Zr, ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0342] In an embodiment, and as applicable throughout this disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-K dielectric (HfOx, Al2O3, etc.), or a combination of oxide and high-K, between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In an embodiment, and as applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nm to 8 nm. In an embodiment, and as applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size approximately in the range of 20 nm or greater.

[0343] In one embodiment, after depositing the ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example, by atomic layer deposition (ALD), a layer comprising a metal (e.g., layer 3102B, such as 5-10 nanometers of titanium nitride, tantalum nitride, or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. An anneal is then performed. In one embodiment, the anneal is performed for a time period in the range of 1 millisecond to 30 minutes. In one embodiment, the anneal is performed at a temperature in the range of 500-1100 degrees Celsius.

[0344] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is shown.

[0345] refer to Figure 31B, integrated circuit structure 3150 includes a gate structure 3152 over a substrate 3154. In one embodiment, gate structure 3152 is over or above a semiconductor channel structure 3156 comprising a single crystalline material, such as single crystal silicon. Gate structure 3152 includes a gate dielectric over the semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may also include an amorphous oxide layer 3153. The gate electrode includes a conductive layer 3152B over the ferroelectric or antiferroelectric polycrystalline material layer 3152A. Conductive layer 3152B includes a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are over or above conductive layer 3152B. Raised source region 3158 and raised drain region 3160 (e.g., regions of a different semiconductor material than the semiconductor channel structure 3156) are on opposite sides of gate structure 3152. The source or drain contact 3162 is electrically connected to the source region 3158 and the drain region 3160 at location 3199 and is separated from the gate structure 3152 by one or both of the interlayer dielectric layer 3164 and the gate dielectric spacer 3166. In one embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166, as shown in FIG. Figure 31B shown.

[0346] Figure 32A A plan view of a plurality of gate lines over a semiconductor fin pair according to another embodiment of the present disclosure is shown.

[0347] refer to Figure 32A , a plurality of active gate lines 3204 are formed over the plurality of semiconductor fins 3200. Dummy gate lines 3206 are at the ends of the plurality of semiconductor fins 3200. The spaces 3208 between the gate lines 3204 / 3206 are locations where trench contacts can be positioned to provide conductive contacts to source or drain regions (e.g., source or drain regions 3251, 3252, 3253, and 3254). In an embodiment, the pattern of the plurality of gate lines 3204 / 3206 or the pattern of the plurality of semiconductor fins 3200 is described as a grid structure. In one embodiment, the grid-like pattern includes a plurality of gate lines 3204 / 3206 spaced apart at a constant pitch and having a constant width, or a pattern of the plurality of semiconductor fins 3200, or both.

[0348] Figure 32B The embodiment according to the present disclosure is shown Figure 32A Cross-sectional view taken along the a-a' axis.

[0349] refer to Figure 32BA plurality of active gate lines 3264 are formed on semiconductor fins 3262 formed above substrate 3260. Dummy gate lines 3266 are located at the ends of semiconductor fins 3262. Dielectric layer 3270 is located outside of dummy gate lines 3266. Trench contact material 3297 is located between active gate lines 3264 and between dummy gate lines 3266 and active gate lines 3264. Embedded source or drain structures 3268 are located in semiconductor fins 3262, between active gate lines 3264 and between dummy gate lines 3266 and active gate lines 3264.

[0350] Active gate line 3264 includes a gate dielectric structure 3272, a work function gate electrode portion 3274, a fill gate electrode portion 3276, and a dielectric cap layer 3278. Dielectric spacers 3280 are arranged along the sidewalls of active gate line 3264 and dummy gate line 3266. In one embodiment, gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, gate dielectric structure 3272 also includes an amorphous oxide layer 3299.

[0351] In another aspect, devices of the same conductivity type (e.g., N-type or P-type) can have differentiated gate electrode stacks for the same conductivity type. However, for comparison purposes, devices of the same conductivity type can have differentiated voltage thresholds (VT) based on modulated doping.

[0352] Figure 33A A cross-sectional view of an NMOS device pair and a PMOS device pair according to an embodiment of the present disclosure is shown. The NMOS device pair has differentiated voltage thresholds based on modulated doping, and the PMOS device pair has differentiated voltage thresholds based on modulated doping.

[0353] refer to Figure 33A, a first NMOS device 3302 is adjacent to a second NMOS device 3304 above a semiconductor active region 3300 (e.g., above a silicon fin or substrate). Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308 (e.g., a work function layer), and a gate electrode conductive fill 3310. In an embodiment, the first gate electrode conductive layer 3308 of the first NMOS device 3302 and the second NMOS device 3304 have the same material and the same thickness, thereby having the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a "standard VT" device, and the second NMOS device 3304 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using modulated doping or differential implant doping in the region 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0354] Reference again Figure 33A , a first PMOS device 3322 is adjacent to a second PMOS device 3324 above a semiconductor active region 3320 (e.g., above a silicon fin or substrate). Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 (e.g., a work function layer), and a gate electrode conductive fill 3330. In an embodiment, the first gate electrode conductive layer 3328 of the first PMOS device 3322 and the second PMOS device 3324 have the same material and the same thickness, thereby having the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a "standard VT" device, and the second PMOS device 3324 is referred to as a "low VT" device. In an embodiment, the differentiated VT is achieved by using modulated doping or differential implant doping in the region 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0355] and Figure 33A compared to, Figure 33B A cross-sectional view of an NMOS device pair and a PMOS device pair according to another embodiment of the present disclosure is shown. The NMOS device pair has differentiated voltage thresholds based on differentiated gate electrode structures, and the PMOS device pair has differentiated voltage thresholds based on differentiated gate electrode structures.

[0356] refer to Figure 33B, a first NMOS device 3352 is adjacent to a second NMOS device 3354 above a semiconductor active region 3350 (e.g., above a silicon fin or substrate). Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3352 includes a first gate electrode conductive layer 3358, such as a first work function layer, and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359, such as a second work function layer, the first gate electrode conductive layer 3358, and the gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In an embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0357] Reference again Figure 33B , a first PMOS device 3372 is adjacent to a second PMOS device 3374 above a semiconductor active region 3370 (e.g., above a silicon fin or substrate). Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A (e.g., a work function layer) having a first thickness and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness and a gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layer 3378A and the gate electrode conductive layer 3378B have the same composition, but the thickness of the gate electrode conductive layer 3378B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3378A (the first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In an embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0358] Reference again Figure 33BAccording to an embodiment of the present disclosure, an integrated circuit structure includes a fin (e.g., a silicon fin, such as 3350). It will be appreciated that the fin has a top (as shown) and sidewalls (into the page and out of the page). A gate dielectric layer 3356 is over the top of the fin and laterally adjacent to the sidewalls of the fin. An N-type gate electrode of device 3354 is over the gate dielectric layer 3356 over the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. It will be appreciated that a first N-type source or drain region can be adjacent to a first side of the gate electrode (e.g., into the page) and a second N-type source or drain region can be adjacent to a second side of the gate electrode (e.g., out of the page), the second side being opposite the first side.

[0359] In one embodiment, the P-type metal layer 3359 includes titanium and nitrogen, and the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2-12 angstroms, and in a specific embodiment, the P-type metal layer 3359 has a thickness in the range of 2-4 angstroms. In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 on the N-type metal layer 3358. In one such embodiment, the conductive fill metal layer 3360 includes tungsten. In a specific embodiment, the conductive fill metal layer 3360 includes 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine.

[0360] Reference again Figure 33B According to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), the first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on the first gate dielectric layer 3356. Furthermore, the structure also includes a second N-type device 3354 having a voltage threshold (VT), the second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0361] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 includes titanium and nitrogen.

[0362] Reference again Figure 33B According to another embodiment of the present disclosure, an integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), the first P-type device 3372 having a first gate dielectric layer 3376, and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. A second P-type device 3378 is also included and has a voltage threshold (VT). A second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness greater than that of the first P-type metal layer 3378A.

[0363] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B both include titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B includes a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and a seam is between the first metal film and the second metal film.

[0364] Reference again Figure 33B According to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. A first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. A second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than that of the second P-type metal layer 3378A.

[0365] In one embodiment, the first N-type device 3352 has a voltage threshold (VT), the second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, the first P-type device 3372 has a voltage threshold (VT), the second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on a second metal film, and a seam is between the first metal film and the second metal film.

[0366] It will be appreciated that more than two types of VT devices for the same conductivity type may be included in the same structure (eg, on the same die). Figure 34A Cross-sectional views of three NMOS devices and three PMOS devices according to an embodiment of the present disclosure are shown, where the three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0367] refer to Figure 34A, a first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 above a semiconductor active region 3400 (e.g., above a silicon fin or substrate). The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from the first NMOS device 3402 and the third NMOS device 3403. Specifically, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408 (e.g., a first work function layer) and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409 (e.g., a second work function layer), the first gate electrode conductive layer 3408, and the gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In an embodiment, the third NMOS device 3403 has a VT that is different from the VT of the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as the gate electrode structure of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device is between the VT of the first NMOS device 3402 and the VT of the second NMOS device 3404. In an embodiment, the differentiated VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using modulated doping or differential implant doping at the region 3412 of the third NMOS device 3403. In one such embodiment, the third N-type device 3403 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the first N-type device 3402 .

[0368] Reference again Figure 34A, a first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 above a semiconductor active region 3420 (e.g., above a silicon fin or substrate). The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have structurally identical or similar gate electrode stacks. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3408A (e.g., a work function layer) having a first thickness and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness and a gate electrode conductive fill 3430. In one embodiment, gate electrode conductive layer 3428A and gate electrode conductive layer 3428B have the same composition, but the thickness (second thickness) of gate electrode conductive layer 3428B is greater than the thickness (first thickness) of gate electrode conductive layer 3428A. In one embodiment, first PMOS device 3422 has a higher VT than second PMOS device 3424. In one such embodiment, first PMOS device 3422 is referred to as a "standard VT" device, and second PMOS device 3424 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, third PMOS device 3423 has a VT that is different from the VT of first PMOS device 3422 and the VT of second PMOS device 3424, even though the gate electrode structure of third PMOS device 3423 is the same as the gate electrode structure of first PMOS device 3422. In one embodiment, the VT of third PMOS device 3423 is between the VT of first PMOS device 3422 and the VT of second PMOS device 3424. In an embodiment, the differentiated VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using modulated doping or differential implant doping at the region 3432 of the third PMOS device 3423. In one such embodiment, the third P-type device 3423 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the first P-type device 3422.

[0369] In the second example, Figure 34BA cross-sectional view of three NMOS devices and three PMOS devices according to another embodiment of the present disclosure is shown, wherein the three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0370] refer to Figure 34B , a first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 above a semiconductor active region 3450 (e.g., above a silicon fin or substrate). The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458 (e.g., a first work function layer) and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459 (e.g., a second work function layer), the first gate electrode conductive layer 3458, and the gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In an embodiment, the third NMOS device 3453 has a VT that is different from the VT of the first NMOS device 3452 and the VT of the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as the gate electrode structure of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VT of the first NMOS device 3452 and the VT of the second NMOS device 3454. In an embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using modulated doping or differential implant doping at region 3462 of the third NMOS device 3453. In one such embodiment, the third N-type device 3453 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the second N-type device 3454 .

[0371] Reference again Figure 34B, a first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 above a semiconductor active region 3470 (e.g., above a silicon fin or substrate). The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have a gate electrode stack that is structurally the same or similar. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A (e.g., a work function layer) having a first thickness and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness and a gate electrode conductive fill 3480. In one embodiment, gate electrode conductive layer 3478A and gate electrode conductive layer 3478B have the same composition, but the thickness (second thickness) of gate electrode conductive layer 3478B is greater than the thickness (first thickness) of gate electrode conductive layer 3478A. In one embodiment, first PMOS device 3472 has a higher VT than second PMOS device 3474. In one such embodiment, first PMOS device 3472 is referred to as a "standard VT" device, and second PMOS device 3474 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, third PMOS device 3473 has a VT that is different from the VT of first PMOS device 3472 and the VT of second PMOS device 3474, even though the gate electrode structure of third PMOS device 3473 is the same as the gate electrode structure of second PMOS device 3474. In one embodiment, the VT of third PMOS device 3473 is between the VT of first PMOS device 3472 and the VT of second PMOS device 3474. In an embodiment, the differentiated VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using modulated doping or differential implant doping at the region 3482 of the third PMOS device 3473. In one such embodiment, the third P-type device 3473 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the second P-type device 3474.

[0372] Figures 35A-35D Cross-sectional views illustrating various operations in a method of fabricating an NMOS device having differentiated voltage thresholds based on differentiated gate electrode structures, in accordance with an embodiment of the present disclosure.

[0373] refer to Figure 35A , wherein a “standard VT NMOS” region (STD VT NMOS) and a “high VT NMOS” region (HIGH VTNMOS) are shown bifurcated on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and over a second semiconductor fin 3504 (e.g., over first and second silicon fins). A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0374] refer to Figure 35B , a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502 , but a portion 3509 of the P-type metal layer 3508 remains on the gate dielectric layer 3506 above the second semiconductor fin 3504 .

[0375] refer to Figure 35C , an N-type metal layer 3510 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502, and on a portion of the P-type metal layer 3509 above the gate dielectric layer 3506 above the second semiconductor fin 3504. In an embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) above the first semiconductor fin 3502, and forming a second N-type device having a voltage threshold (VT) above the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0376] refer to Figure 35D In an embodiment, a conductive fill metal layer 3512 is formed on the N-type metal layer 3510. In one such embodiment, forming the conductive fill metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor.

[0377] Figures 36A-36D Cross-sectional views illustrating various operations in a method of fabricating a PMOS device having differentiated voltage thresholds based on differentiated gate electrode structures, in accordance with an embodiment of the present disclosure.

[0378] refer to Figure 36A, wherein a “standard VT PMOS” region (STD VT PMOS) and a “low VT PMOS” region (LOW VTPMOS) are shown bifurcated on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3606 over a first semiconductor fin 3602 and over a second semiconductor fin 3604 (e.g., over first and second silicon fins). A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0379] refer to Figure 36B , a portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602 , but a portion 3609 of the first P-type metal layer 3608 remains on the gate dielectric layer 3606 above the second semiconductor fin 3604 .

[0380] refer to Figure 36C , a second P-type metal layer 3610 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602, and on a portion 3609 of the first P-type metal layer above the gate dielectric layer 3606 above the second semiconductor fin 3604. In an embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) above the first semiconductor fin 3602, and forming a second P-type device having a voltage threshold (VT) above the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0381] In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same composition. In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same thickness. In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, a seam 3611 is provided between first P-type metal layer 3608 and second P-type metal layer 3610, as shown.

[0382] refer to Figure 36D In an embodiment, a conductive fill metal layer 3612 is formed over the P-type metal layer 3610. In one such embodiment, forming the conductive fill metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor. In one embodiment, an N-type metal layer 3614 is formed over the P-type metal layer 3610 before forming the conductive fill metal layer 3612, as shown. In one such embodiment, the N-type metal layer 3614 is an artifact of the dual metal gate replacement process scheme.

[0383] In another aspect, a metal gate structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. In an example, Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is shown.

[0384] refer to Figure 37 Integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 and a P-well region 3708. N-well region 3704 has a first semiconductor fin 3706 protruding therefrom, and P-well region 3708 has a second semiconductor fin 3710 protruding therefrom. First semiconductor fin 3706 is spaced apart from second semiconductor fin 3710. N-well region 3704 and P-well region 3708 are directly adjacent in semiconductor substrate 3702. Trench isolation structure 3712 is formed on semiconductor substrate 3702 outside and between first semiconductor fin 3706 and second semiconductor fin 3710. First 3706 and second 3710 semiconductor fins extend above trench isolation structure 3712.

[0385] A gate dielectric layer 3714 is formed over the first 3706 and second 3710 semiconductor fins and over the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first 3706 and second 3710 semiconductor fins. A conductive layer 3716 is formed over the gate dielectric layer 3714 above the first semiconductor fin 3706, but not over the gate dielectric layer 3714 above the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is formed over the conductive layer 3716 above the first semiconductor fin 3706, but not over the conductive layer 3716 above the second semiconductor fin 3710. The p-type metal gate layer 3718 is further formed over a portion, but not all, of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. The N-type metal gate layer 3720 is over the second semiconductor fin 3710 , over the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710 , and over the P-type metal gate layer 3718 .

[0386] In one embodiment, an interlayer dielectric (ILD) layer 3722 is formed over the trench isolation structure 3712 on the exterior of the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first 3706 and second 3710 semiconductor fins. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along sidewalls 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 that is below a top surface 3719 of the p-type metal gate layer 3718 along the sidewalls 3726 of the opening 3724 and below a top surface 3721 of the n-type metal gate layer 3720 along the sidewalls 3726 of the opening 3724, as shown.

[0387] In one embodiment, the p-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 comprises titanium and aluminum. In one embodiment, a conductive fill metal layer 3730 is above the n-type metal layer 3720, as shown. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In a specific embodiment, the conductive fill metal layer 3730 comprises 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer 3714 has a layer comprising hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is between the upper portions of the first 3706 and second 3710 semiconductor fins, as shown. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0388] Now only reference Figure 37 On the right side, according to an embodiment of the present disclosure, an integrated circuit structure includes a semiconductor substrate 3702 including an N-well region 3704 with a semiconductor fin 3706 protruding therefrom. A trench isolation structure 3712 is on semiconductor substrate 3702 and around semiconductor fin 3706. Semiconductor fin 3706 extends above trench isolation structure 3712. A gate dielectric layer 3714 is above semiconductor fin 3706. A conductive layer 3716 is above gate dielectric layer 3714 above semiconductor fin 3706. In one embodiment, conductive layer 3716 includes titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is above conductive layer 3716 above semiconductor fin 3706.

[0389] In one embodiment, an interlayer dielectric (ILD) layer 3722 is above the trench isolation structure 3712. The ILD layer has an opening that exposes the semiconductor fin 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewalls of the opening that is lower than the top surface of the P-type metal gate layer 3718 along the sidewalls of the opening. In one embodiment, the P-type metal gate layer 3718 is above the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 includes tungsten. In a specific such embodiment, the conductive fill metal layer 3730 is composed of 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer 3714 includes a layer comprising hafnium and oxygen.

[0390] Figures 38A-38H Cross-sectional views are illustrated of various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow in accordance with an embodiment of the present disclosure.

[0391] refer to Figure 38A , which shows an NMOS (N-type) region and a PMOS (P-type) region, a method of fabricating an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 over a first 3804 and a second 3806 semiconductor fin over a substrate 3800. An opening 3808 is formed in the ILD layer 3802, exposing the first 3804 and the second 3806 semiconductor fins. In one embodiment, the opening 3808 is formed by removing a gate placeholder or dummy gate structure initially located above the first 3804 and the second 3806 semiconductor fins.

[0392] A gate dielectric layer 3810 is formed in the opening 3808 and over a portion of the trench isolation structure 3812 between the first 3804 and second 3806 semiconductor fins and between the first 3804 and second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed over a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, formed over the first 3804 and second 3806 semiconductor fins, as shown. In another embodiment, the gate dielectric layer 3810 is formed directly over the first 3804 and second 3806 semiconductor fins.

[0393] Conductive layer 3814 is formed over gate dielectric layer 3810 formed over first 3804 and second 3806 semiconductor fins. In one embodiment, conductive layer 3814 includes titanium, nitrogen, and oxygen. P-type metal gate layer 3816 is formed over conductive layer 3814 formed over first semiconductor fin 3804 and second semiconductor fin 3806.

[0394] refer to Figure 38B A dielectric etch stop layer 3818 is formed on the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first silicon oxide (e.g., SiO2) layer, an aluminum oxide layer (e.g., Al2O3) on the first silicon oxide layer, and a second silicon oxide (e.g., SiO2) layer on the aluminum oxide layer.

[0395] refer to Figure 38C , mask 3820 is formed on Figure 38B The mask 3820 covers the PMOS region and exposes the NMOS region.

[0396] refer to Figure 38D Dielectric etch stop layer 3818, p-type metal gate layer 3816, and conductive layer 3814 are patterned to provide patterned dielectric etch stop layer 3819, patterned p-type metal gate layer 3817 over patterned conductive layer 3815 over first semiconductor fin 3804 but not over second semiconductor fin 3806. In an embodiment, conductive layer 3814 protects second semiconductor fin 3806 during patterning.

[0397] refer to Figure 38E ,from Figure 38D The structure of the mask 3820 is removed. Figure 38F ,from Figure 38E The patterned dielectric etch stop layer 3819 is removed from the structure.

[0398] refer to Figure 38G An n-type metal gate layer 3822 is formed over the second semiconductor fin 3806, over a portion of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and over the patterned p-type metal gate layer 3817. In an embodiment, a patterned conductive layer 3815, a patterned p-type metal gate layer 3817, and an n-type metal gate layer 3822 are further formed along sidewalls 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface that is below a top surface of the patterned p-type metal gate layer 3817 along the sidewalls 3824 of the opening 3808 and below a top surface of the n-type metal gate layer 3822 along the sidewalls 3824 of the opening 3808.

[0399] refer to Figure 38H A conductive fill metal layer 3826 is formed over the n-type metal layer 3822. In one embodiment, the conductive fill metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0400] In another aspect, a double silicide structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. As an exemplary process flow, Figures 39A-39H Depicted are cross-sectional views representing various operations in a method of fabricating a bisulicide based integrated circuit, in accordance with an embodiment of the present disclosure.

[0401] refer to Figure 39A , wherein NMOS and PMOS regions are shown bifurcated on a common substrate, a method of fabricating an integrated circuit structure includes forming a first gate structure 3902, which may include a dielectric sidewall spacer 3903, over a first fin 3904, such as a first silicon fin. A second gate structure 3952, which may include a dielectric sidewall spacer 3953, is formed over a second fin 3954, such as a second silicon fin. An insulating material 3906 is formed adjacent to the first gate structure 3902 over the first fin 3904 and adjacent to the second gate structure 3952 over the second fin 3954. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask during a double silicide process.

[0402] refer to Figure 39B , a first portion of the insulating material 3906 is removed from above the first fin 3904 but not from above the second fin 3954 to expose first 3908 and second 3910 source or drain regions of the first fin 3904 adjacent to the first gate structure 3902. In an embodiment, the first 3908 and second 3910 source or drain regions are epitaxial regions formed within a recessed portion of the first fin 3904, as shown. In one such embodiment, the first 3908 and second 3910 source or drain regions include silicon and germanium.

[0403] refer to Figure 39C , a first metal silicide layer 3912 is formed on the first 3908 and second 3910 source or drain regions of the first fin 3904. In one embodiment, by Figure 39B A layer including nickel and platinum is deposited on the structure, the layer including nickel and platinum is annealed, and unreacted portions of the layer including nickel and platinum are removed to form a first metal silicide layer 3912.

[0404] refer to Figure 39DAfter forming the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed from over the second fin 3954 to expose third 3958 and fourth 3960 source or drain regions of the second fin 3954 adjacent to the second gate structure 3952. In an embodiment, the second 3958 and third 3960 source or drain regions are formed within the second fin 3954, such as within the second silicon fin, as shown. However, in another embodiment, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within a recessed portion of the second fin 3954. In one such embodiment, the third 3958 and fourth 3960 source or drain regions comprise silicon.

[0405] refer to Figure 39E , the first metal layer 3914 is formed on Figure 39D , i.e., on the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions of the second fin 3954. A second metal silicide layer 3962 is then formed on the third 3958 and fourth 3960 source or drain regions of the second fin 3954. For example, the second metal silicide layer 3962 is formed from the first metal layer 3914 using an annealing process. In an embodiment, the composition of the second metal silicide layer 3962 is different from the composition of the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, e.g., with Figure 39D The opening trench is conformal, as shown.

[0406] refer to Figure 39F In an embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 over each of the first 3908 , second 3910 , third 3958 , and fourth 3960 source or drain regions.

[0407] refer to Figure 39G In an embodiment, the second metal layer 3918 is formed on Figure 39F In an embodiment, the composition of the second metal layer 3918 is different from that of the U-shaped metal layer 3916.

[0408] refer to Figure 39H In an embodiment, the third metal layer 3920 is formed on Figure 39G In an embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition.

[0409] Reference again Figure 39HAccording to an embodiment of the present disclosure, an integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) above a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be appreciated that the first fin has a top (shown as 3904A) and sidewalls (entering the page and exiting the page). The first gate electrode 3902 includes a first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and includes a first gate electrode above the first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite the first side 3902A.

[0410] The first 3908 and second 3910 semiconductor source or drain regions are respectively adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902. The first 3930 and second 3932 trench contact structures are respectively above the first 3908 and second 3910 semiconductor source or drain regions that are adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902. The first metal silicide layer 3912 is respectively directly between the first 3930 and second 3932 trench contact structures and the first 3908 and second 3910 semiconductor source or drain regions.

[0411] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be appreciated that the second fin has a top (shown as 3954A) and sidewalls (entering the page and exiting the page). The second gate electrode 3952 includes a second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954, and includes a second gate electrode above the second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

[0412] The third 3958 and fourth 3960 semiconductor source or drain regions are adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. Third 3970 and fourth 3972 trench contact structures are respectively above the third 3958 and fourth 3960 semiconductor source or drain regions adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952. A second metal silicide layer 3962 is respectively directly between the third 3970 and fourth 3972 trench contact structures and the third 3958 and fourth 3960 semiconductor source or drain regions. In one embodiment, the first metal silicide layer 3912 includes at least one metal species that is not included in the second metal silicide layer 3962.

[0413] In one embodiment, the second metal silicide layer 3962 includes titanium and silicon. The first metal silicide layer 3912 includes nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 also includes germanium. In one embodiment, the first metal silicide layer 3912 also includes titanium, for example, which is incorporated into the first metal silicide layer 3912 during the subsequent formation of the second metal silicide layer 3962 using the first metal layer 3914. In one such embodiment, the silicide layer already formed on the PMOS source or drain region is further modified by the annealing process used to form the silicide region on the NMOS source or drain region. This may result in the silicide layer on the PMOS source or drain region having a very small percentage of the total silicide metal. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region is not modified or substantially unchanged by the annealing process used to form the silicide region on the NMOS source or drain region.

[0414] In one embodiment, the first 3908 and second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are formed in the fin 3954 and are not embedded epitaxial regions.

[0415] In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 disposed entirely on and above the U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 comprises titanium, and the T-shaped metal layer 3918 comprises cobalt. In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all include a third metal layer 3920 disposed on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a specific embodiment, the third metal layer 3920 and the U-shaped metal layer comprise titanium, and the T-shaped metal layer 3918 comprises cobalt.

[0416] In another aspect, a trench contact structure, such as for a source or drain region, is described. In an example, Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to an embodiment of the present disclosure is shown. Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device according to another embodiment of the present disclosure is shown.

[0417] refer to Figure 40A , integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is over fin 4002. A gate electrode 4006 is over gate dielectric layer 4004. In one embodiment, gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In one embodiment, a dielectric cap 4012 is over gate electrode 4006 and over gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite first side 4006A. Dielectric spacers 4013 are located along sidewalls of gate electrode 4006. In one embodiment, gate dielectric layer 4004 is further located between a first one of dielectric spacers 4013 and first side 4006A of gate electrode 4006, and between a second one of dielectric spacers 4013 and second side 4006B of gate electrode 4006, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4002 and the gate dielectric layer 4004 .

[0418] First 4014 and second 4016 semiconductor source or drain regions are adjacent to first 4006A and second 4006B sides, respectively, of gate electrode 4006. In one embodiment, first 4014 and second 4016 semiconductor source or drain regions are within fin 4002, as shown. However, in another embodiment, first 4014 and second 4016 semiconductor source or drain regions are embedded epitaxial regions formed within recesses in fin 4002.

[0419] The first 4018 and second 4020 trench contact structures are respectively located above the first 4014 and second 4016 semiconductor source or drain regions adjacent to the first 4006A and second 4006B sides of the gate electrode 4006. The first 4018 and second 4020 trench contact structures each include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 disposed entirely above and above the U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In one such embodiment, the U-shaped metal layer 4022 includes titanium, and the T-shaped metal layer 4024 includes cobalt. In one embodiment, the first 4018 and second 4020 trench contact structures each include a third metal layer 4026 disposed above the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, third metal layer 4026 and U-shaped metal layer 4022 include titanium, and T-shaped metal layer 4024 includes cobalt.

[0420] A first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is further on and in contact with a portion of one of the dielectric spacers 4013 and on and in contact with a portion of the dielectric cap 4012. A second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is on and coupled to the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is further on and in contact with a portion of another one of the dielectric spacers 4013 and on and in contact with another portion of the dielectric cap 4012.

[0421] In an embodiment, a metal silicide layer 4032 is directly between the first 4018 and second 4020 trench contact structures and the first 4014 and second 4016 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4032 comprises titanium and silicon. In a particular embodiment, the first 4014 and second 4016 semiconductor source or drain regions are first and second N-type semiconductor source or drain regions.

[0422] refer to Figure 40B , integrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is over fin 4052. A gate electrode 4056 is over gate dielectric layer 4054. In one embodiment, gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060. In one embodiment, a dielectric cap 4062 is over gate electrode 4056 and over gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite first side 4056A. Dielectric spacers 4063 are located along sidewalls of gate electrode 4056. In one embodiment, gate dielectric layer 4054 is further located between a first one of dielectric spacers 4063 and first side 4056A of gate electrode 4056, and between a second one of dielectric spacers 4063 and second side 4056B of gate electrode 4056, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4052 and the gate dielectric layer 4054 .

[0423] First 4064 and second 4066 semiconductor source or drain regions are adjacent to first 4056A and second 4056B sides, respectively, of gate electrode 4056. In one embodiment, first 4064 and second 4066 semiconductor source or drain regions are embedded epitaxial regions formed in recesses 4065 and 4067, respectively, of fin 4052, as shown. However, in another embodiment, first 4064 and second 4066 semiconductor source or drain regions are within fin 4052.

[0424] The first 4068 and second 4070 trench contact structures are respectively located above the first 4064 and second 4066 semiconductor source or drain regions adjacent to the first 4056A and second 4056B sides of the gate electrode 4056. The first 4068 and second 4070 trench contact structures each include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 disposed entirely above and above the U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one such embodiment, the U-shaped metal layer 4072 includes titanium and the T-shaped metal layer 4074 includes cobalt. In one embodiment, the first 4068 and second 4070 trench contact structures each also include a third metal layer 4076 disposed above the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, third metal layer 4076 and U-shaped metal layer 4072 include titanium, and T-shaped metal layer 4074 includes cobalt.

[0425] A first trench contact via 4078 is electrically connected to the first trench contact 4068. In a particular embodiment, the first trench contact via 4078 is on and coupled to the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is further on and in contact with a portion of one of the dielectric spacers 4063 and on and in contact with a portion of the dielectric cap 4062. A second trench contact via 4080 is electrically connected to the second trench contact 4070. In a particular embodiment, the second trench contact via 4080 is on and coupled to the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is further on and in contact with a portion of another one of the dielectric spacers 4063 and on and in contact with another portion of the dielectric cap 4062.

[0426] In one embodiment, a metal silicide layer 4082 is directly between the first 4068 and second 4070 trench contact structures and the first 4064 and second 4066 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4082 comprises nickel, platinum, and silicon. In a specific embodiment of this type, the first 4064 and second 4066 semiconductor source or drain regions are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further comprises germanium. In another embodiment, the metal silicide layer 4082 further comprises titanium.

[0427] One or more embodiments described herein relate to using metal chemical vapor deposition for wraparound semiconductor contacts. Embodiments may be applicable to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0428] Certain embodiments may include fabricating a titanium or similar metal layer using low-temperature (e.g., less than 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of a contact metal to provide a conformal source or drain contact. Implementing such a conformal source or drain contact may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

[0429] To provide context, sputtering can be used to deposit metal onto semiconductor contact layers. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering schemes have poor or incomplete metal-semiconductor junctions at device contact surfaces due to the angle of incidence of the deposition.

[0430] According to one or more embodiments of the present disclosure, a low-temperature chemical vapor deposition process is implemented to fabricate the contact metal to provide conformality in three dimensions and maximize the metal-semiconductor junction contact area. The resulting larger contact area can reduce the resistance of the junction. Embodiments can include deposition on a semiconductor surface having a non-planar topography, where the topography of a region refers to the surface shape and features themselves, and the non-planar topography includes surface shapes and features that are not planar or portions of surface shapes and features, i.e., surface shapes and features that are not completely planar.

[0431] Embodiments described herein may include fabricating wraparound contact structures. In one such embodiment, the use of a pure metal conformally deposited onto a transistor source-drain contact by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the available area of ​​the metal-semiconductor contact and reduce resistance, thereby improving transistor device performance. In embodiments, the lower temperature of deposition minimizes junction resistance per unit area.

[0432] It should be appreciated that various integrated circuit structures can be manufactured using an integrated scheme involving metal layer deposition processes as described herein. According to an embodiment of the present disclosure, a method of manufacturing an integrated circuit structure includes providing a substrate having features thereon in a chemical vapor deposition (CVD) chamber having an RF source. The method also includes reacting titanium tetrachloride (TiCl4) and hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate.

[0433] In an embodiment, the titanium layer has a total atomic composition comprising 98% or more titanium and 0.5-2% chlorine. In alternative embodiments, high-purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V) are fabricated using similar processes. In an embodiment, there is relatively little film thickness variation; for example, in an embodiment, all coverages are greater than 50% and nominal values ​​are 70% or greater (i.e., thickness variation is 30% or less). In an embodiment, the thickness measured on silicon (Si) or silicon germanium (SiGe) is thicker than on other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In an embodiment, the film composition includes approximately 0.5% Cl (or less than 1%) as an impurity, with substantially no other observed impurities. In an embodiment, the deposition process enables metal coverage on non-line-of-sight surfaces, such as surfaces hidden from view by sputter deposition. The embodiments described herein can be implemented to improve transistor device drive by reducing the external resistance of current driven through the source and drain contacts.

[0434] According to an embodiment of the present disclosure, the substrate is characterized by exposing a source or drain contact trench of a semiconductor source or drain structure. The titanium layer (or other high purity metal layer) is a conductive contact layer for the semiconductor source or drain structure. Figure 41A 、 Figure 41B 、 Figure 42 、 Figures 43A-43C and Figure 44 Exemplary embodiments of such implementations are described.

[0435] Figure 41A A cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to an embodiment of the present disclosure is shown.

[0436] refer to Figure 41A , semiconductor structure 4100 includes a gate structure 4102 over a substrate 4104. Gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. Source region 4108 and drain region 4110 are on opposite sides of gate structure 4102. Source or drain contacts 4112 are electrically connected to source region 4108 and drain region 4110 and are separated from gate structure 4102 by one or both of an interlayer dielectric 4114 and a gate dielectric spacer 4116. Source region 4108 and drain region 4110 are regions of substrate 4104.

[0437] In an embodiment, the source or drain contact 4112 includes a high-purity metal layer 4112A, such as described above, and a conductive trench fill material 4112B. In one embodiment, the high-purity metal layer 4112A has a total atomic composition comprising 98% or greater titanium. In one such embodiment, the high-purity metal layer 4112A also includes 0.5-2% chlorine. In an embodiment, the high-purity metal layer 4112A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 4112B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0438] Figure 41B A cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region according to an embodiment of the present disclosure is shown.

[0439] refer to Figure 41B, semiconductor structure 4150 includes a gate structure 4152 above a substrate 4154. Gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. Source region 4158 and drain region 4160 are on opposite sides of gate structure 4152. Source or drain contacts 4162 are electrically connected to source region 4158 and drain region 4160 and are separated from gate structure 4152 by one or both of an interlayer dielectric layer 4164 or a gate dielectric spacer 4166. Source region 4158 and drain region 4160 are epitaxial or embedded material regions formed in the etched away areas of substrate 4154. As shown, in an embodiment, source region 4158 and drain region 4160 are elevated source and drain regions. In specific such embodiments, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

[0440] In an embodiment, the source or drain contact 4162 includes a high-purity metal layer 4162A, such as described above, and a conductive trench fill material 4162B. In one embodiment, the high-purity metal layer 4162A has a total atomic composition comprising 98% or greater titanium. In one such embodiment, the high-purity metal layer 4162A also includes 0.5-2% chlorine. In an embodiment, the high-purity metal layer 4162A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 4162B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0441] Therefore, in the embodiments, reference is made to Figure 41A and Figure 41B , the integrated circuit structure includes a feature having a surface (a source or drain contact trench exposing a semiconductor source or drain structure). A high purity metal layer 4112A or 4162A is on the surface of the source or drain contact trench. It should be recognized that the contact formation process can involve consumption of exposed silicon or germanium or silicon germanium material of the source or drain region. Such consumption may reduce device performance. In contrast, according to embodiments of the present disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not corroded or consumed, or is substantially not corroded or consumed below the source or drain contact trench. In one such embodiment, the lack of consumption or corrosion is caused by the low temperature deposition of the high purity metal contact layer.

[0442] Figure 42 A plan view of multiple gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0443] refer to Figure 42, a plurality of active gate lines 4204 are formed over the plurality of semiconductor fins 4200. Dummy gate lines 4206 are at the ends of the plurality of semiconductor fins 4200. The spaces 4208 between the gate lines 4204 / 4206 are where trench contacts can be formed as conductive contacts to source or drain regions (e.g., source or drain regions 4251, 4252, 4253, and 4254).

[0444] Figures 43A-43C The flowchart of various operations in the method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 42 Cross-sectional view taken along the a-a' axis.

[0445] refer to Figure 43A A plurality of active gate lines 4304 are formed on semiconductor fins 4302 formed above a substrate 4300. Dummy gate lines 4306 are located at the ends of semiconductor fins 4302. A dielectric layer 4310 is disposed between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. Embedded source or drain structures 4308 are located in the semiconductor fins 4302 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. The active gate lines 4304 include a gate dielectric layer 4312, a work function gate electrode portion 4314, a fill gate electrode portion 4316, and a dielectric cap layer 4318. Dielectric spacers 4320 are arranged along the sidewalls of the active gate lines 4304 and the dummy gate lines 4306.

[0446] refer to Figure 43B , portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 are removed to provide openings 4330 where trench contacts are to be formed. Removing the portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 may cause the embedded source or drain structure 4308 to be etched to provide an etched embedded source or drain structure 4332 that may have an upper saddle-shaped morphology, as shown. Figure 43B shown.

[0447] refer to Figure 43C Trench contacts 4334 are formed in the openings 4330 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304. Each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive fill material 4338.

[0448] Figure 44 The embodiment of the present disclosure shows an integrated circuit structure along the Figure 42Cross-sectional view taken along the b-b' axis.

[0449] refer to Figure 44 , fin 4402 is shown above substrate 4404. A lower portion of fin 4402 is surrounded by trench isolation material 4404. An upper portion of fin 4402 has been removed to enable growth of embedded source and drain structures 4406. Trench contacts 4408 are formed in openings in dielectric layer 4410 that expose embedded source and drain structures 4406. The trench contacts include a metal contact layer 4412 and a conductive fill material 4414. It should be appreciated that, in accordance with an embodiment, the metal contact layer 4412 extends to the top of the trench contacts 4408, as shown. Figure 44 However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact portion 4408, and is somewhat recessed within the trench contact portion 4408, for example, similar to Figure 43C Illustration of the metal contact layer 4436 in FIG.

[0450] Therefore, the common reference Figure 42 、 Figures 43A-43C and Figure 44According to an embodiment of the present disclosure, an integrated circuit structure includes a semiconductor fin (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fin (4200, 4302, 4402) has a top and sidewalls. A gate electrode (4204, 4304) is above the top and adjacent to the sidewall of a portion of the semiconductor fin (4200, 4302, 4402). The gate electrode (4204, 4304) defines a channel region in the semiconductor fin (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) has a non-planar topography at a first end of the channel region on a first side of the gate electrode (4204, 4304). A second semiconductor source or drain structure (4252, 4332, 4406) is provided at a second end of the channel region on a second side of the gate electrode (4204, 4304), the second end being opposite the first end and the second side being opposite the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar morphology. A metal contact material (4336, 4412) is directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact material (4336, 4412) conforms to the non-planar morphology of the first semiconductor source or drain structure (4251, 4332, 4406) and conforms to the non-planar morphology of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In an embodiment, the metal contact material (4336, 4412) has a total atomic composition comprising 95% or greater of a single metal species. In one such embodiment, the metal contact material (4336, 4412) has a total atomic composition comprising 98% or greater of titanium. In a specific such embodiment, the total atomic composition of the metal contact material (4336, 4412) further comprises 0.5-2% of chlorine. In an embodiment, the metal contact material (4336, 4412) has a thickness variation of 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0452] In an embodiment, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a raised central portion and lower side portions, e.g. Figure 44In an embodiment, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a saddle-shaped portion, for example, Figure 43C As shown in .

[0453] In an embodiment, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both comprise silicon. In an embodiment, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both further comprise germanium, for example in the form of silicon germanium.

[0454] In an embodiment, the metal contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) is further extended along the sidewalls of a trench in the dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal contact material (4336) decreases along the sidewalls of the trench from 4336A at the first semiconductor source or drain structure (4332) to a position (4336B) above the first semiconductor source or drain structure (4332). Figure 43C In an embodiment, the conductive fill material (4338, 4414) is on the metal contact material (4336, 4412) in the trench, as shown in FIG. Figure 43C and Figure 44 shown.

[0455] In an embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (eg, Figure 42The gate electrode (4204, 4304) is also above a top portion of the second semiconductor fin and adjacent to a sidewall of the portion, the gate electrode defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is at a first end of the channel region of the second semiconductor fin on a first side of the gate electrode (4204, 4304), the third semiconductor source or drain structure having a non-flat morphology. A fourth semiconductor source or drain structure (4254, 4332, 4406) is at a second end of the channel region of the second semiconductor fin on a second side of the gate electrode (4204, 4304), the second end being opposite to the first end, the fourth semiconductor source or drain structure (4254, 4332, 4406) having a non-flat morphology. The metal contact material (4336, 4412) is directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406), and the metal contact material (4336, 4412) is conformal to the non-flat morphology of the third semiconductor source or drain structure (4253, 4332, 4406) and conformal to the non-flat morphology of the fourth semiconductor source or drain structure (4254, 4332, 4406). In an embodiment, the metal contact material (4336, 4412) is continuous between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, right side 4406), and is continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0456] In another aspect, a hard mask material may be used to preserve (stop corrosion) and may remain where the conductive trench contacts are interrupted above the dielectric material in the trench line locations, such as at the contact plug locations. Figure 45A and Figure 45B A plan view and corresponding cross-sectional views are respectively shown of an integrated circuit structure including a trench contact plug having a hard mask material thereon according to an embodiment of the present disclosure.

[0457] refer to Figure 45A and Figure 45BIn one embodiment, an integrated circuit structure 4500 includes a fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are located above the fin 4502A. Each gate structure in the gate structures 4506 is oriented in a direction 4508 orthogonal to the fin 4502A and has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of a first pair 4506A / 4506B of gate structures 4506. A contact plug 4514B is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of a second pair 4506B / 4506C of gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hardmask material 4518.

[0458] In an embodiment, the lower dielectric material 4516 of the contact plug 4516B includes silicon and oxygen, such as silicon oxide or silicon dioxide. The upper hard mask material 4518 of the contact plug 4516B includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0459] In an embodiment, trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on lower conductive structure 4520. In one embodiment, dielectric cap 4522 of trench contact structure 4512 has an upper surface that is coplanar with an upper surface of upper hard mask material 4518 of contact plug 4514B, as shown.

[0460] In one embodiment, individual gate structures in the plurality of gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of the individual gate structures in the plurality of gate structures 4506 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown. In one embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0461] Reference again Figure 45A and Figure 45BIn one embodiment, an integrated circuit structure 4500 includes a plurality of fins 4502, such as a plurality of silicon fins. Individual fins in the plurality of fins 4502 are oriented along a first direction 4504. A plurality of gate structures 4506 are disposed over the plurality of fins 4502. Individual gate structures in the plurality of gate structures 4506 are oriented along a second direction 4508 orthogonal to the first direction 4504. Each gate structure in the plurality of gate structures 4506 has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is disposed over a first fin 4502A in the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. A contact plug 4514A is disposed over a second fin 4502B in the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518 .

[0462] In an embodiment, the lower dielectric material 4516 of the contact plug 4516A includes silicon and oxygen, such as silicon oxide or silicon dioxide. The upper hard mask material 4518 of the contact plug 4516A includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0463] In an embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as shown.

[0464] In one embodiment, each gate structure in the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each gate structure in the plurality of gate structures 4506 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as shown. In one embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0465] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process can be implemented to form a contact structure for semiconductor structure manufacturing (e.g., for integrated circuit manufacturing). In an embodiment, the contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve additional photolithography processes that utilize strict alignment of the photolithographic contact pattern with the existing gate pattern in combination with selective contact etching. For example, another process can include patterning a multi-(gate) grid, wherein the contacts and contact plugs are patterned separately.

[0466] According to one or more embodiments described herein, a contact formation method involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of photolithography operations with super tight registration budgets. In one such embodiment, the approach enables the use of inherently highly selective wet etching (e.g., relative to dry or plasma etching) to produce contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug photolithography operation. In one such embodiment, the approach enables the elimination of the need for photolithography operations (as used in other approaches) that would otherwise be critical to producing the contact pattern. In an embodiment, a trench contact grid is not patterned separately, but is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0467] Figures 46A-46D Depicted are cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including a trench contact plug having a hard mask material thereon, in accordance with an embodiment of the present disclosure.

[0468] refer to Figure 46A A method of fabricating an integrated circuit structure includes forming a plurality of fins, wherein individual fins 4602 of the plurality of fins are oriented along a first direction 4604. Individual fins 4602 of the plurality of fins may include diffusion regions 4606. A plurality of gate structures 4608 are formed over the plurality of fins. Individual gate structures of the plurality of gate structures 4508 are oriented along a second direction 4610 orthogonal to the first direction 4604 (e.g., direction 4610 into and out of the page). A sacrificial material structure 4612 is formed between a first pair of gate structures 4608. A contact plug 4614 is formed between a second pair of gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask material 4618 is formed over the lower dielectric material 4616.

[0469] In an embodiment, gate structure 4608 includes a sacrificial or dummy gate stack and dielectric spacers 4609. The sacrificial or dummy gate stack may be composed of polysilicon or silicon nitride pillars or some other sacrificial material that may be referred to as dummy gate material.

[0470] refer to Figure 46B ,from Figure 46A The sacrificial material structure 4612 is removed from the structure to form an opening 4620 between the first pair of gate structures 4608.

[0471] refer to Figure 46C , a trench contact structure 4622 is formed in the opening 4620 between the first pair of gate structures 4608. Additionally, in an embodiment, as part of forming the trench contact structure 4622, the gate structure 4608 may be formed in the opening 4620 between the first pair of gate structures 4608. Figure 46A and Figure 46B The hard mask 4618 is planarized. The final contact plug 4614 ′ includes an upper hard mask material 4616 and an upper hard mask material 4624 formed of the hard mask material 4618 .

[0472] In one embodiment, the lower dielectric material 4616 of each of the contact plugs 4614′ includes silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614′ includes silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614′.

[0473] refer to Figure 46D , the sacrificial or dummy gate stack of gate structure 4608 is replaced in a replacement gate process scheme. In such a scheme, the dummy gate material is removed and replaced with a permanent gate electrode material, such as a polysilicon or silicon nitride pillar material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, as opposed to being formed from an earlier process.

[0474] Thus, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Furthermore, in an embodiment, a top portion of the permanent gate structure 4630 is removed, for example, by an etching process, and replaced with a dielectric cap 4636. In an embodiment, the dielectric caps 4636 of individual permanent gate structures in the permanent gate structure 4630 have upper surfaces that are coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614′.

[0475] Reference again Figures 46A-46DIn an embodiment, the replacement gate process is performed after forming the trench contact structure 4622 , as shown. However, according to other embodiments, the replacement gate process is performed before forming the trench contact structure 4622 .

[0476] In another aspect, a contact over active gate structure (COAG) structure and process are described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The approaches described herein can be used to reduce the standard cell area by enabling the formation of a gate contact over an active gate region. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure.

[0477] In technologies where space and layout constraints are somewhat relaxed compared to current generations, contact to the gate structure can be made by forming a contact to a portion of the gate electrode disposed over the isolation region. As an example, Figure 47A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0478] refer to Figure 47A , semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed in substrate 4702 and within isolation region 4706. One or more gate lines (also referred to as multi-lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over diffusion or active region 4704 and over a portion of isolation region 4706. Source or drain contacts (also referred to as trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contact to trench contacts 4710A and 4710B, respectively. A separate gate contact 4714 and an overlying gate contact via 4716 provide contact to gate line 4708B. Compared to the source or drain trench contacts 4710A or 4710B, from a plan view perspective, the gate contact 4714 is disposed over the isolation region 4706, but not over the diffusion or active region 4704. Furthermore, neither the gate contact 4714 nor the gate contact via 4716 is disposed between the source or drain trench contacts 4710A and 4710B.

[0479] Figure 47BA cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Figure 47B , semiconductor structure or device 4700B (e.g. Figure 47A 4700A) includes a non-planar diffusion or active region 4704C (e.g., a fin structure) formed from a substrate 4702 and within an isolation region 4706. A gate line 4708B is disposed over the non-planar diffusion or active region 4704B and over a portion of the isolation region 4706. As shown, the gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752, along with a dielectric cap layer 4754. Also visible from this perspective is a gate contact 4714 and an overlying gate contact via 4716, along with an overlying metal interconnect 4760, all disposed in an interlayer dielectric stack or layer 4770. Figure 47B Also seen in the perspective view of FIG, gate contact 4714 is disposed over isolation region 4706 but not over non-planar diffusion or active region 4704B.

[0480] Reference again Figure 47A and Figure 47B , the arrangement of semiconductor structures or devices 4700A and 4700B respectively places the gate contact above the isolation region. Such an arrangement wastes layout space. However, placing the gate contact above the active area would require an extremely tight registration budget, or the gate size would have to be increased to provide a large enough space for the gate contact to land. In addition, historically, gate contacts above the diffusion region have been avoided because there is a risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address the above issues by providing a feasible way to make contact structures that contact the portion of the gate electrode formed above the diffusion or active region, and the resulting structure.

[0481] As an example, Figure 48A FIG2 shows a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Figure 48A, semiconductor structure or device 4800A includes a diffusion or active region 4804 disposed in substrate 4802 and within isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffusion or active region 4804 and over a portion of isolation region 4806. Source or drain contacts, such as contacts 4810A and 4810B, are disposed over the source and drain regions of semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contact to trench contacts 4810A and 4810B, respectively. A gate contact via 4816, without an intervening separate gate contact layer, provides contact to gate line 4808B. Figure 47A In contrast, from a plan view perspective, gate contact 4816 is disposed over diffusion or active region 4804 and between source or drain contacts 4810A and 4810B.

[0482] Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Figure 48B , semiconductor structure or device 4800B (e.g. Figure 48A 4800A) includes a non-planar diffusion or active region 4804B (e.g., a fin structure) formed from a substrate 4802 and within an isolation region 4806. A gate line 4808B is disposed over the non-planar diffusion or active region 4804B and over a portion of the isolation region 4806. As shown, the gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852, along with a dielectric cap layer 4854. Also visible from this perspective is a gate contact via 4816, along with an overlying metal interconnect 4860, both disposed in an interlayer dielectric stack or layer 4870. Figure 48B It is also seen from the perspective view that the gate contact via 4816 is disposed above the non-planar diffusion or active area 4804B.

[0483] So, refer again Figure 48A and Figure 48B In an embodiment, the trench contact vias 4812A, 4812B and the gate contact via 4816 are formed in the same layer and are substantially coplanar. Figure 47A and Figure 47B In contrast, the contact to the gate line would otherwise comprise an additional gate contact layer, which could, for example, extend perpendicularly to the corresponding gate line. Figure 48A and Figure 48BIn the described structures, structures 4800A and 4800B are fabricated so that contacts can land directly from the metal interconnect layer on the active gate portion without shorting to the adjacent source and drain regions. In an embodiment, such an arrangement provides a large area reduction in the circuit layout by eliminating the need to extend the transistor gate over the isolation region to form a reliable contact. As used throughout this document, in an embodiment, reference to the active portion of the gate refers to that portion of the gate line or structure that is disposed (from a plan view) above the active or diffusion region of the underlying substrate. In an embodiment, reference to the passive portion of the gate refers to that portion of the gate line or structure that is disposed (from a plan view) above the isolation region of the underlying substrate.

[0484] In an embodiment, semiconductor structure or device 4800 is a non-planar device, such as, but not limited to, a finFET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is formed by or in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 4808A-4808C surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, such as in a gate-all-around device, at least the channel region is fabricated as a discrete three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C each completely surround the channel region.

[0485] More generally, one or more embodiments relate to an approach for landing a gate contact via directly on an active transistor gate and a structure formed thereby. Such an approach can eliminate the need to extend a gate line over an isolation region for contact purposes. Such an approach can also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In an embodiment, the elimination of the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having different etching characteristics than the gate dielectric material cap layer already used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., GILA).

[0486] As an exemplary fabrication scheme, Figures 49A-49D Cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present disclosure.

[0487] refer to Figure 49A, a semiconductor structure 4900 is provided after the trench contacts (TCN) are formed. It should be appreciated that the specific arrangement of structure 4900 is used for illustrative purposes only, and a variety of possible layouts may benefit from embodiments of the disclosure described herein. The semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E disposed above a substrate 4902. The gate stack structure may include a gate dielectric layer and a gate electrode. Trench contacts, such as contacts to diffusion regions of the substrate 4902 (e.g., trench contacts 4910A-4910C), are also included in the structure 4900 and are separated from the gate stack structures 4908A-4908E by dielectric spacers 4920. An insulating cap layer 4922 may be disposed on the gate stack structures 4908A-4908E (e.g., GILA), also as Figure 49A As shown. Figure 49A As shown, contact barrier regions or "contact plugs" (eg, regions 4923 made of an interlayer dielectric material) may be included in the region where contact formation is to be blocked.

[0488] In an embodiment, providing structure 4900 involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of lithographic operations with super tight registration budgets. In one such embodiment, the approach enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching) to produce contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithographic operation. In one such embodiment, the approach enables the elimination of the need for lithographic operations (as used in other approaches) that would otherwise be critical to producing the contact pattern. In an embodiment, the trench contact grid is not patterned separately, but is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0489] In addition, the gate stack structures 4908A-4908E can be manufactured by a replacement gate process. In such an embodiment, the dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, as opposed to being performed from an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etch process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etch process including water-based NH4OH or tetraethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etch including water-based phosphoric acid.

[0490] In an embodiment, one or more of the methods described herein substantially contemplates dummy gate and replacement gate processes in conjunction with dummy and replacement contact processes to achieve structure 4900. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a specific such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than approximately 600 degrees Celsius, for example, after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0491] refer to Figure 49B , the trench contacts 4910A-4910C of the structure 4900 are recessed into the spacer 4920 to provide recessed trench contacts 4911A-4911C having a height lower than the top surface of the spacer 4920 and the insulating cap layer 4922. An insulating cap layer 4924 is then formed on the recessed trench contacts 4911A-4911C (e.g., TILA). According to an embodiment of the present disclosure, the insulating cap layer 4924 on the recessed trench contacts 4911A-4911C is composed of a material having different etching characteristics than the insulating cap layer 4922 on the gate stack structures 4908A-4908E. As will be seen in subsequent processing operations, such a difference can be exploited to selectively etch one of 4922 / 4924 relative to the other.

[0492] The trench contacts 4910A-4910C can be recessed by a process that is selective to the materials of the spacers 4920 and the insulating cap layer 4922. For example, in one embodiment, the trench contacts 4910A-4910C are recessed by an etching process, such as a wet etching process or a dry etching process. The insulating cap layer 4924 can be formed by a process suitable for providing a conformal and sealing layer over the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulating cap layer 4924 is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, such as by chemical mechanical polishing (CMP), to provide the insulating cap layer 4924 material only over the trench contacts 4910A-4910C and re-expose the spacers 4920 and the insulating cap layer 4922.

[0493] Regarding suitable material combinations for insulating cap layers 4922 / 4924, in one embodiment, one of the pairs 4922 / 4924 is composed of silicon oxide and the other is composed of silicon nitride. In another embodiment, one of the pairs 4922 / 4924 is composed of silicon oxide and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pairs 4922 / 4924 is composed of silicon oxide and the other is composed of silicon carbide. In another embodiment, one of the pairs 4922 / 4924 is composed of silicon nitride and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pairs 4922 / 4924 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pairs 4922 / 4924 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pairs 4922 / 4924 is composed of carbon-doped silicon nitride and the other is composed of silicon carbide.

[0494] refer to Figure 49C , an interlayer dielectric (ILD) 4930 and a hard mask 4932 stack are formed and patterned to provide, for example, Figure 49B Metal (0) trench 4934 is patterned above the structure.

[0495] The interlayer dielectric (ILD) 4930 can be composed of a material suitable for electrically isolating the metal features ultimately formed therein while maintaining a robust structure between front-end and back-end processing. Furthermore, in an embodiment, the composition of the ILD 4930 is selected to be consistent with the via etch selectivity for the trench contact dielectric cap patterning, as described below in conjunction with Figure 49DAs described in more detail. In one embodiment, ILD 4930 is composed of a single or a few layers of silicon oxide or a single or a few layers of carbon-doped oxide (CDO) material. However, in other embodiments, ILD 4930 has a dual-layer composition, with the top layer being composed of a different material than the underlying bottom portion of ILD 4930. Hard mask layer 4932 can be composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, hard mask layer 4932 is substantially composed of carbon, for example, as a cross-linked organic polymer layer. In other embodiments, silicon nitride or a carbon-doped silicon nitride layer is used as hard mask 4932. The stack of interlayer dielectric (ILD) 4930 and hard mask 4932 can be patterned by photolithography and etching processes.

[0496] refer to Figure 49D , a via opening 4936 (e.g., VCT) is formed in the interlayer dielectric (ILD) 4930 extending from the metal (0) trench 4934 to one or more of the recessed trench contacts 4911A-4911C. For example, in Figure 49D , a via opening is formed to expose the recessed trench contacts 4911A and 4911C. Forming the via opening 4936 includes etching both the interlayer dielectric (ILD) 4930 and corresponding portions of the insulating cap layer 4924. In one such embodiment, a portion of the insulating cap layer 4922 is exposed during patterning of the interlayer dielectric (ILD) 493 (e.g., a portion of the insulating cap layer 4922 above the gate stack structures 4908B and 4908E). In this embodiment, the insulating cap layer 4924 is etched to form the via opening 4936 selectively relative to the insulating cap layer 4922 (i.e., without significantly etching or affecting the insulating cap layer 4922).

[0497] In one embodiment, the via opening pattern is ultimately transferred to the insulating cap layer 4924 (i.e., the trench contact insulating cap layer) by an etching process without etching the insulating cap layer 4922 (i.e., the gate insulating cap layer). The insulating cap layer 4924 (TILA) can be composed of any of the following materials or a combination thereof: silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides and silicides, including zirconium oxide, hafnium oxide, lanthanum oxide, or a combination thereof. The layer can be deposited using any of the following techniques: CVD, ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD. The corresponding plasma dry etching has been developed as a combination of chemical and physical sputtering mechanisms. Conformal polymer deposition can be used to control material removal rate, etch profile, and film selectivity. The dry etch is typically produced using a mixture of gases including NF3, CHF3, C4F8, HBr, and O2, with typical pressures in the range of 30-100 mTorr and a plasma bias of 50-1000 W. The dry etch can be designed to achieve significant etch selectivity between the cap layer 4924 (TILA) and the 4922 (GILA) layer to minimize the loss of 4922 (GILA) during the dry etch of 4929 (TILA) to form contacts to the source / drain regions of the transistor.

[0498] Reference again Figure 49D , it is recognized that a similar approach can be implemented to manufacture a via opening pattern that is ultimately transferred to the insulating cap layer 4922 (i.e., the trench contact insulating cap layer) by an etching process without etching the insulating cap layer 4924 (i.e., the gate insulating cap layer).

[0499] To further illustrate the concept of Contact Over Active Gate (COAG) technology, Figure 50 A plan view and corresponding cross-sectional views of an integrated circuit structure having a trench contact including an overlying insulating cap layer according to an embodiment of the present disclosure are shown.

[0500] refer to Figure 50 , the integrated circuit structure 5000 includes a gate line 5004 over a semiconductor substrate or fin 5002, such as a silicon fin. The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating cap layer 5006 on the gate stack 5005. Dielectric spacers 5008 are along sidewalls of the gate stack 5005, and in an embodiment, along sidewalls of the gate insulating cap layer 5006, as shown.

[0501] The trench contacts 5010 are adjacent to the sidewalls of the gate lines 5004 with dielectric spacers 5008 therebetween. Each of the trench contacts 5010 includes a conductive contact structure 5011 and a trench contact insulating cap layer 5012 thereon.

[0502] Reference again Figure 50 , a gate contact via 5014 is formed in the opening of the gate insulating cap layer 5006 and electrically contacts the gate stack 5005. In an embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a location above the semiconductor substrate or fin 5002 and laterally between the trench contacts 5010, as shown. In one such embodiment, the trench contact insulating cap layer 5012 on the conductive contact structure 5011 prevents the gate contact via 5014 from shorting the gate to the source or the gate to the drain.

[0503] Reference again Figure 50 , trench contact vias 5016 are formed in openings of the trench contact insulating cap layer 5012 and electrically contact corresponding conductive contact structures 5011. In an embodiment, the trench contact vias 5016 electrically contact corresponding conductive contact structures 5011 at locations above the semiconductor substrate or fin 5002 and laterally adjacent to the gate stack 5005 of the gate line 5004, as shown. In one such embodiment, the gate insulating cap layer 5006 on the gate stack 5005 prevents the trench contact vias 5016 from shorting the source to the gate or the drain to the gate.

[0504] It will be appreciated that different structural relationships between the insulating gate cap layer and the insulating trench contact cap layer can be produced. As an example, Figures 51A-51F Cross-sectional views of various integrated circuit structures are shown, each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer, according to embodiments of the present disclosure.

[0505] refer to Figure 51A 、 Figure 51B and Figure 51C, integrated circuit structures 5100A, 5100B, and 5100C each include a fin 5102, such as a silicon fin. Although shown in cross-section, it is to be understood that the fin 5102 has a top 5102A and sidewalls (entering and exiting the page of the illustrated perspective view). First 5104 and second 5106 gate dielectric layers are above the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. First 5108 and second 5110 gate electrodes are above the first 5104 and second 5106 gate dielectric layers, respectively, above the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. The first 5108 and second 5110 gate electrodes each include a conformal conductive layer 5109A (e.g., a work function setting layer) and a conductive fill material 5109B above the conformal conductive layer 5109A. The first 5108 and second 5110 gate electrodes each have a first side 5112 and a second side 5114 opposite the first side 5112. The first 5108 and second 5110 gate electrodes each also have an insulating cap 5116 having a top surface 5118.

[0506] A first dielectric spacer 5120 is adjacent to a first side 5112 of the first gate electrode 5108. A second dielectric spacer 5122 is adjacent to a second side 5114 of the second gate electrode 5110. A semiconductor source or drain region 5124 is adjacent to the first 5120 and second 5122 dielectric spacers. A trench contact structure 5126 is over the semiconductor source or drain region 5124 adjacent to the first 5120 and second 5122 dielectric spacers.

[0507] The trench contact structure 5126 includes an insulating cap 5128 on the conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has a top surface 5129 that is substantially coplanar with the top surface 5118 of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes. In one embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into the recess 5132 in the first 5120 and second 5122 dielectric spacers. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 is suspended above the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recess 5132 in the first 5120 and second 5122 dielectric spacers and, therefore, does not overhang the conductive structure 5130 of the trench contact structure 5126.

[0508] It should be appreciated that the conductive structure 5130 of the trench contact structure 5126 may not be rectangular, such as Figures 51A-51C For example, the conductive structure 5130 of the trench contact structure 5126 may have Figure 51A A cross-sectional geometry similar or identical to the geometry shown for conductive structure 5130A as shown in the projection of .

[0509] In an embodiment, the insulating cap 5128 of the trench contact structure 5126 has a different composition than the insulating cap 5116 of the first 5108 and second 5110 gate electrodes. In one such embodiment, the insulating cap 5128 of the trench contact structure 5126 comprises a carbide material, such as a silicon carbide material. The insulating cap 5116 of the first 5108 and second 5110 gate electrodes comprises a nitride material, such as a silicon nitride material.

[0510] In an embodiment, the insulating caps 5116 of the first 5108 and second 5110 gate electrodes each have a bottom surface 5117A that is lower than the bottom surface 5128A of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG. Figure 51A In another embodiment, the insulating caps 5116 of the first 5108 and second 5110 gate electrodes each have a bottom surface 5117A that is substantially coplanar with the bottom surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG. Figure 51B In another embodiment, the insulating caps 5116 of the first 5108 and the second 5110 gate electrodes each have a bottom surface 5117C that is higher than the bottom surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG. Figure 51C shown.

[0511] In an embodiment, the conductive structure 5130 of the trench contact structure 5128 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 disposed entirely on and above the U-shaped metal layer 5134, and a third metal layer 5138 disposed on the T-shaped metal layer 5136. The insulating cap 5128 of the trench contact structure 5126 is disposed on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 include titanium, and the T-shaped metal layer 5136 includes cobalt. In a specific such embodiment, the T-shaped metal layer 5136 also includes carbon.

[0512] In an embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicide layer 5140 comprises titanium and silicon. In a specific such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 comprises nickel, platinum, and silicon. In a specific such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In another specific such embodiment, the metal silicide layer further comprises germanium.

[0513] In the examples, reference Figure 51D , the conductive via 5150 is over and electrically connected to a portion of the first gate electrode 5108 that is above the top 5102A of the fin 5102. The conductive via 5150 is in an opening 5152 in the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is over a portion of the insulating cap 5128 of the trench contact structure 5126 but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a specific such embodiment, the conductive via 5150 is in an etched portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0514] In the examples, reference Figure 51E , the conductive via 5160 is over and electrically connected to a portion of the trench contact structure 5126. The conductive via is in an opening 5162 of the insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is over a portion of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes, but is not electrically connected to the first 5108 and second 5110 gate electrodes. In a particular such embodiment, the conductive via 5160 is in an etched portion 5164 of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes.

[0515] Reference again Figure 51E In an embodiment, the conductive via 5160 is Figure 51D The conductive via 5150 has a second conductive via of the same structure. In one such embodiment, such second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, such second conductive via 5160 is fused with the conductive via 5150 to form an electrical shorting contact 5170, as shown in FIG. Figure 51F shown.

[0516] The methods and structures described herein can enable the formation of other structures or devices that are impossible or difficult to manufacture using other methods. In a first example, Figure 52A FIG2 shows a plan view of another semiconductor device having a gate contact via disposed above an active portion of a gate according to another embodiment of the present disclosure. Figure 52A, a semiconductor structure or device 5200 includes a plurality of gate structures 5208A-5208C interdigitated with a plurality of trench contacts 5210A and 5210B (these features are disposed above an active region of a substrate, not shown). A gate contact via 5280 is formed over the active portion of gate structure 5208B. Gate contact via 5280 is also disposed over the active portion of gate structure 5208C, coupling gate structures 5208B and 5208C. It should be appreciated that a trench contact isolation cap layer (e.g., TILA) may be used to isolate the intervening trench contacts 5210B from the contacts 5280. Figure 52A The contact configuration may provide an easier way to bundle adjacent gate lines in a layout without routing the bundled lines through upper layers of metallization, thereby enabling a smaller cell area or a less complex wiring scheme, or both.

[0517] In the second example, Figure 52B FIG2 shows a plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts according to another embodiment of the present disclosure. Figure 52B , a semiconductor structure or device 5250 includes a plurality of gate structures 5258A-5258C interdigitated with a plurality of trench contacts 5260A and 5260B (these features are disposed above an active region of the substrate, not shown). Trench contact vias 5290 are formed on trench contacts 5260A. Trench contact vias 5290 are also disposed on trench contacts 5260B, coupling trench contacts 5260A and 5260B. It should be appreciated that a gate isolation cap layer (e.g., by a GILA process) can be used to isolate the intervening gate structures 5258B from the trench contact vias 5290. Figure 52B The contact configuration may provide an easier way to bundle adjacent trench contacts in a layout without routing the bundle wires through upper layers of metallization, thereby enabling a smaller cell area or a less complex wiring scheme, or both.

[0518] The insulating cap layer for the gate electrode may be manufactured using several deposition operations and, as a result, may include artifacts of the multiple deposition manufacturing process. Figures 53A-53E Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including a gate stack with an overlying insulating cap layer are illustrated in accordance with an embodiment of the present disclosure.

[0519] refer to Figure 53A, starting structure 5300 includes a gate stack 5304 above a substrate or fin 5302. Gate stack 5304 includes a gate dielectric layer 5306, a conformal conductive layer 5308, and a conductive fill material 5310. In an embodiment, gate dielectric layer 5306 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer is a work function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxide layer 5312, such as a thermal or chemical silicon dioxide or silicon oxide layer, is between substrate or fin 5302 and gate dielectric layer 5306. Dielectric spacers 5314, such as silicon nitride spacers, are adjacent to sidewalls of gate stack 5304. Dielectric gate stack 5304 and dielectric spacers 5314 are contained within an interlayer dielectric (ILD) layer 5316. In an embodiment, gate stack 5304 is formed using a replacement gate and replacement gate dielectric processing scheme. A mask 5318 is patterned over the gate stack 5304 and the ILD layer 5316 to provide an opening 5320 exposing the gate stack 5304 .

[0520] refer to Figure 53B The gate stack 5304, including the gate dielectric layer 5306, the conformal conductive layer 5308, and the conductive fill material 5310, is recessed relative to the dielectric spacer 5314 and the layer 5316 using one or more selective etching processes. The mask 5318 is then removed. The recessing provides a cavity 5322 above the recessed gate stack 5324.

[0521] In another embodiment not shown, the conformal conductive layer 5308 and the conductive fill material 5310 are recessed relative to the dielectric spacer 5314 and layer 5316, but the gate dielectric layer 5306 is not recessed or is only minimally recessed. It should be appreciated that in other embodiments, a maskless approach based on a high etch selectivity is used for recessing.

[0522] refer to Figure 53C , performing the first deposition process in multiple deposition processes for manufacturing the gate insulating cap layer. The first deposition process is used to form Figure 53B The first insulating layer 5326 is conformal to the structure of the gate stack 5324. In one embodiment, the first insulating layer 5326 includes silicon and nitrogen. For example, the first insulating layer 5326 is a silicon nitride (Si3N4) layer, a silicon-rich silicon nitride layer, a silicon-poor silicon nitride layer, or a carbon-doped silicon nitride layer. In one embodiment, the first insulating layer 5326 only partially fills the cavity 5322 above the recessed gate stack 5324, as shown.

[0523] refer to Figure 53DThe first insulating layer 5326 is subjected to a deep etching process, such as an anisotropic etching process, to provide a first portion 5328 of the insulating cap layer. The first portion 5328 of the insulating cap layer only partially fills the cavity 5322 above the recessed gate stack 5324.

[0524] refer to Figure 53E , ad...

Claims

1. An integrated circuit structure comprising: a fin comprising silicon, the fin having a lower fin portion and an upper fin portion; an insulating structure directly adjacent a sidewall of the lower fin portion of the fin; a first gate electrode over the upper fin portion and over the first portion of the insulating structure; a second gate electrode over the upper fin portion and over the second portion of the insulating structure; a first dielectric spacer along sidewalls of the first gate electrode; as well as a second dielectric spacer along a sidewall of the second gate electrode, the second dielectric spacer being continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode; Wherein, a portion of the combination of the first dielectric spacer and the second dielectric spacer is conformal to the non-planar uppermost surface of the third portion of the insulating structure.

2. The integrated circuit structure according to claim 1, wherein: The first dielectric spacer and the second dielectric spacer include silicon and nitrogen.

3. The integrated circuit structure according to claim 1 , further comprising: Embedded source or drain structures are on opposite sides of the first gate electrode and on opposite sides of the second gate electrode.

4. The integrated circuit structure according to claim 1, wherein: The insulating structure includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filling material directly laterally (directly laterally) on the second insulating layer.

5. The integrated circuit structure according to claim 4, wherein: The first insulating layer is a non-doped insulating layer including nitrogen and oxygen.

6. The integrated circuit structure according to claim 4, wherein: The second insulating layer includes silicon and nitrogen.

7. The integrated circuit structure according to claim 4, wherein: The dielectric fill material includes silicon and oxygen.

8. An integrated circuit structure comprising: a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion; a second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion; an insulating structure directly adjacent to a sidewall of a lower fin portion of the first fin and directly adjacent to a sidewall of a lower fin portion of the second fin; a gate electrode over an upper fin portion of the first fin, over an upper fin portion of the second fin, and over a first portion of the insulating structure; a first dielectric spacer along sidewalls of an upper fin portion of the first fin; as well as a second dielectric spacer along sidewalls of an upper fin portion of the second fin, the second dielectric spacer being continuous with the first dielectric spacer over a second portion of the insulating structure between the first fin and the second fin, Wherein, a portion of the combination of the first dielectric spacer and the second dielectric spacer conforms to a non-planar uppermost surface of the second portion of the insulating structure.

9. The integrated circuit structure according to claim 8, wherein: The first dielectric spacer and the second dielectric spacer include silicon and nitrogen.

10. The integrated circuit structure according to claim 8, further comprising: An embedded source or drain structure on an opposite side of the gate electrode, the embedded source or drain structure having a bottom surface along sidewalls of an upper fin portion of the first fin and the second fin and lower than a top surface of the first dielectric spacer and the second dielectric spacer, and the embedded source or drain structure having a top surface along sidewalls of an upper fin portion of the first fin and the second fin and higher than a top surface of the first dielectric spacer and the second dielectric spacer.

11. The integrated circuit structure according to claim 8, wherein: The insulating structure includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filling material directly laterally (directly laterally) on the second insulating layer.

12. The integrated circuit structure according to claim 11, wherein: The first insulating layer is a non-doped insulating layer including nitrogen and oxygen.

13. The integrated circuit structure according to claim 11, wherein: The second insulating layer includes silicon and nitrogen.

14. The integrated circuit structure according to claim 11, wherein: The dielectric fill material includes silicon and oxygen.

15. A method of manufacturing an integrated circuit structure, the method comprising: forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion; forming an insulating structure directly adjacent to a sidewall of the lower fin portion of the fin; forming a first gate structure and a second gate structure over the upper fin portion and over the first and second portions of the insulating structure, respectively; forming a dielectric material conformal to the upper fin portion of the fin, to the first gate structure and the second gate structure, and to a third portion of the insulating structure between the first gate structure and the second gate structure; forming a hard mask material over the dielectric material; recessing the hard mask material to expose a portion of the dielectric material that is conformal with the upper fin portion of the fin and conformal with the first gate structure and the second gate structure, the recessed hard mask material covering a portion of the dielectric material that is conformal with the third portion of the insulating structure between the first gate structure and the second gate structure; as well as anisotropically etching the dielectric material and subsequently removing the recessed hard mask material to form a first dielectric spacer along a sidewall of the first gate structure and a second dielectric spacer along a sidewall of the second gate structure, the second dielectric spacer being continuous with the first dielectric spacer over the third portion of the insulating structure between the first and second gate structures, Wherein, a portion of the combination of the first dielectric spacer and the second dielectric spacer is conformal to the non-planar uppermost surface of the third portion of the insulating structure.

16. The method according to claim 15, wherein Recessing the hard mask material includes wet etching the hard mask material.

17. The method according to claim 15, wherein: Recessing the hard mask material includes using an ashing, dry etching, or plasma etching process.

18. The method according to claim 15, wherein Forming the hard mask material includes forming a carbon-based hard mask material.

19. The method according to claim 15, wherein The first gate structure and the second gate structure are dummy gate structures, and the method further includes: The first gate structure and the second gate structure are replaced with a permanent gate dielectric and a gate electrode stack.

20. The method of claim 15, further comprising: Embedded source or drain structures are formed on opposite sides of the first gate structure and on opposite sides of the second gate structure.

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