Pitch division interconnects for advanced integrated circuit fabric manufacture

Abstract

Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and in particular, in the field of 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent to the first interconnect line and having a width different from a width of the first interconnect line. A third interconnect line is immediately adjacent to the second interconnect line. A fourth interconnect line is immediately adjacent to the third interconnect line and has a width that is the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent to the fourth interconnect line and has a width that is the same as the width of the first interconnect line.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed November 30, 2017, entitled “Advanced Integrated Circuit Structure Fabrication,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure are in the field of advanced integrated circuit structure manufacturing, and more specifically, in the field of 10-nanometer node and smaller integrated circuit structure manufacturing and the resulting structures. Background Technology

[0004] For decades, feature scaling in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling to increasingly smaller features allows for greater density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of a larger number of memory or logic devices onto a single chip, resulting in the manufacture of products with greater capacity. However, this drive for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device has become increasingly important.

[0005] Variations in conventional and currently known manufacturing processes may limit their potential for further expansion to the 10-nanometer or sub-10-nanometer node range. Therefore, manufacturing the functional components required for future technology nodes may require introducing new methods or integrating new technologies into current manufacturing processes, or replacing existing processes altogether. Attached Figure Description

[0006] Figure 1A A cross-sectional view of the initial structure is shown after the deposition of a hard mask material layer formed on the interlayer dielectric (ILD) layer, but before its patterning.

[0007] Figure 1B This shows the patterning of the hard mask layer by halving the spacing. Figure 1A A cross-sectional view of the structure.

[0008] Figure 2A This is a schematic diagram of a four-part spacing arrangement for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0009] Figure 2B A cross-sectional view of a semiconductor fin manufactured using a pitched quartering method according to an embodiment of the present disclosure is shown.

[0010] Figure 3AThis is a schematic diagram of a fused fin spacing quadrant for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0011] Figure 3B A cross-sectional view of a semiconductor fin manufactured using a fused fin pitch quartering method according to an embodiment of the present disclosure is shown.

[0012] Figures 4A-4C Cross-sectional views illustrating various operations in a method of manufacturing a plurality of semiconductor fins according to embodiments of the present disclosure are shown.

[0013] Figure 5A A cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure according to an embodiment of the present disclosure is shown.

[0014] Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure is shown.

[0015] Figures 6A-6D Cross-sectional views are shown of various operations in manufacturing a three-layer trench isolation structure according to embodiments of the present disclosure.

[0016] Figures 7A-7E An oblique three-dimensional cross-sectional view is shown of various operations in a method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure.

[0017] Figures 8A-8F The diagram illustrates various operations along the path of a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure. Figure 7E A slightly projected cross section taken along the a-a' axis.

[0018] Figure 9A The following diagram illustrates an integrated circuit structure comprising a permanent gate stack and an epitaxial source or drain region, according to embodiments of the present disclosure. Figure 7E A slightly projected cross section taken along the a-a' axis.

[0019] Figure 9B This illustration shows an integrated circuit structure including epitaxial source or drain regions and multilayer trench isolation structures according to embodiments of the present disclosure. Figure 7E The cross-sectional view taken along the b-b' axis.

[0020] Figure 10 A cross-sectional view of an integrated circuit structure taken at the source or drain position according to an embodiment of the present disclosure is shown.

[0021] Figure 11 A cross-sectional view of another integrated circuit structure taken at the source or drain location according to an embodiment of the present disclosure is shown.

[0022] Figures 12A-12D Cross-sectional views are shown of various operations in a method of manufacturing an integrated circuit structure, taken at the source or drain location according to embodiments of the present disclosure.

[0023] Figure 13A and Figure 13B A plan view illustrating various operations in a method for patterning a fin with multiple gate spacings for forming a local isolation structure, according to embodiments of the present disclosure, is shown.

[0024] Figures 14A-14D A plan view is shown illustrating various operations in a method for patterning fins with single-gate spacing for forming a local isolation structure, according to another embodiment of the present disclosure.

[0025] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multiple gate spacings for local isolation, according to an embodiment of the present disclosure, is shown.

[0026] Figure 16A A cross-sectional view of an integrated circuit structure with fins for local isolation is shown according to another embodiment of the present disclosure.

[0027] Figure 16B A cross-sectional view is shown, illustrating an embodiment of the present disclosure, in which a fin isolation structure can be formed to replace the position of the gate electrode.

[0028] Figures 17A-17C Various depth possibilities for fin cuts manufactured using a fin trimming isolation method are shown according to embodiments of the present disclosure.

[0029] Figure 18 Plan view and corresponding cross-sectional view taken along the a-a' axis are shown, illustrating possible options for comparing the depth of a local location of a fin cut within the fin with the depth of a wider location, according to embodiments of the present disclosure.

[0030] Figure 19A and Figure 19B Cross-sectional views are shown of various operations in a method for selecting the location of a stress source at the end of a fin having a wide cut, according to embodiments of the present disclosure.

[0031] Figure 20A and Figure 20B Cross-sectional views are shown of various operations in a method for selecting the location of a fin end stress source at the end of a fin with a partial cut, according to embodiments of the present disclosure.

[0032] Figures 21A-21MCross-sectional views are shown of various operations in a method for manufacturing an integrated circuit structure with differentiated fin-end dielectric plugs according to embodiments of the present disclosure.

[0033] Figures 22A-22D A cross-sectional view of an exemplary structure of a PMOS fin end stress source dielectric plug according to an embodiment of the present disclosure is shown.

[0034] Figure 23A A cross-sectional view of another semiconductor structure having fin-end stress-induced features is shown according to another embodiment of the present disclosure.

[0035] Figure 23B A cross-sectional view of another semiconductor structure having fin-end stress-induced features is shown according to another embodiment of the present disclosure.

[0036] Figure 24A An oblique view of a fin having uniaxial tensile stress according to an embodiment of the present disclosure is shown.

[0037] Figure 24B An oblique view of a fin having uniaxial compressive stress according to an embodiment of the present disclosure is shown.

[0038] Figure 25A and Figure 25B The diagram shows plan views illustrating various operations in a method for patterning a fin with a single gate spacing to form a local isolation structure at a selected gate line cut-out location, according to embodiments of the present disclosure.

[0039] Figures 26A-26C The embodiments of the present disclosure are shown for... Figure 25B Cross-sectional views of various possibilities for dielectric plugs in different regions of the structure for multi-cut and fin trim isolation (FTI) local fin cut locations and multi-cut locations only.

[0040] Figure 27A Plan view and corresponding cross-sectional view of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer body according to an embodiment of the present disclosure are shown.

[0041] Figure 27B A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cutout with a dielectric plug extending beyond the dielectric spacer of the gate line, according to another embodiment of the present disclosure, are shown.

[0042] Figures 28A-28FCross-sectional views of various operations in a method of manufacturing an integrated circuit structure having a gate line cutout with a dielectric plug according to another embodiment of the present disclosure are shown, the dielectric plug having an upper portion extending outside the dielectric spacer of the gate line and a lower portion extending into the gate line dielectric spacer.

[0043] Figures 29A-29C A plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to an embodiment of the present disclosure, are shown.

[0044] Figures 30A-30D Cross-sectional views are shown of various operations in a method for manufacturing an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to another embodiment of the present disclosure.

[0045] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is shown.

[0046] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is shown.

[0047] Figure 32A A plan view of a plurality of gate lines situated above a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0048] Figure 32B The following is illustrated according to an embodiment of the present disclosure. Figure 32A A cross-sectional view taken along the a-a' axis.

[0049] Figure 33A Cross-sectional views of an NMOS device pair and a PMOS device pair according to embodiments of the present disclosure are shown, the NMOS device pair having a differentiated voltage threshold based on modulated doping, and the PMOS device pair having a differentiated voltage threshold based on modulated doping.

[0050] Figure 33B Cross-sectional views of an NMOS device pair and a PMOS device pair according to another embodiment of the present disclosure are shown. The NMOS device pair has a differentiated voltage threshold based on a differentiated gate electrode structure, and the PMOS device pair has a differentiated voltage threshold based on a differentiated gate electrode structure.

[0051] Figure 34ACross-sectional views of three NMOS devices and three PMOS devices according to embodiments of the present disclosure are shown. The three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0052] Figure 34B Cross-sectional views of three NMOS devices and three PMOS devices according to another embodiment of the present disclosure are shown. The three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0053] Figures 35A-35D Cross-sectional views are shown of various operations in a method for manufacturing an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to embodiments of the present disclosure.

[0054] Figures 36A-36D Cross-sectional views are shown of various operations in a method for manufacturing a PMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to embodiments of the present disclosure.

[0055] Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is shown.

[0056] Figures 38A-38H Cross-sectional views are shown of various operations in a method for fabricating an integrated circuit structure using a dual-metal gate replacement gate process flow according to embodiments of the present disclosure.

[0057] Figures 39A-39H Cross-sectional views are shown illustrating various operations in a method for manufacturing a dual-silicide-based integrated circuit according to embodiments of the present disclosure.

[0058] Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to an embodiment of the present disclosure is shown.

[0059] Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device is shown according to another embodiment of the present disclosure.

[0060] Figure 41A A cross-sectional view of a semiconductor device having conductive contacts on the source or drain region according to an embodiment of the present disclosure is shown.

[0061] Figure 41BA cross-sectional view of another semiconductor device having conductive contacts on a raised source or drain region according to an embodiment of the present disclosure is shown.

[0062] Figure 42 A plan view of a plurality of gate lines situated above a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0063] Figures 43A-43C The diagram illustrates various operations along the path of a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure. Figure 42 A cross-sectional view taken along the a-a' axis.

[0064] Figure 44 The following diagram illustrates the edge of an integrated circuit structure according to an embodiment of the present disclosure. Figure 42 The cross-sectional view taken along the b-b' axis.

[0065] Figure 45A and Figure 45B Plan view and corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to embodiments of the present disclosure, are shown respectively.

[0066] Figures 46A-46D Cross-sectional views are shown of various operations in a method of manufacturing an integrated circuit structure including trench contact plugs having hard mask material thereon, according to embodiments of the present disclosure.

[0067] Figure 47A A plan view of a semiconductor device having a gate contact disposed on the non-active portion of the gate electrode is shown. Figure 47B A cross-sectional view of a nonplanar semiconductor device having a gate contact disposed on the non-active portion of the gate electrode is shown.

[0068] Figure 48A A plan view of a semiconductor device having a gate contact via disposed on an active portion of a gate electrode, according to an embodiment of the present disclosure, is shown. Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on an active portion of a gate electrode, according to an embodiment of the present disclosure, is shown.

[0069] Figures 49A-49D Cross-sectional views are shown illustrating various operations in a method of manufacturing a semiconductor structure having a gate contact structure disposed on an active portion of the gate, according to embodiments of the present disclosure.

[0070] Figure 50 Plan view and corresponding cross-sectional view of an integrated circuit structure having a trench contact portion including an overlying insulating cap layer according to an embodiment of the present disclosure are shown.

[0071] Figures 51A-51F Cross-sectional views of various integrated circuit structures according to embodiments of the present disclosure are shown, each integrated circuit structure having a trench contact including an overlying insulating cap and a gate stack including an overlying insulating cap.

[0072] Figure 52A A plan view of another semiconductor device having a gate contact via disposed on an active portion of the gate, according to another embodiment of the present disclosure, is shown.

[0073] Figure 52B A plan view of another semiconductor device having a trench contact via that couples trench contacts according to another embodiment of the present disclosure is shown.

[0074] Figures 53A-53E Cross-sectional views are shown illustrating various operations in a method of manufacturing an integrated circuit structure with a gate stack having an overlying insulating cap layer, according to embodiments of the present disclosure.

[0075] Figure 54 This is a schematic diagram of the four-way spacing of trenches for manufacturing interconnect structures according to an embodiment of the present disclosure.

[0076] Figure 55A A cross-sectional view of a metallization layer manufactured using a pitched quartering scheme according to an embodiment of the present disclosure is shown.

[0077] Figure 55B A cross-sectional view is shown above a metallization layer manufactured using a pitch reduction scheme, which is above a metallization layer manufactured using a pitch quartering scheme, according to an embodiment of the present disclosure.

[0078] Figure 56A A cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is shown, in which a metallization layer having one metal line composition is situated above a metallization layer having a different metal line composition.

[0079] Figure 56B A cross-sectional view is shown of an integrated circuit structure according to an embodiment of the present disclosure, wherein a metallization layer having one metal line composition is coupled to a metallization layer having a different metal line composition.

[0080] Figures 57A-57C Cross-sectional views of individual interconnects with various liner and conductive cap arrangements according to embodiments of the present disclosure are shown.

[0081] Figure 58 A cross-sectional view of an integrated circuit structure, according to an embodiment of the present disclosure, is shown, in which four metallization layers having one metal line composition and spacing are positioned above two metallization layers having different metal line compositions and smaller spacing.

[0082] Figures 59A-59D Cross-sectional views of various interconnect and via arrangements having a bottom conductive layer according to embodiments of the present disclosure are shown.

[0083] Figures 60A-60D A cross-sectional view is shown of a structural arrangement of recessed line morphology for a BEOL metallization layer according to an embodiment of the present disclosure.

[0084] Figures 61A-61D A cross-sectional view of a structural arrangement for a stepped-line morphology of a BEOL metallization layer according to an embodiment of the present disclosure is shown.

[0085] Figure 62A Plan view and corresponding cross-sectional view taken along the a-a' axis of a plan view of the metallization layer according to an embodiment of the present disclosure are shown.

[0086] Figure 62B A cross-sectional view of a wire end or plug according to an embodiment of the present disclosure is shown.

[0087] Figure 62C Another cross-sectional view of a wire end or plug according to an embodiment of the present disclosure is shown.

[0088] Figures 63A-63F Plan views and corresponding cross-sectional views representing various operations in the final processing scheme of the plug according to embodiments of the present disclosure are shown.

[0089] Figure 64A A cross-sectional view of a conductive wire plug having a seam, according to an embodiment of the present disclosure, is shown.

[0090] Figure 64B A cross-sectional view of a stack of metallization layers including conductive wire plugs at the lower metal wire location is shown according to an embodiment of the present disclosure.

[0091] Figure 65 A first view of the cell layout for memory cells is shown.

[0092] Figure 66 A first view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0093] Figure 67 A second view showing the cell layout of the memory cells is shown.

[0094] Figure 68 A second view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0095] Figure 69 A third view of the cell layout for the memory cells is shown.

[0096] Figure 70 A third view is shown of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure.

[0097] Figure 71A and Figure 71B Bit cell layouts and schematic diagrams for a six-transistor (6T) static random access memory (SRAM) according to embodiments of the present disclosure are shown respectively.

[0098] Figure 72 Cross-sectional views of two different layouts for the same standard cell according to embodiments of the present disclosure are shown.

[0099] Figure 73 A plan view of four different unit arrangements specified by an even (E) or odd (O) indicator according to embodiments of the present disclosure is shown.

[0100] Figure 74 A plan view of a block-level multigrid according to an embodiment of the present disclosure is shown.

[0101] Figure 75 An exemplary acceptable (through) layout based on standard units with different versions is shown according to embodiments of this disclosure.

[0102] Figure 76 An exemplary unacceptable (failure) layout based on standard units with different versions is shown according to embodiments of this disclosure.

[0103] Figure 77 Another exemplary acceptable (through) layout based on a standard unit with a different version is shown according to an embodiment of this disclosure.

[0104] Figure 78 Partially cut plan view and corresponding cross-sectional view of a fin-based thin-film resistor structure according to an embodiment of the present disclosure are shown, wherein the cross-sectional view is cut along the a-a' axis of the partially cut plan view.

[0105] Figures 79-83 Plan views and corresponding cross-sectional views are shown representing various operations in a method for manufacturing a fin-based thin-film resistor structure according to embodiments of the present disclosure.

[0106] Figure 84 A plan view of a fin-based thin-film resistor structure having various exemplary positions for anode or cathode electrode contacts according to embodiments of the present disclosure is shown.

[0107] Figures 85A-85DA plan view of various fin geometries for manufacturing fin-based precision resistors according to embodiments of the present disclosure is shown.

[0108] Figure 86 A cross-sectional view of a photolithographic mask structure according to an embodiment of the present disclosure is shown.

[0109] Figure 87 A computing device according to one embodiment of the present disclosure is shown.

[0110] Figure 88 An interpolator including one or more embodiments of the present disclosure is shown.

[0111] Figure 89 This is an isometric view of a mobile computing platform according to an embodiment of the present disclosure, which employs an IC manufactured according to one or more processes described herein or includes one or more features described herein.

[0112] Figure 90 A cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure is shown. Detailed Implementation

[0113] The fabrication of advanced integrated circuit structures is described. Numerous specific details, such as specific integration and material systems, are set forth in the following description to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail to avoid unnecessarily obscuring embodiments of this disclosure. Furthermore, it should be recognized that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

[0114] The following detailed descriptions are merely illustrative in nature and are not intended to limit the scope of the subject matter or the application and use of such embodiments. As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary should not be construed as being preferred or advantageous over other implementations. Furthermore, it is not intended to be limited by any express or implied theory presented in the foregoing technical field, background art, summary of the invention, or the following detailed descriptions.

[0115] This specification includes references to "one embodiment" or "embodiment". The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0116] Terminology. The following paragraphs provide definitions or contexts for terms found in this disclosure (including the appended claims):

[0117] "Comprising". This term is open-ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0118] "Configured to". Various units or components can be described or claimed to be "configured to" perform one or more tasks. In this context, "configured to" is used to imply a structure by indicating that the unit or component includes a structure that performs one or more of those tasks during operation. Thus, even when the specified unit or component is not currently in operation (e.g., not turned on or active), it can be said that the unit or component is configured to perform a task. The detailed description of a unit or circuit or component being "configured to" perform one or more tasks is explicitly intended not to invoke 35 USC § 112, paragraph 6 for that unit or component.

[0119] "First," "second," etc. As used in this article, these terms serve as markers for the nouns that follow them and do not imply any kind of order (e.g., spatial, temporal, logical, etc.).

[0120] "Coupled" – as described below, means elements, nodes, or features that are "coupled" together. As used herein, unless otherwise explicitly stated, "coupled" means that one element, node, or feature is directly or indirectly connected to (or communicates with) another element, node, or feature (or directly or indirectly communicates with it), and not necessarily in a mechanical way.

[0121] Furthermore, certain terms used in the following description are for reference only and are not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to directions provided for reference in the accompanying drawings. Terms such as “front,” “back,” “rear,” “side,” “outer,” and “inner” describe the orientation or position, or both, of a part of a component within a consistent but arbitrary frame of reference, which can be clearly understood by referring to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0122] "Suppression"—as used in this application—is used to describe reducing or minimizing an effect. When a component or feature is described as suppressing a behavior, movement, or condition, it can completely prevent the result or consequence or future state. Additionally, "suppression" can also refer to reducing or diminishing a consequence, performance, or effect that might occur under other circumstances. Therefore, when a component, element, or feature is described as suppressing a result or state, it does not necessarily completely prevent or eliminate said result or state.

[0123] The embodiments described herein may relate to front-end process (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any lines).

[0124] The embodiments described herein may relate to back-end process (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using lines on a wafer, such as one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0125] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although exemplary processing schemes can be illustrated using the FEOL processing scenario, such methods can also be applied to BEOL processing. Similarly, although exemplary processing schemes can be illustrated using the BEOL processing scenario, such methods can also be applied to FEOL processing.

[0126] Spacing division and patterning schemes can be implemented to achieve the embodiments described herein, or can be included as part of the embodiments described herein. Spacing division patterning typically refers to halving the spacing, quartering the spacing, etc. Spacing division schemes can be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, photolithography is first performed to print unidirectional lines (e.g., strictly unidirectional or predominantly unidirectional) with predefined spacing. Then, spacing division processing is performed as a technique to increase line density.

[0127] In embodiments, the term "grid structure" used for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a closely spaced grid structure. In one such embodiment, the close spacing cannot be directly achieved by a selected lithography. For example, a pattern based on a selected lithography may be formed first, but the spacing may be halved using spacer mask patterning, as is known in the art. Furthermore, the initial spacing may be quartered by a second round of spacer mask patterning. Thus, the grid-like pattern described herein may have metal lines, ILD lines, or hard mask lines spaced at a generally consistent spacing and having a generally consistent width. For example, in some embodiments, the spacing variation is within 10 percent, and the width variation is within 10 percent; and in some embodiments, the spacing variation is within 5 percent, and the width variation is within 5 percent. Patterns can be fabricated by halving the spacing, quartering the spacing, or other spacing divisions. In embodiments, the grid is not necessarily a single spacing.

[0128] In the first example, the spacing can be halved to double the line density of the manufactured grid structure. Figure 1A A cross-sectional view of the initial structure is shown after the deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer, but before its patterning. Figure 1B This shows the patterning of the hard mask layer by halving the spacing. Figure 1A A cross-sectional view of the structure.

[0129] refer to Figure 1A The initial structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102. A patterned mask 106 is disposed above the hard mask material layer 104. The patterned mask 106 has spacers 108 formed on the sidewalls of the hard mask material layer 104 along its feature lines.

[0130] refer to Figure 1B The hard mask material layer 104 is patterned using a halving-pitch method. Specifically, the patterned mask 106 is first removed. The resulting spacer 108 pattern has either doubled the density of the mask 106 or halved the pitch or features of the mask 106. For example, the pattern of the spacer 108 is transferred to the hard mask material layer 104 by an etching process to form a patterned hard mask 110, as shown in FIG1B. In one such embodiment, the patterned hard mask 110 is formed with a grid pattern having unidirectional lines. The grid pattern of the patterned hard mask 110 can be a closely pitched grid pattern. For example, a closely pitched pattern may not be directly achievable using a selected photolithography technique. Furthermore, although not shown, the initial pitch can be quartered by a second round of spacer mask patterning. Therefore, Figure 1BThe grid pattern of the patterned hard mask 110 can have hard mask lines spaced apart from each other at a constant pitch and having a constant width. The achieved size can be much smaller than the critical size of the photolithography technique used.

[0131] Therefore, for front-end process (FEOL) or back-end process (BEOL) or both, the uniform thickness film can be patterned using photolithography and etching processes. This can involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It should be recognized that other pitch division methods can also be implemented. In any case, in the embodiments, the mesh layout can be fabricated using a selected photolithography method (e.g., 193nm immersion lithography (193i)). Pitch division can be implemented to increase the line density in the mesh layout by a factor of n. The formation of a mesh layout using 193i lithography plus a pitch division of "n" times can be specified as 193i+P / n pitch division. In one such embodiment, 193nm immersion scaling can utilize cost-effective pitch division for many generations.

[0132] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to shrink. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0133] However, scaling multi-gate transistors has not been without consequences. As the size of these fundamental building blocks of microelectronic circuits decreases and as the absolute number of fundamental building blocks manufactured in a given area increases, the constraints on the semiconductor processes used to manufacture these building blocks have become overwhelming.

[0134] According to one or more embodiments of this disclosure, a spacing quadrating method is implemented for patterning a semiconductor layer to form semiconductor fins. In one or more embodiments, a fused fin spacing quadrating method is implemented.

[0135] Figure 2A This is a schematic diagram of a spacing quartering method 200 for manufacturing semiconductor fins according to an embodiment of the present disclosure. Figure 2B A cross-sectional view of a semiconductor fin manufactured using a pitched quartering method according to an embodiment of the present disclosure is shown.

[0136] refer to Figure 2AIn operation (a), a photoresist layer (PR) is patterned to form a photoresist feature 202. The photoresist feature 202 can be patterned using standard photolithography techniques such as 193 immersion lithography. In operation (b), a material layer, such as an insulating layer or a dielectric hard mask layer, is patterned using the photoresist feature 202 to form a first backbone (BB1) feature 204. A first spacer (SP1) feature 206 is then formed adjacent to the sidewalls of the first backbone feature 204. In operation (c), the first backbone feature 204 is removed to leave only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206', as shown below. Figure 2A As shown. Depending on the required spacing and size of the BB2 feature (208, described below), this thinning can be performed (as shown) before or after the removal of BB1 (feature 204). In operation (d), the first spacer feature 206 or the thinned first spacer feature 206' is used to pattern a material layer, such as an insulating layer or a dielectric hard mask layer, to form the second backbone (BB2) feature 208. A second spacer (SP2) feature 210 is then formed adjacent to the sidewalls of the second backbone feature 208. In operation (e), the second backbone feature 208 is removed to leave only the second spacer feature 210. The remaining second spacer feature 210 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a spacing of quarters relative to the initially patterned photoresist feature 202. As an example, refer to Figure 2B The second spacer feature 210 is used as a mask for patterning (e.g., dry or plasma etching patterning) to form a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer. Figure 2B In the example, all of the multiple semiconductor fins 250 have substantially the same spacing and interval.

[0137] It should be recognized that the spacing between the initial patterned photoresist features can be modified to change the structural outcome of the spacing quadrant process. In the example, Figure 3A This is a schematic diagram of a fused fin spacing quartering 300 for manufacturing semiconductor fins according to an embodiment of the present disclosure. Figure 3B A cross-sectional view of a semiconductor fin manufactured using a fused fin pitch quartering method according to an embodiment of the present disclosure is shown.

[0138] refer to Figure 3AIn operation (a), a photoresist layer (PR) is patterned to form photoresist feature 302. Standard lithography techniques such as 193 immersion lithography can be used, but with an interval (e.g., an interval referred to as a sub-design rule space) that may ultimately conflict with the design rules required to produce a pattern with a uniform spacing. In operation (b), a material layer, such as an insulating layer or a dielectric hard mask layer, is patterned using photoresist feature 302 to form a first backbone (BB1) feature 304. A first spacer body (SP1) feature 306 is then formed adjacent to the sidewalls of the first backbone feature 304. However, with… Figure 2A The illustrated scheme contrasts with the more compact photoresist features 302, where some of the adjacent first spacer features 306 are fused spacer features. In operation (c), the first backbone features 304 are removed to leave only the first spacer features 306. Before or after removing the first backbone features 304, some of the first spacer features 306 may be thinned to form thinned first spacer features 306', as shown. Figure 3A As shown in the diagram. In operation (d), a material layer, such as an insulating layer or a dielectric hard mask layer, is patterned using the first spacer feature 306 and a thinned first spacer feature 306' to form a second backbone (BB2) feature 308. A second spacer (SP2) feature 310 is then formed adjacent to the sidewalls of the second backbone feature 308. However, at locations where the BB2 feature 308 is a fused feature, for example in… Figure 3A At the center BB2 feature 308, no second spacer is formed. In operation (e), the second backbone feature 308 is removed to leave only the second spacer feature 310. The remaining second spacer feature 310 can then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins with a spacing of quarters relative to the initially patterned photoresist feature 302.

[0139] As an example, see reference Figure 3B The second spacer feature 310 is used as a mask for patterning (e.g., dry or plasma etching patterning) to form a plurality of semiconductor fins 350, such as silicon fins formed from a bulk silicon layer. However, in Figure 3B In the example, the multiple semiconductor fins 350 have varying spacing and intervals. Such a fused fin spacer patterning method can be implemented to substantially eliminate the presence of fins in certain locations within the pattern of the multiple fins. Therefore, fusing the first spacer feature 306 in certain locations allows for the fabrication of six or four fins based on two first backbone features 304, typically resulting in eight fins, as combined... Figure 2A and Figure 2BIn one example, the fins in the plate have a closer spacing than is typically allowed by creating fins at a uniform spacing and then cutting off unwanted fins, although the latter approach can still be implemented according to the embodiments described herein.

[0140] In an exemplary embodiment, reference is made to Figure 3B The integrated circuit structure includes a first plurality of semiconductor fins 352 having the longest dimension along a first direction (y, entering the page). Adjacent individual semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart by a first amount (S1) in a second direction (x) orthogonal to the first direction. A second plurality of semiconductor fins 354 having the longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart by a first amount (S1) in the second direction. The nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are each spaced apart by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1, but less than twice the first amount S1. In another embodiment, the second amount S2 is more than twice the first amount S1.

[0141] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with an underlying monocrystalline silicon substrate. In one embodiment, individual fins of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 have sidewalls that taper outwardly from the top to the bottom along a second direction x. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0142] In another exemplary embodiment, reference is made to Figure 3A and Figure 3BA method of manufacturing an integrated circuit structure includes forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). A primary spacer structure 306 is formed adjacent to the sidewalls of the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). The primary spacer structure 306 between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) is fused. The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed, and first, second, third, and fourth secondary backbone structures 308 are provided. The second and third secondary backbone structures (e.g., the middle pair of secondary backbone structures 308) are fused. A secondary spacer structure 310 is formed adjacent to the sidewalls of the first, second, third, and fourth secondary backbone structures 308. The first, second, third, and fourth secondary backbone structures 308 are then removed. Then, the semiconductor material is patterned using the secondary spacer structure 310 to form semiconductor fins 350 in the semiconductor material.

[0143] In one embodiment, the first primary backbone structure and the second primary backbone structure are patterned using a sub-design rule spacing between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). In one embodiment, the semiconductor material comprises silicon. In one embodiment, individual semiconductor fins in semiconductor fin 350 have sidewalls that taper outward from the top to the bottom of the individual semiconductor fins in semiconductor fin 350 along a second direction x. In one embodiment, semiconductor fin 350 is continuous with an underlying monocrystalline silicon substrate. In one embodiment, patterning the semiconductor material using a secondary spacer structure 310 includes forming a first plurality of semiconductor fins 352 having the longest dimension along a first direction y, wherein adjacent individual semiconductor fins in the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x orthogonal to the first direction y. A second plurality of semiconductor fins 354 having the longest dimension along the first direction y are formed, wherein adjacent individual semiconductor fins in the second plurality of semiconductor fins 354 are spaced apart from each other by a first amount S1 in the second direction x. The nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are spaced apart from each other by a second amount S2 in the second direction x. In an embodiment, the second amount S2 is greater than the first amount S1. In one such embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is greater than twice the first amount S1 but less than three times the first amount S1. In an embodiment, as... Figure 3BAs shown, the first plurality of semiconductor fins 352 have exactly five semiconductor fins, and the second plurality of semiconductor fins 354 have exactly five semiconductor fins.

[0144] On the other hand, it should be recognized that fin trimming processes, in which fin removal is performed as an alternative to fin fusion, can trim (remove) fins either during hard mask patterning or by physically removing the fins. As an example of the latter approach, Figures 4A-4C Cross-sectional views are shown illustrating various operations in a method for manufacturing a plurality of semiconductor fins according to embodiments of the present disclosure.

[0145] refer to Figure 4A A patterned hard mask layer 402 is formed over a semiconductor layer 404, such as a bulk single-crystal silicon layer. (See reference) Figure 4B Then, fins 406 are formed in semiconductor layer 404 using processes such as dry etching or plasma etching. (See reference) Figure 4C For example, a masking and etching process is used to remove selected fins 406. In the illustrated example, one fin 406 is removed, leaving a residual fin stump 408. In such a "fin trimming last" approach, the hard mask 402 is patterned as a whole to provide a grid structure without removing or modifying individual features. The total number of fins is not modified until after the fins are manufactured.

[0146] In another aspect, multilayer trench isolation regions, which may be referred to as shallow trench isolation (STI) structures, can be implemented between semiconductor fins. In an embodiment, multilayer STI structures are formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0147] It may be desirable to use bulk silicon for fin-based or tri-gate transistors. However, a concern is that the region beneath the active silicon fin portion of the device (sub-fin) (e.g., the gate control region, or HSi) is eliminated or not gate-controlled. This means that leakage paths may exist through the sub-fin region if the source or drain region is at or below the HSi point. It is likely that leakage paths in the sub-fin region should be controlled for proper device operation.

[0148] One approach to solving the above problems involves using a trap injection operation, in which the sub-fin region is heavily doped (e.g., much greater than 2E18 / cm). 3 This cut off leakage in the sub-fins, but also resulted in significant doping in the fins. Adding halo implants further increased fin doping, allowing the tips of the wire fins to be doped at a high level (e.g., greater than approximately 1E18 / cm). 3 ).

[0149] Another approach involves doping via sub-fin doping without having to deliver the same level of doping to the HSi portion of the fin. The process can involve selectively doping the sub-fin regions of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer via, for example, diffusion from a tri-gate doped glass sub-fin. For example, selective doping of the sub-fin regions of a tri-gate or FinFET transistor can mitigate sub-fin leakage while keeping the fin doping very low. A solid-state doping source (e.g., p-type and n-type doped oxides, nitrides, or carbides) is incorporated into the transistor process flow (after recessing from the fin sidewalls) to deliver well doping to the sub-fins while keeping the fin bulk relatively undoped.

[0150] Therefore, the process can include using a solid source doped layer (e.g., boron-doped oxide) deposited on the fins after fin etching. Later, after trench filling and polishing, the doped layer is recessed along with the trench fill material to define the fin height (HSi) for the device. This operation removes the doped layer from the fin sidewalls above the HSi. Thus, the doped layer exists only along the fin sidewalls in the sub-fin region, ensuring precise control over dopant placement. After drive-in annealing, the high doping is confined to the sub-fin region, rapidly transitioning to the low doping in the adjacent region of the fin above the HSi (thus forming the channel region of the transistor). Typically, borosilicate glass (BSG) is used for NMOS fin doping, while phosphosilicate (PSG) or arsenicsilicate (AsSG) layers are used for PMOS fin doping. In one example, this P-type solid dopant source layer is a BSG layer with a boron concentration in the range of approximately 0.1–10 wt%. In another example, this N-type solid-state dopant source layer is a PSG layer or an AsSG layer with phosphorus or arsenic concentrations in the range of approximately 0.1-10 wt%, respectively. A silicon nitride cap layer may be included on the doped layer, and then a silicon dioxide or silicon oxide filler material may be included on the silicon nitride cap layer.

[0151] According to another embodiment of this disclosure, for relatively thin fins (e.g., fins with a width less than about 20 nanometers), sub-fin leakage is sufficiently low, wherein an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filling material is included on the silicon nitride cap layer. It should be appreciated that such a structure can also be used to implement doping of the sub-fin region, such as halo doping.

[0152] Figure 5A A cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure according to an embodiment of the present disclosure is shown.

[0153] refer to Figure 5A The integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (Hsi). A first insulating layer 504 is directly on the sidewall of the lower fin portion 502A of the fin 502. A second insulating layer 506 is directly on the first insulating layer 504, which is directly on the sidewall of the lower fin portion 502A of the fin 502. A dielectric filling material 508 is laterally directly adjacent to the second insulating layer 506, which is directly on the first insulating layer 504, which is directly on the sidewall of the lower fin portion 502A of the fin 502.

[0154] In an embodiment, the first insulating layer 504 is an undoped insulating layer comprising silicon and oxygen, such as silicon oxide or silicon dioxide. In an embodiment, the first insulating layer 504 comprises silicon and oxygen and contains no other atomic species with a concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 504 has a thickness in the range of 0.5-2 nanometers.

[0155] In an embodiment, the second insulating layer 506 comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-depleted silicon nitride insulating layer. In an embodiment, the second insulating layer 506 has a thickness in the range of 2-5 nanometers.

[0156] In one embodiment, the dielectric filling material 508 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In another embodiment, the gate electrode is ultimately formed on top of and laterally adjacent to the sidewall of the upper fin portion 502B of the fin 502.

[0157] It should be recognized that during processing, the upper fin portion of the semiconductor fin may be etched or consumed. Furthermore, the trench isolation structure between the fins may also be etched to have a non-planar morphology, or may be formed to have a non-planar morphology during manufacturing. As an example, Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure is shown.

[0158] refer to Figure 5BThe integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 in the region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, has a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 in the region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end portion 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 also has a second end portion 574B that is substantially coplanar with the shoulder feature 564 of the second fin 562. The second insulating layer 576 is directly on the first insulating layer 574, and the first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562.

[0159] The dielectric filling material 578 is laterally adjacent to the second insulating layer 576 directly on the first insulating layer 574. The first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562. In an embodiment, the dielectric filling material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric filling material 578 is below at least one of the shoulder features 554 of the first fin 552 and below at least one of the shoulder features 564 of the second fin 562, such as... Figure 5B As shown.

[0160] In an embodiment, the first insulating layer 574 is an undoped insulating layer comprising silicon and oxygen, such as silicon oxide or silicon dioxide. In an embodiment, the first insulating layer 574 comprises silicon and oxygen, and contains no other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 574 has a thickness in the range of 0.5-2 nanometers.

[0161] In an embodiment, the second insulating layer 576 comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-depleted silicon nitride insulating layer. In an embodiment, the second insulating layer 576 has a thickness in the range of 2-5 nanometers.

[0162] In one embodiment, the dielectric filling material 578 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In another embodiment, the gate electrode is ultimately formed on top of and laterally adjacent to the sidewall of the upper fin portion 552B of the first fin 552, and on top of and laterally adjacent to the sidewall of the upper fin portion 562B of the second fin 562. The gate electrode is also formed on the dielectric filling material 578 between the first fin 552 and the second fin 562.

[0163] Figures 6A-6D Cross-sectional views are shown of various operations in manufacturing a three-layer trench isolation structure according to embodiments of the present disclosure.

[0164] refer to Figure 6A The method of manufacturing an integrated circuit structure includes forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on the fin 602 and conforms to the fin 602, such as... Figure 6B As shown. In an embodiment, the first insulating layer 604 comprises silicon and oxygen, and contains no other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0165] refer to Figure 6C The second insulating layer 606 is formed directly on and conformally to the first insulating layer 604. In an embodiment, the second insulating layer 606 comprises silicon and nitrogen. A dielectric filling material 608 is formed directly on the second insulating layer 606, such as... Figure 6D As shown.

[0166] In an embodiment, the method also involves recessing the dielectric filling material 608, the first insulating layer 604, and the second insulating layer 606 to provide an exposed upper fin portion 602A (e.g., Figures 5A and 506). Figure 5B The fin-like portion 502B, 552B, or 562B) is a fin-like part 602. The resulting structure can be combined as follows. Figure 5A or Figure 5B In one embodiment, recessing the dielectric filler 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, recessing the dielectric filler 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching or dry etching process.

[0167] In one embodiment, a first insulating layer 604 is formed using a chemical vapor deposition process. In another embodiment, a second insulating layer 606 is formed using a chemical vapor deposition process. In yet another embodiment, a dielectric filler material 608 is formed using a spin-coating process. In one such embodiment, the dielectric filler material 608 is a spin-coated material and is exposed to a vapor treatment, for example, before or after a recess etching process, to provide a cured material comprising silicon and oxygen. In yet another embodiment, a gate electrode is ultimately formed on top of the sidewall of the upper fin portion of the fin 602 and laterally adjacent to the sidewall of the upper fin portion of the fin 602.

[0168] In another approach, gate sidewall spacer material can be retained over specific trench isolation regions as a protection against corrosion of the trench isolation regions during subsequent processing operations. For example, Figure 7A Figure 7E shows an oblique three-dimensional cross-sectional view of various operations in a method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure.

[0169] refer to Figure 7A A method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewall of the lower fin portion 702A of the fin 702. A gate structure 706 is formed over the upper fin portion 702B and the insulating structure 704. In an embodiment, the gate structure is a placeholder or dummy gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed conformally to the upper fin portion 702B of the fin 702, conformally to the gate structure 706, and conformally to the insulating structure 704.

[0170] refer to Figure 7B The hard mask material 710 is formed on the dielectric material 708. In this embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

[0171] refer to Figure 7C The hard mask material 710 is recessed to form a recessed hard mask material 712, exposing the portion of the dielectric material 708 conformally to the upper fin portion 702B of the fin 702 and conformally to the gate structure 706. The recessed hard mask material 712 covers the portion of the dielectric material 708 conformally to the insulating structure 704. In one embodiment, a wet etching process is used to recess the hard mask material 710. In another embodiment, an ashing, dry etching, or plasma etching process is used to recess the hard mask material 710.

[0172] refer to Figure 7DAnisotropic etching is performed on the dielectric material 708 to form a patterned dielectric material 714 along the sidewall of the gate structure 706 (as a dielectric spacer 714A), along the sidewall of the upper fin portion 702B of the fin 702, and on the insulating structure 704.

[0173] refer to Figure 7E ,from Figure 7D The hard mask material 712 is removed from the recessed structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and a gate electrode stack. In an embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

[0174] Refer again Figure 7E In one embodiment, the integrated circuit structure 700 includes a first fin (left 702), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure also includes a second fin (right 702), such as a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is directly adjacent to the sidewall of the lower fin portion 702A of the first fin and directly adjacent to the sidewall of the lower fin portion 702A of the second fin. A gate electrode 706 is located on the upper fin portion 702B of the first fin (left 702), on the upper fin portion 702B of the second fin (right 702), and on a first portion 704A of the insulating structure 704. The first dielectric spacer 714A runs along the sidewall of the upper fin portion 702B of the first fin (left 702), and the second dielectric spacer 702C runs along the sidewall of the upper fin portion 702B of the second fin (right 702). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B above the second portion 704B of the insulating structure 704 located between the first fin (left 702) and the second fin (right 702).

[0175] In the embodiments, the first and second dielectric spacers 714B and 714C comprise silicon and nitrogen, such as stoichiometric Si3N4 silicon nitride, silicon-rich silicon nitride, or silicon-poor silicon nitride.

[0176] In an embodiment, the integrated circuit structure 700 further includes an embedded source or drain structure on the opposite side of the gate electrode 706. This embedded source or drain structure has a bottom surface below the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, and a top surface above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, as described below. Figure 9B As described above. In an embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filling material laterally directly on the second insulating layer, as also described below. Figure 9B As stated above.

[0177] Figures 8A-8F The diagram illustrates various operations along the path of a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure. Figure 7E A slightly projected cross section taken along the a-a' axis.

[0178] refer to Figure 8A A method for manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion ( Figure 8A (Not visible in the middle) and the upper fin portion 702B. The insulating structure 704 is formed to be directly adjacent to the sidewall of the lower fin portion 702A of the fin 702. A pair of gate structures 706 are formed above the upper fin portion 702B and the insulating structure 704. It should be understood that Figures 8A-8F The perspective view shown is slightly projected to show a portion of the gate structure 706 and insulating structure in front of (outside the page) the upper fin portion 702B, wherein the upper fin portion extends slightly into the page. In an embodiment, the gate structure 706 is a placeholder or dummy gate structure comprising a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0179] refer to Figure 8B , which corresponds to the combination Figure 7A The described process operation involves forming the dielectric material 708 conformally to the upper fin portion 702B of the fin 702, conformally to the gate structure 706, and conformally to the exposed portion of the insulating structure 704.

[0180] refer to Figure 8C , which corresponds to the combination Figure 7B The described process involves forming a hard mask material 710 on a dielectric material 708. In this embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-coating process.

[0181] refer to Figure 8D , which corresponds to the combination Figure 7C The process operation involves recessing the hard mask material 710 to form a recessed hard mask material 712, exposing the portion of the dielectric material 708 conformally to the upper fin portion 702B of the fin 702 and conformally to the gate structure 706. The recessed hard mask material 712 covers the portion of the dielectric material 708 conformally to the insulating structure 704. In one embodiment, a wet etching process is used to recess the hard mask material 710. In another embodiment, an ashing, dry etching, or plasma etching process is used to recess the hard mask material 710.

[0182] refer to Figure 8E , which corresponds to the combination Figure 7D The process involves anisotropic etching of the dielectric material 708 to form a patterned dielectric material 714 along the sidewall of the gate structure 706 (as part 714A), along the sidewall of the upper fin part 702B of the fin 702, and on the insulating structure 704.

[0183] refer to Figure 8F , which corresponds to the combination Figure 7E The described process operation, from Figure 8E The hard mask material 712 is removed from the recessed structure. In an embodiment, the gate structure 706 is a dummy gate structure, and the process includes replacing the gate structure 706 with a permanent gate dielectric and a gate electrode stack. In an embodiment, a further process includes forming an embedded source or drain structure on opposite sides of the gate structure 706, as described in more detail below.

[0184] Refer again Figure 8F In an embodiment, the integrated circuit structure 700 includes a fin 702, such as a silicon fin, the fin 702 having a lower fin portion ( Figure 8F(Not visible in the image) and the upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewall of the lower fin portion of the fin 702. The first gate electrode (left 706) is above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. The second gate electrode (right 706) is above the upper fin portion 702B and above the second portion 704A' of the insulating structure 704. The first dielectric spacer (right 714A of left 706) is along the sidewall of the first gate electrode (left 706), and the second dielectric spacer (left 714A of right 706) is along the sidewall of the second gate electrode (right 706). The second dielectric spacer is continuous with the first dielectric spacer on the third portion 704A' of the insulating structure 704 between the first gate electrode (left 706) and the second gate electrode (right 706).

[0185] Figure 9A The following diagram illustrates an integrated circuit structure comprising a permanent gate stack and an epitaxial source or drain region, according to embodiments of the present disclosure. Figure 7E A slightly projected cross section taken along the a-a' axis. Figure 9B This illustration shows an integrated circuit structure including epitaxial source or drain regions and multilayer trench isolation structures according to embodiments of the present disclosure. Figure 7E The cross-sectional view taken along the b-b' axis.

[0186] refer to Figure 9A and Figure 9B In one embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on the opposite side of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below the top surface 990 of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above the top surface of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702.

[0187] In an embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926, such as... Figure 9A As shown. In one embodiment where the permanent gate structure 920 is over the insulating structure 704, the permanent gate structure 920 is formed on a residual polysilicon portion 930, which may be a residue of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0188] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric filling material 906 laterally directly on the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer comprising silicon and oxygen. In one embodiment, the second insulating layer 904 comprises silicon and nitrogen. In one embodiment, the dielectric filling material 906 comprises silicon and oxygen.

[0189] In another aspect, epitaxial embedded source or drain regions are implemented as source or drain structures for semiconductor fins. As an example, Figure 10 A cross-sectional view of an integrated circuit structure taken at the source or drain position according to an embodiment of the present disclosure is shown.

[0190] refer to Figure 10 The integrated circuit structure 1000 includes P-type devices, such as P-type metal-oxide-semiconductor (PMOS) devices. The integrated circuit structure 1000 also includes N-type devices, such as N-type metal-oxide-semiconductor (PMOS) devices.

[0191] Figure 10 The PMOS device includes a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, the upper portion of the fins 1002 has been removed, and the same or different semiconductor materials are grown to form the source or drain structure 1004. It should be understood that the source or drain structures 1004 will appear identical in a cross-sectional view taken from either side of the gate electrode; for example, they will appear substantially identical on the source side and on the drain side. In an embodiment, as described, the source or drain structure 1004 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as shown, the source or drain structure 1004 has strong facets. In an embodiment, conductive contacts 1008 are formed on the source or drain structure 1004. However, in one such embodiment, the strong facets and the wide growth of the source or drain structure 1004 at least partially inhibit the good coverage of the conductive contact 1008.

[0192] Figure 10The NMOS device includes a second plurality of semiconductor fins 1052, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, the upper portion of the fins 1052 has been removed, and the same or different semiconductor materials have been grown to form source or drain structures 1054. It should be understood that the source or drain structures 1054 will appear identical in cross-sectional views taken from either side of the gate electrode; for example, they will appear substantially identical on the source side and on the drain side. In an embodiment, as described above, the source or drain structure 1054 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as shown, the source or drain structure 1054 has a weaker facet relative to the source or drain structure 1004. In an embodiment, conductive contacts 1058 are formed on the source or drain structure 1054. In one such embodiment, the weaker facets and the narrower growth of the resulting source or drain structure 1054 (compared to the source or drain structure 1004) enhance the good coverage of the conductive contact 1058.

[0193] The shape of the source or drain structure of a PMOS device can be modified to improve the contact area with the overlying contact portion. For example, Figure 11 A cross-sectional view of another integrated circuit structure taken at the source or drain location according to an embodiment of the present disclosure is shown.

[0194] refer to Figure 11 The integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is formed on a first side of a first gate electrode (which may be formed on an upper fin portion such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 on a second side of such a first gate electrode opposite to the first side. In an embodiment, the first epitaxial source or drain structure 1104 and the second epitaxial source or drain structure include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick profile, as shown in FIG11. A first conductive electrode 1108 is placed on the first epitaxial source or drain structure 1104.

[0195] Refer again Figure 11In one embodiment, the integrated circuit structure 1100 further includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is formed on a first side of the second gate electrode (which may be formed on an upper fin portion, such as a channel portion of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 on a second side of such a second gate electrode opposite to the first side. In one embodiment, the third epitaxial source or drain structure 1154 and the fourth epitaxial source or drain structure include silicon and have a profile substantially the same as the profile 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is located above the third epitaxial source or drain structure 1154.

[0196] In one embodiment, the first epitaxial source or drain structure 1104 has a relatively weak facet. In another embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers.

[0197] In one embodiment, the first epitaxial source or drain structure 1104 varies with a germanium concentration gradient of approximately 20% at the bottom 1104A of the first epitaxial source or drain structure 1104 to approximately 45% at the top 1104B of the first epitaxial source or drain structure 1104. In another embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus or arsenic atoms.

[0198] Figures 12A-12D Cross-sectional views are shown at the source or drain locations according to embodiments of the present disclosure, illustrating various operations during the fabrication of an integrated circuit structure.

[0199] refer to Figure 12A A method of manufacturing an integrated circuit structure includes forming fins, such as silicon fins formed from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In an embodiment, although not shown, a gate electrode is formed on a portion of the upper fin portion 1202B of the fin 1202 at a location where the page enters. Such a gate electrode has a first side opposite a second side and defines source or drain locations on both the first and second sides. For example, for illustrative purposes, Figures 12A-12DThe cross-sectional position of the view is taken at one of the source or drain positions on one side of the gate electrode.

[0200] refer to Figure 12B This causes the source or drain position of the fin 1202 to be recessed to form a recessed fin portion 1206. The recessed source or drain position of the fin 1202 can be on one side of the gate electrode and on a second side of the gate electrode. (See reference) Figure 12A and Figure 12B In both embodiments, the dielectric spacer 1204 is formed along a portion of the sidewall of the fin 1202, for example, on one side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below the top surface 1204A of the dielectric spacer 1204.

[0201] refer to Figure 12C An epitaxial source or drain structure 1208 is formed on the recessed fin 1206, for example, thereby potentially forming on one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 on a second side of such a gate electrode. In an embodiment, the epitaxial source or drain structure 1208 comprises silicon and germanium and has a matchstick profile, such as... Figure 12C As shown in the figure. In an embodiment, the dielectric spacer 1204 is included and extends along the lower portion 1208A of the sidewall of the epitaxial source or drain structure 1208, as shown.

[0202] refer to Figure 12D A conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive filler material 1201B. In one embodiment, the conductive electrode 1210 follows the contour of the epitaxial source or drain structure 1208, as shown. In other embodiments, the upper portion of the epitaxial source or drain structure 1208 is etched during the fabrication of the conductive electrode 1210.

[0203] In another aspect, fin trimming isolation (FTI) and single-gate spacing for fins used for isolation are described. Non-planar transistors utilizing fins of semiconductor material protruding from the substrate surface employ gate electrodes that enclose two, three, or even all sides of the fin (i.e., dual-gate, tri-gate, nanowire transistors). Typically, source and drain regions are then formed in the fin on either side of the gate electrode, or formed as regrown portions of the fin. To isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or space can be formed between two adjacent fins. Such isolation gaps typically require some form of masking etching. Once isolated, the gate stack is then typically patterned again on the individual fins using some form of masking etching (e.g., line etching or aperture etching, depending on the specific implementation).

[0204] A potential problem with the fin isolation technology described above is that the gate is not self-aligned with the tip of the fin, and the alignment of the gate stack pattern with the semiconductor fin pattern depends on the overlap of these two patterns. This adds a lithographic overlap tolerance to the size settings of the semiconductor fin and the isolation gap, where the fin needs to be longer and the isolation gap is larger than the isolation gap required for a given level of transistor functionality. Therefore, device architectures and fabrication techniques that reduce this over-sized setting offer highly advantageous improvements in transistor density.

[0205] Another potential problem with the fin isolation technology described above is that the stress in the semiconductor fins required to improve carrier mobility can be lost from the channel region of the transistor, leaving excessive unconstrained fin surface during manufacturing, allowing fin strain to relax. Therefore, device architectures and fabrication techniques that maintain higher levels of desired fin stress offer advantageous improvements in nonplanar transistor performance.

[0206] According to embodiments of this disclosure, through-gate fin isolation architectures and techniques are described herein. In the illustrated exemplary embodiments, non-planar transistors in microelectronic devices such as integrated circuits (ICs) are isolated from each other in a manner self-aligned to the gate electrodes of the transistors. While embodiments of this disclosure are applicable to virtually any IC employing non-planar transistors, exemplary ICs include, but are not limited to: microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0207] In one embodiment, an isolation region is used to electrically isolate the two ends of adjacent semiconductor fins from each other, and this isolation region is positioned relative to the gate electrode using only a single patterned mask level. In another embodiment, a plurality of sacrificial berth strips with a fixed spacing are formed using a single mask. A first subset of the berth strips defines the location or size of the isolation region, while a second subset defines the location or size of the gate electrode. In some embodiments, the first subset of the berth strips is removed, and an isolation notch is created in the semiconductor fin in the opening obtained by removing the first subset, while the second subset of the berth strips is ultimately replaced by a non-sacrificial gate electrode stack. Because the subset of berths used for gate electrode replacement is used to form the isolation region, this method and the resulting architecture are referred to herein as “through-gate” isolation. For example, one or more through-gate isolation embodiments described herein can achieve higher transistor density and higher levels of favorable transistor channel stress.

[0208] Greater transistor density can be achieved by utilizing the isolation defined after the placement or definition of the gate electrode, because the fin isolation can be perfectly sized and placed on-field using the gate electrode, such that the gate electrode and isolation region are integer multiples of the minimum feature spacing of a single masking level. In other embodiments where there is a lattice mismatch between the semiconductor fin and the substrate on which the fin is disposed, a greater degree of strain is maintained by defining the isolation after the placement or definition of the gate electrode. For such embodiments, other features of the transistor formed before defining the ends of the fin (e.g., the gate electrode and additional source or drain material) help to mechanically maintain fin strain after creating isolation notches in the fin.

[0209] To provide further context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are separated from their adjacent cells by two or more dummy gates, which have buried fins. Cells are isolated by etching the fins beneath these two or more dummy gates, which connect one cell to another. Scaling can be significantly beneficial if the number of dummy gates separating adjacent cells can be reduced from two or more to one. As mentioned above, one approach requires two or more dummy gates. The fins beneath the two or more dummy gates are etched during fin patterning. A potential problem with this approach is that the dummy gates consume space on the chip that can be used for cells. In embodiments, the approach described herein makes it possible to separate adjacent cells using only a single dummy gate.

[0210] In this embodiment, the fin trimming isolation method is implemented as a self-aligned patterning scheme. Here, the fins beneath a single gate are etched away. Thus, adjacent cells can be separated by a single dummy gate. Advantages of this approach include saving on-chip space and allowing for greater computational power over a given area. This approach also allows fin trimming to be performed at sub-fin spacing distances.

[0211] Figure 13A and Figure 13B A plan view illustrating various operations in a method for patterning a fin with multiple gate spacings for forming a local isolation structure, according to embodiments of the present disclosure, is shown.

[0212] refer to Figure 13A Multiple fins 1302 are shown having a length along a first direction 1304. A grid 1306 is shown along a second direction 1308 orthogonal to the first direction 1304, with spacing 1307 between the grids defining the locations for the final formation of multiple gate lines.

[0213] refer to Figure 13B A portion of multiple fins 1302 is cut (e.g., removed by an etching process) to leave fins 1310 with cutouts 1312 therein. Therefore, the isolation structure ultimately formed in the cutouts 1312 has a size exceeding that of a single gate line, for example, the size of three gate lines 1306. Thus, a gate structure ultimately formed along the positions of the gate lines 1306 is formed, at least partially, over the isolation structure formed in the cutouts 1312. Therefore, the cutouts 1312 are relatively wide fin cutouts.

[0214] Figures 14A-14D A plan view is shown illustrating various operations in a method for patterning fins with single-gate spacing for forming a local isolation structure, according to another embodiment of the present disclosure.

[0215] refer to Figure 14A A method of manufacturing an integrated circuit structure includes forming a plurality of fins 1402, each of which has a longest dimension along a first direction 1404. A plurality of gate structures 1406 are situated above the plurality of fins 1402, each of which has a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In an embodiment, the gate structure 1406 is, for example, a sacrificial or dummy gate line manufactured from polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0216] refer to Figure 14BA dielectric material structure 1410 is formed between adjacent gate structures in a plurality of gate structures 1406.

[0217] refer to Figure 14C A portion 1412 of one of the plurality of gate structures 1406 is removed to expose a portion 1414 of each of the plurality of fins 1402. In an embodiment, removing a portion 1412 of one of the plurality of gate structures 1406 involves using a photolithographic window 1416 that is wider than the width 1418 of the portion 1412 of one of the plurality of gate structures 1406.

[0218] refer to Figure 14D The exposed portion 1414 of each of the plurality of fins 1402 is removed to form a notch region 1420. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed using a dry or plasma etching process. In an embodiment, removing the exposed portion 1414 of each of the plurality of fins 1402 involves etching to a depth less than the height of the plurality of fins 1402. In one such embodiment, this depth is greater than the depth of the source or drain regions in the plurality of fins 1402. In an embodiment, this depth is deeper than the depth of the active portion of the plurality of fins 1402 to provide isolation margin. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially without etching the source or drain regions (e.g., epitaxial source or drain regions) of the plurality of fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without lateral etching or substantially without lateral etching of the source or drain regions (e.g., epitaxial source or drain regions) of the plurality of fins 1402.

[0219] In one embodiment, the cut-out region 1420 is ultimately filled with an insulating layer at the location of the removed portion 1414 of each of the plurality of fins 1402. Exemplary insulating layer or “multi-cut-out” or “plug” structures are described below. However, in other embodiments, only a portion of the cut-out region 1420 is filled with an insulating layer, and then a conductive structure is formed therein. The conductive structure can be used as a local interconnect. In another embodiment, before filling the cut-out region 1420 with an insulating layer or with an insulating layer that accommodates a local interconnect structure, dopant can be implanted or delivered through the cut-out region 1420 to the local cut-out portions of one or more fins via a solid source dopant layer.

[0220] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multiple gate spacings for local isolation, according to an embodiment of the present disclosure, is shown.

[0221] refer to Figure 15The silicon fin 1502 has a first fin portion 1504 laterally adjacent to the second fin portion 1506. The first fin portion 1504 is separated from the second fin portion 1506 by a wider cut 1508, for example, as in combination. Figure 13A and Figure 13B The wider notch 1508 has a width X. A dielectric filler 1510 is formed in the wider notch 1508 and electrically isolates the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are on the silicon fin 1502, each of which may include a gate dielectric and a gate electrode stack 1514, a dielectric cap 1516, and a sidewall spacer 1518. Two gate lines (the two gate lines 1512 on the left) occupy the wider notch 1508, thereby effectively separating the first fin portion 1504 from the second fin portion 1506 by two dummy gates or passive gates.

[0222] In contrast, the fin portion can separate individual gate distances. As an example, Figure 16A A cross-sectional view of an integrated circuit structure having fins with single gate spacing for local isolation, according to another embodiment of the present disclosure, is shown.

[0223] refer to Figure 16A The silicon fin 1602 has a first fin portion 1604 laterally adjacent to the second fin portion 1606. The first fin portion 1604 is separated from the second fin portion 1606 by a narrower cut 1608, for example, by combining... Figures 14A-14D The narrower cut 1608 has a width Y, where Y is less than... Figure 15 The X. Dielectric filler material 1610 is formed in the narrower notch 1608 and electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are on the silicon fin 1602, each of which may include a gate dielectric and gate electrode stack 1614, a dielectric cap layer 1616, and a sidewall spacer 1618. The dielectric filler material 1610 occupies the position where a single gate line was previously located, thereby separating the first fin portion 1604 from the second fin portion 1606 by a single "plugged" gate line. In one embodiment, residual spacer material 1620 is retained on the sidewalls at the location of the removed gate line portion, as shown. It should be appreciated that other regions of the fin 1602 may be isolated from each other by two or more passive gate lines (region 1622 with three passive gate lines) manufactured by an earlier, wider fin notch process, as described below.

[0224] Refer again Figure 16AThe integrated circuit structure 1600 includes a fin 1602, such as a silicon fin. The fin 1602 has its longest dimension along a first direction 1650. An isolation structure 1610 separates a first upper portion 1604 of the fin 1602 from a second upper portion 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0225] A first gate structure 1612A is located on a first upper portion 1604 of the fin 1602, and has the longest dimension along a second direction 1652 (e.g., entering the page) orthogonal to the first direction 1650. The center 1613A of the first gate structure 1612A is spaced apart from the center 1611 of the isolation structure 1610 along the first direction 1650 by a distance. A second gate structure 1612B is located on the first upper portion 1604 of the fin, and has the longest dimension along the second direction 1652. The center 1613B of the second gate structure 1612B is spaced apart from the center 1613A of the first gate structure 1612A along the first direction 1650 by a distance. A third gate structure 1612C is located on a second upper portion 1606 of the fin 1602, and has the longest dimension along the second direction 1652. The center 1613C of the third gate structure 1612C is spaced apart from the center 1611 of the isolation structure 1610 along the first direction 1650 by a distance. In an embodiment, the isolation structure 1610 has a top that is substantially coplanar with the top of the first gate structure 1612A, the top of the second gate structure 1612B, and the top of the third gate structure 1612C, as shown.

[0226] In an embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between the sidewalls of the high-k gate dielectric layer 1662, as shown for an exemplary third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C also includes an insulating cap 1616 on the gate electrode 1660 and on the sidewalls of the high-k gate dielectric layer 1662.

[0227] In one embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of the fin 1602 located between the first gate structure 1612A and the isolation structure 1610. A second epitaxial semiconductor region 1664B is on the first upper portion 1604 of the fin 1602 located between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is on a second upper portion 1606 of the fin 1602 located between the third gate structure 1612C and the isolation structure 1610. In one embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions comprise silicon and germanium. In another embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions comprise silicon.

[0228] In one embodiment, the isolation structure 1610 induces stress on a first upper portion 1604 and a second upper portion 1606 of the fin 1602. In one embodiment, the stress is compressive stress. In another embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer in which a conductive structure is then formed. The conductive structure can be used as a local interconnect. In one embodiment, dopant is injected or delivered into local cutouts of one or more fins by a solid source dopant layer before the isolation structure 1610 is formed using the insulating layer or the insulating layer that houses the local interconnect structure.

[0229] On the other hand, it should be recognized that an isolation structure, such as the isolation structure 1610 described above, can be formed instead of an active gate electrode at a local location or a wider location of the fin cut. Furthermore, the depth of such local or wider locations of the fin cut can be formed to vary relative to each other within the fin. In the first example, Figure 16B A cross-sectional view is shown, illustrating an embodiment of the present disclosure, in which a fin isolation structure can be formed to replace the position of the gate electrode.

[0230] refer to Figure 16BA fin, such as a silicon fin, is formed above a substrate 1682 and may be continuous with the substrate 1682. The fin 1680 has a fin tip or a wide fin cutout 1684, which may be formed during fin patterning, for example, in the final fin trimming method described above. The fin 1680 also has a partial cutout 1686, in which a portion of the fin 1680 is removed, for example, using a fin trimming isolation method in which a dielectric plug replaces a dummy gate, as described above. An active gate electrode 1688 is formed on the fin and, for illustrative purposes, is shown slightly in front of the fin 1680, with the fin 1680 in the background, where the dashed line represents the area covered in the front view. A dielectric plug 1690 may be formed at the fin tip or the wide fin cutout 1684, instead of using an active gate at such a location. Alternatively, a dielectric plug 1692 may be formed at the partial notch 1686 instead of using an active gate at such a location. It should be understood that the epitaxial source or drain region 1694 is also shown at the location of the fin 1680 between the active gate electrode 1688 and the plug 1690 or 1692. Furthermore, in embodiments, the surface roughness of the tip of the fin at the partial notch 1686 is rougher than that of the tip of the fin at a wider notch location, such as… Figure 16B As shown.

[0231] Figures 17A-17C Various depth possibilities for fin cuts made using a fin trimming isolation method according to embodiments of the present disclosure are shown.

[0232] refer to Figure 17A Semiconductor fins 1700, such as silicon fins, are formed above and may be continuous with the lower substrate 1702. Fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B, as defined by the insulating structure 1704 relative to the height of the fin 1700. A local fin isolation notch 1706A divides the fin 1700 into a first fin portion 1710 and a second fin portion 1712. Figure 17A In the example, as shown along the a-a' axis, the depth of the local fin isolation notch 1706A is the entire depth from the fin 1700 to the substrate 1702.

[0233] refer to Figure 17B In the second example, as shown along the a-a' axis, the depth of the local fin isolation notch 1706B is greater than the entire depth from the fin 1700 to the substrate 1702. That is, the notch 1706B extends into the underlying substrate 1702.

[0234] refer to Figure 17CIn the third example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706C is less than the entire depth of the fin 1700, but deeper than the upper surface of the isolation structure 1704. (See again...) Figure 17C In the fourth example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706D is less than the entire depth of the fin 1700 and is at a level that is approximately coplanar with the upper surface of the isolation structure 1704.

[0235] Figure 18 Plan view and corresponding cross-sectional view taken along the a-a' axis are shown, illustrating possible options for comparing the depth of a local location of a fin cut within the fin with the depth of a wider location, according to embodiments of the present disclosure.

[0236] refer to Figure 18 First and second semiconductor fins 1800 and 1802, such as silicon fins, have upper fin portions 1800B and 1802B extending over an insulating structure 1804. Both fins 1800 and 1802 have fin ends or wide fin cutouts 1806, which may be formed during fin patterning, for example, in the final fin trimming method described above. Both fins 1800 and 1802 also have partial cutouts 1808, where a portion of fin 1800 or 1802 is removed, for example, using a fin trimming isolation method in which a dielectric plug replaces a dummy gate, as described above. In embodiments, the surface roughness of the ends of fins 1800 and 1802 at partial cutout 1808 is rougher than that of the ends of the fins at location 1806, such as... Figure 18 As shown.

[0237] refer to Figure 18 The cross-sectional view shows the lower fin portions 1800A and 1802A below the height of the insulating structure 1804. Furthermore, the cross-sectional view shows the residual portion 1810 of the fins removed in the final fin trimming process prior to the formation of the insulating structure 1804, as described above. Although shown protruding above the substrate, the residual portion 1810 can also be at the level of the substrate or into the substrate, as shown by the additional exemplary wide cut depth 1820. It should be appreciated that the wide cuts 1806 of the fins 1800 and 1802 can also be at the level described for cut depth 1820, an example of which is shown. The partial cut 1808 can have the same characteristics as those for... Figures 17A-17C An example depth corresponding to the described depth is shown in the figure.

[0238] Common Reference Figure 16A , Figure 16B , Figures 17A-17C and Figure 18According to embodiments of the present disclosure, an integrated circuit structure includes a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction. A first isolation structure along the first direction separates a first end of a first portion of the fin from a first end of a second portion of the fin. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. A gate structure includes a gate electrode located above the top of a region of the first portion of the fin and laterally adjacent to the sidewalls of that region. The gate structure has a width along the first direction, and the center of the gate structure is spaced apart from the center of the first isolation structure along the first direction by a distance. A second isolation structure is located above a second end of the first portion of the fin, the second end being opposite the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness smaller than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced apart from the center of the gate structure along the first direction by a distance.

[0239] In one embodiment, the first end of the first portion of the fin has a fan-shaped morphology, as shown in FIG16B. In one embodiment, a first epitaxial semiconductor region is located on the first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is located on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have widths along a second direction orthogonal to the first direction, and the width along the second direction is wider than the width of the first portion of the fin below the gate structure along the second direction, for example, as in combination. Figure 11 and Figure 12D The extensional features shown, for example in Figure 11 and Figure 12D The perspective view shown has a width wider than the fin portion where the epitaxial feature is grown. In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along the sidewall of the gate electrode.

[0240] Common Reference Figure 16A , Figure 16B , Figures 17A-17C and Figure 18According to another embodiment of this disclosure, the integrated circuit structure includes a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure along this direction separates a first end of a first portion of the fin from a first end of a second portion of the fin. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode located above the top of a region of the first portion of the fin and laterally adjacent to the sidewalls of that region. A second isolation structure is located above a second end of the first portion of the fin, the second end being opposite to the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0241] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In another embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along this direction, and the gate structure has a width along this direction. The second isolation structure has a width along this direction. In one embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure along this direction by a distance, and the center of the second isolation structure is spaced apart from the center of the gate structure along this direction by the distance.

[0242] Common Reference Figure 16A , Figure 16B , Figures 17A-17C and Figure 18 According to another embodiment of this disclosure, the integrated circuit structure includes a first fin comprising silicon, the first fin having a top and sidewalls, wherein the top has a longest dimension along a direction, and a discontinuity along said direction separates a first end portion of a first portion of the first fin from a first end portion of a second portion of the fin. The first portion of the first fin has a second end portion opposite to the first end portion, and the first end portion of the first portion of the fin has a depth. The integrated circuit structure also includes a second fin comprising silicon, the second fin having a top and sidewalls, wherein the top has a longest dimension along said direction. The integrated circuit structure also includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, wherein the top has a longest dimension along said direction, and the depth of the top is not coplanar with the depth of the first end portion of the first portion of the fin.

[0243] In one embodiment, the depth of the first end of the first portion of the fin is lower than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is higher than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth lower than the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth higher than the top of the remaining fin portion.

[0244] In another embodiment, a dielectric plug formed in the position of a localized or wide fin cutout can be adjusted to provide specific stress to the fin or fin portion. In such an embodiment, the dielectric plug may be referred to as a fin end stress source.

[0245] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements to such devices can be made through channel stress induced from a multi-plug-in process. Embodiments may include inducing mechanical stress in the channel of a metal-oxide-semiconductor field-effect transistor (MOSFET) using material properties from the multi-plug-in process. As a result, the induced stress can improve the transistor's mobility and drive current. Furthermore, the plug-in filling method described herein can allow for the elimination of any seams or voids formed during deposition.

[0246] To provide context, the unique material properties of the plug filler, manipulated to adjoint fins, can induce stress within the channel. According to one or more embodiments, by adjusting the composition of the plug filler material, deposition, and post-processing conditions, the stress in the channel is modulated to benefit both NMOS and PMOS transistors. Furthermore, such plugs can exist at greater depths within the fin substrate compared to other common stress-generating techniques such as epitaxial sources or drains. The properties of the plug filler that achieve this effect also eliminate seams or porosity during deposition and mitigate certain defect modes during the process.

[0247] To provide further context, currently, there is no artificial stress engineering for gate (multi) plugs. Stress enhancement from conventional stress sources such as epitaxial sources or drains, dummy multi-gate removal, stress liner, etc., unfortunately tends to decrease as device pitch decreases. To address one or more of these problems, according to one or more embodiments of this disclosure, additional stress sources are incorporated into the transistor structure. Another potential benefit of this process is the elimination of seams or pores within the plug, which are common in other chemical vapor deposition methods.

[0248] Figure 19A and Figure 19B Cross-sectional views are shown of various operations in a method, for example, the method of selecting the end of a fin with a wide cut as part of the final process of fin trimming, according to an embodiment of the present disclosure.

[0249] refer to Figure 19A A fin 1900, such as a silicon fin, is formed above and may be continuous with the substrate 1902. The fin 1900 has fin tips or wide fin cutouts 1904, which may be formed, for example, during fin patterning, as described above in the final fin trimming method. Active gate electrode locations 1908 and dummy gate electrode locations 1908 are formed above the fin 1900 and, for illustrative purposes, are shown slightly in front of the fin 1900, with the fin 1900 in the background, where the dashed lines represent the covered area in the front view. It should be appreciated that an epitaxial source or drain region 1910 is also shown at the location of the fin 1900 between gate locations 1906 and 1908. Furthermore, an interlayer dielectric material 1912 is included at the location of the fin 1900 between gate locations 1906 and 1908.

[0250] refer to Figure 19BThe gate occupant structure or dummy gate location 1908 is removed to expose the fin tip and wide fin cutout 1904. This removal creates an opening 1920, in which a dielectric plug, such as a fin tip stress source dielectric plug, can eventually be formed.

[0251] Figure 20A and Figure 20B Cross-sectional views are shown of various operations in a method according to embodiments of the present disclosure for selecting the fin end stress location at the fin end with a partial cut as part of, for example, the fin trimming isolation process described above.

[0252] refer to Figure 20A A fin 2000, such as a silicon fin, is formed above and may be continuous with the substrate 2002. The fin 2000 has a partial notch 2004, wherein a portion of the fin 2000 is removed, for example, using a fin trimming isolation method in which a dummy gate is removed and the fin is etched in a localized location, as described above. Active gate electrode locations 2006 and dummy gate electrode locations 2008 are formed above the fin 2000 and, for illustrative purposes, are shown slightly in front of the fin 2000, with the fin 2000 in the background, where the dashed lines represent the covered area in the front view. It should be appreciated that an epitaxial source or drain region 2010 is also shown at the location of the fin 2000 between gate locations 2006 and 2008. Furthermore, an interlayer dielectric material 2012 is included at the location of the fin 2000 between gate locations 2006 and 2008.

[0253] refer to Figure 20B The gate occupant structure or dummy gate electrode location 2008 is removed to expose the fin tip with a partial cutout 2004. This removal creates an opening 2020, in which a dielectric plug, such as a stress-source dielectric plug for the fin tip, can eventually be formed.

[0254] Figures 21A-21M Cross-sectional views are shown of various operations in a method for manufacturing an integrated circuit structure with differentiated fin-end dielectric plugs according to embodiments of the present disclosure.

[0255] refer to Figure 21AThe initial structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the initial structure 2100 includes a first fin 2102, such as a first silicon fin, formed above and potentially continuous with the substrate 2104. The first fin 2102 has fin ends 2106, which may be formed by partial or wide fin cutouts. A first active gate electrode location 2108 and a first dummy gate electrode location 2110 are formed above the first fin 2102 and, for illustrative purposes, are shown slightly in front of the first fin 2102, with the first fin 2102 in the background, where the dashed lines represent the area covered in the front view. An epitaxial N-type source or drain region 2112, such as an epitaxial silicon source or drain structure, is also shown at the location of the first fin 2102 between gate locations 2108 and 2110. Furthermore, an interlayer dielectric material 2114 is included at the location of the first fin 2102 between gate positions 2108 and 2110.

[0256] The PMOS region of the initial structure 2100 includes a second fin 2122, such as a second silicon fin, formed above and potentially continuous with the substrate 2104. The second fin 2122 has fin tips 2126, which may be formed by partial or wide fin cutouts. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed above the second fin 2122 and, for illustrative purposes, are shown slightly in front of the second fin 2122, with the second fin 2122 in the background, where the dashed lines represent the covered area in the front view. An epitaxial P-type source or drain region 2132, such as an epitaxial silicon-germanium source or drain structure, is also shown at the location of the second fin 2122 between gate locations 2128 and 2130. Furthermore, an interlayer dielectric material 2134 is included at the location of the second fin 2122 between gate locations 2128 and 2130.

[0257] refer to Figure 21B The first and second dummy gate electrodes at positions 2110 and 2130, respectively, are removed. During removal, the fin tip 2106 of the first fin 2102 and the fin tip 2126 of the second fin 2122 are exposed. This removal also creates openings 2116 and 2136, respectively, in which dielectric plugs, such as fin tip stress source dielectric plugs, can eventually be formed.

[0258] refer to Figure 21C Material lining 2140 and Figure 21B The structure is conformally formed. In an embodiment, the material liner comprises silicon and nitrogen, such as a silicon nitride material liner.

[0259] refer to Figure 21D Protective canopies such as metal nitride layers 2142 are formed in Figure 21C In terms of structure.

[0260] refer to Figure 21E Hard mask material 2144, such as carbon-based hard mask material, is formed in Figure 21D The photolithographic mask or mask stack 2146 is formed on the hard mask material 2144.

[0261] refer to Figure 21F ,from Figure 21E The structure removes a portion of the hard mask material 2144 and a portion of the protective crown layer 2142 from the PMOS region. It also removes the photolithography mask or mask stack 2146.

[0262] refer to Figure 21G The second material liner 2148 and Figure 21F The structure is conformally formed. In an embodiment, the second material liner comprises silicon and nitrogen, such as a second silicon nitride material liner. In an embodiment, the second material liner 2148 has different stress states to adjust the stress in the exposed plug.

[0263] refer to Figure 21H The second hard mask material 2150, such as the second carbon-based hard mask material, is formed in... Figure 21G The structure is above the structure and then recessed into the opening 2136 of the PMOS region of the structure.

[0264] refer to Figure 21I ,from Figure 21H The structure etches away the second material substrate 2148 to remove the second material substrate 2148 from the NMOS region and recesses the second material substrate 2148 in the PMOS region of the structure.

[0265] refer to Figure 21J ,from Figure 21I The structure removes hard mask material 2144, protective canopy 2142, and second hard mask material 2150. Compared to opening 2136, this removal leaves two different filling structures for opening 2116.

[0266] refer to Figure 21K Insulating filler material 2152 is formed in Figure 21J The structure is planarized within openings 2116 and 2136. In an embodiment, the insulating filler material 2152 is a flowable oxide material, such as flowable silicon oxide or silicon dioxide.

[0267] refer to Figure 21L The insulating filler material 2152 is recessed into Figure 21KWithin the openings 2116 and 2136 of the structure, recessed insulating filler material 2154 is formed. In an embodiment, a vapor oxidation process is performed as part of the recessing process, or a vapor oxidation process is performed after the recessing process to solidify the recessed insulating filler material 2154. In one such embodiment, the recessed insulating filler material 2154 shrinks, thereby inducing tensile stress on the fins 2102 and 2122. However, there is less tensile stress-inducing material in the PMOS region than in the NMOS region.

[0268] refer to Figure 21M The third material lining 2156 in Figure 21L The structure is above. In an embodiment, the third material liner 2156 comprises silicon and nitrogen, such as a third silicon nitride material liner. In an embodiment, the third material liner 2156 prevents the recessed insulating filler 2154 from being etched away during subsequent source or drain contact etching.

[0269] Figures 22A-22D A cross-sectional view of an exemplary structure of a PMOS fin end stress source dielectric plug according to an embodiment of the present disclosure is shown.

[0270] refer to Figure 22A The opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but recessed relative to the upper portion of the material liner 2140. A recessed insulating filler 2154 is located within the second material liner 2148 and has an upper surface coplanar with the upper surface of the second material liner 2148. A third material liner 2156 is located within the upper portion of the material liner 2140 and is located on the upper surface of the insulating filler 2154 and the upper surface of the second material liner 2148. The third material liner 2156 has a seam 2157, for example, as an artifact of the deposition process for forming the third material liner 2156.

[0271] refer to Figure 22B The opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but recessed relative to the upper portion of the material liner 2140. A recessed insulating filler 2154 is located within the second material liner 2148 and has an upper surface coplanar with the upper surface of the second material liner 2148. A third material liner 2156 is located within the upper portion of the material liner 2140 and is located on the upper surface of the insulating filler 2154 and the upper surface of the second material liner 2148. The third material liner 2156 has no seams.

[0272] refer to Figure 22C The opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but recessed relative to the upper portion of the material liner 2140. A recessed insulating filler 2154 is within and above the second material liner 2148 and has an upper surface above the upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140 and on the upper surface of the insulating filler 2154. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0273] refer to Figure 22D The opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but recessed relative to the upper portion of the material liner 2140. A recessed insulating filler 2154 is within the second material liner 2148 and has an upper surface recessed below the upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140 and is located on the upper surface of the insulating filler 2154 and the upper surface of the second material liner 2148. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0274] Common Reference Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figures 21A-21M as well as Figure 22A - Figure 22DAccording to embodiments of this disclosure, an integrated circuit structure includes a fin, such as silicon, having a top and sidewalls. The top has its longest dimension along a direction. A first isolation structure is located above a first end of the fin. A gate structure includes a gate electrode located above the top of a region of the fin and laterally adjacent to the sidewalls of that region. The gate structure is spaced apart from the first isolation structure along this direction. A second isolation structure is located above a second end of the fin, opposite to the first end. The second isolation structure is spaced apart from the gate structure along this direction. Both the first and second isolation structures include a first dielectric material (e.g., material liner 2140) laterally surrounding a recessed second dielectric material (e.g., a second material liner 2148) that is different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., a recessed insulating filler 2154) that is different from the first and second dielectric materials.

[0275] In one embodiment, both the first and second isolation structures further include a fourth dielectric material (e.g., a third material liner 2156) laterally surrounded by the upper portion of the first dielectric material, the fourth dielectric material being on the upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on the upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a generally vertical central seam. In yet another such embodiment, the fourth dielectric material has no seam.

[0276] In one embodiment, the third dielectric material has an upper surface coplanar with the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface below the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface above the upper surface of the second dielectric material, and the third dielectric material further lies above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In such an embodiment, the gate electrode is a P-type gate electrode.

[0277] In one embodiment, a first isolation structure has a width along the direction, a gate structure has a width along the direction, and a second isolation structure has a width along the direction. In such an embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure along the direction by a distance, and the center of the second isolation structure is spaced apart from the center of the gate structure along the direction by the distance. In one embodiment, both the first and second isolation structures are located in corresponding trenches in an interlayer dielectric layer.

[0278] In one such embodiment, a first source or drain region is located between the gate structure and the first isolation structure. A second source or drain region is located between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further includes a high-k dielectric layer located between the gate electrode and the fin and along the sidewall of the gate electrode.

[0279] In another respect, the depth of individual dielectric plugs can vary within the architecture formed either within the semiconductor structure or on a common substrate. As an example, Figure 23A A cross-sectional view of another semiconductor structure having fin-end stress-induced features according to another embodiment of the present disclosure is shown. Reference Figure 23A This includes a shallow dielectric plug 2308A and a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as shown, the shallow dielectric plug 2308C is located at a depth approximately equal to the depth of the semiconductor fin 2302 within the substrate 2304, while the deep dielectric plugs 2308B and 2308C are located at a depth less than the depth of the semiconductor fin 2302 within the substrate 2304.

[0280] Refer again Figure 23A Such an arrangement allows for stress amplification on the fin trimming isolation (FTI) device within trenches etched deeper into the substrate 2304, providing isolation between adjacent fins 2302. This approach can be implemented to increase on-chip transistor density. In an embodiment, the stress effect induced by plug filling on the transistor is amplified in the FTI transistor because stress transfer occurs in both the fins and the substrate, or just beneath the transistor.

[0281] In another respect, the width or amount of the tensile stress-induced oxide layer included in the dielectric plug can be varied within the semiconductor structure or within an architecture formed on a common substrate, for example, depending on whether the device is a PMOS or NMOS device. As an example, Figure 23B A cross-sectional view of another semiconductor structure having fin-end stress-induced features according to another embodiment of the present disclosure is shown. Reference Figure 23B In a particular embodiment, the NMOS device includes a relatively larger tensile stress-induced oxide layer 2350 than the corresponding PMOS device.

[0282] Refer again Figure 23BIn embodiments, differentiated plug fills are implemented to induce appropriate stresses in NMOS and PMOS devices. For example, NMOS plugs 2308D and 2308E have a larger volume and a wider tensile stress-induced oxide layer 2350 than PMOS plugs 2308F and 2308G. The plug fills can be patterned to induce different stresses in NMOS and PMOS devices. For example, a PMOS device can be opened using photolithographic patterning (e.g., widening the dielectric plug trench for the PMOS device), in which case different fill options can be implemented to differentiate the plug fill in the NMOS device from the plug fill in the PMOS device. In an exemplary embodiment, reducing the volume of the flowable oxide in the plug on the PMOS device can reduce the induced tensile stress. In one such embodiment, compressive stress may primarily originate from, for example, the compressive stress source and drain regions. In other embodiments, using different plug liner layers or different fill materials provides adjustable stress control.

[0283] As described above, it should be recognized that the multi-plug stress effect can be beneficial to both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to embodiments of this disclosure, the semiconductor fin is a uniaxially stressed semiconductor fin. A uniaxially stressed semiconductor fin can be stressed uniaxially using tensile stress or compressive stress. For example, according to one or more embodiments of this disclosure, Figure 24A An oblique view of a fin with tensile uniaxial stress is shown, while Figure 24B An oblique view of a fin with compressive uniaxial stress is shown.

[0284] refer to Figure 24A The semiconductor fin 2400 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2400 on either side of the channel region (C). The discrete channel region of the semiconductor fin 2400 has a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing away from each other and toward the ends 2402 and 2404).

[0285] refer to Figure 24BThe semiconductor fin 2450 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2450 on either side of the channel region (C). The discrete channel region of the semiconductor fin 2450 has a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (arrows pointing towards each other and originating from ends 2452 and 2454). Therefore, the embodiments described herein can be implemented to improve transistor mobility and drive current, thereby allowing for faster circuit and chip execution.

[0286] In another aspect, there may be a relationship between the location of the gate line cut (multiple cut) and the location of the fin trimming isolation (FTI) local fin cut. In an embodiment, the FTI local cut is made only at the locations where the multiple cut is made. However, in such an embodiment, the FTI cut may not necessarily be made at every location where the multiple cut is made.

[0287] Figure 25A and Figure 25B The diagram shows plan views illustrating various operations in a method for patterning a fin with a single gate spacing to form a local isolation structure in a selected gate line cut-out location, according to embodiments of the present disclosure.

[0288] refer to Figure 25A A method of manufacturing an integrated circuit structure includes forming a plurality of fins 2502, wherein an individual fin of the plurality of fins 2502 has the longest dimension along a first direction 2504. A plurality of gate structures 2506 are situated above the plurality of fins 2502, wherein an individual fin of the gate structures 2506 has the longest dimension along a second direction 2508 orthogonal to the first direction 2504. In an embodiment, the gate structure 2506 is, for example, a sacrificial or dummy gate line manufactured from polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0289] Refer again Figure 25AA dielectric material structure 2510 is formed between adjacent gate structures in a plurality of gate structures 2506. Portions 2512 and 2513 of two gate structures in the plurality of gate structures 2506 are removed to expose a portion of each of the plurality of fins 2502. In an embodiment, removing portions 2512 and 2513 of two gate structures in the gate structure 2506 involves using a photolithographic window wider than the width of each of portions 2512 and 2513 of the gate structure 2506. The exposed portion of each of the plurality of fins 2502 at location 2512 is removed to form a notch region 2520. In an embodiment, the exposed portion of each of the plurality of fins 2502 is removed using a dry or plasma etching process. However, the exposed portion of each of the plurality of fins 2502 at location 2513 is masked to prevent removal. In an embodiment, regions 2512 / 2520 represent both a multi-notch and a local fin notch in FTI. However, location 2513 only represents a multi-notch.

[0290] refer to Figure 25B The locations 2512 / 2520 of the multi-cut and FTI local fin cuts and the location 2513 of the multi-cut are filled with an insulating structure 2530, such as a dielectric plug. Exemplary insulating structures or "multi-cut" or "plug" structures are described below.

[0291] Figures 26A-26C The embodiments of the present disclosure are shown for... Figure 25B Cross-sectional views of various possibilities for dielectric plugs in different regions of the structure for multi-cut and FTI local fin cut locations, as well as for multi-cut locations only.

[0292] refer to Figure 26A ,along Figure 25B The a-a' axis of the structure shows a cross-sectional view of portion 2600A of the dielectric plug 2530 at position 2513. Portion 2600A of the dielectric plug 2530 is shown on the uncut fin 2502 and between the dielectric material structures 2510.

[0293] refer to Figure 26B ,along Figure 25B The b-b' axis of the structure shows a cross-sectional view of portion 2600B of the dielectric plug 2530 at position 2512. Portion 2600B of the dielectric plug 2530 is shown at the cut fin position 2520 and between the dielectric material structures 2510.

[0294] refer to Figure 26C ,along Figure 25BThe c-c' axis of the structure shows a cross-sectional view of a portion 2600C of the dielectric plug 2530 at location 2512. The portion 2600C of the dielectric plug 2530 is shown as a trench isolation structure 2602 between the fins 2502 and the dielectric material structure 2510. In the embodiment described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating filler material 2602C on the second insulating layer 2602B.

[0295] Common Reference Figure 25A , Figure 25B and Figures 26A-26C According to embodiments of this disclosure, a method of manufacturing an integrated circuit structure includes forming a plurality of fins, individual fins of the plurality of fins being along a first direction. A plurality of gate structures are formed on the plurality of fins, individual gate structures of the gate structures being along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent gate structures of the plurality of gate structures. A portion of a first gate structure of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins. A portion of a second gate structure of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed at the location of the removed first portion of the plurality of fins. A second insulating structure is formed at the location of the removed second portion of the plurality of gate structures.

[0296] In one embodiment, removing portions of the first and second gate structures of the plurality of gate structures involves using a photolithographic window wider than the width of each of the portions of the first and second gate structures of the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth less than the height of the plurality of fins. In such an embodiment, this depth is greater than the depth of the source or drain regions of the plurality of fins. In one embodiment, the plurality of fins comprises silicon fins and is continuous with a portion of the underlying silicon substrate.

[0297] Common Reference Figure 16A , Figure 25A , Figure 25B and Figures 26A-26CAccording to another embodiment of this disclosure, the integrated circuit structure includes a fin comprising silicon, the fin having a longest dimension along a first direction. An isolation structure is located above an upper portion of the fin, the isolation structure having a center along the first direction. A first gate structure is located above the upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure along the first direction by a distance. A second gate structure is located above the upper portion of the fin, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure along the first direction by the distance. A third gate structure is located above the upper portion of the fin on the side of the isolation structure opposite to the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure along the first direction by the distance.

[0298] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode located on and between the sidewalls of the high-k gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap located on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0299] In one embodiment, a first epitaxial semiconductor region is located on the upper portion of a fin between a first gate structure and an isolation structure. A second epitaxial semiconductor region is located on the upper portion of a fin between a first gate structure and a second gate structure. A third epitaxial semiconductor region is located on the upper portion of a fin between a third gate structure and an isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0300] Common Reference Figure 16A , Figure 25A , Figure 25B and Figures 26A-26CAccording to another embodiment of this disclosure, the integrated circuit structure includes a shallow trench isolation (STI) structure between pairs of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is located on the STI structure, having a center along the first direction. A first gate structure is located on the STI structure, having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure along the first direction by a distance. A second gate structure is located on the STI structure, having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure along the first direction by the distance. A third gate structure is located on the STI structure, on the side of the isolation structure opposite to the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure along the first direction by the distance.

[0301] In one embodiment, each of the first, second, and third gate structures includes a gate electrode located on and between the sidewalls of the high-k gate dielectric layer. In such an embodiment, each of the first, second, and third gate structures further includes an insulating cap located on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, the semiconductor fin pair is a silicon fin pair.

[0302] On the other hand, whether multiple notches and FTI local fin notches are together or only multiple notches are used, the insulating structure or dielectric plug used to fill the notch location can extend laterally into the dielectric spacer of the corresponding notch gate line, or even beyond the dielectric spacer of the corresponding notch gate line.

[0303] In the first example, the shape of the grooved contact portion is not affected by the multi-cut dielectric plug. Figure 27A Plan view and corresponding cross-sectional view of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer body according to an embodiment of the present disclosure are shown.

[0304] refer to Figure 27AThe integrated circuit structure 2700A includes a first silicon fin 2702 having the longest dimension along a first direction 2703. A second silicon fin 2704 also has the longest dimension along the first direction 2703. An insulating material 2706 is placed between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is placed above the first silicon fin 2702 and the second silicon fin 2704 along a second direction 2709, which is orthogonal to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and a first end 2708C and a second end 2708D. The gate line 2708 has a discontinuity 2710 above the insulating material 2706 and between the first end 2708C and the second end 2708D. The discontinuity 2710 is filled with a dielectric plug 2712.

[0305] The trench contact 2714 is located on the first silicon fin 2702 and the second silicon fin 2704 along the second direction 2709 at the first side 2708A of the gate line 2708. The trench contact 2714 is continuous on the insulating material 2706 at a position 2715 laterally adjacent to the dielectric plug 2712. The dielectric spacer 2716 is laterally located between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The width (W2) of the dielectric spacer 2716 laterally adjacent to the dielectric plug 2712 is thinner than the width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0306] In one embodiment, the second trench contact 2718 is positioned along a second direction 2709 on the second side 2708B of the gate line 2708, above the first silicon fin 2702 and the second silicon fin 2704. The second trench contact 2718 is continuous on the insulating material 2706 at a position 2719 laterally adjacent to the dielectric plug 2712. In such an embodiment, the second dielectric spacer 2720 is laterally located between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The width of the second dielectric spacer laterally adjacent to the dielectric plug 2712 is thinner than the width laterally adjacent to the second side 2708B of the gate line 2708.

[0307] In one embodiment, gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, dielectric plug 2712 comprises the same material as dielectric spacer 2714, but is discrete from dielectric spacer 2714. In one embodiment, dielectric plug 2712 comprises a different material than dielectric spacer 2714.

[0308] In the second example, the shape of the grooved contact is affected by the multi-cut dielectric plug. Figure 27B A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cutout with a dielectric plug extending beyond the dielectric spacer of the gate line, according to another embodiment of the present disclosure, are shown.

[0309] refer to Figure 27B The integrated circuit structure 2700B includes a first silicon fin 2752 having the longest dimension along a first direction 2753. A second silicon fin 2754 also has the longest dimension along the first direction 2753. An insulating material 2756 is placed between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is placed above the first silicon fin 2752 and the second silicon fin 2754 along a second direction 2759, which is orthogonal to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and a first end 2758C and a second end 2758D. The gate line 2758 has a discontinuity 2760 above the insulating material 2756 and between the first end 2758C and the second end 2758D. The discontinuity 2760 is filled with a dielectric plug 2762.

[0310] The trench contact 2764 is located on the first silicon fin 2752 and the second silicon fin 2754 along the second direction 2759 at the first side 2758A of the gate line 2758. The trench contact 2764 is continuous on the insulating material 2756 at a position 2765 laterally adjacent to the dielectric plug 2762. The dielectric spacer 2766 is laterally located between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is along the first side 2758A of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762 that is thinner than the width (W2) laterally adjacent to the dielectric spacer 2766.

[0311] In one embodiment, the second trench contact 2768 is located on the second side 2758B of the gate line 2758, over the first silicon fin 2752 and the second silicon fin 2754 along the second direction 2759. The second trench contact 2768 is continuous over the insulating material 2756 at a position 2769 laterally adjacent to the dielectric plug 2762. In such an embodiment, the second dielectric spacer 2770 is laterally located between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is along the second side 2758B of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. The width of the second trench contact 2768 laterally adjacent to the dielectric plug 2762 is thinner than the width laterally adjacent to the second dielectric spacer 2770.

[0312] In one embodiment, gate line 2758 includes a high-k dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, dielectric plug 2762 comprises the same material as dielectric spacer 2764 but is discrete from dielectric spacer 2764. In one embodiment, dielectric plug 2762 comprises a different material from dielectric spacer 2764.

[0313] In the third example, where the dielectric plug for multiple notch locations tapers gradually from the top to the bottom of the plug, Figures 28A-28F Cross-sectional views of various operations in a method of manufacturing an integrated circuit structure having a gate line cutout with a dielectric plug according to another embodiment of the present disclosure are shown, the dielectric plug having an upper portion extending outside the dielectric spacer of the gate line and a lower portion extending into the gate line dielectric spacer.

[0314] refer to Figure 28A Multiple gate lines 2802 are formed on structure 2804, such as on a trench isolation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, for example, having a dummy gate electrode 2806 and a dielectric cap 2808. A portion of such a sacrificial or dummy gate line can be replaced later in a gate replacement process, for example, after the dielectric plug formation described below. Dielectric spacers 2810 are placed along the sidewalls of the gate lines 2802. A dielectric material 2812, such as an inter-dielectric layer, is placed between the gate lines 2802. A mask 2814 is formed and photolithographically patterned to expose a portion of one of the gate lines 2802.

[0315] refer to Figure 28BWhen mask 2814 is in place, the central gate line 2802 is removed using an etching process. Then, mask 2814 is removed. In one embodiment, the etching process etches a portion of the dielectric spacer 2810 of the removed gate line 2802, thereby forming a reduced dielectric spacer 2816. Furthermore, the upper portion of the dielectric material 2812 exposed by mask 2814 is etched in the etching process, thereby forming an etched dielectric material portion 2818. In a particular embodiment, residual dummy gate material 2820, such as residual polysilicon, is retained in the structure as an artifact of an incomplete etching process.

[0316] refer to Figure 28C Hard mask 2822 is formed in Figure 28B On top of the structure. The hard mask 2822 can be used with Figure 28B The upper part of the structure is conformal, especially conformal with the corroded dielectric material part 2818.

[0317] refer to Figure 28D For example, an etching process can be used to remove residual dummy gate material 2820, which can be chemically similar to the etching process used to remove the center gate line in gate line 2802. In an embodiment, a hard mask 2822 protects the etched dielectric material portion 2818 from further etching during the removal of residual dummy gate material 2820.

[0318] refer to Figure 28E The hard mask 2822 is removed. In one embodiment, the hard mask 2822 is removed without or substantially without further corroding the corroded dielectric material portion 2818.

[0319] refer to Figure 28F Dielectric plug 2830 is formed in Figure 28E The upper portion of the dielectric plug 2830 is above the corroded dielectric material portion 2818, for example, effectively extending beyond the initial spacer 2810. The lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, effectively entering but not exceeding the initial spacer 2810. As a result, the dielectric plug 2830 has a tapered profile, such as... Figure 28F As shown in the diagram. It should be recognized that the dielectric plug 2830 can be manufactured from the materials and processes described above for other multi-cut or FTI plugs or fin end stress sources.

[0320] In another scenario, a portion of the occupier gate structure or dummy gate structure can be retained above the trench isolation region beneath the permanent gate structure, serving as a protective structure to prevent corrosion of the trench isolation region during gate replacement processes. For example... Figures 29A-29CA plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to an embodiment of the present disclosure, are shown.

[0321] refer to Figures 29A-29C The integrated circuit structure includes a fin 2902, such as a silicon fin, protruding from a semiconductor substrate 2904. The fin 2902 has a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top 2902C and a sidewall 2902D. An isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulating material 2906C having a top surface 2907. A semiconductor material 2908 is located on a portion of the top surface 2907 of the insulating material 2906C. The semiconductor material 2908 is separated from the fin 2902.

[0322] A gate dielectric layer 2910 is located above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further located on a semiconductor material 2908 on a portion of the top surface 2907 of the insulating material 2906C. An intercalary additional gate dielectric layer 2911, such as an oxide portion of the fin 2902, may be located between the gate dielectric layer 2910 above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. A gate electrode 2912 is located above the gate dielectric layer 2910 above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is further situated on a gate dielectric layer 2910 on a semiconductor material 2908 on a portion of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912, and a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side being opposite to the first side. In the embodiment described above, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulating material 2606C.

[0323] In one embodiment, the semiconductor material 2908 on a portion of the top surface 2907 of the insulating material 2906C is or comprises polycrystalline silicon. In one embodiment, the top surface 2907 of the insulating material 2906C has a concave depression, and as shown, the semiconductor material 2908 is located within this concave depression. In one embodiment, the isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A and 2906B) along the bottom and sidewalls of the insulating material 2906C. In such an embodiment, a portion of the second insulating material (2906A or 2906B or both 2906A and 2906B) along the sidewalls of the insulating material 2906C has a top surface located above the uppermost surface of the insulating material 2906, as shown. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A and 2906B) is higher than or coplanar with the uppermost surface of the semiconductor material 2908.

[0324] In one embodiment, the semiconductor material 2908 on a portion of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view perspective, the location of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along a first side of the gate electrode 2912. The second dielectric spacer 2922 is along a second side of the gate electrode 2912. In such an embodiment, the gate dielectric layer 2910 also extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, such as... Figure 29B As shown.

[0325] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive fill metal layer 2912B over the work function layer 2912A. In one such embodiment, the conductive fill metal layer 2912B includes tungsten. In a particular embodiment, the conductive fill metal layer 2912B includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, an insulating cap 2924 is on the gate electrode 2912 and may extend over the gate dielectric layer 2910, such as... Figure 29B As shown.

[0326] Figures 30A-30DCross-sectional views of various operations in a method for fabricating an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to another embodiment of this disclosure, are shown. Perspective views along... Figure 29C The a-a' axis portion of the structure.

[0327] refer to Figure 30A A method for manufacturing an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top 3000C and a sidewall 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A occupier gate electrode 3006 is located above the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The occupier gate electrode 3006 comprises a semiconductor material.

[0328] Despite from Figure 30A The angle is not shown (but) Figure 29C (The location of the part is shown in the figure). A first source or drain region can be formed adjacent to the first side of the occupier gate electrode 3006, and a second source or drain region can be formed adjacent to the second side of the occupier gate electrode 3006, the second side being opposite to the first side. In addition, a gate dielectric spacer can be formed along the sidewall of the occupier gate electrode 3006, and an interlayer dielectric (ILD) layer can be formed laterally adjacent to the occupier gate electrode 3006.

[0329] In one embodiment, the occupier gate electrode 3006 is or comprises polysilicon. In one embodiment, the top surface 3005 of the insulating material 3004C of the isolation structure 3004 has a concave depression, as shown. A portion of the occupier gate electrode 3006 is located in this concave depression. In one embodiment, the isolation structure 3004 includes a second insulating material (3004A or 3004B or both 3004A and 3004B) along the bottom and sidewalls of the insulating material 3004C, as shown. In such an embodiment, a portion of the second insulating material (3004A or 3004B or both 3004A and 3004B) along the sidewall of the insulating material 3004C has a top surface above at least a portion of the top surface 3005 of the insulating material 3004C. In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A and 3004B) is located above the lowest surface of a portion of the occupier gate electrode 3006.

[0330] refer to Figure 30BFor example, along Figure 30A The placeholder gate electrode 3006 is etched from the top 3000C and sidewall 3000D of the upper fin portion 3000B in direction 3008. This etching process can be referred to as a gate replacement process. In an embodiment, the etching or gate replacement process is not completed, and a portion 3012 of the placeholder gate electrode 3006 is left on at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0331] refer to Figure 30A and Figure 30B In one embodiment, the oxide portion 3010 of the upper fin portion 3000B formed before the formation of the placeholder gate electrode 3006 is retained during the etching process, as shown. However, in another embodiment, a placeholder gate dielectric layer is formed before the formation of the placeholder gate electrode 3006 and is removed after etching the placeholder gate electrode.

[0332] refer to Figure 30C A gate dielectric layer 3014 is formed on the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed on the oxide portion 3010 of the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, as shown. In another embodiment, where the oxide portion 3010 of the upper fin portion 3000B is removed after etching the placeholder gate electrode, the gate dielectric layer 3014 is formed directly on the upper fin portion 3000B, on the top 3000C of the upper fin portion 3000B, and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In any case, in the embodiments, the gate dielectric layer 3014 is further formed on a portion 3012 of the occupier gate electrode 3006 on a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0333] refer to Figure 30D A permanent gate electrode 3016 is formed on the gate dielectric layer 3014 above the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further formed on the gate dielectric layer 3014 on the portion 3012 of the occupier gate electrode 3006 on the top surface 3005 of the insulating material 3004C.

[0334] In one embodiment, forming a permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A comprises titanium and nitrogen. In another such embodiment, the work function layer 3016A comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, forming a permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B over the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In an embodiment, an insulating gate cap layer 3018 is formed on the permanent gate electrode 3016.

[0335] In another aspect, some embodiments of this disclosure include an amorphous high-k layer for a gate electrode in a gate dielectric structure. In other embodiments, the gate dielectric structure includes a partially or fully crystalline high-k layer for a gate electrode. In one embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0336] In the embodiments, this document describes ways to increase the charge in the device channel and improve subthreshold behavior by employing ferroelectric or antiferroelectric gate oxides. Ferroelectric and antiferroelectric gate oxides can increase channel charge to achieve higher currents and also produce steeper turn-on behavior.

[0337] To provide context, hafnium or zirconium (Hf or Zr)-based ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconium titanate (PZT), thus enabling compatibility with highly scalable logic technologies. FE or AFE materials possess two characteristics that improve logic transistor performance: (1) higher charge in the channel achieved through FE or AFE polarization, and (2) steeper conduction behavior due to sharp FE or AFE transitions. These properties can improve transistor performance by increasing current and reducing subthreshold sway (SS).

[0338] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is shown.

[0339] refer to Figure 31AThe integrated circuit structure 3100 includes a gate structure 3102 above a substrate 3104. In one embodiment, the gate structure 3102 is above or on a semiconductor channel structure 3106 comprising a single-crystal material such as single-crystal silicon. The gate structure 3102 includes a gate dielectric over the semiconductor channel structure 3106 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and may be a barrier layer, a work function layer, or a template layer that enhances the crystallinity of the FE or AFE layer. One or more gate fill layers 3102C are on or above the conductive layer 3102B. A source region 3108 and a drain region 3110 are on opposite sides of the gate structure 3102. The source or drain contact 3112 is electrically connected to the source region 3108 and the drain region 3110 at position 3149, and is spaced apart from the gate structure 3102 by an interlayer dielectric layer 3114 or a gate dielectric spacer 3116. Figure 31A In the example, source region 3108 and drain region 3110 are regions of substrate 3104. In an embodiment, source or drain contact 3112 includes a barrier layer 3112A and a conductive trench filler 3112B. In one embodiment, a ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along the dielectric spacer 3116, such as... Figure 31A As shown.

[0340] In the embodiments, and throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, having a Zr:Hr ratio of 50:50 or having more Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0341] In the embodiments, and throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, having a Zr:Hr ratio of 80:20 or having more Zr, even up to 100% Zr, ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0342] In embodiments, and throughout the disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-k dielectric (HfOx, Al2O3, etc.), or a combination of oxide and high-k, between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In embodiments, and throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness ranging from 1 nanometer to 8 nanometers. In embodiments, and throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size generally in the range of 20 nanometers or larger.

[0343] In one embodiment, after depositing a ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example by atomic layer deposition (ALD), a layer comprising a metal (e.g., layer 3102B, such as 5-10 nm titanium nitride, tantalum nitride, or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Annealing is then performed. In one embodiment, annealing is performed over a time period ranging from 1 millisecond to 30 minutes. In another embodiment, annealing is performed at a temperature ranging from 500 to 1100 degrees Celsius.

[0344] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is shown.

[0345] refer to Figure 31BThe integrated circuit structure 3150 includes a gate structure 3152 above a substrate 3154. In one embodiment, the gate structure 3152 is above or on a semiconductor channel structure 3156 comprising a single-crystal material such as single-crystal silicon. The gate structure 3152 includes a gate dielectric over the semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may also include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B on the ferroelectric or antiferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are on or above the conductive layer 3152B. A raised source region 3158 and a raised drain region 3160 (e.g., regions of semiconductor material different from the semiconductor channel structure 3156) are on opposite sides of the gate structure 3152. Source or drain contact 3162 is electrically connected at location 3199 to source region 3158 and drain region 3160, and is spaced from gate structure 3152 by one or both of interlayer dielectric layer 3164 or gate dielectric spacer 3166. In an embodiment, source or drain contact 3162 includes barrier layer 3162A and conductive trench filler 3162B. In one embodiment, ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along dielectric spacer 3166, such as... Figure 31B As shown.

[0346] Figure 32A A plan view of a plurality of gate lines on a pair of semiconductor fins according to another embodiment of the present disclosure is shown.

[0347] refer to Figure 32A Multiple active gate lines 3204 are formed on multiple semiconductor fins 3200. Dummy gate lines 3206 are located at the ends of the multiple semiconductor fins 3200. The spacing 3208 between the gate lines 3204 / 3206 is a location where trench contacts can be positioned to provide conductive contacts to source or drain regions (e.g., source or drain regions 3251, 3252, 3253, and 3254). In embodiments, the pattern of the multiple gate lines 3204 / 3206 or the pattern of the multiple semiconductor fins 3200 is described as a grid structure. In one embodiment, the grid pattern includes multiple gate lines 3204 / 3206 spaced at a constant pitch and having a constant width, or a pattern of multiple semiconductor fins 3200, or both.

[0348] Figure 32B The following is illustrated according to an embodiment of the present disclosure. Figure 32A A cross-sectional view taken along the a-a' axis.

[0349] refer to Figure 32B Multiple active gate lines 3264 are formed on a semiconductor fin 3262 formed above a substrate 3260. Dummy gate lines 3266 are located at the ends of the semiconductor fin 3262. A dielectric layer 3270 is located outside the dummy gate lines 3266. Trench contact material 3297 is located between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. An embedded source or drain structure 3268 is located in the semiconductor fin 3262, between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0350] The active gate line 3264 includes a gate dielectric structure 3272, a work function gate electrode portion 3274, a filled gate electrode portion 3276, and a dielectric cap layer 3278. Dielectric spacers 3280 are arranged along the sidewalls of the active gate line 3264 and the dummy gate line 3266. In one embodiment, the gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299.

[0351] In another respect, devices of the same conductivity type (e.g., N-type or P-type) can have differentiated gate electrode stacks for the same conductivity type. However, for contrast purposes, devices of the same conductivity type can have differentiated voltage thresholds (VT) based on modulated doping.

[0352] Figure 33A Cross-sectional views of an NMOS device pair and a PMOS device pair according to embodiments of the present disclosure are shown, the NMOS device pair having a differentiated voltage threshold based on modulated doping, and the PMOS device pair having a differentiated voltage threshold based on modulated doping.

[0353] refer to Figure 33AA first NMOS device 3302 is adjacent to a second NMOS device 3304 on a semiconductor active region 3300 (e.g., on a silicon fin or substrate). Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308 (e.g., a work function layer), and a gate electrode conductive fill 3310. In an embodiment, the first gate electrode conductive layer 3308 of the first NMOS device 3302 and the second NMOS device 3304 have the same material and the same thickness, thus having the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a "standard VT" device, and the second NMOS device 3304 is referred to as a "high VT" device. In an embodiment, differentiated VT is achieved by using modulated doping or differentiated implantation doping in region 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0354] Refer again Figure 33A A first PMOS device 3322 is adjacent to a second PMOS device 3324 on a semiconductor active region 3320 (e.g., on a silicon fin or substrate). Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 (e.g., a work function layer), and a gate electrode conductive fill 3330. In an embodiment, the first gate electrode conductive layer 3328 of the first PMOS device 3322 and the second PMOS device 3324 have the same material and the same thickness, thus having the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a "standard VT" device, and the second PMOS device 3324 is referred to as a "low VT" device. In an embodiment, differentiated VT is achieved by using modulated doping or differentiated implantation doping in region 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0355] and Figure 33A compared to, Figure 33B Cross-sectional views of an NMOS device pair and a PMOS device pair according to another embodiment of the present disclosure are shown. The NMOS device pair has a differentiated voltage threshold based on a differentiated gate electrode structure, and the PMOS device pair has a differentiated voltage threshold based on a differentiated gate electrode structure.

[0356] refer to Figure 33BA first NMOS device 3352 is adjacent to a second NMOS device 3354 on a semiconductor active region 3350 (e.g., on a silicon fin or substrate). Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3352 includes a first gate electrode conductive layer 3358, such as a first work function layer, and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359, such as a second work function layer, a first gate electrode conductive layer 3358, and a gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0357] Refer again Figure 33B A first PMOS device 3372 is adjacent to a second PMOS device 3374 on a semiconductor active region 3370 (e.g., on a silicon fin or substrate). Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness, and a gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layer 3378A and the gate electrode conductive layer 3378B have the same composition, but the thickness of the gate electrode conductive layer 3378B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3378A (the first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In this embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0358] Refer again Figure 33BAccording to embodiments of this disclosure, the integrated circuit structure includes a fin (e.g., a silicon fin, such as 3350). It should be appreciated that the fin has a top (as shown) and sidewalls (entry and exit). A gate dielectric layer 3356 is located above the top of the fin and laterally adjacent to the sidewalls of the fin. An N-type gate electrode of device 3354 is located above the gate dielectric layer 3356 above the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. It will be appreciated that a first N-type source or drain region may be adjacent to a first side (e.g., entry) of the gate electrode, and a second N-type source or drain region may be adjacent to a second side (e.g., exit) of the gate electrode, the second side being opposite to the first side.

[0359] In one embodiment, the P-type metal layer 3359 comprises titanium and nitrogen, and the N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2-12 angstroms, and in a particular embodiment, the P-type metal layer 3359 has a thickness in the range of 2-4 angstroms. In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 on the N-type metal layer 3358. In one such embodiment, the conductive fill metal layer 3360 comprises tungsten. In a particular embodiment, the conductive fill metal layer 3360 comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

[0360] Refer again Figure 33B According to another embodiment of this disclosure, the integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), a first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on the first gate dielectric layer 3356. Furthermore, it also includes a second N-type device 3354 having a voltage threshold (VT), a second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0361] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 comprises titanium and nitrogen.

[0362] Refer again Figure 33B According to another embodiment of this disclosure, the integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), a first P-type device 3372 having a first gate dielectric layer 3376, and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. A second P-type device 3378 is also included and has a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness greater than the thickness of the first P-type metal layer 3378A.

[0363] In one embodiment, the VT of the second P-type device 3374 is lower than that of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B comprise titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B comprises a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and a seam is formed between the first metal film and the second metal film.

[0364] Refer again Figure 33B According to another embodiment of this disclosure, the integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. The first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. The second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than the thickness of the second P-type metal layer 3378A.

[0365] In one embodiment, a first N-type device 3352 has a voltage threshold (VT), a second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, a first P-type device 3372 has a voltage threshold (VT), a second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, a third P-type metal layer 3378B includes a first metal film on a second metal film, and a seam is formed between the first metal film and the second metal film.

[0366] It should be recognized that more than two types of VT devices for the same conductivity type can be included in the same structure (e.g., on the same die). In the first example, Figure 34A Cross-sectional views of three NMOS devices and three PMOS devices according to embodiments of the present disclosure are shown. The three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0367] refer to Figure 34AThe first NMOS device 3402 is adjacent to the second NMOS device 3404 and the third NMOS device 3403 on the semiconductor active region 3400 (e.g., on a silicon fin or substrate). The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from that of the first NMOS device 3402 and the third NMOS device 3403. Specifically, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408 (e.g., a first work function layer) and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409 (e.g., a second work function layer), a first gate electrode conductive layer 3408, and a gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In this embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In this embodiment, the third NMOS device 3403 has a different VT than the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as that of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device is between the VT of the first NMOS device 3402 and the VT of the second NMOS device 3404. In this embodiment, the differentiated VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using modulated doping or differentiated implanted doping at region 3412 of the third NMOS device 3403. In one such embodiment, the third N-type device 3403 has a channel region with a dopant concentration different from that of the channel region of the first N-type device 3402.

[0368] Refer again Figure 34AA first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 on a semiconductor active region 3420 (e.g., on a silicon fin or substrate). The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have structurally identical or similar gate electrode stacks. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from that of the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3408A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness, and a gate electrode conductive fill 3430. In one embodiment, gate electrode conductive layers 3428A and 3428B have the same composition, but the thickness of gate electrode conductive layer 3428B (second thickness) is greater than the thickness of gate electrode conductive layer 3428A (first thickness). In another embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In such an embodiment, the first PMOS device 3422 is referred to as a "standard VT" device, and the second PMOS device 3424 is referred to as a "low VT" device. In another embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In another embodiment, the third PMOS device 3423 has a different VT than the first PMOS device 3422 and the second PMOS device 3424, even though the gate electrode structure of the third PMOS device 3423 is the same as the gate electrode structure of the first PMOS device 3422. In one embodiment, the VT of the third PMOS device 3423 is between the VT of the first PMOS device 3422 and the VT of the second PMOS device 3424. In an embodiment, the differential VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using modulated doping or differential implantation doping in region 3432 of the third PMOS device 3423. In one such embodiment, the channel region of the third P-type device 3423 has a dopant concentration different from that of the channel region of the first P-type device 3422.

[0369] In the second example, Figure 34BCross-sectional views of three NMOS devices and three PMOS devices according to another embodiment of the present disclosure are shown. The three NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and the three PMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping.

[0370] refer to Figure 34B A first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 on a semiconductor active region 3450 (e.g., on a silicon fin or substrate). The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from that of the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458 (e.g., a first work function layer) and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459 (e.g., a second work function layer), a first gate electrode conductive layer 3458, and a gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In this embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In this embodiment, the third NMOS device 3453 has a different VT than the first NMOS device 3452 and the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as that of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VT of the first NMOS device 3452 and the second NMOS device 3454. In this embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using modulated doping or differentiated implanted doping at region 3462 of the third NMOS device 3453. In one such embodiment, the channel region of the third N-type device 3453 has a dopant concentration that is different from that of the channel region of the second N-type device 3454.

[0371] Refer again Figure 34B A first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 on a semiconductor active region 3470 (e.g., on a silicon fin or substrate). The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have structurally identical or similar gate electrode stacks. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from that of the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness, and a gate electrode conductive fill 3480. In one embodiment, gate electrode conductive layers 3478A and 3478B have the same composition, but the thickness of gate electrode conductive layer 3478B (second thickness) is greater than the thickness of gate electrode conductive layer 3478A (first thickness). In another embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In such an embodiment, the first PMOS device 3472 is referred to as a "standard VT" device, and the second PMOS device 3474 is referred to as a "low VT" device. In another embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In another embodiment, the third PMOS device 3473 has a different VT than the first PMOS device 3472 and the second PMOS device 3474, even though the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VT of the first PMOS device 3472 and the VT of the second PMOS device 3474. In an embodiment, the differential VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using modulated doping or differential implantation doping in region 3482 of the third PMOS device 3473. In one such embodiment, the channel region of the third P-type device 3473 has a dopant concentration different from that of the channel region of the second P-type device 3474.

[0372] Figures 35A-35D Cross-sectional views are shown of various operations in a method for manufacturing an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to embodiments of the present disclosure.

[0373] refer to Figure 35A The “Standard VT NMOS” region (STD VT NMOS) and the “High VT NMOS” region (HIGH VT NMOS) are shown to branch on a common substrate. The method of fabricating the integrated circuit structure includes forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and a second semiconductor fin 3504 (e.g., over the first and second silicon fins). A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and the second semiconductor fin 3504.

[0374] refer to Figure 35B A portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502, but a portion 3509 of the P-type metal layer 3508 remains on the gate dielectric layer 3506 above the second semiconductor fin 3504.

[0375] refer to Figure 35C An N-type metal layer 3510 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502, and on a portion 3509 of the P-type metal layer on the gate dielectric layer 3506 above the second semiconductor fin 3504. In an embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) on the first semiconductor fin 3502, and forming a second N-type device having a voltage threshold (VT) on the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0376] refer to Figure 35D In one embodiment, a conductive filler metal layer 3512 is formed on an N-type metal layer 3510. In one such embodiment, forming the conductive filler metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0377] Figures 36A-36D Cross-sectional views are shown of various operations in a method for manufacturing a PMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to embodiments of the present disclosure.

[0378] refer to Figure 36AThe “Standard VT PMOS” region (STD VT PMOS) and the “Low VT PMOS” region (LOW VT PMOS) are shown to branch on a common substrate. The method of fabricating the integrated circuit structure includes forming a gate dielectric layer 3606 on a first semiconductor fin 3602 and a second semiconductor fin 3604 (e.g., on the first and second silicon fins). A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 on the first semiconductor fin 3602 and the second semiconductor fin 3604.

[0379] refer to Figure 36B A portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602, but a portion 3609 of the first P-type metal layer 3608 remains on the gate dielectric layer 3606 above the second semiconductor fin 3604.

[0380] refer to Figure 36C A second P-type metal layer 3610 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602, and on a portion 3609 of the first P-type metal layer on the gate dielectric layer 3606 above the second semiconductor fin 3604. In an embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) on the first semiconductor fin 3602, and forming a second P-type device having a voltage threshold (VT) on the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0381] In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same composition. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, a seam 3611 is located between the first P-type metal layer 3608 and the second P-type metal layer 3610, as shown.

[0382] refer to Figure 36D In one embodiment, a conductive filler metal layer 3612 is formed on top of a P-type metal layer 3610. In one such embodiment, forming the conductive filler metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, an N-type metal layer 3614 is formed on the P-type metal layer 3610 prior to forming the conductive filler metal layer 3612, as shown. In one such embodiment, the N-type metal layer 3614 is an artifact of a bimetallic gate replacement process.

[0383] In another aspect, a metal gate structure for a complementary metal-oxide-semiconductor (CMOS) semiconductor device is described. In the example, Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is shown.

[0384] refer to Figure 37 The integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 and a P-well region 3708. The N-well region 3704 has a first semiconductor fin 3706 protruding therefrom, and the P-well region 3708 has a second semiconductor fin 3710 protruding therefrom. The first semiconductor fin 3706 and the second semiconductor fin 3710 are spaced apart. The N-well region 3704 and the P-well region 3708 are directly adjacent in the semiconductor substrate 3702. A trench isolation structure 3712 is located on the semiconductor substrate 3702, outside and between the first semiconductor fin 3706 and the second semiconductor fin 3710. The first fin 3706 and the second fin 3710 extend over the trench isolation structure 3712.

[0385] A gate dielectric layer 3714 is located on the first semiconductor fin 3706 and the second semiconductor fin 3710 and on the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first semiconductor fin 3706 and the second semiconductor fin 3710. A conductive layer 3716 is located on the gate dielectric layer 3714 above the first semiconductor fin 3706, but not on the gate dielectric layer 3714 above the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is located on the conductive layer 3716 above the first semiconductor fin 3706, but not on the conductive layer 3716 above the second semiconductor fin 3710. The p-type metal gate layer 3718 is further located on a portion, but not all, of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. The N-type metal gate layer 3720 is on the second semiconductor fin 3710, on the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and on the p-type metal gate layer 3718.

[0386] In one embodiment, an interlayer dielectric (ILD) layer 3722 is located above a trench isolation structure 3712 on the exterior of the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first 3706 and the second 3710 semiconductor fins. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along the sidewall 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 that lies below the top surface 3719 of the p-type metal gate layer 3718 along the sidewall 3726 of the opening 3724 and below the top surface 3721 of the n-type metal gate layer 3720 along the sidewall 3726 of the opening 3724, as shown.

[0387] In one embodiment, the p-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 comprises titanium and aluminum. In one embodiment, a conductive fill metal layer 3730 is situated above the n-type metal layer 3720, as shown. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In a particular embodiment, the conductive fill metal layer 3730 comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 has a layer comprising hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is situated between the upper portions of the first 3706 and the second 3710 semiconductor fins, as shown. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0388] For reference only. Figure 37 On the right side, according to an embodiment of the present disclosure, the integrated circuit structure includes a semiconductor substrate 3702, which includes an N-well region 3704 having semiconductor fins 3706 protruding therefrom. A trench isolation structure 3712 is on the semiconductor substrate 3702 and surrounds the semiconductor fins 3706. The semiconductor fins 3706 extend over the trench isolation structure 3712. A gate dielectric layer 3714 is on the semiconductor fins 3706. A conductive layer 3716 is on the gate dielectric layer 3714 on the semiconductor fins 3706. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is on the conductive layer 3716 on the semiconductor fins 3706.

[0389] In one embodiment, an interlayer dielectric (ILD) layer 3722 is located above a trench isolation structure 3712. The ILD layer has an opening that exposes a semiconductor fin 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewall of the opening, which is lower than the top surface of the P-type metal gate layer 3718 along the sidewall of the opening. In one embodiment, the P-type metal gate layer 3718 is located above the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is located above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In a particular embodiment, the conductive fill metal layer 3730 is composed of 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, a gate dielectric layer 3714 comprises a layer containing hafnium and oxygen.

[0390] Figures 38A-38H Cross-sectional views are shown of various operations in a method for fabricating an integrated circuit structure using a dual-metal gate replacement gate process flow according to embodiments of the present disclosure.

[0391] refer to Figure 38A The diagram illustrates NMOS (N-type) and PMOS (P-type) regions. A method for fabricating an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 over first 3804 and second 3806 semiconductor fins above a substrate 3800. An opening 3808 is formed in the ILD layer 3802, exposing the first 3804 and second 3806 semiconductor fins. In one embodiment, the opening 3808 is formed by removing a gate occupier or dummy gate structure initially present above the first 3804 and second 3806 semiconductor fins.

[0392] A gate dielectric layer 3810 is formed in the opening 3808 and on a portion of the trench isolation structure 3812 above and between the first 3804 and the second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed on a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, formed on the first 3804 and the second 3806 semiconductor fins, as shown. In another embodiment, the gate dielectric layer 3810 is formed directly on the first 3804 and the second 3806 semiconductor fins.

[0393] A conductive layer 3814 is formed on the gate dielectric layer 3810 formed on the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed on the conductive layer 3814 formed on the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0394] refer to Figure 38B A dielectric etch stop layer 3818 is formed on a p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first silicon oxide (e.g., SiO2) layer, an aluminum oxide layer (e.g., Al2O3) on the first silicon oxide layer, and a second silicon oxide (e.g., SiO2) layer on the aluminum oxide layer.

[0395] refer to Figure 38C Mask 3820 is formed in Figure 38B The structure is above the PMOS region. Mask 3820 covers the PMOS region and exposes the NMOS region.

[0396] refer to Figure 38D The dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819 and a patterned p-type metal gate layer 3817 on a patterned conductive layer 3815 over the first semiconductor fin 3804 but not over the second semiconductor fin 3806. In an embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during patterning.

[0397] refer to Figure 38E ,from Figure 38D The structure was removed using a mask 3820. (Reference) Figure 38F ,from Figure 38E The structure removes the patterned dielectric etch stop layer 3819.

[0398] refer to Figure 38GAn n-type metal gate layer 3822 is formed on the second semiconductor fin 3806, on a portion of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and on a patterned p-type metal gate layer 3817. In an embodiment, a patterned conductive layer 3815, a patterned p-type metal gate layer 3817, and an n-type metal gate layer 3822 are further formed along the sidewall 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface that is located below the top surface of the patterned p-type metal gate layer 3817 along the sidewall 3824 of the opening 3808 and below the top surface of the n-type metal gate layer 3822 along the sidewall 3824 of the opening 3808.

[0399] refer to Figure 38H A conductive filler metal layer 3826 is formed on top of an n-type metal layer 3822. In one embodiment, the conductive filler metal layer 3826 is formed by depositing a tungsten-containing film using a tungsten hexafluoride (WF6) precursor via atomic layer deposition (ALD).

[0400] In another aspect, a double silicide structure for complementary metal-oxide-semiconductor (CMOS) semiconductor devices is described. As an exemplary process flow, Figures 39A-39H Cross-sectional views are shown illustrating various operations in a method for manufacturing a dual-silicide-based integrated circuit according to embodiments of the present disclosure.

[0401] refer to Figure 39A The NMOS and PMOS regions are shown to branch off on a common substrate. A method of fabricating an integrated circuit structure includes forming a first gate structure 3902, which may include dielectric sidewall spacers 3903 on a first fin 3904, such as a first silicon fin. A second gate structure 3952, which may include dielectric sidewall spacers 3953, is formed on a second fin 3954, such as a second silicon fin. An insulating material 3906 is formed adjacent to the first gate structure 3902 on the first fin 3904 and adjacent to the second gate structure 3952 on the second fin 3954. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask during a double silicide process.

[0402] refer to Figure 39BA first portion of the insulating material 3906 is removed from the first fin 3904 but not from the second fin 3954 to expose the first fin 3904's first 3908 and second 3910 source or drain regions adjacent to the first gate structure 3902. In an embodiment, the first 3908 and second 3910 source or drain regions are epitaxial regions formed within a recessed portion of the first fin 3904, as shown. In one such embodiment, the first 3908 and second 3910 source or drain regions comprise silicon and germanium.

[0403] refer to Figure 39C A first metal silicide layer 3912 is formed on the first 3908 and second 3910 source or drain regions of the first fin 3904. In one embodiment, by... Figure 39B A layer comprising nickel and platinum is deposited on the structure, the layer comprising nickel and platinum is annealed, and unreacted portions of the layer comprising nickel and platinum are removed to form a first metal silicide layer 3912.

[0404] refer to Figure 39D After forming the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed from the second fin 3954 to expose the third 3958 and fourth 3960 source or drain regions of the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the second 3958 and third 3960 source or drain regions are formed within the second fin 3954, for example, within a second silicon fin, as shown. However, in another embodiment, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within a recessed portion of the second fin 3954. In one such embodiment, the third 3958 and fourth 3960 source or drain regions comprise silicon.

[0405] refer to Figure 39E The first metal layer 3914 is formed on Figure 39D Structurally, that is, on the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions. A second metal silicide layer 3962 is then formed on the third 3958 and fourth 3960 source or drain regions of the second fin 3954. For example, the second metal silicide layer 3962 is formed from the first metal layer 3914 using an annealing process. In an embodiment, the composition of the second metal silicide layer 3962 differs from the composition of the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, for example, with... Figure 39D The opening grooves are conformal, as shown in the figure.

[0406] refer to Figure 39FIn one embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 over each of the source or drain regions of the first 3908, second 3910, third 3958, and fourth 3960.

[0407] refer to Figure 39G In the embodiment, the second metal layer 3918 is formed on Figure 39F The structure is on a U-shaped metal layer 3916. In an embodiment, the composition of the second metal layer 3918 is different from that of the U-shaped metal layer 3916.

[0408] refer to Figure 39H In the embodiment, the third metal layer 3920 is formed on Figure 39G The third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0409] Refer again Figure 39H According to embodiments of this disclosure, the integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) above a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be understood that the first fin has a top (shown as 3904A) and sidewalls (entry and exit pages). A first gate electrode 3902 includes a first gate dielectric layer located above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and includes a first gate electrode located above the first gate dielectric layer located above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite to the first side 3902A.

[0410] The first semiconductor source or drain regions 3908 and 3910 are adjacent to the first 3902A and 3902B sides of the first gate electrode 3902, respectively. The first trench contact structures 3930 and 3932 are respectively located on the first semiconductor source or drain regions 3908 and 3910 adjacent to the first 3902A and 3902B sides of the first gate electrode 3902. The first metal silicide layer 3912 is directly between the first trench contact structures 3930 and 3932 and the first semiconductor source or drain regions 3908 and 3910, respectively.

[0411] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be understood that the second fin has a top (shown as 3954A) and sidewalls (entry and exit points). A second gate electrode 3952 includes a second gate dielectric layer located above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954, and includes a second gate electrode located above the second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite to the first side 3952A.

[0412] The third 3958 and fourth 3960 semiconductor source or drain regions are adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. The third 3970 and fourth 3972 trench contact structures are respectively located on the third 3958 and fourth 3960 semiconductor source or drain regions adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952. The second metal silicide layer 3962 is directly between the third 3970 and fourth 3972 trench contact structures and the third 3958 and fourth 3960 semiconductor source or drain regions. In an embodiment, the first metal silicide layer 3912 includes at least one metal type not included in the second metal silicide layer 3962.

[0413] In one embodiment, the second metal silicide layer 3962 comprises titanium and silicon. The first metal silicide layer 3912 comprises nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 further comprises germanium. In one embodiment, the first metal silicide layer 3912 further comprises titanium, for example, incorporated into the first metal silicide layer 3912 during the subsequent formation of the second metal silicide layer 3962 using the first metal layer 3914. In one such embodiment, the silicide layer already formed on the PMOS source or drain region is further modified by the annealing process used to form silicide regions on the NMOS source or drain region. This may result in the silicide layer on the PMOS source or drain region having a very small percentage of all silicide metals. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region is not used in the annealing process for forming silicide regions on the NMOS source or drain region, or is substantially unchanged.

[0414] In one embodiment, the first 3908 and second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In such an embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are formed in the fin 3954 and are not embedded epitaxial regions.

[0415] In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 on and over the U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 includes titanium, and the T-shaped metal layer 3918 includes cobalt. In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all include a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer include titanium, and the T-shaped metal layer 3918 includes cobalt.

[0416] In another aspect, trench contact structures, for example, for the source or drain regions, are described. In the example, Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to an embodiment of the present disclosure is shown. Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device is shown according to another embodiment of the present disclosure.

[0417] refer to Figure 40AThe integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is on the fin 4002. A gate electrode 4006 is on the gate dielectric layer 4004. In an embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In an embodiment, a dielectric cap 4012 is on the gate electrode 4006 and on the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite to the first side 4006A. A dielectric spacer 4013 is along the sidewall of the gate electrode 4006. In one embodiment, the gate dielectric layer 4004 is further between a first dielectric spacer 4013 and the first side 4006A of the gate electrode 4006, and between a second dielectric spacer 4013 and the second side 4006B of the gate electrode 4006, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is present between the fin 4002 and the gate dielectric layer 4004.

[0418] The first 4014 and the second 4016 semiconductor source or drain regions are adjacent to the first 4006A and the second 4006B sides of the gate electrode 4006, respectively. In one embodiment, the first 4014 and the second 4016 semiconductor source or drain regions are in the fin 4002, as shown. However, in another embodiment, the first 4014 and the second 4016 semiconductor source or drain regions are embedded epitaxial regions formed in the recesses of the fin 4002.

[0419] The first 4018 and the second 4020 trench contact structures are respectively located above the first 4014 and the second 4016 semiconductor source or drain regions adjacent to the first 4006A and the second 4006B sides of the gate electrode 4006. Both the first 4018 and the second 4020 trench contact structures include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 on and around the U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In one such embodiment, the U-shaped metal layer 4022 comprises titanium, and the T-shaped metal layer 4024 comprises cobalt. In one embodiment, both the first 4018 and the second 4020 trench contact structures include a third metal layer 4026 on the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 comprise titanium, and the T-shaped metal layer 4024 comprises cobalt.

[0420] A first trench contact via 4028 is electrically connected to a first trench contact portion 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to a third metal layer 4026 of the first trench contact portion 4018. The first trench contact via 4028 further lies on and contacts a portion of one of the dielectric spacers 4013 and a portion of the dielectric cap 4012. A second trench contact via 4030 is electrically connected to a second trench contact portion 4020. In a particular embodiment, the second trench contact via 4030 lies on and couples to the third metal layer 4026 of the second trench contact portion 4020. The second trench contact via 4030 further lies on and contacts a portion of another of the dielectric spacers 4013 and another portion of the dielectric cap 4012.

[0421] In one embodiment, the metal silicide layer 4032 is directly between the first 4018 and the second 4020 trench contact structures and the first 4014 and the second 4016 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4032 comprises titanium and silicon. In this particular embodiment, the first 4014 and the second 4016 semiconductor source or drain regions are first and second N-type semiconductor source or drain regions.

[0422] refer to Figure 40B The integrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is on the fin 4052. A gate electrode 4056 is on the gate dielectric layer 4054. In an embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060. In an embodiment, a dielectric cap 4062 is on the gate electrode 4056 and on the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite to the first side 4056A. A dielectric spacer 4063 is along the sidewall of the gate electrode 4056. In one embodiment, the gate dielectric layer 4054 is further between a first dielectric spacer 4063 and the first side 4056A of the gate electrode 4056, and between a second dielectric spacer 4063 and the second side 4056B of the gate electrode 4056, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is present between the fin 4052 and the gate dielectric layer 4054.

[0423] The first 4064 and the second 4066 semiconductor source or drain regions are adjacent to the first 4056A and the second 4056B sides of the gate electrode 4056, respectively. In one embodiment, the first 4064 and the second 4066 semiconductor source or drain regions are embedded epitaxial regions formed in the recesses 4065 and 4067 of the fin 4052, respectively, as shown. However, in another embodiment, the first 4064 and the second 4066 semiconductor source or drain regions are within the fin 4052.

[0424] The first 4068 and the second 4070 trench contact structures are respectively located above the first 4064 and the second 4066 semiconductor source or drain regions adjacent to the first 4056A and the second 4056B sides of the gate electrode 4056. Both the first 4068 and the second 4070 trench contact structures include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 on and over the U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one such embodiment, the U-shaped metal layer 4072 comprises titanium, and the T-shaped metal layer 4074 comprises cobalt. In one embodiment, both the first 4068 and the second 4070 trench contact structures further include a third metal layer 4076 on the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 comprise titanium, and the T-shaped metal layer 4074 comprises cobalt.

[0425] A first trench contact via 4078 is electrically connected to a first trench contact portion 4068. In a particular embodiment, the first trench contact via 4078 is on and coupled to a third metal layer 4076 of the first trench contact portion 4068. The first trench contact via 4078 further lies on and contacts a portion of one of the dielectric spacers 4063 and a portion of the dielectric cap 4062. A second trench contact via 4080 is electrically connected to a second trench contact portion 4070. In a particular embodiment, the second trench contact via 4080 lies on and couples to the third metal layer 4076 of the second trench contact portion 4070. The second trench contact via 4080 further lies on and contacts a portion of another of the dielectric spacers 4063 and another portion of the dielectric cap 4062.

[0426] In one embodiment, the metal silicide layer 4082 is directly between the first 4068 and second 4070 trench contact structures and the first 4064 and second 4066 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4082 comprises nickel, platinum, and silicon. In a particular embodiment, the first 4064 and second 4066 semiconductor source or drain regions are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further comprises germanium. In one embodiment, the metal silicide layer 4082 further comprises titanium.

[0427] One or more embodiments described herein relate to the use of metal chemical vapor deposition for all-around semiconductor contacts. Embodiments may be applicable to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin film.

[0428] Specific embodiments may include fabricating a titanium or similar metal layer using low-temperature (e.g., below 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of the contact metal to provide a conformal source or drain contact. Implementing such a conformal source or drain contact can improve the performance of three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS).

[0429] To provide context, sputtering can be used to deposit metal onto the semiconductor contact layer. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering schemes result in poor or incomplete metal-semiconductor junctions on the device contact surface, with an angle to the incident deposition.

[0430] According to one or more embodiments of this disclosure, a low-temperature chemical vapor deposition process is performed to fabricate contact metals to provide conformality in three dimensions and maximize the contact area of ​​the metal-semiconductor junction. The resulting larger contact area can reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface having a non-planar topography, wherein the topography of the region refers to the surface shape and feature itself, and the non-planar topography includes uneven surface shapes and features or portions of surface shapes and features, i.e., not completely flat surface shapes and features.

[0431] The embodiments described herein may include fabricating a surround contact structure. In one such embodiment, the use of pure metal conformally deposited onto the source-drain contact of a transistor via chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can increase the usable area of ​​the metal-semiconductor contact and reduce resistance, thereby improving the performance of the transistor device. In this embodiment, the lower deposition temperature results in minimized junction resistance per unit area.

[0432] It should be recognized that various integrated circuit structures can be fabricated using integration schemes involving metal layer deposition processes as described herein. According to embodiments of this disclosure, a method of fabricating an integrated circuit structure includes providing a substrate having features in a chemical vapor deposition (CVD) chamber having an RF source. The method further includes reacting titanium tetrachloride (TiCl4) with hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate.

[0433] In the embodiments, the titanium layer has a total atomic composition comprising 98% or more titanium and 0.5-2% chlorine. In alternative embodiments, high-purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V) are fabricated using similar processes. In the embodiments, there is a relatively small variation in film thickness; for example, in the embodiments, all coverage is greater than 50%, and the nominal value is 70% or greater (i.e., the thickness variation is 30% or less). In the embodiments, the thickness measured on silicon (Si) or silicon germanium (SiGe) is thicker than the thickness measured on other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In the embodiments, the film composition includes approximately 0.5% Cl (or less than 1%) as an impurity, with substantially no other observed impurities. In the embodiments, the deposition process allows the metal to be deposited on non-visible surfaces, such as surfaces hidden from view by sputtering deposition. The embodiments described herein can be implemented to improve transistor device driving by reducing the external resistance of the current driven through the source and drain contacts.

[0434] According to embodiments of this disclosure, the substrate is characterized by exposing source or drain contact trenches of a semiconductor source or drain structure. A titanium layer (or other high-purity metal layer) is used as a conductive contact layer for the semiconductor source or drain structure. The following is combined with... Figure 41A , Figure 41B , Figure 42 , Figures 43A-43C and Figure 44 An exemplary embodiment of such an implementation is described.

[0435] Figure 41AA cross-sectional view of a semiconductor device having conductive contacts on the source or drain region according to an embodiment of the present disclosure is shown.

[0436] refer to Figure 41A The semiconductor structure 4100 includes a gate structure 4102 above a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. A source region 4108 and a drain region 4110 are located on opposite sides of the gate structure 4102. A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110, and is spaced apart from the gate structure 4102 by one or both of an interlayer dielectric 4114 or a gate dielectric spacer 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0437] In one embodiment, the source or drain contact 4112 includes, for example, a high-purity metal layer 4112A as described above and a conductive trench filler material 4112B. In one embodiment, the high-purity metal layer 4112A has a total atomic composition comprising 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metal layer 4112A further includes 0.5-2% chlorine. In another embodiment, the high-purity metal layer 4112A has a thickness variation of 30% or less. In another embodiment, the conductive trench filler material 4112B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0438] Figure 41B A cross-sectional view of another semiconductor device having conductive contacts on a raised source or drain region according to an embodiment of the present disclosure is shown.

[0439] refer to Figure 41B Semiconductor structure 4150 includes a gate structure 4152 above a substrate 4154. Gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. Source region 4158 and drain region 4160 are located on opposite sides of gate structure 4152. Source or drain contact 4162 is electrically connected to source region 4158 and drain region 4160 and is spaced from gate structure 4152 by one or both of interlayer dielectric layer 4164 or gate dielectric spacer 4166. Source region 4158 and drain region 4160 are epitaxial or embedded material regions formed in etched areas of substrate 4154. As shown, in this embodiment, source region 4158 and drain region 4160 are raised source and drain regions. In this specific embodiment, the elevated source and drain regions are elevated silicon source and drain regions or elevated silicon-germanium source and drain regions.

[0440] In one embodiment, the source or drain contact 4162 includes, for example, a high-purity metal layer 4162A as described above and a conductive trench filler material 4162B. In one embodiment, the high-purity metal layer 4162A has a total atomic composition comprising 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metal layer 4162A further includes 0.5-2% chlorine. In another embodiment, the high-purity metal layer 4162A has a thickness variation of 30% or less. In another embodiment, the conductive trench filler material 4162B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

[0441] Therefore, in the embodiments, a unified reference is used. Figure 41A and Figure 41B The integrated circuit structure includes surface features (source or drain contact trenches exposing semiconductor source or drain structures). A high-purity metal layer 4112A or 4162A is applied to the surface of the source or drain contact trench. It should be understood that the contact formation process can involve consuming the exposed silicon or germanium or silicon-germanium material in the source or drain region. Such consumption may degrade device performance. In contrast, according to embodiments of this disclosure, the surfaces (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structures are not etched or consumed, or are substantially not etched or consumed beneath the source or drain contact trench. In one such embodiment, the lack of consumption or etching results from the low-temperature deposition of the high-purity metal contact layer.

[0442] Figure 42 A plan view of a plurality of gate lines on a pair of semiconductor fins according to an embodiment of the present disclosure is shown.

[0443] refer to Figure 42 Multiple active gate lines 4204 are formed on multiple semiconductor fins 4200. Dummy gate lines 4206 are located at the ends of the multiple semiconductor fins 4200. The spacing 4208 between gate lines 4204 / 4206 is the location where trench contacts can be formed as conductive contacts leading to source or drain regions (e.g., source or drain regions 4251, 4252, 4253, and 4254).

[0444] Figures 43A-43C The diagram illustrates various operations along the path of a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure. Figure 42 A cross-sectional view taken along the a-a' axis.

[0445] refer to Figure 43AMultiple active gate lines 4304 are formed on a semiconductor fin 4302 formed above a substrate 4300. Dummy gate lines 4306 are located at the ends of the semiconductor fins 4302. A dielectric layer 4310 is interposed between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. An embedded source or drain structure 4308 is located in the semiconductor fins 4302 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. The active gate lines 4304 include a gate dielectric layer 4312, a work function gate electrode portion 4314, a filled gate electrode portion 4316, and a dielectric cap layer 4318. Dielectric spacers 4320 are arranged along the sidewalls of the active gate lines 4304 and the dummy gate lines 4306.

[0446] refer to Figure 43B The dielectric layer 4310 is removed in portions between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 to provide an opening 4330 at the location where a trench contact is to be formed. Removing the dielectric layer 4310 in portions between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 may result in the etching of an embedded source or drain structure 4308 to provide an etched embedded source or drain structure 4332 that may have an upper saddle-shaped morphology, such as... Figure 43B As shown.

[0447] refer to Figure 43C Trench contacts 4334 are formed between active gate lines 4304 and in openings 4330 between dummy gate lines 4306 and active gate lines 4304. Each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive filler material 4338.

[0448] Figure 44 The following diagram illustrates the edge of an integrated circuit structure according to an embodiment of the present disclosure. Figure 42 The cross-sectional view taken along the b-b' axis.

[0449] refer to Figure 44 Fin 4402 is shown above substrate 4404. The lower portion of fin 4402 is surrounded by trench isolation material 4404. The upper portion of fin 4402 has been removed to allow for the growth of embedded source and drain structures 4406. Trench contacts 4408 are formed in openings in dielectric layer 4410, exposing the embedded source and drain structures 4406. The trench contacts include a metal contact layer 4412 and a conductive filler material 4414. It should be understood that, according to an embodiment, the metal contact layer 4412 extends to the top of the trench contact 4408, as... Figure 44 As shown in the diagram. However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact portion 4408, and there are some recesses within the trench contact portion 4408, for example, similar to... Figure 43C The drawing shows the metal contact layer 4436 in the diagram.

[0450] Therefore, common reference Figure 42 , Figures 43A-43C and Figure 44 According to embodiments of this disclosure, the integrated circuit structure includes semiconductor fins (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have a top and sidewalls. Gate electrodes (4204, 4304) are located above the top and adjacent to a portion of the sidewalls of the semiconductor fins (4200, 4302, 4402). The gate electrodes (4204, 4304) define a channel region within the semiconductor fins (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is located at a first end of the channel region on a first side of the gate electrodes (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non-planar topography. The second semiconductor source or drain structure (4252, 4332, 4406) is located at the second end of the channel region on the second side of the gate electrode (4204, 4304), with the second end opposite to the first end and the second side opposite to the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar topography. The metal contact materials (4336, 4412) are directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact materials (4336, 4412) conform to the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conform to the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In one embodiment, the metal contact materials (4336, 4412) have a total atomic composition comprising 95% or more of a single metal species. In one such embodiment, the metal contact materials (4336, 4412) have a total atomic composition comprising 98% or more of titanium. In a specific embodiment, the total atomic composition of the metal contact materials (4336, 4412) further includes 0.5-2% chlorine. In another embodiment, the metal contact materials (4336, 4412) have a thickness variation of 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0452] In the embodiments, the non-planar topography of both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) includes a raised central portion and a lower side portion, for example, as... Figure 44 As shown in the illustration. In the embodiment, the non-planar topography of both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) includes a saddle-shaped portion, for example, as shown in the illustration. Figure 43C As shown in the image.

[0453] In this embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) comprise silicon. In this embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) also comprise germanium, for example, in the form of silicon-germanium.

[0454] In one embodiment, the metal contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) further extends along the sidewalls of a trench in the dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal contact material (4336) along the sidewalls of the trench decreases from 4336A at the first semiconductor source or drain structure (4332) to a position (4336B) above the first semiconductor source or drain structure (4332). Figure 43CAn example is shown. In an embodiment, conductive filler material (4338, 4414) is applied to the metal contact material (4336, 4412) within the trench, as... Figure 43C and Figure 44 As shown.

[0455] In an embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (e.g., Figure 42 The upper fins are 4200, 4302, and 4402. Gate electrodes (4204, 4304) are also located on top of a portion of the second semiconductor fin and adjacent to the sidewall of that portion, defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is located at a first end of the channel region of the second semiconductor fin on the first side of the gate electrodes (4204, 4304), and this third semiconductor source or drain structure has a non-planar topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is located at a second end of the channel region of the second semiconductor fin on the second side of the gate electrodes (4204, 4304), the second end opposite to the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) also has a non-planar topography. The metal contact materials (4336, 4412) are directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406). The metal contact materials (4336, 4412) conform to the non-planar topography of the third semiconductor source or drain structure (4253, 4332, 4406) and conform to the non-planar topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In the embodiment, the metal contact materials (4336, 4412) are continuous between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, right side 4406), and are continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0456] On the other hand, a hard mask material can be used to preserve (prevent corrosion) and can be retained at locations where the conductive trench contact is interrupted above the dielectric material in the trench line position, such as at the contact plug position. For example, Figure 45A and Figure 45B Plan view and corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to embodiments of the present disclosure, are shown respectively.

[0457] refer to Figure 45A and Figure 45B In this embodiment, the integrated circuit structure 4500 includes a fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are situated on the fin 4502A. Individual gate structures within the gate structures 4506 are aligned along a direction 4508 orthogonal to the fin 4502A and have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is situated on the fin 4502A and directly between the dielectric sidewall spacers 4510 of the first pair 4506A / 4506B of the gate structures 4506. A contact plug 4514B is situated on the fin 4502A and directly between the dielectric sidewall spacers 4510 of the second pair 4506B / 4506C of the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0458] In an embodiment, the lower dielectric material 4516 of the contact plug 4516B comprises silicon and oxygen, such as silicon oxide or silicon dioxide. The upper hard mask material 4518 of the contact plug 4516B comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-depleted nitride.

[0459] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown.

[0460] In an embodiment, an individual gate structure among the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of an individual gate structure among the plurality of gate structures 4506 has an upper surface coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown. In an embodiment, although not shown, a thin oxide layer such as thermal or chemical silicon oxide or silicon dioxide layer is present between the fin 4502A and the gate dielectric layer 4526.

[0461] Refer again Figure 45A and Figure 45BIn this embodiment, the integrated circuit structure 4500 includes a plurality of fins 4502, such as a plurality of silicon fins. Individual fins of the plurality of fins 4502 are along a first direction 4504. A plurality of gate structures 4506 are on the plurality of fins 4502. An individual gate structure of the plurality of gate structures 4506 is along a second direction 4508 orthogonal to the first direction 4504. An individual gate structure of the plurality of gate structures 4506 has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is on a first fin 4502A of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. A contact plug 4514A is on a second fin 4502B of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0462] In an embodiment, the lower dielectric material 4516 of the contact plug 4516A comprises silicon and oxygen, such as silicon oxide or silicon dioxide. The upper hard mask material 4518 of the contact plug 4516A comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-depleted nitride.

[0463] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as shown.

[0464] In an embodiment, an individual gate structure among the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of an individual gate structure among the plurality of gate structures 4506 has an upper surface coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as shown. In an embodiment, although not shown, a thin oxide layer such as thermal or chemical silicon oxide or silicon dioxide layer is present between the fin 4502A and the gate dielectric layer 4526.

[0465] One or more embodiments of this disclosure relate to a gate alignment contact process. Such a process can be implemented to form contact structures for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In embodiments, the contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve additional photolithography processes combined with selective contact etching, utilizing a tight registration of the photolithographic contact pattern with an existing gate pattern. For example, another process may include patterning of multiple (gate) grids, wherein the contacts and contact plugs are patterned separately.

[0466] According to one or more embodiments described herein, the contact formation method involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern, while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, this approach enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching) to create contact openings. In embodiments, the contact pattern is formed by utilizing the existing gate pattern in conjunction with contact plug photolithography operations. In one such embodiment, this approach enables the elimination of the need for photolithography operations that are otherwise crucial for creating the contact pattern (as used in other approaches). In embodiments, the trench contact mesh is not patterned separately but formed between multiple (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after the gate grid patterning but before the gate grid dicing.

[0467] Figures 46A-46D Cross-sectional views are shown of various operations in a method of manufacturing an integrated circuit structure including trench contact plugs having hard mask material thereon, according to embodiments of the present disclosure.

[0468] refer to Figure 46A A method of manufacturing an integrated circuit structure includes forming a plurality of fins, with individual fins 4602 of the plurality of fins along a first direction 4604. Individual fins 4602 may include diffusion regions 4606. A plurality of gate structures 4608 are formed on the plurality of fins. Individual gate structures 4508 are formed along a second direction 4610 orthogonal to the first direction 4604 (e.g., direction 4610 for entering / exiting a page). Sacrificial material structures 4612 are formed between first pairs of gate structures 4608. Contact plugs 4614 are between second pairs of gate structures 4608. The contact plugs include a lower dielectric material 4616. A hard mask material 4618 is on the lower dielectric material 4616.

[0469] In an embodiment, the gate structure 4608 includes a sacrificial or dummy gate stack and a dielectric spacer 4609. The sacrificial or dummy gate stack may be made of polysilicon or silicon nitride pillars or some other sacrificial material that may be referred to as a dummy gate material.

[0470] refer to Figure 46B ,from Figure 46A The sacrificial material structure 4612 is removed from the structure to form an opening 4620 between the first pair in the gate structure 4608.

[0471] refer to Figure 46C A trench contact structure 4622 is formed in the opening 4620 between the first pair of gate structures 4608. Furthermore, in an embodiment, as part of forming the trench contact structure 4622, [the following is a description of a specific component / structure]. Figure 46A and Figure 46B The hard mask 4618 is planarized. The final contact plug 4614' includes an upper hard mask material 4616 and an upper hard mask material 4624 formed from the hard mask material 4618.

[0472] In an embodiment, the lower dielectric material 4616 of each of the contact plugs 4614' comprises silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614' comprises silicon and nitrogen. In an embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0473] refer to Figure 46D In a gate replacement process, the sacrificial or dummy gate stack of gate structure 4608 is replaced. In such a process, the dummy gate material, such as polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, as opposed to being performed from an earlier process.

[0474] Therefore, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Furthermore, in embodiments, for example, the top portion of the permanent gate structure 4630 is removed by an etching process and replaced with a dielectric cap 4636. In embodiments, the dielectric cap 4636 of an individual permanent gate structure within the permanent gate structure 4630 has an upper surface coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0475] Refer again Figures 46A-46D In one embodiment, a gate replacement process is performed after the trench contact structure 4622 is formed, as shown. However, according to other embodiments, the gate replacement process is performed before the trench contact structure 4622 is formed.

[0476] In another aspect, a contact (COAG) structure and process over an active gate structure are described. One or more embodiments of this disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of this disclosure relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The manner described herein can be used to reduce the standard cell area by enabling the formation of gate contacts over an active gate region. In one or more embodiments, the gate contact structure manufactured to contact the gate electrode is a self-aligned via structure.

[0477] In techniques that slightly relax space and layout constraints compared to current generations, contacts with the gate structure can be created by forming a contact with a portion of the gate electrode disposed above the isolation region. As an example, Figure 47A A plan view of a semiconductor device having a gate contact disposed on the non-active portion of the gate electrode is shown.

[0478] refer to Figure 47A The semiconductor structure or device 4700A includes a diffused or active region 4704 disposed in a substrate 4702 and within an isolation region 4706. One or more gate lines (also referred to as multiple lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffused or active region 4704 and a portion of the isolation region 4706. Source or drain contacts (also referred to as trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of the semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contact with trench contacts 4710A and 4710B, respectively. A separate gate contact 4714 and an overlying gate contact via 4716 provide contact with gate line 4708B. Compared to the source or drain trench contact 4710A or 4710B, the gate contact 4714, viewed from a plan view, is disposed above the isolation region 4706, but not above the diffusion or active region 4704. Furthermore, neither the gate contact 4714 nor the gate contact via 4716 is disposed between the source or drain trench contacts 4710A and 4710B.

[0479] Figure 47B A cross-sectional view of a non-planar semiconductor device is shown, featuring a gate contact disposed on the non-active portion of the gate electrode. (Reference) Figure 47B Semiconductor structure or device 4700B (e.g.) Figure 47A The non-planar version of device 4700A includes a non-planar diffused or active region 4704C (e.g., a fin structure) formed from substrate 4702 and within isolation region 4706. Gate line 4708B is disposed over the non-planar diffused or active region 4704B and a portion of isolation region 4706. As shown, gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752, together with a dielectric cap layer 4754. From this perspective view, gate contact 4714 and overlying gate contact via 4716, together with overlying metal interconnect 4760, are also visible, all disposed within an interlayer dielectric stack or layer 4770. Figure 47B The perspective view also shows that the gate contact 4714 is disposed above the isolation region 4706, but not above the non-planar diffusion or active region 4704B.

[0480] Refer again Figure 47A and Figure 47B The semiconductor structures or devices 4700A and 4700B are arranged with the gate contacts placed above the isolation region. This arrangement wastes layout space. However, placing the gate contacts above the active region requires extremely tight registration budgets, or the gate size must be increased to provide sufficient space for the gate contacts to land. Furthermore, historically, gate contacts above diffusion regions have been avoided due to the risk of penetrating other gate materials (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address these problems by providing a feasible method for fabricating a contact structure that partially contacts a gate electrode formed above a diffusion or active region, and the resulting structure.

[0481] As an example, Figure 48A A plan view of a semiconductor device having a gate contact via disposed on the active portion of the gate electrode, according to an embodiment of the present disclosure, is shown. (Refer to...) Figure 48AThe semiconductor structure or device 4800A includes a diffused or active region 4804 disposed in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffused or active region 4804 and a portion of the isolation region 4806. Source or drain contacts, such as contacts 4810A and 4810B, are disposed over the source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contacts with trench contact vias 4810A and 4810B, respectively. A gate contact via 4816 without an intervening separate gate contact layer provides contact with gate line 4808B. Figure 47A In contrast, from a plan view perspective, the gate contact 4816 is disposed above the diffusion region or active region 4804 and between the source or drain contacts 4810A and 4810B.

[0482] Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on the active portion of the gate electrode, according to an embodiment of the present disclosure, is shown. (Refer to...) Figure 48B Semiconductor structures or devices 4800B (e.g.) Figure 48A The non-planar version of device 4800A includes a non-planar diffused or active region 4804B (e.g., a fin structure) formed from substrate 4802 and within isolation region 4806. Gate line 4808B is disposed over the non-planar diffused or active region 4804B and a portion of isolation region 4806. As shown, gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852, together with a dielectric cap layer 4854. A gate contact via 4816, together with an overlay metal interconnect 4860, is also visible in this perspective view; both are disposed within an interlayer dielectric stack or layer 4870. Figure 48B The perspective view also shows that the gate contact via 4816 is disposed above the non-planar diffusion or active region 4804B.

[0483] Therefore, refer to again Figure 48A and Figure 48B In this embodiment, trench contact vias 4812A and 4812B and gate contact via 4816 are formed in the same layer and are substantially coplanar. Figure 47A Compared to Figure 47B, the contact portion leading to the gate line may, in other cases, include an additional gate contact layer, for example, which may extend perpendicular to the corresponding gate line. However, in combination Figure 48A and Figure 48BIn the described structure, structures 4800A and 4800B are fabricated such that the contacts can land directly on the metal interconnect layer on the active gate portion without shorting to adjacent source and drain regions. In embodiments, such an arrangement provides a significant area reduction in the circuit layout by eliminating the need to extend the transistor gate over the isolation region to form reliable contacts. As used throughout this document, in embodiments, the reference to the active portion of the gate refers to the portion of the gate line or structure disposed above the active or diffused region of the underlying substrate (from a plan view perspective). In embodiments, the reference to the passive portion of the gate refers to the portion of the gate line or structure disposed above the isolation region of the underlying substrate (from a plan view perspective).

[0484] In one embodiment, the semiconductor structure or device 4800 is a non-planar device, such as, but not limited to, a fin FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed within a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C surround at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, such as in a gate-enclosed device, at least the channel region is fabricated as a discrete three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C completely surround the channel region.

[0485] More generally, one or more embodiments relate to a method for directly landing gate contact vias on the gate of an active transistor and the structure formed therefrom. This method eliminates the need to extend gate lines over an isolation region to achieve the contact purpose. It also eliminates the need for a separate gate contact (GCN) layer for conducting signals from the gate lines or structure. In embodiments, this elimination is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material (e.g., TILA) in the process flow. This additional dielectric material serves as a trench contact dielectric cap layer having different etch characteristics than the gate dielectric cap layer already used for trench contact alignment in a gate alignment contact process (GAP) (e.g., GILA).

[0486] As an example manufacturing solution Figures 49A-49D Cross-sectional views are shown illustrating various operations in a method of manufacturing a semiconductor structure having a gate contact structure disposed on an active portion of the gate, according to embodiments of the present disclosure.

[0487] refer to Figure 49AA semiconductor structure 4900 is provided after the trench contact (TCN) is formed. It should be understood that the specific arrangement of structure 4900 is merely illustrative, and various possible arrangements may benefit from embodiments of the disclosure described herein. Semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E disposed over substrate 4902. The gate stack structure may include a gate dielectric layer and a gate electrode. Trench contacts, such as those leading to a diffusion region of substrate 4902 (e.g., trench contacts 4910A-4910C), are also included in structure 4900 and spaced apart from gate stack structures 4908A-4908E by dielectric spacers 4920. An insulating cap layer 4922 may be disposed on gate stack structures 4908A-4908E (e.g., GILA), as well as... Figure 49A As shown. Also as Figure 49A As shown, a contact blocking area or "contact plug" (e.g., region 4923 made of interlayer dielectric material) may be included in the region where the contact portion is to be blocked.

[0488] In one embodiment, the provided structure 4900 relates to forming a contact pattern that is substantially perfectly aligned with an existing gate pattern, while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, this approach enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching) to create contact openings. In another embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with contact plug photolithography operations. In yet another embodiment, this approach eliminates the need for photolithography operations that are otherwise crucial for creating the contact pattern (as used in other approaches). In another embodiment, the trench contact mesh is not patterned individually but formed between multiple (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after the gate grid patterning but before the gate grid dicing.

[0489] Furthermore, gate stack structures 4908A-4908E can be fabricated using a gate replacement process. In such an approach, dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, in contrast to an earlier process. In embodiments, the dummy gate is removed using a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including water-based NH4OH or tetraethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including water-based phosphoric acid.

[0490] In embodiments, one or more methods described herein are substantially contemplated as combining dummy gate and replacement gate processes with dummy and replacement contact processes to achieve structure 4900. In one such embodiment, a replacement contact process is performed after the replacement gate process to allow for high-temperature annealing of at least a portion of the permanent gate stack. For example, in a specific such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature above approximately 600 degrees Celsius, for instance, after the formation of the gate dielectric layer. Annealing is performed prior to the formation of the permanent contacts.

[0491] refer to Figure 49B The trench contacts 4910A-4910C of structure 4900 are recessed within spacer 4920 to provide recessed trench contacts 4911A-4911C having a height lower than the top surface of spacer 4920 and insulating cap 4922. An insulating cap 4924 is then formed on the recessed trench contacts 4911A-4911C (e.g., TILA). According to embodiments of this disclosure, the insulating cap 4924 on the recessed trench contacts 4911A-4911C is made of a material having etch characteristics different from those of the insulating cap 4922 on gate stack structures 4908A-4908E. In subsequent processing operations, it will be seen that this difference can be utilized to selectively etch one of 4922 / 4924 relative to the other.

[0492] The trench contacts 4910A-4910C can be recessed using a selective process for the materials of the spacer 4920 and the insulating cap 4922. For example, in one embodiment, the trench contacts 4910A-4910C are recessed using an etching process such as a wet etching process or a dry etching process. The insulating cap 4924 can be formed using a process suitable for providing a conformal and sealing layer over the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulating cap 4924 is formed as a conformal layer over the entire structure using a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example, by chemical mechanical polishing (CMP) to provide the insulating cap 4924 material only over the trench contacts 4910A-4910C, and to re-expose the spacer 4920 and the insulating cap 4922.

[0493] Regarding the suitable material combination for the insulating cap layer 4922 / 4924, in one embodiment, one of the 4922 / 4924 pairs is composed of silicon oxide, while the other is composed of silicon nitride. In another embodiment, one of the 4922 / 4924 pairs is composed of silicon oxide, while the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 pairs is composed of silicon oxide, while the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 pairs is composed of silicon nitride, while the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 pairs is composed of silicon nitride, while the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 pairs is composed of silicon carbide, while the other is composed of silicon carbide.

[0494] refer to Figure 49C The interlayer dielectric (ILD) 4930 and hard mask 4932 stack are formed and patterned to provide, for example, in Figure 49B The structure is topped with patterned metal (0) grooves 4934.

[0495] The interlayer dielectric (ILD) 4930 can be composed of a material suitable for electrically isolating the metallic features ultimately formed therein, while maintaining a robust structure between front-end and back-end processing. Furthermore, in the embodiments, the composition of the ILD 4930 is selected to be consistent with the via etching selectivity for patterning the dielectric cap layer of the trench contact, as described below. Figure 49DIn more detail, in one embodiment, ILD 4930 is composed of one or more layers of silicon oxide or one or more layers of carbon-doped oxide (CDO) material. However, in other embodiments, ILD 4930 has a bilayer composition, with its top layer composed of a material different from the bottom portion of the lower layer of ILD 4930. The hard mask layer 4932 may be composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer 4932 is substantially composed of carbon, for example, as a crosslinked organic polymer layer. In other embodiments, silicon nitride or carbon-doped silicon nitride layers are used as the hard mask 4932. The stack of interlayer dielectric (ILD) 4930 and hard mask 4932 can be patterned by photolithography and etching processes.

[0496] refer to Figure 49D Through-hole openings 4936 (e.g., VCT) are formed in the interlayer dielectric (ILD) 4930, extending from the metal (0) trench 4934 to one or more of the recessed trench contacts 4911A-4911C. For example, in Figure 49D In this embodiment, via openings are formed to expose recessed trench contacts 4911A and 4911C. Forming via opening 4936 includes etching both the interlayer dielectric (ILD) 4930 and a corresponding portion of the corresponding insulating cap layer 4924. In one such embodiment, a portion of the insulating cap layer 4922 is exposed during patterning of the interlayer dielectric (ILD) 493 (e.g., the portion of the insulating cap layer 4922 above the gate stack body structures 4908B and 4908E). In this embodiment, the insulating cap layer 4924 is etched to selectively form via opening 4936 relative to the insulating cap layer 4922 (i.e., without significantly etching or affecting the insulating cap layer 4922).

[0497] In one embodiment, the via opening pattern is ultimately transferred to the insulating cap layer 4924 (i.e., the trench contact insulating cap layer) via an etching process without etching the insulating cap layer 4922 (i.e., the gate insulating cap layer). The insulating cap layer 4924 (TILA) can be composed of any or a combination of the following materials: silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides and silicides, including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof. This layer can be deposited using any of the following techniques: CVD, ALD, PECVD, PVD, HDP-assisted CVD, and low-temperature CVD. Corresponding plasma dry etching has been developed as a combination of chemical and physical sputtering mechanisms. Consistent polymer deposition can be used to control material removal rate, etching profile, and film selectivity. Dry etching typically utilizes a mixture of gases, including NF3, CHF3, C4F8, HBr, and O2, with typical pressures in the range of 30-100 mTorr and plasma biases of 50-1000 watts. Dry etching can be designed to achieve significant etch selectivity between the cap layer 4924 (TILA) and the 4922 (GILA) layer, minimizing losses in 4922 (GILA) during dry etching of 4929 (TILA), thereby forming contacts leading to the source / drain regions of the transistor.

[0498] Refer again Figure 49D It should be recognized that a similar approach can be used to create a via opening pattern, which is ultimately transferred to the insulating cap 4922 (i.e., the trench contact insulating cap) by an etching process without etching the insulating cap 4924 (i.e., the gate insulating cap).

[0499] To further illustrate the concept of contact above the active gate (COAG) technology, Figure 50 Plan view and corresponding cross-sectional view of an integrated circuit structure having a trench contact portion including an overlying insulating cap layer according to an embodiment of the present disclosure are shown.

[0500] refer to Figure 50 The integrated circuit structure 5000 includes a gate line 5004 above a semiconductor substrate, such as a silicon fin, or a fin 5002. The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating cap 5006 on the gate stack 5005. A dielectric spacer 5008 runs along the sidewall of the gate stack 5005, and in an embodiment, along the sidewall of the gate insulating cap 5006, as shown.

[0501] The trench contact 5010 is adjacent to the sidewall of the gate line 5004, and a dielectric spacer 5008 is provided between the gate line 5004 and the trench contact 5010. Each trench contact in the trench contact 5010 includes a conductive contact structure 5011 and a trench contact insulating cap layer 5012 on the conductive contact structure 5011.

[0502] Refer again Figure 50 A gate contact via 5014 is formed in an opening in the gate insulating cap 5006 and electrically contacts the gate stack 5005. In an embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a location on the semiconductor substrate or fin 5002 and laterally located between the trench contacts 5010, as shown. In such an embodiment, the trench contact insulating cap 5012 on the conductive contact structure 5011 prevents the gate contact via 5014 from shorting the gate to the source or the gate to the drain.

[0503] Refer again Figure 50 A trench contact via 5016 is formed in the opening of the trench contact insulating cap 5012 and electrically contacts the corresponding conductive contact structure 5011. In an embodiment, the trench contact via 5016 electrically contacts the corresponding conductive contact structure 5011 at a location on the semiconductor substrate or fin 5002 and laterally adjacent to the gate stack 5005 of the gate line 5004, as shown. In such an embodiment, the gate insulating cap 5006 on the gate stack 5005 prevents the trench contact via 5016 from shorting the source to the gate or shorting the drain to the gate.

[0504] It should be recognized that different structural relationships can be created between the insulating gate cap layer and the insulating trench contact cap layer. As an example, Figures 51A-51F Cross-sectional views of various integrated circuit structures according to embodiments of the present disclosure are shown, each integrated circuit structure having a trench contact including an overlying insulating cap and a gate stack including an overlying insulating cap.

[0505] refer to Figure 51A , Figure 51B and Figure 51CIntegrated circuit structures 5100A, 5100B, and 5100C each include a fin 5102, such as a silicon fin. Although shown as a cross-sectional view, it should be understood that the fin 5102 has a top 5102A and sidewalls (in / out of the page showing the perspective view). First gate dielectric layers 5104 and 5106 are laterally adjacent to the top fin 5102A and the sidewalls of the fin 5102, respectively. First gate electrodes 5108 and 5110 are laterally adjacent to the top fin 5102A and the sidewalls of the fin 5102, respectively, above the first gate dielectric layers 5104 and 5106. Both the first gate electrodes 5108 and 5110 include a conformal conductive layer 5109A (e.g., a work function setting layer) and a conductive filler material 5109B above the conformal conductive layer 5109A. The first gate electrode 5108 and the second gate electrode 5110 both have a first side 5112 and a second side 5114 opposite to the first side 5112. The first gate electrode 5108 and the second gate electrode 5110 also both have an insulating cap 5116, which has a top surface 5118.

[0506] The first dielectric spacer 5120 is adjacent to the first side 5112 of the first gate electrode 5108. The second dielectric spacer 5122 is adjacent to the second side 5114 of the second gate electrode 5110. The semiconductor source or drain region 5124 is adjacent to the first 5120 and the second 5122 dielectric spacers. The trench contact structure 5126 is on the semiconductor source or drain region 5124 adjacent to the first 5120 and the second 5122 dielectric spacers.

[0507] The trench contact structure 5126 includes an insulating cap 5128 on the conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has a top surface 5129 that is generally coplanar with the top surface 5118 of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes. In one embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into a recess 5132 in the first 5120 and second 5122 dielectric spacers. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 is suspended above the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recess 5132 in the first 5120 and second 5122 dielectric spacers, and therefore is not suspended above the conductive structure 5130 of the trench contact structure 5126.

[0508] It should be recognized that the conductive structure 5130 of the trench contact structure 5126 does not have to be rectangular, such as... Figures 51A-51CAs shown in the diagram. For example, the conductive structure 5130 of the trench contact structure 5126 can have the same characteristics as... Figure 51A The cross-sectional geometry shown in the projection is similar to or the same as the geometry shown for the conductive structure 5130A.

[0509] In one embodiment, the insulating cap 5128 of the trench contact structure 5126 has a different composition than the insulating cap 5116 of the first 5108 and second 5110 gate electrodes. In one such embodiment, the insulating cap 5128 of the trench contact structure 5126 comprises a carbide material, such as silicon carbide. The insulating cap 5116 of the first 5108 and second 5110 gate electrodes comprises a nitride material, such as silicon nitride.

[0510] In the embodiment, the insulating caps 5116 of the first 5108 and the second 5110 gate electrodes both have a bottom surface 5117A that is lower than the bottom surface 5128A of the insulating cap 5128 of the trench contact structure 5126, such as Figure 51A As shown. In another embodiment, the insulating caps 5116 of the first 5108 and the second 5110 gate electrodes both have a bottom surface 5117A that is substantially coplanar with the bottom surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as shown. Figure 51B As shown. In another embodiment, the insulating caps 5116 of the first 5108 and the second 5110 gate electrodes both have a bottom surface 5117C that is higher than the bottom surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as shown. Figure 51C As shown.

[0511] In one embodiment, the conductive structure 5130 of the trench contact structure 5128 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 on and over the U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. An insulating cap 5128 of the trench contact structure 5126 is located on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 comprise titanium, and the T-shaped metal layer 5136 comprises cobalt. In a particular such embodiment, the T-shaped metal layer 5136 also includes carbon.

[0512] In one embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicide layer 5140 comprises titanium and silicon. In a particular embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 comprises nickel, platinum, and silicon. In a particular embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In yet another particular embodiment, the metal silicide layer further comprises germanium.

[0513] In the embodiment, reference Figure 51D A conductive via 5150 is located on and electrically connected to the portion of the first gate electrode 5108 above the top 5102A of the fin 5102. The conductive via 5150 is located in an opening 5152 within the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is on a portion of the insulating cap 5128 of the trench contact structure 5126, but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular embodiment, the conductive via 5150 is located in the etched portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0514] In the embodiment, reference Figure 51E A conductive via 5160 is located on a portion of the trench contact structure 5126 and electrically connected to that portion. The conductive via is in the opening 5162 of the insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is on a portion of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes, but is not electrically connected to the first 5108 and second 5110 gate electrodes. In a particular embodiment, the conductive via 5160 is in the etched portion 5164 of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes.

[0515] Refer again Figure 51E In the embodiment, the conductive via 5160 is connected to... Figure 51D The conductive via 5150 has a second conductive via with the same structure. In one such embodiment, the second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, the second conductive via 5160 is fused with the conductive via 5150 to form an electrically short-circuit contact 5170, such as... Figure 51F As shown.

[0516] The methods and structures described herein enable the creation of other structures or devices that are impossible or difficult to manufacture using other methods. In the first example, Figure 52A A plan view of another semiconductor device having a gate contact via disposed on an active portion of the gate, according to another embodiment of the present disclosure, is shown. (Refer to...) Figure 52A The semiconductor structure or device 5200 includes a plurality of gate structures 5208A-5208C that intersect with a plurality of trench contacts 5210A and 5210B (these features are disposed above the active region of the substrate, not shown). A gate contact via 5280 is formed on the active portion of the gate structure 5208B. The gate contact via 5280 is also disposed on the active portion of the gate structure 5208C, coupling the gate structures 5208B and 5208C. It should be appreciated that a trench contact isolation cap layer (e.g., TILA) can be used to isolate the intermediate trench contact 5210B from the contact 5280. Figure 52A The contact configuration provides an easier way to bundle adjacent gate lines in the layout without routing the bundled lines through a metallized upper layer, thus enabling smaller cell areas or less complex circuit schemes, or both.

[0517] In the second example, Figure 52B A plan view of another semiconductor device having a trench contact via with a pair of coupled trench contacts, according to another embodiment of the present disclosure, is shown. (Refer to...) Figure 52B The semiconductor structure or device 5250 includes a plurality of gate structures 5258A-5258C that intersect with a plurality of trench contacts 5260A and 5260B (these features are disposed above the active region of the substrate, not shown). A trench contact via 5290 is formed on the trench contact 5260A. The trench contact via 5290 is also disposed on the trench contact 5260B, coupling the trench contacts 5260A and 5260B. It should be appreciated that an intervening gate structure 5258B can be isolated from the trench contact via 5290 using a gate isolation cap layer (e.g., via a GILA process). Figure 52B The contact configuration provides an easier way to bundle adjacent trench contacts in a layout without routing the bundling wires through a metallized upper layer, thus enabling smaller unit areas or less complex wiring schemes, or both.

[0518] An insulating cap layer for a gate electrode can be fabricated using several deposition operations, and as a result, the insulating cap layer can comprise an artifact manufactured through multiple deposition processes. For example, Figures 53A-53E Cross-sectional views are shown illustrating various operations in a method of manufacturing an integrated circuit structure including a gate stack having an overlying insulating cap layer, according to embodiments of the present disclosure.

[0519] refer to Figure 53A The initial structure 5300 includes a gate stack 5304 above a substrate or fin 5302. The gate stack 5304 includes a gate dielectric layer 5306, a conformal conductive layer 5308, and a conductive filler material 5310. In an embodiment, the gate dielectric layer 5306 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer is a work function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxide layer 5312, such as a thermal or chemical silicon dioxide or silicon oxide layer, is located between the substrate or fin 5302 and the gate dielectric layer 5306. A dielectric spacer 5314, such as a silicon nitride spacer, is adjacent to the sidewall of the gate stack 5304. The dielectric gate stack 5304 and the dielectric spacer 5314 are housed within an interlayer dielectric (ILD) layer 5316. In an embodiment, the gate stack 5304 is formed using a replacement gate and a replacement gate dielectric processing scheme. A mask 5318 is patterned over the gate stack 5304 and the ILD layer 5316 to provide an opening 5320 that exposes the gate stack 5304.

[0520] refer to Figure 53B Using one or more selective etching processes, a gate stack 5304, comprising a gate dielectric layer 5306, a conformal conductive layer 5308, and a conductive filler material 5310, is recessed relative to the dielectric spacer 5314 and layer 5316. The mask 5318 is then removed. The recess provides a cavity 5322 over the recessed gate stack 5324.

[0521] In another embodiment, not shown, the conformal conductive layer 5308 and the conductive filler 5310 are recessed relative to the dielectric spacer 5314 and layer 5316, but the gate dielectric layer 5306 is not recessed or is only minimally recessed. It should be understood that in other embodiments, a maskless approach based on highly etch-selective methods is used for the recess.

[0522] refer to Figure 53C The fi...

Claims

1. An integrated circuit structure, comprising: The first interlayer dielectric (ILD) layer above the substrate; A plurality of first conductive interconnects spaced apart in and by the first ILD layer, each of the plurality of first conductive interconnects including a first conductive barrier layer having a first barrier component, and each of the plurality of first conductive interconnects including a first conductive filler having a first filler component, and the plurality of first conductive interconnects including: A first interconnect with a width; A second interconnect line is located immediately adjacent to the first interconnect line, and the second interconnect line has a width different from that of the first interconnect line; A third interconnect line adjacent to the second interconnect line, the third interconnect line having a width, wherein the width of the third interconnect line is different from the width of the second interconnect line, and wherein the width of the third interconnect line is different from the width of the first interconnect line; A fourth interconnect line adjacent to the third interconnect line, the fourth interconnect line having the same width as the second interconnect line, wherein the first spacing between the first interconnect line and the third interconnect line is different from the second spacing between the second interconnect line and the fourth interconnect line; A fifth interconnect line adjacent to the fourth interconnect line, the fifth interconnect line having the same width as the first interconnect line; and A sixth interconnect line adjacent to the fifth interconnect line, the sixth interconnect line having the same width as the second interconnect line; The second ILD layer above the first ILD layer; and In the second ILD layer and spaced apart by the second ILD layer, each of the second plurality of conductive interconnects has a width greater than the maximum width of the first interconnect, the second interconnect, the third interconnect, the fourth interconnect, the fifth interconnect, and the sixth interconnect in the first plurality of conductive interconnects, and each of the second plurality of conductive interconnects includes a second conductive barrier layer having a second barrier component, the second barrier component of the second conductive barrier layer being different from the first barrier component of the first conductive barrier layer, wherein one of the first barrier component or the second barrier component includes an outer layer and an inner layer, one of the outer layer or the inner layer having a first metal type not included in the other of the outer layer or the inner layer, and the other of the outer layer or the inner layer having a second metal type not included in the first of the outer layer or the inner layer, and each of the second plurality of conductive interconnects includes a second conductive filler having a second filler component, the second filler component of the second conductive filler being different from the first filler component of the first conductive filler.

2. An integrated circuit structure, comprising: The first interlayer dielectric (ILD) layer above the substrate; A plurality of first conductive interconnects spaced apart in and by the first ILD layer, each of the plurality of first conductive interconnects including a first conductive barrier layer having a first barrier component, and each of the plurality of first conductive interconnects including a first conductive filler having a first filler component, and the plurality of first conductive interconnects including: A first interconnect with a width; A second interconnect line adjacent to the first interconnect line, the second interconnect line having a width, wherein the width of the second interconnect line is different from the width of the first interconnect line; A third interconnect line adjacent to the second interconnect line, the third interconnect line having a width different from the width of the first interconnect line, wherein the width of the third interconnect line is different from the width of the second interconnect line; A fourth interconnect line adjacent to the third interconnect line, the fourth interconnect line having the same width as the second interconnect line, wherein the first spacing between the first interconnect line and the third interconnect line is different from the second spacing between the second interconnect line and the fourth interconnect line; A fifth interconnect line adjacent to the fourth interconnect line, the fifth interconnect line having the same width as the first interconnect line; A sixth interconnect line adjacent to the fifth interconnect line, the sixth interconnect line having the same width as the second interconnect line; and A seventh interconnect line adjacent to the sixth interconnect line, the seventh interconnect line having the same width as the third interconnect line; The second ILD layer above the first ILD layer; and In the second ILD layer and spaced apart by the second ILD layer, each of the second plurality of conductive interconnects has a width greater than the maximum width of the first interconnect, the second interconnect, the third interconnect, the fourth interconnect, the fifth interconnect, the sixth interconnect, and the seventh interconnect in the first plurality of conductive interconnects, and each of the second plurality of conductive interconnects includes a second conductive barrier layer having a second barrier component, the second barrier component of the second conductive barrier layer being different from the first barrier component of the first conductive barrier layer, wherein one of the first barrier component or the second barrier component includes an outer layer and an inner layer, one of the outer layer or the inner layer having a first metal type not included in the other of the outer layer or the inner layer, and the other of the outer layer or the inner layer having a second metal type not included in the first of the outer layer or the inner layer, and each of the second plurality of conductive interconnects includes a second conductive filler having a second filler component, the second filler component of the second conductive filler being different from the first filler component of the first conductive filler.

3. A method for manufacturing an integrated circuit structure, the method comprising: A first plurality of conductive interconnects spaced apart by the first interlayer dielectric (ILD) layer are formed in a first interlayer dielectric (ILD) layer above a substrate. Each of the first plurality of conductive interconnects includes a first conductive barrier layer having a first barrier component, and each of the first plurality of conductive interconnects includes a first conductive filler having a first filler component. The first plurality of conductive interconnects are formed using a spacer-based spacing quadrating process. A first set of spacers serves as a mask during etching in a first etching process. The first plurality of conductive interconnects includes: a first interconnect having a width; a second interconnect adjacent to the first interconnect having a width different from that of the first interconnect; and a second interconnect adjacent to the first interconnect having a width different from that of the first interconnect. A third interconnect line is described above, the third interconnect line having a width, wherein the width of the third interconnect line is different from the width of the second interconnect line, and wherein the width of the third interconnect line is different from the width of the first interconnect line; a fourth interconnect line is adjacent to the third interconnect line, the fourth interconnect line having the same width as the second interconnect line, wherein a first spacing between the first interconnect line and the third interconnect line is different from a second spacing between the second interconnect line and the fourth interconnect line; a fifth interconnect line is adjacent to the fourth interconnect line, the fifth interconnect line having the same width as the first interconnect line; and a sixth interconnect line is adjacent to the fifth interconnect line, the sixth interconnect line having the same width as the second interconnect line; and A second plurality of conductive interconnects spaced apart by the second ILD layer are formed in a second ILD layer above the first ILD layer. The second plurality of conductive interconnects are formed using a spacer-based pitch halving process. The second set of spacers serves as a mask during etching in a second etching process. Each of the second plurality of conductive interconnects has a width greater than the maximum width of the first, second, third, fourth, fifth, and sixth interconnects in the first plurality of conductive interconnects. Each of the second plurality of conductive interconnects includes a second conductive barrier layer having a second barrier component. The second barrier component of the conductive barrier layer is different from the first barrier component of the first conductive barrier layer, wherein one of the first barrier component or the second barrier component includes an outer layer and an inner layer, one of the outer layer or the inner layer has a first metal type not included in the other of the outer layer or the inner layer, and the other of the outer layer or the inner layer has a second metal type not included in the first of the outer layer or the inner layer, and each of the second plurality of conductive interconnects includes a second conductive filler having a second filling component, the second filling component of the second conductive filler being different from the first filling component of the first conductive filler.

4. The method according to claim 3, wherein, The first plurality of conductive interconnects have a spacing of no more than 40 nanometers between adjacent lines, and wherein the second plurality of conductive interconnects have a spacing of 44 nanometers or greater between adjacent lines.

5. The method according to claim 3, wherein, The spacer-based spacing quarting process and the spacer-based spacing halving process are based on immersion 193nm lithography.

6. The method according to claim 3, further comprising: A third plurality of conductive interconnects are formed in a third ILD layer above the second ILD layer, spaced apart by the third ILD layer, wherein the third plurality of conductive interconnects are not formed using a spacing division.

7. The method according to claim 3, further comprising: Before forming the second plurality of conductive interconnects, a third plurality of conductive interconnects spaced apart by the third ILD layer are formed in a third ILD layer above the first ILD layer, wherein the third plurality of conductive interconnects are formed using a spacer-based spacing quadrature process. After forming the second plurality of conductive interconnects, a fourth plurality of conductive interconnects spaced apart by the fourth ILD layer are formed in the fourth ILD layer above the second ILD layer, wherein the fourth plurality of conductive interconnects are formed using a spacer-based pitch halving process. A fifth plurality of conductive interconnects are formed in a fifth ILD layer above the fourth ILD layer, wherein the fifth plurality of conductive interconnects are formed using a spacer-based pitch halving process. A sixth plurality of conductive interconnects, spaced apart by the sixth ILD layer, are formed in a sixth ILD layer above the fifth ILD layer, wherein the sixth plurality of conductive interconnects are formed using a spacer-based pitch halving process; and A seventh plurality of conductive interconnects are formed in the seventh ILD layer above the sixth ILD layer, wherein the seventh plurality of conductive interconnects are not formed using a spacing division.

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