Fin-end plug structure for advanced integrated circuit structure manufacturing

Abstract

The present invention discloses a fin end plug structure for advanced integrated circuit structure manufacturing. The embodiments of the present disclosure belong to the field of advanced integrated circuit structure manufacturing, and in particular to the field of 10 nanometer node and smaller integrated circuit structure manufacturing and the resulting structures. In an example, the integrated circuit structure includes a first isolation structure above the first end of the fin. The gate structure is above the fin and is spaced apart from the first isolation structure along the direction. The second isolation structure is above the second end of the fin, the second end being opposite to the first end. The second isolation structure is spaced apart from the gate structure. Both the first isolation structure and the second isolation structure include a first dielectric material that laterally surrounds a recessed second dielectric material that is different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material that is different from the first and second dielectric materials.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed on November 30, 2017, entitled “ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION,” the entire contents of which are hereby incorporated by reference herein. Technical Field

[0003] Embodiments of the present disclosure pertain to the field of advanced integrated circuit structure fabrication, and in particular to the field of 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. Background Art

[0004] Over the past few decades, the scaling of features in integrated circuits has been a driving force in the evolving semiconductor industry. Scaling to smaller and smaller features has enabled increased functional unit density within the limited real estate of semiconductor chips. For example, shrinking transistor sizes allow for the integration of an increasing number of memory or logic devices on a chip, leading to the manufacture of products with increased capacity. However, this drive for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device has become increasingly significant.

[0005] Variability in conventional and currently known manufacturing processes may limit the possibility of extending them further into the 10 nm node or sub-10 nm node range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into current manufacturing processes, or their replacement by current manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A Illustrated is a cross-sectional view of a starting structure of a hard mask material layer formed on an inter-layer dielectric (ILD) layer after deposition but before patterning.

[0007] Figure 1B Illustrated after patterning the hard mask layer by bisecting the pitch Figure 1A Cross-sectional view of the structure.

[0008] Figure 2A FIG. 4 is a schematic diagram of a pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0009] Figure 2B A cross-sectional view of a semiconductor fin fabricated using a pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0010] Figure 3A FIG. 4 is a schematic diagram of a fused fin pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0011] Figure 3B A cross-sectional view of a semiconductor fin fabricated using a fused fin pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0012] Figures 4A-4C are cross-sectional views illustrating various operations in a method of fabricating a plurality of semiconductor fins, in accordance with an embodiment of the present disclosure.

[0013] Figure 5A Illustrated is a cross-sectional view of a pair of semiconductor fins separated by a triple-layer trench isolation structure according to an embodiment of the present disclosure.

[0014] Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another triple-layer trench isolation structure according to another embodiment of the present disclosure is illustrated.

[0015] Figures 6A-6D Illustrated are cross-sectional views of various operations in the fabrication of a triple-layer trench isolation structure in accordance with an embodiment of the present disclosure.

[0016] Figures 7A-7E Angled three dimensional cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present disclosure.

[0017] Figures 8A-8F The present invention illustrates various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0018] Figure 9A An embodiment of the present disclosure is provided for illustrating an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0019] Figure 9B The invention illustrates an integrated circuit structure including an epitaxial source or drain region and a multi-layer trench isolation structure according to an embodiment of the present disclosure. Figure 7E A cross-sectional view taken along the b-b' axis.

[0020] Figure 10 A cross-sectional view of an integrated circuit structure taken at a source or drain location according to an embodiment of the present disclosure is illustrated.

[0021] Figure 11A cross-sectional view of another integrated circuit structure taken at a source or drain location according to an embodiment of the present disclosure is illustrated.

[0022] Figures 12A-12D Illustrated are cross-sectional views representing various operations in fabricating an integrated circuit structure and taken at a source or drain location, in accordance with an embodiment of the present disclosure.

[0023] Figure 13A and 13B Illustrated are plan views showing various operations in a method of patterning a fin with multiple gate spacers for forming a local isolation structure, in accordance with an embodiment of the present disclosure.

[0024] Figures 14A-14D Illustrated are plan views showing various operations in a method of patterning a fin having a single gate spacer for forming a local isolation structure in accordance with another embodiment of the present disclosure.

[0025] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multiple gate spacers for local isolation according to an embodiment of the present disclosure is illustrated.

[0026] Figure 16A A cross-sectional view of an integrated circuit structure having a fin with a single gate spacer for local isolation according to another embodiment of the present disclosure is illustrated.

[0027] Figure 16B A cross-sectional view showing a location at which a fin isolation structure may be formed instead of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0028] Figures 17A-17C Various depth possibilities for fin cuts fabricated using the fin trim isolation method are illustrated according to embodiments of the present disclosure.

[0029] Figure 18 Illustrated are a plan view and corresponding cross-sectional view taken along the aa' axis showing possible options for depth of a localized location versus a wider location of a fin cutout within a fin, according to an embodiment of the present disclosure.

[0030] Figure 19A and 19B Illustrated are cross-sectional views of various operations in a method of selecting a fin tip stressor location at a fin tip having a wide notch, in accordance with an embodiment of the present disclosure.

[0031] Figure 20A and 20B Illustrated are cross-sectional views of various operations in a method of selecting a fin tip stressor location at a fin tip having a localized notch, in accordance with an embodiment of the present disclosure.

[0032] Figures 21A-21M Illustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure with differentiated fin-end dielectric plugs, in accordance with an embodiment of the present disclosure.

[0033] 22A-22D illustrate cross-sectional views of exemplary structures of PMOS fin end stressor dielectric plugs according to embodiments of the present disclosure.

[0034] Figure 23A A cross-sectional view of another semiconductor structure having fin tip stress-inducing features according to another embodiment of the present disclosure is illustrated.

[0035] Figure 23B A cross-sectional view of another semiconductor structure having fin tip stress-inducing features according to another embodiment of the present disclosure is illustrated.

[0036] Figure 24A Angled views of fins having uniaxial tensile stress are illustrated according to embodiments of the present disclosure.

[0037] Figure 24B Angled views of fins with uniaxial compressive stress are illustrated according to embodiments of the present disclosure.

[0038] Figure 25A and 25B Illustrated are plan views representing various operations in a method of patterning a fin having a single gate spacer for forming a local isolation structure in a select gate line cut location, in accordance with an embodiment of the present disclosure.

[0039] Figures 26A-26C Cross-sectional views illustrating various possibilities for a dielectric plug for use in accordance with embodiments of the present disclosure Figure 25B Poly cuts and fin trim isolation (FTI) local fin cut locations and poly cut only locations in various areas of the structure.

[0040] Figure 27A Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer of the gate line according to an embodiment of the present disclosure.

[0041] Figure 27B Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having a gate line cutout with a dielectric plug extending beyond a dielectric spacer of the gate line according to another embodiment of the present disclosure.

[0042] Figures 28A-28FIllustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure having a gate line cutout with a dielectric plug having an upper portion extending beyond a dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line in accordance with another embodiment of the present disclosure.

[0043] Figures 29A-29C Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having residual dummy gate material at a portion of a bottom portion of a permanent gate stack according to an embodiment of the present disclosure.

[0044] Figures 30A-30D Illustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure having residual dummy gate material at a bottom portion of a permanent gate stack in accordance with another embodiment of the present disclosure.

[0045] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is illustrated.

[0046] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is illustrated.

[0047] Figure 32A A plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is illustrated.

[0048] Figure 32B The embodiment according to the present disclosure is illustrated along Figure 32A A cross-sectional view taken along the a-a' axis.

[0049] Figure 33A Illustrated are cross-sectional views of a pair of NMOS devices having differentiated voltage thresholds based on modulation doping and a pair of PMOS devices having differentiated voltage thresholds based on modulation doping according to an embodiment of the present disclosure.

[0050] Figure 33B Illustrated are cross-sectional views of a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0051] Figure 34A Illustrated are cross-sectional views of a group of three NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping and a group of three PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping according to an embodiment of the present disclosure.

[0052] Figure 34B Illustrated are cross-sectional views of a group of three NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping and a group of three PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping according to another embodiment of the present disclosure.

[0053] Figures 35A-35D Illustrated are cross-sectional views of various operations in a method of fabricating an NMOS device having differentiated voltage thresholds based on differentiated gate electrode structures in accordance with another embodiment of the present disclosure.

[0054] Figures 36A-36D Illustrated are cross-sectional views of various operations in a method of fabricating a PMOS device having differentiated voltage thresholds based on differentiated gate electrode structures in accordance with another embodiment of the present disclosure.

[0055] Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is illustrated.

[0056] Figures 38A-38H Illustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow in accordance with an embodiment of the present disclosure.

[0057] Figures 39A-39H Illustrated are cross-sectional views representing various operations in a method of fabricating a bisulicide based integrated circuit, in accordance with an embodiment of the present disclosure.

[0058] Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to an embodiment of the present disclosure is illustrated.

[0059] Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device according to another embodiment of the present disclosure is illustrated.

[0060] Figure 41A A cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to an embodiment of the present disclosure is illustrated.

[0061] Figure 41B A cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region according to an embodiment of the present disclosure is illustrated.

[0062] Figure 42 A plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is illustrated.

[0063] Figures 43A-43C The present invention illustrates various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Figure 42 A cross-sectional view taken along the a-a' axis.

[0064] Figure 44 The invention illustrates an embodiment of the present invention for an integrated circuit structure. Figure 42 A cross-sectional view taken along the b-b' axis.

[0065] Figure 45A and 45B A plan view and a corresponding cross-sectional view are respectively illustrated of an integrated circuit structure including a trench contact plug having a hard mask material thereon according to an embodiment of the present disclosure.

[0066] Figures 46A-46D Illustrated are cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including a trench contact plug having a hard mask material thereon, in accordance with an embodiment of the present disclosure.

[0067] Figure 47A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is illustrated. Figure 47B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is illustrated.

[0068] Figure 48A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated. Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0069] Figures 49A-49D Illustrated are cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present disclosure.

[0070] Figure 50 Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having a trench contact with an overlying insulating cap layer according to an embodiment of the present disclosure.

[0071] Figures 51A-51F Illustrated are cross-sectional views of various integrated circuit structures each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer according to embodiments of the present disclosure.

[0072] Figure 52AA plan view of another semiconductor device having a gate contact via disposed over an active portion of a gate according to another embodiment of the present disclosure is illustrated.

[0073] Figure 52B A plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts according to another embodiment of the present disclosure is illustrated.

[0074] Figures 53A-53E Illustrated are cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a gate stack with an overlying insulating cap layer, in accordance with an embodiment of the present disclosure.

[0075] Figure 54 is a schematic diagram of a pitch quartering method for fabricating trenches for an interconnect structure according to an embodiment of the present disclosure.

[0076] Figure 55A Illustrated is a cross-sectional view of a metallization layer fabricated using a pitch quartering scheme according to an embodiment of the present disclosure.

[0077] Figure 55B Illustrated is a cross-sectional view of a metallization layer fabricated using a pitch-halving scheme over a metallization layer fabricated using a pitch-quartering scheme according to an embodiment of the present disclosure.

[0078] Figure 56A Illustrated is a cross-sectional view of an integrated circuit structure having a metallization layer constructed with a different metal line over a metallization layer constructed with a different metal line according to an embodiment of the present disclosure.

[0079] Figure 56B Illustrated is a cross-sectional view of an integrated circuit structure having a metallization layer constructed with a dissimilar metal line coupled to a metallization layer constructed with a different metal line according to an embodiment of the present disclosure.

[0080] Figures 57A-57C Illustrated are cross-sectional views of various interconnect lines with various arrangements of liner and conductive capping structures according to embodiments of the present disclosure.

[0081] Figure 58 Illustrated is a cross-sectional view of an integrated circuit structure having four metallization layers utilizing different metal line compositions and pitches over two metallization layers utilizing one metal line composition and smaller pitches in accordance with an embodiment of the present disclosure.

[0082] Figures 59A-59D Illustrated are cross-sectional views of various interconnect line and via arrangements with a bottom conductive layer according to embodiments of the present disclosure.

[0083] Figures 60A-60DIllustrated is a cross-sectional view of a structural arrangement for a recessed line topography of a BEOL metallization layer according to an embodiment of the present disclosure.

[0084] Figures 61A-61D Illustrated is a cross-sectional view of a structural arrangement for a stepped line profile of a BEOL metallization layer according to an embodiment of the present disclosure.

[0085] Figure 62A A plan view of a metallization layer according to an embodiment of the present disclosure and a corresponding cross-sectional view taken along an aa′ axis of the plan view of the metallization layer are illustrated.

[0086] Figure 62B Illustrated is a cross-sectional view of a wire end or plug according to an embodiment of the present disclosure.

[0087] Figure 62C Another cross-sectional view of a wire end or plug is illustrated according to an embodiment of the present disclosure.

[0088] Figures 63A-63F Illustrated are plan views and corresponding cross-sectional views illustrating various operations in a plug finishing scheme according to an embodiment of the present disclosure.

[0089] Figure 64A Illustrated is a cross-sectional view of a wire plug having a seam therein according to an embodiment of the present disclosure.

[0090] Figure 64B A cross-sectional view of a metallization layer stack including a conductive plug at a lower metal line location according to an embodiment of the present disclosure is illustrated.

[0091] Figure 65 A first view of a cell layout for a memory cell is illustrated.

[0092] Figure 66 A first view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is illustrated.

[0093] Figure 67 A second view of a cell layout for a memory cell is illustrated.

[0094] Figure 68 Illustrated is a second view of a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure.

[0095] Figure 69 A third view illustrating a cell layout for a memory cell is shown.

[0096] Figure 70 A third view illustrating a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is illustrated.

[0097] Figure 71A and 71B A bit cell layout and a schematic diagram for a six-transistor (6T) static random access memory (SRAM) according to an embodiment of the present disclosure are respectively illustrated.

[0098] Figure 72 Illustrated are cross-sectional views of two different layouts for the same standard cell according to embodiments of the present disclosure.

[0099] Figure 73 Illustrated are plan views of four different cell arrangements indicating even (E) or odd (O) designations according to an embodiment of the present disclosure.

[0100] Figure 74 A plan view of a block-level aggregation grid according to an embodiment of the present disclosure is illustrated.

[0101] Figure 75 Exemplary acceptable (passing) layouts based on standard cells with different versions according to an embodiment of the present disclosure are illustrated.

[0102] Figure 76 Exemplary unacceptable (failing) layouts based on standard cells with different versions according to an embodiment of the present disclosure are illustrated.

[0103] Figure 77 Another exemplary acceptable (passing) layout based on standard cells with different versions according to an embodiment of the present disclosure is illustrated.

[0104] Figure 78 A partially cut plan view and a corresponding cross-sectional view of a fin-based thin film resistor structure according to an embodiment of the present disclosure are illustrated, wherein the cross-sectional view is taken along the aa′ axis of the partially cut plan view.

[0105] Figures 79-83 Illustrated are plan views and corresponding cross-sectional views representing various operations in a method of fabricating a fin-based thin film resistor structure, in accordance with an embodiment of the present disclosure.

[0106] Figure 84 Illustrated are plan views of fin-based thin film resistor structures with various exemplary locations for anode or cathode electrode contacts according to embodiments of the present disclosure.

[0107] Figures 85A-85D Illustrated are plan views of various fin geometries used to fabricate fin-based precision resistors according to embodiments of the present disclosure.

[0108] Figure 86A cross-sectional view of a photolithography mask structure according to an embodiment of the present disclosure is illustrated.

[0109] Figure 87 A computing device according to one embodiment of the present disclosure is illustrated.

[0110] Figure 88 An interposer including one or more embodiments of the present disclosure is illustrated.

[0111] Figure 89 Illustrated is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0112] Figure 90 Illustrated is a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] Advanced integrated circuit structure fabrication is described. In the following description, numerous specific details, such as specific integration and material organization regimes, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0114] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present invention or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, summary, or the following detailed description.

[0115] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner in accordance with the present disclosure.

[0116] Terminology. The following paragraphs provide definitions or context for terms that appear in this disclosure, including the appended claims.

[0117] "Comprising": This term is open ended. As used in the following claims, this term does not exclude additional structures or operations.

[0118] "Configured to": Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform those one or more tasks during operation. As such, a specified unit or component may be said to be configured to perform the tasks even when the unit or component is not currently operating (e.g., not turned on or inactive). Reciting a unit, circuit, or component as "configured to" perform one or more tasks expressly does not intend to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit or component.

[0119] “First,” “second,” etc.: As used herein, these terms serve as labels for the nouns that follow them and do not imply any type of ordering (eg, spatial, temporal, logical, etc.).

[0120] “Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element or node or feature is directly or indirectly joined to (or directly or indirectly connected to) another element or node or feature, and not necessarily mechanically.

[0121] In addition, certain terms may be used in the following description for reference purposes only, and the terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the accompanying drawings to which reference is made. Terms such as "front," "rear," "back," "side," "outer," and "inner" describe the orientation or position, or both, of parts of a component within a consistent but arbitrary reference frame, which is clarified by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0122] "Inhibit" - As used herein, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, motion, or condition, it may completely prevent the result, consequence, or future state. Additionally, "inhibit" may also mean reducing or mitigating a consequence, property, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or condition, it need not completely prevent or eliminate the result or condition.

[0123] Embodiments described herein may involve front-end-of-the-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally encompasses any process up to (but not including) the deposition of metal interconnect layers. After the final FEOL operations, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0124] The embodiments described herein may relate to back-end-of-the-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using on-wafer wiring (e.g., one or more metallization layers). BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. During this BEOL portion of the manufacturing phase, contacts (pads), interconnect wires, vias, and dielectric structures are formed. Modern IC processes can include more than 10 metal layers in the BEOL.

[0125] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0126] Pitch segmentation processing and patterning schemes can be implemented to enable the embodiments described herein, or can be included as part of the embodiments described herein. Pitch segmentation patterning generally refers to pitch halving, pitch quartering, etc. The pitch segmentation scheme can be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or primarily unidirectional) at a predefined pitch. Pitch segmentation processing is then implemented as a technique for increasing line density.

[0127] In an embodiment, the term "grating structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a grating structure with a tight pitch. In one such embodiment, the tight pitch is not directly achievable by the selected lithography. For example, a pattern based on the selected lithography can be formed first, but the pitch can be divided into two equal parts by patterning using a spacer mask, as is known in the art. Further, the original pitch can be divided into four equal parts by a second round of spacer mask patterning. Thus, the grating pattern described herein can have metal lines, ILD lines, or hard mask lines that are spaced apart at a substantially uniform pitch and have a substantially uniform width. For example, in some embodiments, the pitch variation will be within 10% and the width variation will be within 10%, and in some embodiments, the pitch variation will be within 5% and the width variation will be within 5%. The pattern can be manufactured by pitch halving or pitch quartering, or other pitch division methods. In an embodiment, the grating is not necessarily a single pitch.

[0128] In a first embodiment, a pitch halving may be achieved to double the linear density of the fabricated grid structure. Figure 1A Illustrated is a cross-sectional view of a starting structure of a hard mask material layer formed on an inter-layer dielectric (ILD) layer after deposition but before patterning. Figure 1B Illustrated after patterning the hard mask layer by bisecting the pitch Figure 1A Cross-sectional view of the structure.

[0129] refer to Figure 1A , a starting structure 100 has a hard mask material layer 104 formed on an inter-layer dielectric (ILD) layer 102. A patterned mask 106 is deposited on the hard mask material layer 104. The patterned mask 106 has spacers 108 formed on the hard mask material layer 104 along the sidewalls of its features (lines).

[0130] refer to Figure 1B , the hard mask material layer 104 is patterned using a pitch-halving method. Specifically, the patterned mask 106 is first removed. The resulting pattern of spacers 108 has double the density, or half the pitch or features of the mask 106. The pattern of spacers 108 is transferred to the hard mask material layer 104 by, for example, an etching process to form a patterned hard mask 110, as shown. Figure 1B As depicted in FIG. In one such embodiment, the patterned hard mask 110 is formed with a grid pattern having unidirectional lines. The grid pattern of the patterned hard mask 110 can be a grid structure with a tight pitch. For example, the tight pitch may not be directly achievable by the selected photolithography technique. Further, although not shown, the original pitch can be divided into four equal parts by a second round of spacer mask patterning. Thus, Figure 1B The grid-like pattern of the patterned hard mask 110 can have hard mask lines spaced at a constant pitch and having a constant width relative to each other. The dimensions achieved can be much smaller than the critical dimensions of the employed photolithography techniques.

[0131] Thus, for either the front-end of the line (FEOL) or back-end of the line (BEOL), or both integration schemes, a blanket film can be patterned using lithography and etching processes that can involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It will be appreciated that other pitch partitioning methods can also be implemented. In any case, in an embodiment, a grid-like layout can be fabricated using a selected lithography method such as 193nm immersion lithography (193i). Pitch partitioning can be implemented to increase the line density in the grid-like layout by a factor of n. The formation of a grid-like layout using 193i lithography plus "n" times the pitch partitioning can be designated as 193i+P / n pitch partitioning. In one such embodiment, 193nm immersion scaling can be extended for many generations using cost-effective pitch partitioning.

[0132] In the manufacture of integrated circuit devices, multi-gate transistors such as tri-gate transistors are becoming increasingly popular as device dimensions continue to shrink. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator structures. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-throughput bulk silicon substrate infrastructure.

[0133] However, scaling multi-gate transistors is not without its challenges. As the dimensions of these basic building blocks of microelectronic circuits decrease and as the sheer number of basic building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become prohibitive.

[0134] According to one or more embodiments of the present disclosure, a pitch quartering method is implemented for patterning a semiconductor layer to form semiconductor fins. In one or more embodiments, a fused fin pitch quartering method is implemented.

[0135] Figure 2A is a schematic diagram of a pitch quartering method 200 for manufacturing semiconductor fins according to an embodiment of the present disclosure. Figure 2B A cross-sectional view of a semiconductor fin fabricated using a pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0136] refer to Figure 2A, at operation (a), a photoresist layer (PR) is patterned to form a photoresist feature 202. The photoresist feature 202 can be patterned using a standard photolithography processing technique such as 193 immersion lithography. At operation (b), the photoresist feature 202 is used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form a first pillar (backbone) (BB1) feature 204. A first spacer (SP1) feature 206 is then formed adjacent to the sidewall of the first pillar feature 204. At operation (c), the first pillar feature 204 is removed to leave only the first spacer feature 206. Before or during the removal of the first pillar feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206', as shown. Figure 2A As depicted in . This thinning can be performed before (as depicted) or after the removal of BB1 (feature 204), depending on the necessary spacing and sizing required for the BB2 features (208, described below). At operation (d), the first spacer features 206 or the thinned first spacer features 206' are used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form second pillar (BB2) features 208. Second spacer (SP2) features 210 are then formed adjacent to the sidewalls of the second pillar features 208. At operation (e), the second pillar features 208 are removed to leave only the second spacer features 210. The remaining second spacer features 210 can then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins having a pitch quarter-sized relative to the initial patterned photoresist features 202. As an example, refer to Figure 2B , a plurality of semiconductor fins 250 , such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 210 as a mask for patterning (eg, dry or plasma etch patterning). Figure 2B In the example, the plurality of semiconductor fins 250 always have substantially the same pitch and spacing.

[0137] It will be appreciated that the spacing between the initially patterned photoresist features can be modified to vary the structural outcome of the pitch quartering process. In the example, Figure 3A FIG. 3 is a schematic diagram of a fused fin pitch quartering method 300 for fabricating semiconductor fins according to an embodiment of the present disclosure. Figure 3B A cross-sectional view of a semiconductor fin fabricated using a fused fin pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0138] refer to Figure 3AAt operation (a), a photoresist layer (PR) is patterned to form photoresist features 302. The photoresist features 302 may be patterned using standard photolithographic process techniques such as 193 immersion lithography, but at spacings that may ultimately interfere with the design rule required to produce a uniform, multiple-pitch pattern (e.g., referred to as sub-design rule spacings). At operation (b), the photoresist features 302 are used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form first pillar (BB1) features 304. First spacer (SP1) features 306 are then formed adjacent to the sidewalls of the first pillar features 304. However, unlike Figure 2A As a result of the closer photoresist features 302 than illustrated in FIG, some of the adjacent first spacer features 306 are fused spacer features. At operation (c), the first pillar features 304 are removed to leave only the first spacer features 306. Before or after removing the first pillar features 304, some of the first spacer features 306 may be thinned to form thinned first spacer features 306′, as shown in FIG. Figure 3A At operation (d), a material layer, such as an insulating or dielectric hard mask layer, is patterned using the first spacer features 306 and the thinned first spacer features 306' to form second pillar (BB2) features 308. Second spacer (SP2) features 310 are then formed adjacent to the sidewalls of the second pillar features 308. However, in locations where the BB2 features 308 are fused features, such as in Figure 3A No second spacer is formed at the central BB2 feature 308 of the photoresist. At operation (e), the second pillar feature 308 is removed to leave only the second spacer feature 310. The remaining second spacer features 310 can then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins having a pitch that is equal to the size of the initial patterned photoresist feature 302.

[0139] As an example, refer to Figure 3B , a plurality of semiconductor fins 350, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 310 as a mask for patterning (eg, dry or plasma etch patterning). Figure 3B In the example of FIG. 3 , the plurality of semiconductor fins 350 have varying pitches and spacings. Such a fused fin spacer patterning method can be implemented to essentially eliminate the presence of fins in certain locations of the pattern of the plurality of fins. Thus, fusing the first spacer features 306 in certain locations allows for the generation of eight fins based on two first pillar features 304 (which typically generate eight fins, as described with reference to FIG. 3 ). Figure 2A and 2BIn one example, the fins in the plate have a tighter pitch than would normally be allowed by creating the fins with a uniform pitch and then cutting away the unwanted fins, but the latter approach can still be achieved according to embodiments described herein.

[0140] In an exemplary embodiment, reference is made to Figure 3B In an integrated circuit structure, a first plurality of semiconductor fins 352 has a longest dimension along a first direction (y, into the page). Adjacent semiconductor fins 353 in the first plurality of semiconductor fins 352 are spaced apart by a first amount (S11) in a second direction (x) orthogonal to the first direction y. A second plurality of semiconductor fins 354 has a longest dimension along the first direction y. Adjacent semiconductor fins 355 in the second plurality of semiconductor fins 354 are spaced apart by a first amount (S1) in the second direction. Proximally adjacent semiconductor fins 356 and 357 belonging to the first and second plurality of semiconductor fins 352 and 354, respectively, are spaced apart by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1 but less than twice the first amount S1. In another embodiment, the second amount S2 is greater than twice the first amount S1.

[0141] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with an underlying single crystalline silicon substrate. In one embodiment, each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 has sidewalls that taper outwardly from a top to a bottom of each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 along a second direction x. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0142] In another exemplary embodiment, referring to Figure 3A and 3BA method for fabricating an integrated circuit structure includes forming a first primary pillar feature 304 (BB1 on the left) and a second primary pillar feature 304 (BB1 on the right). A primary spacer structure 306 is formed adjacent to the sidewalls of the first primary pillar feature 304 (BB1 on the left) and the second primary pillar feature 304 (BB1 on the right). The primary spacer structure 306 between the first primary pillar feature 304 (BB1 on the left) and the second primary pillar feature 304 (BB1 on the right) is fused. The first primary pillar feature (BB1 on the left) and the second primary pillar feature (BB1 on the right) are removed, and first, second, third, and fourth secondary pillar features 308 are provided. The second and third secondary pillar features (e.g., the center pair of secondary pillar features 308) are fused. A secondary spacer structure 310 is formed adjacent to the sidewalls of the first, second, third, and fourth secondary pillar features 308. The first, second, third, and fourth secondary pillar features 308 are then removed. The semiconductor material is then patterned with secondary spacer structures 310 to form semiconductor fins 350 in the semiconductor material.

[0143] In one embodiment, the first primary pillar structure 304 (BB1 on the left) and the second primary pillar structure 304 (BB1 on the right) are patterned with sub-design regular spacing between the first and second primary pillar structures. In one embodiment, the semiconductor material comprises silicon. In one embodiment, each of the semiconductor fins 350 has sidewalls that taper outwardly from the top to the bottom of each of the semiconductor fins 350 along a second direction x. In one embodiment, the semiconductor fins 350 are continuous with the underlying single crystalline silicon substrate. In one embodiment, patterning the semiconductor material with the secondary spacer structures 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, wherein adjacent semiconductor fins in the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x orthogonal to the first direction y. A second plurality of semiconductor fins 354 are formed to have a longest dimension along the first direction y, wherein adjacent semiconductor fins in the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount S1 in the second direction x. The closest semiconductor fins 356 and 357 belonging to the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354, respectively, are spaced apart from each other in the second direction x by a second number S2. In an embodiment, the second number S2 is greater than the first number S1. In one such embodiment, the second number S2 is less than two times the first number S1. In another such embodiment, the second number S2 is greater than two times but less than three times the first number S1. In an embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 254 has exactly five semiconductor fins, as shown in FIG. Figure 3B As described in .

[0144] In another aspect, it is appreciated that in a fin trimming process that performs fin removal as an alternative to the fused fin method, the fins may be trimmed (removed) during hard mask patterning or by physically removing the fins. As an example of the latter approach, Figures 4A-4C are cross-sectional views illustrating various operations in a method of fabricating a plurality of semiconductor fins, in accordance with an embodiment of the present disclosure.

[0145] refer to Figure 4A , a patterned hard mask layer 402 is formed on a semiconductor layer 404 such as a bulk single crystal silicon layer. Figure 4B , and then forming fins 406 in the semiconductor layer 404 by, for example, a dry or plasma etching process. Figure 4C , using, for example, a masking and etching process to remove selected fins 406. In the example shown, one of the fins 406 is removed, and a residual fin root 408 may be left, as shown. Figure 4C In such a "fin trim finish" approach, the hard mask 402 is patterned as a whole to provide a grid structure without removing or modifying individual features. The fin population is not modified until after the fins are fabricated.

[0146] In another aspect, multi-layer trench isolation regions, which may be referred to as shallow trench isolation (STI) structures, may be implemented between semiconductor fins. In an embodiment, a multi-layer STI structure is formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0147] Using bulk silicon for fins or tri-gate-based transistors can be desirable. However, there is a concern that the region (sub-fin) below the active silicon fin portion of the device (e.g., the gate-controlled region or HSi) is weakened or not gate-controlled. Consequently, if the source or drain region is at or below the HSi point, a leakage path may exist through the sub-fin region. This may be the case, and leakage paths in the sub-fin region should be controlled for proper device operation.

[0148] One approach to addressing the above-mentioned problem has involved using a method wherein the sub-fin region is heavily doped (e.g., more than 2E18 / cm 3 The addition of a halogen implant further increases the fin doping, causing the ends of the line fins to be doped at high levels (e.g., greater than about 1E18 / cm 3 ).

[0149] Another approach involves doping provided by sub-fin doping without necessarily delivering the same level of doping to the HSi portion of the fin. The process can involve selectively doping the sub-fin region of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer, for example, by outdiffusion of a tri-gate doped glass sub-fin. For example, selectively doping the sub-fin region of a tri-gate or FinFET transistor can mitigate sub-fin leakage while keeping the fin doping low. Incorporating solid-state dopant sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor process flow—after being recessed from the fin sidewalls—delivers well doping to the sub-fin region while keeping the main body of the fin relatively undoped.

[0150] Therefore, the process scheme may include the use of a solid-source doping layer (e.g., boron-doped oxide) deposited on the fin after fin etching. Later, after trench fill and polishing, the doping layer, along with the trench fill material, is recessed to define the fin height (HSi) for the device. This operation removes the doping layer from the fin sidewalls above HSi. As a result, the doping layer is only present along the fin sidewalls in the sub-fin region, ensuring precise control of doping placement. After a drive-in anneal, high doping is confined to the sub-fin region, resulting in a rapid transition to low doping in the adjacent fin region above HSi (which forms the transistor channel region). Generally, borosilicate glass (BSG) is used for NMOS fin doping, while phosphosilicate glass (PSG) or arsenic silicate glass (AsSG) layers are used for PMOS fin doping. In one example, such a P-type solid-state dopant source is a BSG layer with a boron concentration approximately in the range of 0.1–10 mass percent. In another example, such an N-type solid-state dopant source is a PSG layer or an AsSG layer having a phosphorus or arsenic concentration in the range of approximately 0.1-10 mass percent, respectively. A silicon nitride capping layer may be included on the doped layer, and then a silicon dioxide or silicon oxide filling material may be included on the silicon nitride capping layer.

[0151] According to another embodiment of the present disclosure, sub-fin leakage is sufficiently low for relatively thin fins (e.g., fins having a width of less than about 20 nanometers) in which an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filler material is included on the silicon nitride capping layer. It should be appreciated that doping, such as halogen doping, of the sub-fin region can also be achieved with such a structure.

[0152] Figure 5A Illustrated is a cross-sectional view of a pair of semiconductor fins separated by a triple-layer trench isolation structure according to an embodiment of the present disclosure.

[0153] refer to Figure 5AThe integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (H Si ). The first insulating layer 504 is directly on the sidewalls of the lower fin portion 502A of the fin 502. The second insulating layer 506 is directly on the first insulating layer 504 directly on the sidewalls of the lower fin portion 502A of the fin 502. The dielectric filler material 508 is directly laterally adjacent to the second insulating layer 506, and the second insulating layer 506 is directly on the first insulating layer 504 directly on the sidewalls of the lower fin portion 502A of the fin 502.

[0154] In an embodiment, first insulating layer 504 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, first insulating layer 504 comprises silicon and oxygen and does not have an atomic concentration of other atomic species greater than 1E15 atoms per cubic centimeter. In an embodiment, first insulating layer 504 has a thickness in the range of 0.5-2 nanometers.

[0155] In an embodiment, the second insulating layer 506 includes silicon and nitrogen, such as a silicon nitride insulating layer having a stoichiometry of Si 3 N 4 , a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 506 has a thickness in the range of 2-5 nanometers.

[0156] In an embodiment, dielectric fill material 508 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, a gate electrode is ultimately formed over the top of upper fin portion 502B of fin 502 and laterally adjacent to the sidewalls of upper fin portion 502B of fin 502 .

[0157] It is to be appreciated that during processing, the upper fin portion of the semiconductor fin may be eroded or consumed. Furthermore, the trench isolation structures between the fins may also become eroded to have a non-planar topography or may be formed with a non-planar fabrication topography. As an example, Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another triple-layer trench isolation structure according to another embodiment of the present disclosure is illustrated.

[0158] refer to Figure 5BThe integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 in the region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, has a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 in the region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 further has a second end 574B that is substantially coplanar with the shoulder feature 564 of the second fin 562. The second insulating layer 576 is directly on the first insulating layer 574 , which is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562 .

[0159] The dielectric fill material 578 is laterally directly adjacent to the second insulating layer 576, which is directly on the first insulating layer 574, which is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. In an embodiment, the dielectric fill material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric fill material 578 is lower than at least one of the shoulder features 554 of the first fin 552 and lower than at least one of the shoulder features 564 of the second fin 562, as shown in FIG. Figure 5B As described in .

[0160] In an embodiment, the first insulating layer 574 is an undoped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, the first insulating layer 574 includes silicon and oxygen and does not have an atomic concentration of other atomic species greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 574 has a thickness in the range of 0.5-2 nanometers.

[0161] In an embodiment, the second insulating layer 576 includes silicon and nitrogen, such as a silicon nitride insulating layer having a stoichiometric Si 3 N 4 , a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 576 has a thickness in the range of 2-5 nanometers.

[0162] In one embodiment, the dielectric fill material 578 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, a gate electrode is ultimately formed on top of the upper fin portion 552B of the first fin 552 and laterally adjacent to the sidewalls of the upper fin portion 552B of the first fin 552, and on top of the upper fin portion 562B of the second fin 562 and laterally adjacent to the sidewalls of the upper fin portion 562B of the second fin 562. The gate electrode is further formed on the dielectric fill material 578 between the first fin 552 and the second fin 562.

[0163] Figures 6A-6D Illustrated are cross-sectional views of various operations in the fabrication of a triple-layer trench isolation structure in accordance with an embodiment of the present disclosure.

[0164] refer to Figure 6A The method of manufacturing an integrated circuit structure includes forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on the fin 602, and the first insulating layer 604 is conformal to the fin 602, such as Figure 6B In an embodiment, the first insulating layer 604 includes silicon and oxygen, and does not have other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0165] refer to Figure 6C , a second insulating layer 606 is formed directly on the first insulating layer 604, and the second insulating layer 606 is conformal to the first insulating layer 604. In an embodiment, the second insulating layer 606 includes silicon and nitrogen. A dielectric filling material 608 is formed directly on the second insulating layer 606, such as Figure 6D As described in .

[0166] In an embodiment, the method further involves recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 to provide a dielectric fill material 608 having an exposed upper fin portion 602A (eg, such as Figure 5A and 5B The resulting structure may be as shown in FIG. Figure 5A 5B. In one embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching or dry etching process.

[0167] In one embodiment, a chemical vapor deposition process is used to form the first insulating layer 604. In one embodiment, a chemical vapor deposition process is used to form the second insulating layer 606. In one embodiment, a spin-on process is used to form the dielectric fill material 608. In one such embodiment, the dielectric fill material 608 is a spin-on material and is exposed to a steam treatment, for example, before or after a recess etching process, to provide a cured material comprising silicon and oxygen. In one embodiment, a gate electrode is ultimately formed over the top of the upper fin portion of the fin 602 and laterally adjacent to the sidewalls of the upper fin portion of the fin 602.

[0168] In another aspect, gate sidewall spacer material may be retained over certain trench isolation regions as protection against trench isolation region erosion during subsequent processing operations. For example, Figures 7A-7E Angled three dimensional cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present disclosure.

[0169] refer to Figure 7A A method of fabricating an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewalls of the lower fin portion 702A of the fin 702. A gate structure 706 is formed over the upper fin portion 702B and over the insulating structure 704. In an embodiment, the gate structure is a placeholder or dummy gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed conformally with the upper fin portion 702B of the fin 702, with the gate structure 706, and with the insulating structure 704.

[0170] refer to Figure 7B A hard mask material 710 is formed over the dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

[0171] refer to Figure 7C , the hard mask material 710 is recessed to form a recessed hard mask material 712 and expose a portion of the dielectric material 708 that conforms to the upper fin portion 702B of the fin 702 and to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 that conforms to the insulating structure 704. In one embodiment, a wet etching process is used to recess the hard mask material 710. In another embodiment, an ashing, dry etching, or plasma etching process is used to recess the hard mask material 710.

[0172] refer to Figure 7DThe dielectric material 708 is anisotropically etched to form a patterned dielectric material 714 (eg, dielectric spacer 714A) along sidewalls of the gate structure 706 , along portions of sidewalls of the upper fin portion 702B of the fin 702 , and over the insulating structure 704 .

[0173] refer to Figure 7E ,from Figure 7D The recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In an embodiment, further processing includes forming an embedded source or drain structure on an opposite side of the gate structure 706, as described in more detail below.

[0174] Reference again Figure 7E In an embodiment, an integrated circuit structure 700 includes a first fin (702 on the left), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure further includes a second fin (702 on the right), such as a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 directly abuts the sidewalls of the lower fin portion 702A of the first fin and directly abuts the sidewalls of the lower fin portion 702A of the second fin. A gate electrode 706 is disposed over the upper fin portion 702B of the first fin (702 on the left), over the upper fin portion 702B of the second fin (702 on the right), and over the first portion 704 of the insulating structure 704. A first dielectric spacer 714A is disposed along the sidewalls of the upper fin portion 702B of the first fin (702 on the left), and a second dielectric spacer 702C is disposed along the sidewalls of the upper fin portion 702B of the second fin (702 on the right). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B over the second portion 704B of the insulating structure 704 between the first fin ( 702 on the left) and the second fin ( 702 on the right).

[0175] In an embodiment, the first and second dielectric spacers 714B and 714C include silicon and nitrogen, such as a silicon nitride material having a stoichiometry of Si 3 N 4 , a silicon-rich silicon nitride material, or a silicon-poor silicon nitride material.

[0176] In an embodiment, the integrated circuit structure 700 further includes an embedded source or drain structure on opposite sides of the gate electrode 706, the embedded source or drain structure having a bottom surface below the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, and the source or drain structure having a top surface above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, as described below in connection with Figure 9B In an embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric fill material directly and laterally on the second insulating layer, as also described below in connection with Figure 9B As described.

[0177] Figures 8A-8F The present invention illustrates various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0178] refer to Figure 8A The method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion (at Figure 8A An insulating structure 704 is formed directly adjacent to the sidewalls of the lower fin portion 702A of the fin 702. A pair of gate structures 706 are formed above the upper fin portion 702B and above the insulating structure 704. It is to be appreciated that Figures 8A-8F The perspective shown in FIG is slightly projected to show the insulating structure and portion of the gate structure 706 in front of (outside of) the upper fin portion 702B, where the upper fin portion extends slightly into the page. In an embodiment, the gate structure 706 is a placeholder or dummy gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0179] refer to Figure 8B , which corresponds to the connection Figure 7A The depicted process operations form the dielectric material 708 conformally with the upper fin portion 702B of the fin 702 , conformally with the gate structure 706 , and conformally with the exposed portion of the insulating structure 704 .

[0180] refer to Figure 8C , which corresponds to the connection Figure 7B The depicted process operates to form a hard mask material 710 over the dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0181] refer to Figure 8D , which corresponds to the connection Figure 7C The process described above recesses the hard mask material 710 to form a recessed hard mask material 712 and exposes a portion of the dielectric material 708 that conforms to the upper fin portion 702B of the fin 702 and to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 that conforms to the insulating structure 704. In one embodiment, a wet etching process is used to recess the hard mask material 710. In another embodiment, an ashing, dry etching, or plasma etching process is used to recess the hard mask material 710.

[0182] refer to Figure 8E , which corresponds to the connection Figure 7D The depicted process operates to anisotropically etch the dielectric material 708 to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as portion 714A), along portions of the sidewalls of the upper fin portion 702B of the fin 702 , and over the insulating structure 704 .

[0183] refer to Figure 8F , which corresponds to the connection Figure 7E Describe the process operation, from Figure 8E The recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In an embodiment, further processing includes forming an embedded source or drain structure on an opposite side of the gate structure 706, as described in more detail below.

[0184] Reference again Figure 8F In an embodiment, the integrated circuit structure 700 includes a fin 702 such as a silicon fin having a lower fin portion (at Figure 8F The lower fin portion 702B is directly adjacent to the sidewalls of the lower fin portion of the fin 702. The first gate electrode (706 on the left) is located above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. The second gate electrode (706 on the right) is located above the upper fin portion 702B and above the second portion 704A′ of the insulating structure 704. A first dielectric spacer (714A on the right side of the left 706) is located along the sidewalls of the first gate electrode (706 on the left), and a second dielectric spacer (714A on the left side of the right 706) is located along the sidewalls of the second gate electrode (706 on the right). The second dielectric spacer is continuous with the first dielectric spacer above the third portion 704A″ of the insulating structure 704 between the first gate electrode (706 on the left) and the second gate electrode (706 on the right).

[0185] Figure 9A An embodiment of the present disclosure is provided for illustrating an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis. Figure 9B The invention illustrates an integrated circuit structure including an epitaxial source or drain region and a multi-layer trench isolation structure according to an embodiment of the present disclosure. Figure 7E A cross-sectional view taken along the b-b' axis.

[0186] refer to Figure 9A and 9B In an embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on opposite sides of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below the top surfaces 990 of the first and second dielectric spacers 714B and 714C along sidewalls of the upper fin portions 702B of the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above the top surfaces of the first and second dielectric spacers 714B and 714C along sidewalls of the upper fin portions 702B of the first and second fins 702.

[0187] In an embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926 such as Figure 9A In one embodiment, where permanent gate structure 920 is over insulating structure 704, permanent gate structure 920 is formed on residual polysilicon portion 930, which may be a remnant of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0188] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric filler material 906 directly and laterally on the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric filler material 906 includes silicon and oxygen.

[0189] In another aspect, an epitaxial embedded source or drain region is implemented as a source or drain structure for a semiconductor fin. As an example, Figure 10 A cross-sectional view of an integrated circuit structure taken at a source or drain location according to an embodiment of the present disclosure is illustrated.

[0190] refer to Figure 10The integrated circuit structure 1000 includes a P-type device, such as a P-type metal oxide semiconductor (PMOS) device, and an N-type device, such as an N-type metal oxide semiconductor (NMOS) device.

[0191] Figure 10 The PMOS device includes a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain locations, the upper portions of the fins 1002 have been removed, and the same or different semiconductor material is grown to form a source or drain structure 1004. It is to be appreciated that the source or drain structure 1004 will appear the same in a cross-sectional view taken on either side of the gate electrode, e.g., they will appear essentially the same on the source side as on the drain side. In an embodiment, as depicted, the source or drain structure 1004 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as depicted, the source or drain structure 1004 is strongly faceted. In an embodiment, a conductive contact 1008 is formed above the source or drain structure 1004. However, in one such embodiment, the strong faceting and relatively wide growth of the source or drain structure 1004 at least to some extent inhibits good coverage by the conductive contact 1008 .

[0192] Figure 10 The NMOS device includes a second plurality of semiconductor fins 1052, such as silicon fins formed from bulk silicon substrate 1001. At the source or drain locations, the upper portions of the fins 1052 have been removed, and the same or different semiconductor material is grown to form source or drain structures 1054. It will be appreciated that the source or drain structures 1054 will appear identical in a cross-sectional view taken on either side of the gate electrode, e.g., they will appear essentially identical on the source side as on the drain side. In an embodiment, as depicted, the source or drain structures 1054 have a portion below the upper surface of the insulating structure 1006 and a portion above the upper surface. In an embodiment, as depicted, the source or drain structures 1054 are weakly faceted relative to the source or drain structures 1004. In an embodiment, a conductive contact 1058 is formed over the source or drain structures 1054. In one such embodiment, the relatively weak faceting and resulting relatively narrow growth of the source or drain structure 1054 (as compared to the source or drain structure 1004 ) enhances good coverage by the conductive contact 1058 .

[0193] The shape of the source or drain structure of the PMOS device can be changed to increase the contact area with the overlapping contact portion. For example, Figure 11 A cross-sectional view of another integrated circuit structure taken at a source or drain location according to an embodiment of the present disclosure is illustrated.

[0194] refer to Figure 11 , the integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not depicted, the first epitaxial source or drain structure 1104 is at a first side of a first gate electrode (which may be formed over an upper fin portion of the fin 1102, such as a channel portion), and a second epitaxial source or drain structure is embedded in the first fin 1102 at a second side of such first gate electrode opposite the first side. In an embodiment, the first epitaxial source or drain structure 1104 and the second epitaxial source or drain structure include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick-shaped profile, such as Figure 11 A first conductive electrode 1108 is located on top of the first epitaxial source or drain structure 1104 .

[0195] Reference again Figure 11 In one embodiment, the integrated circuit structure 1100 further includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. Although not depicted, in one embodiment, the third epitaxial source or drain structure 1154 is located on a first side of a second gate electrode (which may be formed above an upper fin portion, such as a channel portion, of the fin 1152). A fourth epitaxial source or drain structure is embedded in the second fin 1152 on a second side of the second gate electrode, opposite the first side. In one embodiment, the third and fourth epitaxial source or drain structures 1154 and 1105 comprise silicon and have a profile substantially identical to the profiles of the first and second epitaxial source or drain structures 1104 and 1105. A second conductive electrode 1158 is located above the third epitaxial source or drain structure 1154.

[0196] In an embodiment, the first epitaxial source or drain structure 1104 is weakly faceted. In an embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers.

[0197] In an embodiment, the first epitaxial source or drain structure 1104 is graded from a germanium concentration of approximately 20% at a bottom 1104A of the first epitaxial source or drain structure 1104 to a germanium concentration of approximately 45% at a top 1104B of the first epitaxial source or drain structure 1104. In an embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

[0198] Figures 12A-12D Illustrated are cross-sectional views representing various operations in fabricating an integrated circuit structure and taken at a source or drain location, in accordance with an embodiment of the present disclosure.

[0199] refer to Figure 12A , a method of manufacturing an integrated circuit structure includes forming a fin, such as a silicon fin, formed from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In an embodiment, although not depicted, a gate electrode is formed over a portion of the upper fin portion 1202B of the fin 1202 at a location that enters the page. Such a gate electrode has a first side opposite to a second side, and a source or drain location is defined on the first and second sides. For example, for illustrative purposes, a gate electrode is cut out at one of the source or drain locations on one of the sides of the gate electrode. Figures 12A-12D The cross-sectional location of the view.

[0200] refer to Figure 12B , the source or drain location of the fin 1202 is recessed to form a recessed fin portion 1206. The recessed source or drain location of the fin 1202 may be at one side of the gate electrode and at a second side of the gate electrode. Figure 12A and 12B Both, in embodiments, the dielectric spacer 1204 is formed along a sidewall of a portion of the fin 1202, such as at a side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below a top surface 1204A of the dielectric spacer 1204.

[0201] refer to Figure 12C , for example, an epitaxial source or drain structure 1208 is formed on the recessed fin 1206, and thus the epitaxial source or drain structure 1208 can be formed at one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 at a second side of such a gate electrode. In an embodiment, the epitaxial source or drain structure 1208 includes silicon and germanium and has a matchstick-shaped profile, such as Figure 12CIn an embodiment, a dielectric spacer 1204 is included and is along a lower portion 1208A of a sidewall of an epitaxial source or drain structure 1208, as depicted.

[0202] refer to Figure 12D , a conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive fill material 1210B. In one embodiment, the conductive electrode 1210 follows the contour of the epitaxial source or drain structure 1208, as depicted. In other embodiments, the upper portion of the epitaxial source or drain structure 1208 is eroded during the fabrication of the conductive electrode 1210.

[0203] In another aspect, fin trim isolation (FTI) and a single gate spacer for isolated fins are described. Non-planar transistors that utilize fins of semiconductor material protruding from the substrate surface employ gate electrodes surrounding two, three, or even all sides of the fin (i.e., dual-gate, tri-gate, nanowire transistors). Source and drain regions are then typically formed in the fin on either side of the gate electrode, or as regrown portions of the fin. In order to isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or spacer can be formed between two adjacent fins. Such an isolation gap generally requires some kind of masked etch. Once isolated, a gate stack is then patterned over each fin, again typically utilizing some kind of masked etch (e.g., line etch or open etch, depending on the specific implementation).

[0204] One potential issue with the aforementioned fin isolation technology is that the gate does not self-align with the end of the fin, and the alignment of the gate stack pattern with the semiconductor fin pattern relies on the overlay of the two patterns. Consequently, photolithographic overlay tolerances are added to the sizing of the semiconductor fin and the isolation gap, requiring the fin to have a greater length and the isolation gap to be larger than they would otherwise be for a given level of transistor functionality. Device architectures and manufacturing techniques that reduce this oversizing therefore offer highly advantageous improvements in transistor density.

[0205] Another potential issue with the fin isolation techniques described above is that the stress in the semiconductor fins, which is desirable for improving carrier mobility, may be lost from the channel region of the transistor where excess fin surface is released during fabrication, allowing fin strain to relax. Device architectures and fabrication techniques that maintain higher levels of desired fin stress therefore provide advantageous improvements in non-planar transistor performance.

[0206] According to embodiments of the present disclosure, through-gate fin isolation architectures and techniques are described herein. In the illustrated exemplary embodiments, non-planar transistors in a microelectronic device, such as an integrated circuit (IC), are isolated from each other in a manner that is self-aligned to the transistor's gate electrode. While embodiments of the present disclosure are applicable to virtually any IC employing non-planar transistors, exemplary ICs include, but are not limited to, microprocessor cores including logic and memory (SRAM) sections, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0207] In an embodiment, isolation regions are used to electrically isolate the two ends of adjacent semiconductor fins from each other, and only one patterned mask level is used to position the isolation regions relative to the gate electrode. In an embodiment, a single mask is used to form a plurality of sacrificial placeholder strips having a fixed pitch, a first subset of the placeholder strips defining the position or size of the isolation region, and a second subset of the placeholder strips defining the position or size of the gate electrode. In certain embodiments, the first subset of the placeholder strips is removed, and an isolation cut is made into the semiconductor fin in the opening resulting from the removal of the first subset, and the second subset of the placeholder strips is ultimately replaced by a non-sacrificial gate electrode stack. Because a subset of the placeholders for gate electrode replacement is used to form the isolation region, the method and resulting architecture are referred to herein as "through-gate" isolation. One or more through-gate isolations described herein may, for example, enable higher transistor densities and higher levels of favorable transistor channel stress.

[0208] With the isolation defined after the gate electrode is placed or defined, greater transistor density can be achieved because the fin isolation can be sized and placed perfectly on-pitch with respect to the gate electrode, so that both the gate electrode and the isolation region are integer multiples of the minimum feature pitch of a single masking level. In other embodiments where the semiconductor fin has a lattice mismatch with the substrate on which the fin is placed, a greater degree of strain can be maintained by defining the isolation after the gate electrode is placed or defined. For such embodiments, other features of the transistor formed before the fin tip is defined (such as the gate electrode and added source or drain material) help mechanically maintain the fin strain after the isolation cut is made into the fin.

[0209] To provide further context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are separated from their neighbors by two or more dummy gates having buried fins. The cells are isolated by etching fins beneath the two or more dummy gates, which connect one cell to another. Scaling can yield significant benefits if the number of dummy gates separating adjacent cells can be reduced from two or more to one. As explained above, one solution requires two or more dummy gates. The fins beneath the two or more dummy gates are etched during fin patterning. A potential problem with such an approach is that the dummy gates consume space on the chip that could be used for cells. In an embodiment, the method described herein enables the use of only a single dummy gate to separate adjacent cells.

[0210] In an embodiment, the fin trim isolation method is implemented as a self-aligned patterning scheme. Here, the fins below a single gate are etched away. Thus, adjacent cells can be separated by a single dummy gate. Advantages of such an approach can include saving space on the chip and allowing more computing power for a given area. This method can also allow fin trimming to be performed at sub-fin pitch distances.

[0211] Figure 13A and 13B Illustrated are plan views showing various operations in a method of patterning a fin with multiple gate spacers for forming a local isolation structure, in accordance with an embodiment of the present disclosure.

[0212] refer to Figure 13A , showing a plurality of fins 1302 having a length along a first direction 1304. Shown is a grid 1306 along a second direction 1308 orthogonal to the first direction 1304 with spaces 1307 therebetween, the grid 1306 defining locations for ultimately forming a plurality of gate lines.

[0213] refer to Figure 13B A portion of the plurality of fins 1302 is cut (e.g., removed by an etching process) to leave a fin 1310 having a cutout 1312 therein. The isolation structure ultimately formed in the cutout 1312 thus has a size larger than a single gate line, for example, the size of three gate lines 1306. Therefore, the gate structure ultimately formed along the location of the gate line 1306 will be formed at least partially above the isolation structure formed in the cutout 1312. Therefore, the cutout 1312 is a relatively wide fin cutout.

[0214] Figures 14A-14D Illustrated are plan views showing various operations in a method of patterning a fin having a single gate spacer for forming a local isolation structure in accordance with another embodiment of the present disclosure.

[0215] refer to Figure 14A The method of fabricating an integrated circuit structure includes forming a plurality of fins 1402, each of the plurality of fins 1402 having a longest dimension along a first direction 1404. A plurality of gate structures 1406 are formed over the plurality of fins 1402, each of the gate structures 1406 having a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In an embodiment, the gate structures 1406 are sacrificial gate lines or dummy gate lines, for example, made of polysilicon. In an embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0216] refer to Figure 14B , a dielectric material structure 1410 is formed between adjacent gate structures 1406 in the plurality of gate structures 1406 .

[0217] refer to Figure 14C , removing a portion 1412 of one of the plurality of gate structures 1406 to expose a portion 1414 of each of the plurality of fins 1402. In an embodiment, removing a portion 1412 of one of the plurality of gate structures 1406 involves using a lithographic window 1416 that is wider than a width 1418 of the portion 1412 of the one of the plurality of gate structures 1406.

[0218] refer to Figure 14D , removing the exposed portion 1414 of each of the plurality of fins 1402 to form the kerf region 1420. In an embodiment, a dry or plasma etching process is used to remove the exposed portion 1414 of each of the plurality of fins 1402. In an embodiment, removing the exposed portion 1414 of each of the plurality of fins 1402 involves etching to a depth that is less than the height of the plurality of fins 1402. In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins 1402. In an embodiment, the depth is deeper than the depth of the active portion of the plurality of fins 1402 to provide an isolation margin. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without laterally etching or substantially laterally etching source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402 .

[0219] In an embodiment, the cutout region 1420 is ultimately filled with an insulating layer, for example, in the location of the removed portion 1414 of each of the plurality of fins 1402. An exemplary insulating layer or "polymer cutout" or "plug" structure is described below. However, in other embodiments, the cutout region 1420 is only partially filled with an insulating layer, and then a conductive structure is formed in the insulating layer. The conductive structure can serve as a local interconnect. In an embodiment, before filling the cutout region 1420 with an insulating layer or with an insulating layer that accommodates a local interconnect structure, dopants can be implanted or delivered through the cutout region 1420 via a solid source dopant layer into the locally cut portion of one or more fins.

[0220] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multiple gate spacers for local isolation according to an embodiment of the present disclosure is illustrated.

[0221] refer to Figure 15 , the silicon fin 1502 has a first fin portion 1504 laterally adjacent to a second fin portion 1506. By relatively wide cutouts 1508 (such as contact Figure 13A and 13B A relatively wide cutout 1508 (as depicted) having a width X separates the first fin portion 1504 from the second fin portion 1506. A dielectric filler material 1510 is formed in the relatively wide cutout 1508 and electrically isolates the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are located above the silicon fin 1502, each of which may include a gate dielectric and gate electrode stack 1514, a dielectric capping layer 1516, and sidewall spacers 1518. Two gate lines (the two gate lines 1512 on the left) occupy the relatively wide cutout 1508 and, as such, effectively separate the first fin portion 1504 from the second fin portion 1506 by two dummy or inactive gates.

[0222] In contrast, the fin sections can be separated by a single gate distance. As an example, Figure 16A A cross-sectional view of an integrated circuit structure having a fin with a single gate spacer for local isolation according to another embodiment of the present disclosure is illustrated.

[0223] refer to Figure 16A , the silicon fin 1602 has a first fin portion 1604 laterally adjacent to a second fin portion 1606. By relatively narrow cutouts 1608 (such as contact Figures 14A-14D The relatively narrow cutout 1608 has a width Y, wherein Y is less than Figure 151608. A dielectric fill material 1610 is formed in the relatively narrow cutout 1608 and electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are located above the silicon fin 1602, each of which can include a gate dielectric and gate electrode stack 1614, a dielectric capping layer 1616, and sidewall spacers 1618. The dielectric fill material 1610 takes the position previously occupied by a single gate line and, as such, separates the first fin portion 1604 from the second fin portion 1606 via a single "plugged" gate line. In one embodiment, residual spacer material 1620 remains on the sidewalls at the location of the removed gate line portion, as depicted. It is to be appreciated that other areas of the fin 1602 may be isolated from each other by two or even more inactive gate lines (area 1622 having three inactive gate lines) made by an earlier, wider fin cutting process, as described below.

[0224] Reference again Figure 16A , integrated circuit structure 1600 includes a fin 1602, such as a silicon fin. Fin 1602 has a longest dimension along a first direction 1650. Isolation structure 1610 separates a first upper portion 1604 of fin 1602 from a second upper portion 1606 of fin 1602 along first direction 1650. Isolation structure 1610 has a center 1611 along first direction 1650.

[0225] A first gate structure 1612A is over the first upper portion 1604 of the fin 1602. The first gate structure 1612A has a longest dimension along a second direction 1652 orthogonal to the first direction 1650 (e.g., into the page). A center 1613A of the first gate structure 1612A is spaced apart from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. A second gate structure 1612B is over the first upper portion 1604 of the fin. The second gate structure 1612B has a longest dimension along the second direction 1652. A center 1613B of the second gate structure 1612B is spaced apart from the center 1613A of the first gate structure 1612A by the pitch along the first direction 1650. A third gate structure 1612C is over the second upper portion 1606 of the fin 1602. The third gate structure 1612C has a longest dimension along the second direction 1652. A center 1613C of the third gate structure 1612C is spaced apart from a center 1611 of the isolation structure 1610 by this pitch along the first direction 1650. In an embodiment, the isolation structure 1610 has a top that is substantially coplanar with a top of the first gate structure 1612A, with a top of the second gate structure 1612B, and with a top of the third gate structure 1612C, as depicted.

[0226] In an embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between the sidewalls of a high-k gate dielectric layer 1662, as illustrated for the exemplary third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewalls of the high-k gate dielectric layer 1662.

[0227] In one embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the isolation structure 1610. A second epitaxial semiconductor region 1664B is located on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is located on the second upper portion 1606 of the fin 1602 between the third gate structure 1612C and the isolation structure 1610. In one embodiment, the first, second, and third epitaxial semiconductor regions 1664A, 1664B, and 1664C include silicon and germanium. In another embodiment, the first, second, and third epitaxial semiconductor regions 1664A, 1664B, and 1664C include silicon.

[0228] In an embodiment, isolation structure 1610 induces stress on first upper portion 1604 of fin 1602 and on second upper portion 1606 of fin 1602. In one embodiment, the stress is compressive. In another embodiment, the stress is tensile. In other embodiments, isolation structure 1610 is a partially filled insulating layer, and then a conductive structure is formed therein. The conductive structure can serve as a local interconnect. In an embodiment, dopants are implanted or delivered into the locally cut portion of the one or more fins via a solid source dopant layer before forming isolation structure 1610 with an insulating layer or with an insulating layer that accommodates a local interconnect structure.

[0229] In another aspect, it is to be appreciated that an isolation structure such as the isolation structure 1610 described above may be formed at a localized location of the fin cut or at a wider location of the fin cut in place of an active gate electrode. Additionally, the depth of such localized locations or wider locations of the fin cut may be formed to vary relative to one another within the fin. In a first example, Figure 16B A cross-sectional view showing a location at which a fin isolation structure may be formed instead of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0230] refer to Figure 16BA fin 1680, such as a silicon fin, is formed over and may be continuous with a substrate 1682. Fin 1680 has a fin tip or wide fin notch 1684, which may be formed during fin patterning, such as in the fin trim finish method described above. Fin 1680 also has a partial notch 1686, where a portion of fin 1680 is removed, for example, using a fin trim isolation method in which a dielectric plug is used in place of a dummy gate as described above. An effective gate electrode 1688 is formed over the fin and, for illustrative purposes, is shown slightly in front of fin 1680 with fin 1680 in the background, with the dashed lines indicating the covered area from a front view. Dielectric plugs 1690 may be formed at the fin tip or wide fin notch 1684 in place of an effective gate at these locations. Additionally or alternatively, dielectric plugs 1692 may be formed at the partial notch 1686 in place of an effective gate at these locations. It is to be appreciated that an epitaxial source or drain region 1694 is also shown at a location of the fin 1680 between the effective gate electrode 1688 and the plug 1690 or 1692. Additionally, in an embodiment, the surface roughness of the fin tip at the localized notch 1686 is rougher than that of the fin tip at the location of the wider notch, as shown in FIG. Figure 16B As described in .

[0231] Figures 17A-17C Various depth possibilities for fin cuts fabricated using the fin trim isolation method are illustrated according to embodiments of the present disclosure.

[0232] refer to Figure 17A , a semiconductor fin 1700, such as a silicon fin, is formed above and may be continuous with an underlying substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B as defined by the height of the insulating structure 1704 relative to the fin 1700. A local fin isolation cut 1706A separates the fin 1700 into a first fin portion 1710 and a second fin portion 1712. Figure 17A In the example shown along the aa′ axis, the depth of the local fin isolation cut 1706A is the full depth of the fin 1700 to the substrate 1702 .

[0233] refer to Figure 17B In the second example, as shown along the aa' axis, the depth of the local fin isolation cut 1706B is deeper than the entire depth of the fin 1700 to the substrate 1702. That is, the cut 1706B extends into the underlying substrate 1702.

[0234] refer to Figure 17C In the third example, as shown along the aa' axis, the depth of the local fin isolation cut 1706C is less than the entire depth of the fin 1700, but deeper than the upper surface of the isolation structure 1704. Referring again to Figure 17C In the fourth example, as shown along the aa′ axis, the depth of the local fin isolation cut 1706D is less than the entire depth of the fin 1700 and is at a level that is approximately coplanar with the upper surface of the isolation structure 1704 .

[0235] Figure 18 Illustrated are a plan view and corresponding cross-sectional view taken along the aa' axis showing possible options for depth of a localized location versus a wider location of a fin cutout within a fin, according to an embodiment of the present disclosure.

[0236] refer to Figure 18 , first and second semiconductor fins 1800 and 1802, such as silicon fins, have upper fin portions 1800B and 1802B extending above an insulating structure 1804. Both fins 1800 and 1802 have a fin tip or wide fin cut 1806, which may be formed during fin patterning, such as in the fin trim finish method described above. Both fins 1800 and 1802 also have a partial cut 1808, where a portion of the fin 1800 or 1802 is removed, such as using a fin trim isolation method in which a dummy gate is replaced with a dielectric plug as described above. In an embodiment, the surface roughness of the tips of the fins 1800 and 1802 at the partial cut 1808 is rougher than the fin tips at the location of 1806, such as Figure 18 As described in .

[0237] refer to Figure 18 1804. Also seen in this cross-sectional view is the remnant 1810 of the fin that has been removed during the fin trimming finish process prior to forming the insulating structure 1804, as described above. Although shown as protruding above the substrate, the remnant 1810 may also be at the level of the substrate or into the substrate, as depicted by the additional exemplary wide cut depth 1820. It is to be appreciated that the wide cut 1806 for the fins 1800 and 1802 may also be at the level described for the cut depth 1820, an example of which is depicted. The local cut 1808 may have a depth corresponding to that for the substrate. Figures 17A-17C Exemplary depths of depth are described, as depicted.

[0238] Common Reference Figure 16A 、 16B, 17A-17C and 18, according to an embodiment of the present disclosure, an integrated circuit structure includes a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. A gate structure includes a gate electrode above the top of the fin and laterally adjacent to a sidewall of a region of the first portion of the fin. The gate structure has a width along the first direction, and the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along the first direction. A second isolation structure is above the second end of the first portion of the fin, the second end being opposite to the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness that is less than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced apart from the center of the gate structure by a pitch along the first direction.

[0239] In one embodiment, the first end of the first portion of the fin has a scalloped morphology, such as Figure 16B As depicted in . In one embodiment, the first epitaxial semiconductor region is on a first portion of the fin between the gate structure and the first isolation structure. The second epitaxial semiconductor region is on a first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction being wider than the width of the first portion of the fin below the gate structure along the second direction, for example, as described in connection with Figure 11 and 12D The epitaxial features described are Figure 11 and 12D The fin portions on which they are grown are wider in the perspective shown in In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along sidewalls of the gate electrode.

[0240] Common Reference Figure 16A 、 16B, 17A-17C and 18, according to another embodiment of the present disclosure, an integrated circuit structure includes a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the direction. The first end of the first portion of the fin has a certain depth. The gate structure includes a gate electrode above the top of the fin and laterally adjacent to a sidewall of a region of the first portion of the fin. A second isolation structure is above the second end of the first portion of the fin, the second end being opposite the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0241] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by a pitch along the direction.

[0242] Common Reference Figure 16A 、 16B , 17A-17C and 18, according to another embodiment of the present disclosure, an integrated circuit structure includes a first fin comprising silicon, the first fin having a top and sidewalls, wherein the top has a longest dimension along a certain direction, and a discontinuity separates a first end of a first portion of the first fin from a first end of a second portion of the fin along the direction. The first portion of the first fin has a second end opposite the first end, and the first end of the first portion of the fin has a certain depth. The integrated circuit structure also includes a second fin comprising silicon, the second fin having a top and sidewalls, wherein the top has a longest dimension along the direction. The integrated circuit structure also includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, wherein the top has a longest dimension along the direction, and the top is non-coplanar with the depth of the first end of the first portion of the fin.

[0243] In one embodiment, the first end of the first portion of the fin has a depth that is lower than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the depth of the first end of the first portion of the fin. In one embodiment, the first end of the first portion of the fin has a depth that is higher than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is lower than the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is higher than the top of the residual fin portion.

[0244] In another aspect, a dielectric plug formed in the location of a localized or wide fin cut can be tailored to provide a specific stress to the fin or fin portion. In such an embodiment, the dielectric plug can be referred to as a fin tip stressor.

[0245] One or more embodiments relate to fabricating fin-based semiconductor devices. Performance improvements for such devices can be achieved through channel stress induced during a polymer plug fill process. Embodiments may include leveraging material properties during the polymer plug fill process to induce mechanical stress in a metal oxide semiconductor field effect transistor (MOSFET) channel. As a result, the induced stress can improve transistor mobility and drive current. Furthermore, the plug fill methods described herein can eliminate any seam or void formation during deposition.

[0246] To provide context, manipulating the unique material properties of the plug fill adjacent to the fin can induce stress within the channel. According to one or more embodiments, by adjusting the composition, deposition, and post-processing conditions of the plug fill material, the stress in the channel is modulated to benefit both NMOS and PMOS transistors. In addition, such a plug can reside deeper in the fin substrate than other common stressor technologies such as epitaxial source or drain. The nature of the plug fill to achieve this effect also eliminates seams or voids during deposition and mitigates certain defect modes during the process.

[0247] To provide further context, there is currently no intentional stress engineering for gate (polymer) plugs. Unfortunately, stress enhancement from traditional stressors, such as epitaxial source or drain, dummy polymer gate removal, stress liners, etc., tends to decrease as device pitch shrinks. To address one or more of the above issues, according to one or more embodiments of the present disclosure, additional stressors are incorporated into the transistor structure. Another possible benefit of utilizing such a process may be the elimination of seams or voids within the plug that may be common when utilizing other chemical vapor deposition methods.

[0248] Figure 19A and 19B Illustrated are cross-sectional views of various operations in a method of selecting fin tip stressor locations at a fin tip having a wide notch (eg, as part of a fin trimming finish process as described above), in accordance with an embodiment of the present disclosure.

[0249] refer to Figure 19A , a fin 1900, such as a silicon fin, is formed over and may be continuous with a substrate 1902. The fin 1900 has a fin tip or wide fin cutout 1904, which may be formed during fin patterning, such as in the fin trimming finishing method described above. An effective gate electrode location 1906 and a dummy gate electrode location 1908 are formed over the fin 1900 and, for purposes of illustration, are shown slightly in front of the fin 1900 with the fin 1900 in the background, with the dotted lines representing the covered area from a front view. It will be appreciated that an epitaxial source or drain region 1910 is also shown at a location on the fin 1900 between the gate locations 1906 and 1908. Additionally, an interlayer dielectric material 1912 is included at a location on the fin 1900 between the gate locations 1906 and 1908.

[0250] refer to Figure 19B , the gate placeholder structure or dummy gate site 1908 is removed, thereby exposing the fin tip or wide fin cutout 1904. This removal creates an opening 1920, where a dielectric plug, such as a fin tip stressor dielectric plug, may ultimately be formed.

[0251] Figure 20A and 20B Illustrated are cross-sectional views of various operations in a method of selecting fin tip stressor locations at a fin tip having a localized notch (eg, as part of a fin trim isolation process as described above), in accordance with an embodiment of the present disclosure.

[0252] refer to Figure 20AA fin 2000, such as a silicon fin, is formed above and may be continuous with a substrate 2002. Fin 2000 has a localized cutout 2004 where a portion of fin 2000 is removed, for example, using a fin trim isolation process in which a dummy gate is removed as described above and the fin is etched in a localized location. An active gate electrode location 2006 and a dummy gate electrode location 2008 are formed above fin 2000 and, for purposes of illustration, are shown slightly in front of fin 2000 with fin 2000 in the background, with dashed lines indicating the covered area from a front view. It should be appreciated that an epitaxial source or drain region 2010 is also shown at a location on fin 2000 between gate locations 2006 and 2008. Additionally, an interlayer dielectric material 2012 is included at a location on fin 2000 between gate locations 2006 and 2008.

[0253] refer to Figure 20B , the gate placeholder structure or dummy gate electrode location 2008 is removed, thereby exposing the fin end with the partial notch 2004. This removal creates an opening 2020, where a dielectric plug, such as a fin end stressor dielectric plug, may eventually be formed.

[0254] Figures 21A-21M Illustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure with differentiated fin-end dielectric plugs, in accordance with an embodiment of the present disclosure.

[0255] refer to Figure 21A , starting structure 2100 includes an NMOS region and a PMOS region. The NMOS region of starting structure 2100 includes a first fin 2102, such as a first silicon fin, formed above and may be continuous with substrate 2104. First fin 2102 has a fin tip 2106, which may be formed by a partial or wide fin cut. A first effective gate electrode location 2108 and a first dummy gate electrode location 2110 are formed above first fin 2102 and, for illustrative purposes, are shown slightly in front of first fin 2102, with first fin 2102 in the background, with dashed lines indicating the covered area from a front view. An epitaxial N-type source or drain region 2112, such as an epitaxial silicon source or drain structure, is also shown at a location on first fin 2102 between gate locations 2108 and 2110. Additionally, an interlayer dielectric material 2114 is included at a location of the first fin 2102 between the gate locations 2108 and 2110 .

[0256] The PMOS region of the starting structure 2100 includes a second fin 2122, such as a second silicon fin, formed above and contiguous with the substrate 2104. The second fin 2122 has a fin tip 2126, which can be formed by a partial or wide fin cut. A second effective gate electrode location 2128 and a second dummy gate electrode location 2130 are formed above the second fin 2122 and, for illustrative purposes, are shown slightly in front of the second fin 2122, with the second fin 2122 in the background, with the dotted line indicating the area covered from a front view. An epitaxial P-type source or drain region 2132, such as an epitaxial silicon germanium source or drain structure, is also shown at a location on the second fin 2122 between the gate locations 2128 and 2130. Additionally, an interlayer dielectric material 2134 is included at a location of the second fin 2122 between the gate locations 2128 and 2130 .

[0257] refer to Figure 21B , the first and second dummy gate electrodes at locations 2110 and 2130 are removed, respectively. Once removed, the fin tip 2106 of the first fin 2102 and the fin tip 2126 of the second fin 2122 are exposed. This removal also creates openings 2116 and 2136, respectively, where dielectric plugs, such as fin tip stressor dielectric plugs, may ultimately be formed.

[0258] refer to Figure 21C ,and Figure 21B The structure of 2140 conformally forms a material liner 2140. In an embodiment, the material liner includes silicon and nitrogen, such as a silicon nitride material liner.

[0259] refer to Figure 21D ,exist Figure 21C A protective cap 2142, such as a metal nitride layer, is formed on the structure.

[0260] refer to Figure 21E ,exist Figure 21D A hard mask material 2144, such as a carbon-based hard mask material, is formed over the structure. A photolithographic mask or mask stack 2146 is formed over the hard mask material 2144.

[0261] refer to Figure 21F ,from Figure 21E In the structure of FIG. 214 , portions of the hard mask material 2144 in the PMOS region and portions of the protective cap layer 2142 are removed. The photolithography mask or mask stack 2146 is also removed.

[0262] refer to Figure 21G ,and Figure 21FThe structure conformally forms a second material liner 2148. In an embodiment, the second material liner includes silicon and nitrogen, such as a second silicon nitride material liner. In an embodiment, the second material liner 2148 has a different stress state to adjust the stress in the exposed plug.

[0263] refer to Figure 21H ,exist Figure 21G A second hard mask material 2150, such as a second carbon-based hard mask material, is formed over the structure and then recessed within the opening 2136 of the PMOS region of the structure.

[0264] refer to Figure 21I ,from Figure 21H The second material liner 2148 is etched from the structure to remove the second material liner 2148 from the NMOS region and to recess the second material liner 2148 in the PMOS region of the structure.

[0265] refer to Figure 21J ,from Figure 21I The hard mask material 2144, the protective cap layer 2142, and the second hard mask material 2150 are removed from the structure of FIG. This removal leaves two different fill structures for the opening 2116 compared to the opening 2136.

[0266] refer to Figure 21K ,exist Figure 21J An insulating fill material 2152 is formed in the openings 2116 and 2136 of the structure and planarized. In an embodiment, the insulating fill material 2152 is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

[0267] refer to Figure 21L ,exist Figure 21K The insulating fill material 2152 is recessed within the openings 2116 and 2136 of the structure to form a recessed insulating fill material 2154. In an embodiment, a steam oxidation process is performed as part of or after the recessing process to cure the recessed insulating fill material 2154. In one such embodiment, the recessed insulating fill material 2154 shrinks, thereby inducing tensile stress on the fins 2102 and 2122. However, there is relatively less tensile stress-inducing material in the PMOS region than in the NOMS region.

[0268] refer to Figure 21M , the third material liner 2156 is in Figure 21LIn one embodiment, the third material liner 2156 includes silicon and nitrogen, such as a third silicon nitride material liner. In one embodiment, the third material liner 2156 prevents the recessed insulating fill material 2154 from being etched away during subsequent source or drain contact etching.

[0269] 22A-22D illustrate cross-sectional views of exemplary structures of PMOS fin end stressor dielectric plugs according to embodiments of the present disclosure.

[0270] 22A , an opening 2136 in the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to the lower portion of material liner 2140 but is recessed relative to the upper portion of material liner 2140. A recessed insulating fill material 2154 is within second material liner 2148 and has an upper surface coplanar with the upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and is located on the upper surface of insulating fill material 2154 and on the upper surface of second material liner 2148. Third material liner 2156 has a seam 2157, for example, as an artifact of the deposition process used to form third material liner 2156.

[0271] 22B , an opening 2136 in the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to the lower portion of material liner 2140 but is recessed relative to the upper portion of material liner 2140. A recessed insulating fill material 2154 is within second material liner 2148 and has an upper surface coplanar with the upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and is on the upper surface of insulating fill material 2154 and on the upper surface of second material liner 2148. Third material liner 2156 has no seam.

[0272] 22C , an opening 2136 in the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to the lower portion of material liner 2140 but is recessed relative to the upper portion of material liner 2140. A recessed insulating fill material 2154 is within and above second material liner 2148 and has an upper surface that is higher than the upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and on the upper surface of insulating fill material 2154. Third material liner 2156 is shown as having no seam, but in other embodiments, third material liner 2156 has a seam.

[0273] refer to Figure 22D , an opening 2136 in the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of opening 2136. A second material liner 2148 is conformal to the lower portion of material liner 2140 but is recessed relative to the upper portion of material liner 2140. A recessed insulating fill material 2154 is within second material liner 2148 and has an upper surface that is recessed below the upper surface of second material liner 2148. A third material liner 2156 is within the upper portion of material liner 2140 and is on the upper surface of insulating fill material 2154 and on the upper surface of second material liner 2148. Third material liner 2156 is shown as having no seam, but in other embodiments, third material liner 2156 has a seam.

[0274] Common Reference Figure 19A 、 19B , 20A, 20B, 21A-21M, and 22A-22D, according to an embodiment of the present disclosure, an integrated circuit structure includes a fin, such as silicon, having a top and sidewalls. The top has a longest dimension along a direction. A first isolation structure is above a first end of the fin. A gate structure includes a gate electrode above the top of the fin and laterally adjacent to a sidewall of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is above a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure along the direction. Both the first and second isolation structures include a first dielectric material (e.g., material liner 2140) that laterally surrounds a recessed second dielectric material (e.g., second material liner 2148) that is different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., recessed insulating fill material 2154) that is different from the first and second dielectric materials.

[0275] In one embodiment, both the first and second isolation structures further include a fourth dielectric material (e.g., third material liner 2156) laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on an upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a substantially vertical central seam. In another such embodiment, the fourth dielectric material has no seam.

[0276] In one embodiment, the third dielectric material has an upper surface that is coplanar with an upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is lower than an upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is higher than an upper surface of the second dielectric material, and the third dielectric material is further above an upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0277] In one embodiment, the first isolation structure has a width along the direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In one such embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by the pitch along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the direction. In one embodiment, both the first and second isolation structures are in corresponding trenches in the interlayer dielectric layer.

[0278] In one such embodiment, the first source or drain region is between the gate structure and the first isolation structure. The second source or drain region is between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further comprises a high-k dielectric layer between the gate electrode and the fin and along the sidewalls of the gate electrode.

[0279] In another aspect, the depth of each dielectric plug can vary within a semiconductor structure or within a structure formed on a common substrate. As an example, Figure 23A FIG2 illustrates a cross-sectional view of another semiconductor structure having fin tip stress-inducing features according to another embodiment of the present disclosure. Figure 23A , including a shallow dielectric plug 2308A along with a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as depicted, shallow dielectric plug 2308A is at a depth approximately equal to the depth of semiconductor fin 2302 within substrate 2304, while the pair of deep dielectric plugs 2308B and 2308C are at a depth less than the depth of semiconductor fin 2302 within substrate 2304.

[0280] Reference again Figure 23ASuch an arrangement can achieve stress amplification on fin trim isolation (FTI) devices in trenches that are etched deeper into the substrate 2304 to provide isolation between adjacent fins 2302. Such an approach can be implemented to increase the density of transistors on a chip. In an embodiment, the stress effects induced by the plug fill on the transistor are amplified in the FTI transistor because stress transfer occurs in both the fin and the substrate or well below the transistor.

[0281] In another aspect, within a semiconductor structure or within an architecture formed on a common substrate, the width or amount of the tensile stress-inducing oxide layer included in the dielectric plug can vary, for example, depending on whether the device is a PMOS device or an NMOS device. As an example, Figure 23B FIG2 illustrates a cross-sectional view of another semiconductor structure having fin tip stress-inducing features according to another embodiment of the present disclosure. Figure 23B In certain embodiments, an NMOS device includes relatively more tensile stress-inducing oxide layer 2350 than a corresponding PMOS device.

[0282] Reference again Figure 23B In an embodiment, plug fills are differentiated to induce appropriate stress in NMOS and PMOS devices. For example, NMOS plugs 2308D and 2308E have a tensile stress-inducing oxide layer 2350 with a larger volume and greater width than PMOS plugs 2308F and 2308G. The plug fills can be patterned to induce different stresses in NMOS and PMOS devices. For example, photolithographic patterning can be used to open the PMOS device (e.g., widen the dielectric plug trench for the PMOS device). In this case, different fill options can be implemented to differentiate the plug fills in NMOS and PMOS devices. In an exemplary embodiment, reducing the volume of flowable oxide in the plug on the PMOS device can reduce the induced tensile stress. In one such embodiment, compressive stress can predominate, for example, due to the application of compressive stress to the source and drain regions. In other embodiments, the use of different plug liners or different fill materials provides adjustable stress control.

[0283] As described above, it is to be understood that the poly plug stress effect can benefit both NMOS transistors (e.g., channel tensile stress) and PMOS transistors (e.g., channel compressive stress). According to an embodiment of the present disclosure, the semiconductor fin is a uniaxially stressed semiconductor fin. The uniaxially stressed semiconductor fin can be uniaxially stressed using tensile stress or using compressive stress. For example, Figure 24A illustrates an angled view of a fin having uniaxial tensile stress according to one or more embodiments of the present disclosure, and Figure 24BAngled views of fins having uniaxial compressive stress are illustrated, according to one or more embodiments of the present disclosure.

[0284] refer to Figure 24A , semiconductor fin 2400 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed on either side of the channel region (C) in semiconductor fin 2400. The discrete channel regions of semiconductor fin 2400 have a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing away from each other and toward ends 2402 and 2404).

[0285] refer to Figure 24B , semiconductor fin 2450 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed on either side of the channel region (C) in semiconductor fin 2450. The discrete channel regions of semiconductor fin 2450 have a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (arrows pointing toward each other and from ends 2452 and 2454). Therefore, the embodiments described herein can be implemented to improve transistor mobility and drive current, thereby enabling faster performing circuits and chips.

[0286] In another aspect, a relationship can exist between the locations where gate line cuts (polymer cuts) are made and the locations where fin trim isolation (FTI) local fin cuts are made. In one embodiment, FTI local fin cuts are made only in the locations where polymer cuts are made. However, in one such embodiment, FTI cuts need not be made at every location where polymer cuts are made.

[0287] Figure 25A and 25B Illustrated are plan views representing various operations in a method of patterning a fin having a single gate spacer for forming a local isolation structure in a select gate line cut location, in accordance with an embodiment of the present disclosure.

[0288] refer to Figure 25A The method of manufacturing an integrated circuit structure includes forming a plurality of fins 2502, each of the plurality of fins 2502 having a longest dimension along a first direction 2504. A plurality of gate structures 2506 are formed over the plurality of fins 2502, each of the gate structures 2506 having a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In an embodiment, the gate structures 2506 are sacrificial gate lines or dummy gate lines, for example, made of polysilicon. In an embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0289] Reference again Figure 25A, a dielectric material structure 2510 is formed between adjacent gate structures in the plurality of gate structures 2506. Portions 2512 and 2513 of two of the plurality of gate structures 2506 are removed to expose a portion of each of the plurality of fins 2502. In an embodiment, removing portions 2512 and 2513 of two of the gate structures 2506 involves using a lithography window that is wider than the width of each of the portions 2512 and 2513 of the gate structures 2506. The exposed portion of each of the plurality of fins 2502 at location 2512 is removed to form a kerf region 2520. In an embodiment, a dry or plasma etch process is used to remove the exposed portion of each of the plurality of fins 2502. However, the exposed portion of each of the plurality of fins 2502 at location 2513 is masked from removal. In an embodiment, region 2512 / 2520 represents both a polymeric kerf and an FTI local fin kerf. However, location 2513 represents only a polymeric kerf.

[0290] refer to Figure 25B The polymer cut and FTI local fin cut locations 2512 / 2520 and polymer cut location 2513 are filled with an insulating structure such as a dielectric plug 2530. An exemplary insulating structure or "polymer cut" or "plug" structure is described below.

[0291] Figures 26A-26C Cross-sectional views illustrating various possibilities for a dielectric plug for use in accordance with embodiments of the present disclosure Figure 25B Polymerization cutouts and FTI localized FIN cutout locations as well as only polymerization cutout locations in various regions of the structure.

[0292] refer to Figure 26A , along Figure 25B The aa′ axis of the structure of FIG shows a cross-sectional view of a portion 2600A of the dielectric plug 2530 at location 2513. The portion 2600A of the dielectric plug 2530 is shown on the uncut fin 2502 and between the dielectric material structures 2510.

[0293] refer to Figure 26B , along Figure 25B The bb′ axis of the structure of FIG shows a cross-sectional view of a portion 2600B of the dielectric plug 2530 at a location 2512 . The portion 2600B of the dielectric plug 2530 is shown over the cut fin location 2520 and between the dielectric material structures 2510 .

[0294] refer to Figure 26C , along Figure 25B2 shows a cross-sectional view of a portion 2600C of the dielectric plug 2530 at a location 2512 along the c-c' axis of the structure. The portion 2600C of the dielectric plug 2530 is shown on the trench isolation structure 2602 between the fins 2502 and between the dielectric material structures 2510. In the embodiment, examples of which are described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating fill material 2602C on the second insulating layer 2602B.

[0295] Referring collectively to Figures 25A, 25B, and 26A-26C, according to an embodiment of the present disclosure, a method for manufacturing an integrated circuit structure includes forming a plurality of fins, each of the plurality of fins being along a first direction. Forming a plurality of gate structures above the plurality of fins, each of the gate structures being along a second direction orthogonal to the first direction. Forming a dielectric material structure between adjacent gate structures of the plurality of gate structures. Removing a portion of a first gate structure of the plurality of gate structures to expose a first portion of each of the plurality of fins. Removing a portion of a second gate structure of the plurality of gate structures to expose a second portion of each of the plurality of fins. Removing the exposed first portion of each of the plurality of fins, but not removing the exposed second portion of each of the plurality of fins. Forming a first insulating structure in the location of the removed first portion of the plurality of fins. Forming a second insulating structure in the location of the removed portion of the second gate structure of the plurality of gate structures.

[0296] In one embodiment, removing portions of the first and second gate structures in the plurality of gate structures involves using a lithographic window wider than a width of each of the portions of the first and second gate structures in the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth less than a height of the plurality of fins. In one such embodiment, the depth is greater than a depth of a source or drain region in the plurality of fins. In one embodiment, the plurality of fins comprises silicon and is continuous with a portion of a silicon substrate.

[0297] Common Reference Figure 16A 、 25A, 25B and 26A-26C, according to another embodiment of the present disclosure, an integrated circuit structure includes a fin including silicon, the fin having a longest dimension along a first direction. An isolation structure is located above an upper portion of the fin, the isolation structure having a center along the first direction. A first gate structure is located above an upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is separated from the center of the isolation structure by a pitch along the first direction. A second gate structure is located above an upper portion of the fin, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is separated from the center of the first gate structure by the pitch along the first direction. A third gate structure is located above the upper portion of the fin opposite to the side of the isolation structure of the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is separated from the center of the isolation structure by the pitch along the first direction.

[0298] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of the high-k gate dielectric layer. In one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0299] In one embodiment, the first epitaxial semiconductor region is located on an upper portion of the fin between the first gate structure and the isolation structure. The second epitaxial semiconductor region is located on an upper portion of the fin between the first gate structure and the second gate structure. The third epitaxial semiconductor region is located on an upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0300] Common Reference Figure 16A 、 25A, 25B and 26A-26C, according to another embodiment of the present disclosure, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is located on the STI structure, the isolation structure having a center along the first direction. A first gate structure is located on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is separated from the center of the isolation structure by a pitch along the first direction. A second gate structure is located on the STI structure, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is separated from the center of the first gate structure by a pitch along the first direction. A third gate structure is located on the STI structure opposite to the side of the isolation structure of the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is separated from the center of the isolation structure by a pitch along the first direction.

[0301] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of the high-k gate dielectric layer. In one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

[0302] In another aspect, whether a polymer cut is made together with an FTI local fin cut or only a polymer cut, the insulating structure or dielectric plug used to fill the cut location can extend laterally into the dielectric spacer of the corresponding cut gate line, or even extend beyond the dielectric spacer of the corresponding cut gate line.

[0303] In a first example where the trench contact shape is not affected by the polymeric notched dielectric plug, Figure 27A Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer of the gate line according to an embodiment of the present disclosure.

[0304] refer to Figure 27AIntegrated circuit structure 2700A includes a first silicon fin 2702 having its longest dimension along a first direction 2703. A second silicon fin 2704 has its longest dimension along the first direction 2703. An insulator material 2706 is located between the first and second silicon fins 2702, 2704. A gate line 2708 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, which is orthogonal to the first direction 2703. Gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. Gate line 2708 has a break 2710 above the insulator material 2706 between the first end 2708C and the second end 2708D of gate line 2708. Break 2710 is filled with a dielectric plug 2712.

[0305] A trench contact 2714 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709 at a first side 2708A of the gate line 2708. The trench contact 2714 is continuous above the insulator material 2706 at a location 2715 laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is laterally located between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712 that is thinner than a width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0306] In one embodiment, a second trench contact 2718 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709 at a second side 2708B of the gate line 2708. The second trench contact 2718 is continuous over the insulator material 2706 at a location 2719 laterally adjacent to the dielectric plug 2712. In one such embodiment, a second dielectric spacer 2720 is laterally between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712 that is thinner than a width laterally adjacent to the second side 2708B of the gate line 2708.

[0307] In one embodiment, gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, dielectric plug 2712 includes the same material as dielectric spacer 2714, but is separate from dielectric spacer 2714. In one embodiment, dielectric plug 2712 includes a different material than dielectric spacer 2714.

[0308] In a second example where the trench contact shape is influenced by a polymeric notched dielectric plug, Figure 27B Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having a gate line cutout with a dielectric plug extending beyond a dielectric spacer of the gate line according to another embodiment of the present disclosure.

[0309] refer to Figure 27B Integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753. A second silicon fin 2754 has a longest dimension along the first direction 2753. An insulator material 2756 is located between the first and second silicon fins 2752, 2754. A gate line 2758 is located above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759, which is orthogonal to the first direction 2753. Gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. Gate line 2758 has a break 2760 between the first end 2758C and the second end 2758D of gate line 2758 above the insulator material 2756. Break 2760 is filled with a dielectric plug 2762.

[0310] A trench contact 2764 is located above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759 at a first side 2758A of the gate line 2758. The trench contact 2764 is continuous over the insulator material 2756 at a location 2765 laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is laterally located between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 extends along the first side 2758A of the gate line 2758, but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762 that is thinner than a width (W2) laterally adjacent to the dielectric spacer 2766.

[0311] In one embodiment, a second trench contact 2768 is located above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759 at a second side 2758B of the gate line 2758. The second trench contact 2768 is continuous above the insulator material 2756 at a location 2769 laterally adjacent to the dielectric plug 2762. In one such embodiment, a second dielectric spacer 2770 is laterally between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 extends along the second side 2758B of the gate line 2758, but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. The second trench contact 2768 has a width laterally adjacent to the dielectric plug 2762 that is thinner than the width laterally adjacent to the second dielectric spacer 2770.

[0312] In one embodiment, gate line 2758 includes a high-k gate dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, dielectric plug 2762 includes the same material as dielectric spacer 2764, but is separate from dielectric spacer 2764. In one embodiment, dielectric plug 2762 includes a different material than dielectric spacer 2764.

[0313] In a third example where the dielectric plug for the convergent cutout location tapers from the top of the plug to the bottom of the plug, Figures 28A-28F Illustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure having a gate line cutout with a dielectric plug having an upper portion extending beyond a dielectric spacer of the gate line and a lower portion extending into the dielectric spacer of the gate line in accordance with another embodiment of the present disclosure.

[0314] refer to Figure 28A A plurality of gate lines 2802 are formed over a structure 2804, such as a trench isolation structure between semiconductor fins. In one embodiment, each of gate lines 2802 is a sacrificial or dummy gate line, for example, having a dummy gate electrode 2806 and a dielectric cap 2808. Portions of such sacrificial or dummy gate lines can be replaced later in a replacement gate process (e.g., after dielectric plug formation described below). Dielectric spacers 2810 are formed along the sidewalls of gate lines 2802. A dielectric material 2812, such as an interlayer dielectric layer, is formed between gate lines 2802. A mask 2814 is formed and photolithographically patterned to expose a portion of one of gate lines 2802.

[0315] refer to Figure 28BWith mask 2814 in place, an etching process is used to remove central gate line 2802. Mask 2814 is then removed. In an embodiment, the etching process erodes the portion of dielectric spacer 2810 of gate line 2802 that was removed, thereby forming a reduced dielectric spacer 2816. Additionally, the etching process erodes the upper portion of dielectric material 2812 exposed by mask 2814, thereby forming an eroded dielectric material portion 2818. In certain embodiments, residual dummy gate material 2820, such as residual polysilicon, remains in the structure as an artifact of the incomplete etching process.

[0316] refer to Figure 28C ,exist Figure 28B A hard mask 2822 is formed on the structure. The hard mask 2822 can be Figure 28B 28. The upper portion of the structure is conformal and in particular conformal to the eroded dielectric material portion 2818.

[0317] refer to Figure 28D The remaining dummy gate material 2820 is removed, for example, using an etching process that can be chemically similar to the etching process used to remove the center gate line in the gate lines 2802. In an embodiment, during the removal of the remaining dummy gate material 2820, the hard mask 2822 protects the eroded dielectric material portion 2818 from further erosion.

[0318] refer to Figure 28E , hard mask 2822 is removed. In one embodiment, hard mask 2822 is removed without or substantially without further etching of the already eroded dielectric material portion 2818.

[0319] refer to Figure 28F ,exist Figure 28E A dielectric plug 2830 is formed in the opening of the structure. The upper portion of the dielectric plug 2830 is above the eroded dielectric material portion 2818, for example, effectively exceeding the original spacer 2810. The lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, effectively entering the original spacer 2810 but not exceeding the original spacer 2810. As a result, the dielectric plug 2830 has a Figure 28F It is to be appreciated that the dielectric plug 2830 can be fabricated from the materials and processes described above for other polymeric notches or FTI plugs or fin tip stressors.

[0320] In another aspect, portions of the placeholder gate structure or dummy gate structure may be retained above the trench isolation region below the permanent gate structure to protect the trench isolation region from erosion during the replacement gate process. Figures 29A-29CIllustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having residual dummy gate material at a portion of a bottom portion of a permanent gate stack according to an embodiment of the present disclosure.

[0321] refer to Figures 29A-29C The integrated circuit structure includes a fin 2902, such as a silicon fin, protruding from a semiconductor substrate 2904. Fin 2902 has a lower fin portion 2902B and an upper fin portion 2902A. Upper fin portion 2902A has a top portion 2902C and sidewalls 2902D. An isolation structure 2906 surrounds lower fin portion 2902B. Isolation structure 2906 includes an insulating material 2906C having a top surface 2907. Semiconductor material 2908 is disposed on a portion of top surface 2907 of insulating material 2906C. Semiconductor material 2908 is separated from fin 2902.

[0322] A gate dielectric layer 2910 is located over a top portion 2902C of the upper fin portion 2902A and laterally abuts sidewalls 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further located over the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. An intervening additional gate dielectric layer 2911, such as an oxidized portion of the fin 2902, may be between the gate dielectric layer 2910 and the top portion 2902C of the upper fin portion 2902A and laterally abuts sidewalls 2902D of the upper fin portion 2902A. A gate electrode 2912 is located over the gate dielectric layer 2910 over the top portion 2902C of the upper fin portion 2902A and laterally abuts sidewalls 2902D of the upper fin portion 2902A. The gate electrode 2912 is further overlying the gate dielectric layer 2910 on the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912, and a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side being opposite the first side. In the embodiments, examples of which are described above, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulating material 2906C.

[0323] In one embodiment, semiconductor material 2908 on the portion of top surface 2907 of insulating material 2906C is or includes polysilicon. In one embodiment, top surface 2907 of insulating material 2906C has a recess, as depicted, and semiconductor material 2908 is located within the recess. In one embodiment, isolation structure 2906 includes a second insulating material (2906A or 2906B, or both 2906A / 2906B) along the bottom and sidewalls of insulating material 2906C. In one such embodiment, the portion of the second insulating material (2906A or 2906B, or both 2906A / 2906B) along the sidewalls of insulating material 2906C has a top surface above the highest surface of insulating material 2906C, as depicted. In one embodiment, the top surface of the second insulating material (2906A or 2906B, or both 2906A / 2906B) is higher than or coplanar with the highest surface of semiconductor material 2908.

[0324] In one embodiment, the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view perspective, the location of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along a first side of the gate electrode 2912. The second dielectric spacer 2922 is along a second side of the gate electrode 2912. In one such embodiment, the gate dielectric layer 2910 further extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as shown in FIG. Figure 29B As described in .

[0325] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive fill metal layer 2912B over the work function layer 2912A. In one such embodiment, the conductive fill metal layer 2912B includes tungsten. In a specific embodiment, the conductive fill metal layer 2912B includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, an insulating cap 2924 is on the gate electrode 2912 and may extend over the gate dielectric layer 2910, as shown. Figure 29B As described in .

[0326] Figures 30A-30DA cross-sectional view illustrating various operations in a method of fabricating an integrated circuit structure having residual dummy gate material at a bottom portion of a permanent gate stack in accordance with another embodiment of the present disclosure. Figure 29C The a-a' axis of the structure.

[0327] refer to Figure 30A The method of fabricating an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top portion 3000C and sidewalls 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A reserved space gate electrode 3006 is located above the top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B. The reserved space gate electrode 3006 includes a semiconductor material.

[0328] Although not from Figure 30A Perspective depiction (but in Figure 29C ), a first source or drain region may be formed adjacent to a first side of the placeholder gate electrode 3006, and a second source or drain region may be formed adjacent to a second side of the placeholder gate electrode 3006, the second side being opposite the first side. Additionally, gate dielectric spacers may be formed along sidewalls of the placeholder gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the placeholder gate electrode 3006.

[0329] In one embodiment, placeholder gate electrode 3006 is or includes polysilicon. In one embodiment, top surface 3005 of insulating material 3004C of isolation structure 3004 has a recess, as depicted. A portion of placeholder gate electrode 3006 is within the recess. In one embodiment, isolation structure 3004 includes a second insulating material (3004A or 3004B, or both) along the bottom and sidewalls of insulating material 3004C, as depicted. In one such embodiment, the portion of the second insulating material (3004A or 3004B, or both) along the sidewalls of insulating material 3004C has a top surface above at least a portion of top surface 3005 of insulating material 3004C. In one embodiment, a top surface of the second insulating material ( 3004A or 3004B, or both 3004A and 3004B) is higher than a lowermost surface of a portion of the placeholder gate electrode 3006 .

[0330] refer to Figure 30B, from the top 3000C and sidewall 3000D of the upper fin portion 3000B, for example, along Figure 30A The placeholder gate electrode 3006 is etched in a direction 3008 of the insulating material 3004C of the isolation structure 3004. This etching process may be referred to as a replacement gate process. In an embodiment, the etching or replacement gate process is incomplete and leaves a portion 3012 of the placeholder gate electrode 3006 located above at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0331] refer to Figure 30A and 30B In both embodiments, the oxidized portion 3010 of the upper fin portion 3000B formed before forming the placeholder gate electrode 3006 is retained during the etching process, as depicted. However, in another embodiment, a placeholder gate dielectric layer is formed before forming the placeholder gate electrode 3006 and is removed after etching the placeholder gate electrode.

[0332] refer to Figure 30C , a gate dielectric layer 3014 is formed over a top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed over the oxidized portion 3010 of the upper fin portion 3000B over the top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B, as depicted. In another embodiment, after the oxidized portion 3010 of the upper fin portion 3000B is removed after etching the pre-placement gate electrode, the gate dielectric layer 3014 is formed directly over the top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B. In either case, in an embodiment, a gate dielectric layer 3014 is further formed on the portion 3012 of the placeholder gate electrode 3006 that is located on the portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004 .

[0333] refer to Figure 30D A permanent gate electrode 3016 is formed over the gate dielectric layer 3014 over the top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further over the gate dielectric layer 3014 over the portion 3012 of the reserved gate electrode 3006 over the portion of the top surface 3005 of the insulating material 3004C.

[0334] In one embodiment, forming the permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A includes titanium and nitrogen. In another such embodiment, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B formed over the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a film comprising tungsten using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor. In one embodiment, an insulating gate cap layer 3018 is formed over the permanent gate electrode 3016.

[0335] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer in a gate dielectric structure for a gate electrode. In other embodiments, a partially or fully crystallized high-k layer is included in a gate dielectric structure for a gate electrode. In one embodiment including a partially or fully crystallized high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystallized high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0336] In an embodiment, methods are described herein for increasing the charge in the device channel and improving subthreshold behavior by employing ferroelectric or antiferroelectric gate oxides. Ferroelectric and antiferroelectric gate oxides can increase the channel charge for higher currents and also enable steeper turn-on behavior.

[0337] To provide context, ferroelectric and antiferroelectric (FE or AFE) materials based on hafnium or zirconium (Hf or Zr) are typically much thinner than ferroelectric materials such as lead zirconate titanate (PZT) and, as such, are compatible with highly scaled logic technologies. FE or AFE materials have two characteristics that can improve the performance of logic transistors: (1) higher charge in the channel due to FE or AFE polarization, and (2) steeper turn-on behavior due to sharp FE or AFE transitions. Such properties can improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0338] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is illustrated.

[0339] refer to Figure 31A, the integrated circuit structure 3100 includes a gate structure 3102 above a substrate 3104. In one embodiment, the gate structure 3102 is above or on a semiconductor channel structure 3106 comprising a single crystalline material such as single crystal silicon. The gate structure 3102 includes a gate dielectric above the semiconductor channel structure 3106 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and can be a barrier layer, a work function layer, or a template layer that enhances the crystallization of the FE or AFE layer. One or more gate fill layers 3102C are on or above the conductive layer 3102B. The source region 3108 and the drain region 3110 are on opposite sides of the gate structure 3102. A source or drain contact 3112 is electrically connected to the source region 3108 and the drain region 3110 at location 3149 and is spaced apart from the gate structure 3102 by one or both of an interlayer dielectric layer 3114 and a gate dielectric spacer 3116. Figure 31A In the example of FIG, the source region 3108 and the drain region 3110 are regions of the substrate 3104. In an embodiment, the source or drain contact 3112 includes a barrier layer 3112A and a conductive trench fill material 3112B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along the dielectric spacer 3116, as shown in FIG. Figure 31A As described in .

[0340] In an embodiment, and as applicable throughout the present disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, wherein the Zr:Hf ratio is 50:50 or Zr is greater. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has an orthorhombic crystallinity of at least 80%.

[0341] In an embodiment, and as applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, wherein the Zr:Hf ratio is 80:20 or greater, and even up to 100% Zr, i.e., ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has a tetragonal crystallinity of at least 80%.

[0342] In an embodiment, and as applicable throughout the present disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-K dielectric (HfOx, Al2O3, etc.), or a combination of oxide and high-K, between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In an embodiment, and as applicable throughout the present disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In an embodiment, and as applicable throughout the present disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size in the range of approximately 20 nanometers or more.

[0343] In one embodiment, after depositing the ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example, by atomic layer deposition (ALD), a layer comprising a metal (e.g., layer 3102B, such as 5-10 nanometers of titanium nitride, tantalum nitride, or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Annealing is then performed. In one embodiment, the annealing is performed for a duration in the range of 1 millisecond to 30 minutes. In one embodiment, the annealing is performed at a temperature in the range of 500-1100 degrees Celsius.

[0344] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is illustrated.

[0345] refer to Figure 31BIntegrated circuit structure 3150 includes a gate structure 3152 over substrate 3154. In one embodiment, gate structure 3152 is over or above a semiconductor channel structure 3156 comprising a single crystalline material, such as single crystal silicon. Gate structure 3152 includes a gate dielectric over semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric comprises a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may further comprise an amorphous oxide layer 3153. The gate electrode comprises a conductive layer 3152B over ferroelectric or antiferroelectric polycrystalline material layer 3152A. Conductive layer 3152B comprises a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are over or above conductive layer 3152B. Raised source region 3158 and raised drain region 3160, such as regions of a different semiconductor material than semiconductor channel structure 3156, are on opposite sides of gate structure 3152. The source or drain contact 3162 is electrically connected to the source region 3158 and the drain region 3160 at location 3199 and is spaced apart from the gate structure 3152 by one or both of the interlayer dielectric layer 3164 and the gate dielectric spacer 3166. In one embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166, as shown in FIG. Figure 31B As described in .

[0346] Figure 32A A plan view of a plurality of gate lines over a pair of semiconductor fins according to another embodiment of the present disclosure is illustrated.

[0347] refer to Figure 32A , a plurality of active gate lines 3204 are formed over the plurality of semiconductor fins 3200. Dummy gate lines 3206 are at the ends of the plurality of semiconductor fins 3200. The spaces 3208 between the gate lines 3204 / 3206 are locations where trench contacts can be located to provide conductive contacts to source or drain regions, such as source or drain regions 3251, 3252, 3253, and 3254. In an embodiment, the pattern of the plurality of gate lines 3204 / 3206 or the pattern of the plurality of semiconductor fins 3200 is described as a grid structure. In an embodiment, the grid-like pattern includes a pattern of the plurality of semiconductor fins 3200 spaced apart at a constant pitch and having a constant width, or the plurality of gate lines 3204 / 3206, or both.

[0348] Figure 32B The embodiment according to the present disclosure is illustrated along Figure 32A A cross-sectional view taken along the a-a' axis.

[0349] refer to Figure 32B A plurality of active gate lines 3264 are formed above semiconductor fins 3262 formed above substrate 3260. Dummy gate lines 3266 are at the ends of semiconductor fins 3262. Dielectric layer 3270 is external to dummy gate lines 3266. Trench contact material 3297 is between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. Embedded source or drain structures 3268 are in semiconductor fins 3262, between the active gate lines 3264, and between the dummy gate lines 3266 and the active gate lines 3264.

[0350] The active gate line 3264 includes a gate dielectric structure 3272, a work function gate electrode portion 3274, a filled gate electrode portion 3276, and a gate electrode capping layer 3278. Dielectric spacers 3280 line the sidewalls of the active gate line 3264 and the dummy gate line 3266. In one embodiment, the gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299.

[0351] In another aspect, devices of the same conductivity type, such as N-type or P-type, can have differentiated gate electrode stacks for the same conductivity type. However, for comparison purposes, devices of the same conductivity type can have differentiated voltage thresholds (VT) based on modulation doping.

[0352] Figure 33A Illustrated are cross-sectional views of a pair of NMOS devices having differentiated voltage thresholds based on modulation doping and a pair of PMOS devices having differentiated voltage thresholds based on modulation doping according to an embodiment of the present disclosure.

[0353] refer to Figure 33A, a first NMOS device 3302 is adjacent to a second NMOS device 3304 above a semiconductor active region 3300, such as a silicon fin or substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308, such as a work function layer, and a gate electrode conductive fill 3310. In an embodiment, the first gate electrode conductive layer 3308 of the first NMOS device 3302 and the second NMOS device 3304 have the same material and the same thickness, and as such, have the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a "standard VT" device, and the second NMOS device 3304 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using modulated or differential implant doping in region 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0354] Reference again Figure 33A A first PMOS device 3322 is adjacent to a second PMOS device 3324 above a semiconductor active region 3320, such as a silicon fin or substrate. Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328, such as a work function layer, and a gate electrode conductive fill 3330. In one embodiment, the first gate electrode conductive layer 3328 of the first PMOS device 3322 and the second PMOS device 3324 have the same material and the same thickness, and thus, have the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a "standard VT" device, and the second PMOS device 3324 is referred to as a "low VT" device. In one embodiment, the differentiated VT is achieved by using modulated or differential implant doping in the region 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0355] and Figure 33A compared to, Figure 33B Illustrated are cross-sectional views of a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present disclosure.

[0356] refer to Figure 33B, a first NMOS device 3352 is adjacent to a second NMOS device 3354 above a semiconductor active region 3350, such as a silicon fin or substrate. Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3352 includes a first gate electrode conductive layer 3358, such as a first work function layer, and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359, such as a second work function layer, the first gate electrode conductive layer 3358, and the gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In an embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0357] Reference again Figure 33B A first PMOS device 3372 is adjacent to a second PMOS device 3374 above a semiconductor active region 3370, such as a silicon fin or substrate. Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A, such as a work function layer, having a first thickness and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness and a gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layer 3378A and the gate electrode conductive layer 3378B have the same composition, but the thickness of the gate electrode conductive layer 3378B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3378A (the first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In an embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0358] Reference again Figure 33BAccording to an embodiment of the present disclosure, an integrated circuit structure includes a fin (e.g., a silicon fin, such as 3350). It will be appreciated that the fin has a top (as shown) and sidewalls (into the page and out of the page). A gate dielectric layer 3356 is located over the top of the fin and laterally abuts the sidewalls of the fin. An N-type gate electrode of device 3354 is located over the gate dielectric layer 3356 over the top of the fin and laterally abuts the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. As will be appreciated, a first N-type source or drain region can abut a first side of the gate electrode (e.g., into the page), and a second N-type source or drain region can abut a second side of the gate electrode (e.g., out of the page), the second side being opposite the first side.

[0359] In one embodiment, the P-type metal layer 3359 includes titanium and nitrogen, and the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2-12 angstroms, and in a specific embodiment, the P-type metal layer 3359 has a thickness in the range of 2-4 angstroms. In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 on the N-type metal layer 3358. In one such embodiment, the conductive fill metal layer 3360 includes tungsten. In a specific embodiment, the conductive fill metal layer 3360 includes 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine.

[0360] Reference again Figure 33B According to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), the first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. Also included is a second N-type device 3354 having a voltage threshold (VT), the second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0361] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 includes titanium and nitrogen.

[0362] Reference again Figure 33B According to an embodiment of the present disclosure, an integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT). First P-type device 3372 includes a first gate dielectric layer 3376 and a first P-type metal layer 3378A on first gate dielectric layer 3376. First P-type metal layer 3378A has a thickness. A second P-type device 3374 is also included, and has a voltage threshold (VT). Second P-type device 3374 includes a second gate dielectric layer 3376 and a second P-type metal layer 3378B on second gate dielectric layer 3376. Second P-type metal layer 3378B has a thickness greater than that of first P-type metal layer 3378A.

[0363] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B include titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not depicted, the second P-type metal layer 3378B includes a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and a seam is between the first metal film and the second metal film.

[0364] Reference again Figure 33B According to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. A first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type gate layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. A second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type gate layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than that of the second P-type metal layer 3378A.

[0365] In one embodiment, the first N-type device 3352 has a voltage threshold (VT), the second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, the first P-type device 3372 has a voltage threshold (VT), the second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on the second metal film and a seam between the first metal film and the second metal film.

[0366] It is to be appreciated that more than two types of VT devices for the same conductivity type may be included in the same structure, such as on the same die. Figure 34A Illustrated are cross-sectional views of a group of three NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping and a group of three PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping according to an embodiment of the present disclosure.

[0367] refer to Figure 34A, a first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 above a semiconductor active region 3400, such as a silicon fin or substrate. The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have gate electrode stacks that are structurally identical or similar. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from the first NMOS device 3402 and the third NMOS device 3403. In particular, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408, such as a first work function layer, and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409, such as a second work function layer, the first gate electrode conductive layer 3408, and the gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In an embodiment, the third NMOS device 3403 has a VT that is different from the VTs of the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as the gate electrode structure of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device 3403 is between the VTs of the first NMOS device 3402 and the second NMOS device 3404. In an embodiment, the differentiated VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using modulated or differential implant doping at region 3412 of the third NMOS device 3403. In one such embodiment, the third N-type device 3403 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the first N-type device 3402 .

[0368] Reference again Figure 34A, a first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 above a semiconductor active region 3420, such as a silicon fin or substrate. The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have gate electrode stacks that are structurally identical or similar. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3428A, such as a work function layer, having a first thickness and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness and a gate electrode conductive fill 3430. In one embodiment, the gate electrode conductive layer 3428A and the gate electrode conductive layer 3428B have the same composition, but the thickness (second thickness) of the gate electrode conductive layer 3428B is greater than the thickness (first thickness) of the gate electrode conductive layer 3428A. In one embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In one such embodiment, the first PMOS device 3422 is referred to as a "standard VT" device, and the second PMOS device 3424 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the third PMOS device 3423 has a VT that is different from the VTs of the first and second PMOS devices 3422 and 3424, even though the gate electrode structure of the third PMOS device 3423 is the same as that of the first PMOS device 3422. In one embodiment, the VT of the third PMOS device 3423 is between the VTs of the first and second PMOS devices 3422 and 3424. In an embodiment, a differentiated VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using modulated or differential implant doping at region 3432 of the third PMOS device 3423. In one such embodiment, the third P-type device 3423 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the first P-type device 3422.

[0369] In the second example, Figure 34B Illustrated are cross-sectional views of a group of three NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping and a group of three PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and based on modulation doping according to another embodiment of the present disclosure.

[0370] refer to Figure 34B , a first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 above a semiconductor active region 3450, such as a silicon fin or substrate. The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have gate electrode stacks that are structurally identical or similar. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458, such as a first work function layer, and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459, such as a second work function layer, the first gate electrode conductive layer 3458, and the gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In an embodiment, the third NMOS device 3453 has a VT that is different from the VTs of the first NMOS device 3452 and the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as the gate electrode structure of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VTs of the first NMOS device 3452 and the second NMOS device 3454. In an embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using modulated or differential implant doping at region 3462 of the third NMOS device 3453. In one such embodiment, the third N-type device 3453 has a channel region having a dopant concentration that is different than the dopant concentration of the channel region of the second N-type device 3454 .

[0371] Reference again Figure 34BA first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 above a semiconductor active region 3470, such as a silicon fin or substrate. The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have gate electrode stacks that are structurally identical or similar. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A, such as a work function layer, having a first thickness and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness and a gate electrode conductive fill 3480. In one embodiment, gate electrode conductive layer 3478A and gate electrode conductive layer 3478B have the same composition, but the thickness (second thickness) of gate electrode conductive layer 3478B is greater than the thickness (first thickness) of gate electrode conductive layer 3478A. In one embodiment, first PMOS device 3472 has a higher VT than second PMOS device 3474. In one such embodiment, first PMOS device 3472 is referred to as a "standard VT" device, and second PMOS device 3474 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, third PMOS device 3473 has a VT that is different from the VTs of first PMOS device 3472 and second PMOS device 3474, even though the gate electrode structure of third PMOS device 3473 is the same as that of second PMOS device 3474. In one embodiment, the VT of third PMOS device 3473 is between the VTs of first PMOS device 3472 and second PMOS device 3474. In an embodiment, a differentiated VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using modulated or differential implant doping at region 3482 of the third PMOS device 3473. In one such embodiment, the third P-type device 3473 has a channel region having a dopant concentration that is different from the dopant concentration of the channel region of the second P-type device 3474.

[0372] Figures 35A-35D Illustrated are cross-sectional views of various operations in a method of fabricating an NMOS device having differentiated voltage thresholds based on differentiated gate electrode structures in accordance with another embodiment of the present disclosure.

[0373] refer to Figure 35A, wherein a "standard VT NMOS" region (STD VT NMOS) and a "high VT NMOS" region (HIGH VTNMOS) are shown as bifurcated on a common substrate, a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and over a second semiconductor fin 3504, such as over first and second silicon fins. A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0374] refer to Figure 35B , a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502 , but a portion 3509 of the P-type metal layer 3508 remains on the gate dielectric layer 3506 above the second semiconductor fin 3504 .

[0375] refer to Figure 35C An N-type metal layer 3510 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502 and on a portion 3509 of the P-type metal layer above the gate dielectric layer 3506 above the second semiconductor fin 3504. In an embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) above the first semiconductor fin 3502, and forming a second N-type device having a voltage threshold (VT) above the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0376] refer to Figure 35D In an embodiment, a conductive fill metal layer 3512 is formed on the N-type metal layer 3510. In one such embodiment, forming the conductive fill metal layer 3512 includes forming a film including tungsten using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor.

[0377] Figures 36A-36D Illustrated are cross-sectional views of various operations in a method of fabricating a PMOS device having differentiated voltage thresholds based on differentiated gate electrode structures in accordance with another embodiment of the present disclosure.

[0378] refer to Figure 36A , wherein a "standard VT PMOS" region (STD VT PMOS) and a "low VT PMOS" region (LOW VTPMOS) are shown as bifurcated on a common substrate, a method of manufacturing an integrated circuit structure includes forming a gate dielectric layer 3606 over a first semiconductor fin 3602 and over a second semiconductor fin 3604, such as over first and second silicon fins. A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0379] refer to Figure 36B , a portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602 , but a portion 3609 of the first P-type metal layer 3608 remains on the gate dielectric layer 3606 above the second semiconductor fin 3604 .

[0380] refer to Figure 36C A second P-type metal layer 3610 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602 and on a portion 3609 of the first P-type metal layer above the gate dielectric layer 3606 above the second semiconductor fin 3604. In an embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) above the first semiconductor fin 3602 and forming a second P-type device having a voltage threshold (VT) above the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0381] In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same composition. In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same thickness. In one embodiment, first P-type metal layer 3608 and second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, seam 3611 is between first P-type metal layer 3608 and second P-type metal layer 3610, as depicted.

[0382] refer to Figure 36D In one embodiment, a conductive fill metal layer 3612 is formed over P-type metal layer 3610. In one such embodiment, forming conductive fill metal layer 3612 includes forming a film comprising tungsten using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor. In one embodiment, an N-type metal layer 3614 is formed over P-type metal layer 3610 prior to forming conductive fill metal layer 3612, as depicted. In one such embodiment, N-type metal layer 3614 is a product of a dual metal gate replacement process scheme.

[0383] In another aspect, a metal gate structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. In an example, Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is illustrated.

[0384] refer to Figure 37Integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 and a P-well region 3708. The N-well region 3704 has a first semiconductor fin 3706 protruding therefrom, and the P-well region 3708 has a second semiconductor fin 3710 protruding therefrom. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710. The N-well region 3704 is directly adjacent to the P-well region 3708 in the semiconductor substrate 3702. A trench isolation structure 3712 is provided on the semiconductor substrate 3702 outside of and between the first semiconductor fin 3706 and the second semiconductor fin 3710. The first semiconductor fin 3706 and the second semiconductor fin 3710 extend above the trench isolation structure 3712.

[0385] A gate dielectric layer 3714 is located on the first semiconductor fin 3706 and the second semiconductor fin 3710 and on the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first semiconductor fin 3706 and the second semiconductor fin 3710. A conductive layer 3716 is located above the first semiconductor fin 3706 but not above the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is located above the first semiconductor fin 3706 but not above the second semiconductor fin 3710. The p-type metal gate layer 3718 also overlies a portion, but not all, of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. An n-type metal gate layer 3720 is located above the second semiconductor fin 3710, above the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and above the p-type metal gate layer 3718.

[0386] In one embodiment, an interlayer dielectric (ILD) layer 3722 is disposed above the trench isolation structure 3712 on the exterior of the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first semiconductor fin 3706 and the second semiconductor fin 3710. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along sidewalls 3726 of the opening 3724, as depicted. In a particular embodiment, the conductive layer 3716 has a top surface 3717 along the sidewalls 3726 of the opening 3724, which is below a top surface 3719 of the p-type gate metal layer 3718 and a top surface 3721 of the n-type metal gate layer 3720 along the sidewalls 3726 of the opening 3724, as depicted.

[0387] In one embodiment, p-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, n-type metal gate layer 3720 includes titanium and aluminum. In one embodiment, conductive fill metal layer 3730 is above n-type metal gate layer 3720, as depicted. In one such embodiment, conductive fill metal layer 3730 includes tungsten. In a specific embodiment, conductive fill metal layer 3730 includes 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, gate dielectric layer 3714 includes a layer including hafnium and oxygen. In one embodiment, a thermal oxide layer or chemical oxide layer 3732 is between the first semiconductor fin 3706 and the upper portion of the second semiconductor fin 3710, as depicted. In one embodiment, semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0388] Now only reference Figure 37 On the right-hand side of FIG. 3 , according to an embodiment of the present disclosure, an integrated circuit structure includes a semiconductor substrate 3702 including an N-well region 3704 with a semiconductor fin 3706 protruding therefrom. A trench isolation structure 3712 is located on semiconductor substrate 3702 around semiconductor fin 3706. Semiconductor fin 3706 extends over trench isolation structure 3712. A gate dielectric layer 3714 is located over semiconductor fin 3706. A conductive layer 3716 is located over gate dielectric layer 3714 over semiconductor fin 3706. In one embodiment, conductive layer 3716 includes titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is located over conductive layer 3716 over semiconductor fin 3706.

[0389] In one embodiment, an interlayer dielectric (ILD) layer 3722 is formed above the trench isolation structure 3712. The ILD layer has an opening that exposes the semiconductor fin 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewalls of the opening that is below the top surface of the P-type metal gate layer 3718 along the sidewalls of the opening. In one embodiment, the P-type metal gate layer 3718 is formed on the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is formed above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In a specific such embodiment, the conductive fill metal layer 3730 comprises 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer 3714 comprises a layer comprising hafnium and oxygen.

[0390] Figures 38A-38HIllustrated are cross-sectional views of various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow in accordance with an embodiment of the present disclosure.

[0391] Reference shows the NMOS (N-type) region and the PMOS (P-type) region Figure 38A The method of fabricating an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 over a substrate 3800 over a first semiconductor fin 3804 and a second semiconductor fin 3806. An opening 3808 is formed in the ILD layer 3802, the opening 3808 exposing the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the opening 3808 is formed by removing gate holders or dummy gate structures initially formed at appropriate locations over the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0392] A gate dielectric layer 3810 is formed in the opening 3808 and over the first and second semiconductor fins 3804, 3806 and on a portion of the trench isolation structure 3812 between the first and second semiconductor fins 3804, 3806. In one embodiment, the gate dielectric layer 3810 is formed on a thermal oxide or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, that is formed on the first and second semiconductor fins 3804, 3806, as depicted. In another embodiment, the gate dielectric layer 3810 is formed directly on the first and second semiconductor fins 3804, 3806.

[0393] A conductive layer 3814 is formed over gate dielectric layer 3810 formed over first semiconductor fin 3804 and second semiconductor fin 3806. In one embodiment, conductive layer 3814 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed over conductive layer 3814 formed over first semiconductor fin 3804 and over second semiconductor fin 3806.

[0394] refer to Figure 38B A dielectric etch stop layer 3818 is formed on the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first silicon oxide layer (e.g., SiO2), an aluminum oxide layer (e.g., Al2O3) on the first silicon oxide layer, and a second silicon oxide layer (e.g., SiO2) on the aluminum oxide layer.

[0395] refer to Figure 38C ,exist Figure 38B A mask 3820 is formed over the structure of FIG. The mask 3820 covers the PMOS region and exposes the NMOS region.

[0396] refer to Figure 38D Dielectric etch stop layer 3818, p-type metal gate layer 3816, and conductive layer 3814 are patterned to provide patterned dielectric etch stop layer 3819 and patterned p-type metal gate layer 3817 over patterned conductive layer 3815 above first semiconductor fin 3804 but not over second semiconductor fin 3806. In an embodiment, conductive layer 3814 protects second semiconductor fin 3806 during patterning.

[0397] refer to Figure 38E ,from Figure 38D The mask 3820 is removed from the structure. Figure 38F ,from Figure 38E The patterned dielectric etch stop layer 3819 is removed from the structure.

[0398] refer to Figure 38G An n-type metal gate layer 3822 is formed over the second semiconductor fin 3806, over the portion of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and over the patterned p-type metal gate layer 3817. In an embodiment, a patterned conductive layer 3815, a patterned p-type metal gate layer 3817, and an n-type metal gate layer 3822 are further formed along sidewalls 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface along the sidewalls 3824 of the opening 3808 that is below the top surface of the patterned p-type gate metal layer 3817 and the top surface of the n-type metal gate layer 3822 along the sidewalls 3824 of the opening 3808.

[0399] refer to Figure 38H A conductive fill metal layer 3826 is formed over the n-type metal gate layer 3822. In one embodiment, the conductive fill metal layer 3826 is formed by depositing a film containing tungsten using atomic layer deposition (ALD) using a tungsten hexafluoride (WF6) precursor.

[0400] In another aspect, a double silicide structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. As an exemplary process flow, Figures 39A-39H Illustrated are cross-sectional views representing various operations in a method of fabricating a bisulicide based integrated circuit, in accordance with an embodiment of the present disclosure.

[0401] refer to Figure 39A, in which an NMOS region and a PMOS region are shown as bifurcated on a common substrate, a method of fabricating an integrated circuit structure includes forming a first gate structure 3902 over a first fin 3904, such as a first silicon fin, which may include dielectric sidewall spacers 3903. A second gate structure 3952 is formed over a second fin 3954, such as a second silicon fin, which may include dielectric sidewall spacers 3953. An insulating material 3906 is formed over the first fin 3904 adjacent to the first gate structure 3902 and over the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask in a double silicide process.

[0402] refer to Figure 39B , a first portion of the insulating material 3906 is removed from over the first fin 3904 but not over the second fin 3954 to expose a first source or drain region 3908 and a second source or drain region 3910 of the first fin 3904 adjacent to the first gate structure 3902. In an embodiment, the first source or drain region 3908 and the second source or drain region 3910 are epitaxial regions formed within a recessed portion of the first fin 3904, as depicted. In one such embodiment, the first source or drain region 3908 and the second source or drain region 3910 include silicon and germanium.

[0403] refer to Figure 39C , forming a first metal silicide layer 3912 on the first source or drain region 3908 and the second source or drain region 3910 of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by the following steps: Figure 39B depositing a layer including nickel and platinum on the structure of the present invention, annealing the layer including nickel and platinum, and removing unreacted portions of the layer including nickel and platinum.

[0404] refer to Figure 39D After forming the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed from over the second fin 3954 to expose a third source or drain region 3958 and a fourth source or drain region 3960 of the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 are formed within the second fin 3954, such as within a second silicon fin, as depicted. However, in another embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 are epitaxial regions formed within a recessed portion of the second fin 3954. In one such embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 comprise silicon.

[0405] refer to Figure 39E ,exist Figure 39D A first metal layer 3914 is formed on the structure of the first fin 3954, that is, on the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960. A second metal silicide layer 3962 is then formed on the third source or drain region 3958 and the fourth source or drain region 3960 of the second fin 3954. The second metal silicide layer 3962 is formed from the first metal layer 3914, for example, using an annealing process. In an embodiment, the second metal silicide layer 3962 is different in composition from the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, for example, with Figure 39D The open trench conforms to the shape of the .

[0406] refer to Figure 39F In an embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 over each of the first source or drain region 3908 , the second source or drain region 3910 , the third source or drain region 3958 , and the fourth source or drain region 3960 .

[0407] refer to Figure 39G In an embodiment, Figure 39F A second metal layer 3918 is formed on the U-shaped metal layer 3916 of the structure. In an embodiment, the second metal layer 3918 is different from the U-shaped metal layer 3916 in composition.

[0408] refer to Figure 39H In an embodiment, Figure 39G A third metal layer 3920 is formed on the second metal layer 3918 of the U-shaped structure. In an embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0409] Reference again Figure 39H According to an embodiment of the present disclosure, an integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) over a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be appreciated that the first fin has a top (shown as 3904A) and sidewalls (e.g., extending into and out of the page). A first gate electrode 3902 includes a first gate dielectric layer over the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and includes a first gate electrode over the first gate dielectric layer over the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite the first side 3902A.

[0410] First and second semiconductor source or drain regions 3908 and 3910, respectively, abut a first side 3902A and a second side 3902B of the first gate electrode 3902. First and second trench contact structures 3930 and 3932, respectively, are over the first and second semiconductor source or drain regions 3908 and 3910 and abut the first side 3902A and the second side 3902B of the first gate electrode 3902. A first metal silicide layer 3912 is directly between the first and second trench contact structures 3930 and 3932 and the first and second semiconductor source or drain regions 3908 and 3910, respectively.

[0411] Integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) over a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be appreciated that the second fin has a top (shown as 3954A) and sidewalls (e.g., extending into and out of the page). A second gate electrode 3952 includes a second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954, and includes a second gate electrode over the second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

[0412] The third and fourth semiconductor source or drain regions 3958 and 3960 are adjacent to the first side 3952A and the second side 3952B of the second gate electrode 3952, respectively. Third and fourth trench contact structures 3970 and 3972 are above the third and fourth semiconductor source or drain regions 3958 and 3960, respectively, and adjacent to the first side 3952A and the second side 3952B of the second gate electrode 3952. A second metal silicide layer 3962 is directly between the third and fourth trench contact structures 3970 and 3972 and the third and fourth semiconductor source or drain regions 3958 and 3960, respectively. In one embodiment, the first metal silicide layer 3912 includes at least one metal species that is not included in the second metal silicide layer 3962.

[0413] In one embodiment, the second metal silicide layer 3962 comprises titanium and silicon. The first metal silicide layer 3912 comprises nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 further comprises germanium. In one embodiment, the first metal silicide layer 3912 further comprises titanium, for example, such as to be incorporated into the first metal silicide layer 3912 during the subsequent formation of the second metal silicide layer 3962 with the first metal layer 3914. In one such embodiment, the silicide layer already formed on the PMOS source or drain region is further modified by an annealing process used to form the silicide region on the NMOS source or drain region. This can result in a silicide layer having a fractional percentage of the total silicide metal on the PMOS source or drain region. However, in other embodiments, the silicide layer already formed on the PMOS source or drain region is not modified or substantially not modified by the annealing process used to form the silicide region on the NMOS source or drain region.

[0414] In one embodiment, first and second semiconductor source or drain regions 3908 and 3910 are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, third and fourth semiconductor source or drain regions 3958 and 3960 are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, third and fourth semiconductor source or drain regions 3958 and 3960 are formed in fin 3954 rather than as embedded epitaxial regions.

[0415] In one embodiment, the first, second, third, and fourth trench contact structures 3930, 3932, 3970, and 3972 all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 above and across the entire U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 includes titanium, and the T-shaped metal layer 3918 includes cobalt. In one embodiment, the first, second, third, and fourth trench contact structures 3930, 3932, 3970, and 3972 all further include a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a specific embodiment, the third metal layer 3920 and the U-shaped metal layer include titanium, and the T-shaped metal layer 3918 includes cobalt.

[0416] In another aspect, a trench contact structure, such as for a source or drain region, is described. In an example, Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to an embodiment of the present disclosure is illustrated. Figure 40BA cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device according to another embodiment of the present disclosure is illustrated.

[0417] refer to Figure 40A Integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is over fin 4002. A gate electrode 4006 is over gate dielectric layer 4004. In one embodiment, gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In one embodiment, a dielectric cap 4012 is over gate electrode 4006 and over gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite first side 4006A. Dielectric spacers 4013 are located along sidewalls of gate electrode 4006. In one embodiment, gate dielectric layer 4004 is further positioned between a first one of dielectric spacers 4013 and first side 4006A of gate electrode 4006, and between a second one of dielectric spacers 4013 and second side 4006B of gate electrode 4006, as depicted. In an embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4002 and the gate dielectric layer 4004 .

[0418] First and second semiconductor source or drain regions 4014 and 4016 are adjacent to first side 4006A and second side 4006B, respectively, of gate electrode 4006. In one embodiment, first and second semiconductor source or drain regions 4014 and 4016 are within fin 4002, as depicted. However, in another embodiment, first and second semiconductor source or drain regions 4014 and 4016 are embedded epitaxial regions formed within a recess of fin 4002.

[0419] First and second trench contact structures 4018 and 4020 are located above first and second semiconductor source or drain regions 4014 and 4016, respectively, and adjacent to first side 4006A and second side 4006B of gate electrode 4006. Both first and second trench contact structures 4018 and 4020 include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 disposed above and extending across the U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 differ in composition. In one such embodiment, the U-shaped metal layer 4022 includes titanium, and the T-shaped metal layer 4024 includes cobalt. In one embodiment, both first and second trench contact structures 4018 and 4020 further include a third metal layer 4026 disposed above the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, third metal layer 4026 and U-shaped metal layer 4022 include titanium, and T-shaped metal layer 4024 includes cobalt.

[0420] A first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is further on and in contact with a portion of one of the dielectric spacers 4013 and on and in contact with a portion of the dielectric cap 4012. A second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is on and coupled to the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is further on and in contact with a portion of another of the dielectric spacers 4013 and on and in contact with another portion of the dielectric cap 4012.

[0421] In an embodiment, a metal silicide layer 4032 is directly between the first and second trench contact structures 4018 and 4020 and the first and second semiconductor source or drain regions 4014 and 4016, respectively. In one embodiment, the metal silicide layer 4032 includes titanium and silicon. In a particular such embodiment, the first and second semiconductor source or drain regions 4014 and 4016 are first and second N-type semiconductor source or drain regions.

[0422] refer to Figure 40BIntegrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is over fin 4052. A gate electrode 4056 is over gate dielectric layer 4054. In one embodiment, gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060. In one embodiment, an insulating cap 4062 is over gate electrode 4056 and over gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite first side 4056A. Dielectric spacers 4063 are located along sidewalls of gate electrode 4056. In one embodiment, gate dielectric layer 4054 is further located between a first one of dielectric spacers 4063 and first side 4056A of gate electrode 4056, and between a second one of dielectric spacers 4063 and second side 4056B of gate electrode 4056, as depicted. In an embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4052 and the gate dielectric layer 4054 .

[0423] First and second semiconductor source or drain regions 4064 and 4066, respectively, abut the first side 4056A and the second side 4056B of the gate electrode 4056. In one embodiment, the first and second semiconductor source or drain regions 4064 and 4066 are embedded epitaxial regions formed in recesses 4065 and 4067, respectively, of the fin 4052, as depicted. However, in another embodiment, the first and second semiconductor source or drain regions 4064 and 4066 are in the fin 4052.

[0424] First and second trench contact structures 4068 and 4070 are located above first and second semiconductor source or drain regions 4064 and 4066, respectively, and adjacent to first side 4056A and second side 4056B of gate electrode 4056. Both first and second trench contact structures 4068 and 4070 include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 disposed above and extending across the U-shaped metal layer 4072. In one embodiment, U-shaped metal layer 4072 and T-shaped metal layer 4074 differ in composition. In one such embodiment, U-shaped metal layer 4072 includes titanium, and T-shaped metal layer 4074 includes cobalt. In one embodiment, both first and second trench contact structures 4068 and 4070 further include a third metal layer 4076 disposed above T-shaped metal layer 4074. In one such embodiment, third metal layer 4076 and U-shaped metal layer 4072 have the same composition. In a particular embodiment, third metal layer 4076 and U-shaped metal layer 4072 include titanium, and T-shaped metal layer 4074 includes cobalt.

[0425] A first trench contact via 4078 is electrically connected to the first trench contact 4068. In a particular embodiment, the first trench contact via 4078 is on and coupled to the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is further on and in contact with a portion of one of the dielectric spacers 4063 and on and in contact with a portion of the dielectric cap 4062. A second trench contact via 4080 is electrically connected to the second trench contact 4070. In a particular embodiment, the second trench contact via 4080 is on and coupled to the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is further on and in contact with a portion of another of the dielectric spacers 4063 and on and in contact with another portion of the dielectric cap 4062.

[0426] In one embodiment, a metal silicide layer 4082 is directly between the first and second trench contact structures 4068 and 4070 and the first and second semiconductor source or drain regions 4064 and 4066, respectively. In one embodiment, the metal silicide layer 4082 comprises nickel, platinum, and silicon. In a specific such embodiment, the first and second semiconductor source or drain regions 4064 and 4066 are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further comprises germanium. In one embodiment, the metal silicide layer 4082 further comprises titanium.

[0427] One or more embodiments described herein relate to using metal chemical vapor deposition for wrap-around semiconductor contacts. The embodiments may be applicable to or include one or more of the following: chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0428] Certain embodiments may include using low-temperature (e.g., less than 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of contact metal to fabricate a titanium or similar metal-containing layer to provide a conformal source or drain contact. Achieving such a conformal source or drain contact may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

[0429] To provide context, sputtering can be used to deposit metal onto semiconductor contact layers. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-semiconductor junctions on device contact surfaces that are angled relative to the deposition incidence.

[0430] According to one or more embodiments of the present disclosure, a low-temperature chemical vapor deposition process is implemented for fabricating contact metals to provide conformality in three dimensions and maximize the metal-semiconductor junction contact area. The resulting larger contact area can reduce the resistance of the junction. Embodiments can include deposition on semiconductor surfaces with uneven topography, where the topography of a region refers to the surface shape and features themselves, and the uneven topography includes uneven surface shapes and features or portions of surface shapes and features, i.e., surface shapes and features that are not completely flat.

[0431] Embodiments described herein may include fabricating wraparound contact structures. In one such embodiment, the use of a pure metal conformally deposited onto a transistor source-drain contact by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the available area of ​​the metal-semiconductor contact and reduce resistance, thereby improving transistor device performance. In embodiments, the relatively low temperature of the deposition results in a minimized resistance per unit area of ​​the junction.

[0432] It will be appreciated that a wide variety of integrated circuit structures can be fabricated using an integrated scheme involving metal-containing layer deposition processes as described herein. According to an embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate having features thereon in a chemical vapor deposition (CVD) chamber having an RF source. The method also includes reacting titanium tetrachloride (TiCl4) and hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate.

[0433] In embodiments, the titanium layer has an overall atomic composition comprising 98% or greater titanium and 0.5-2% chlorine. In alternative embodiments, similar processes are used to fabricate high-purity metal-containing layers of zinc (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In embodiments, there is relatively little film thickness variation; for example, in embodiments, all coverages are greater than 50% and nominally 70% or greater (i.e., thickness variation is 30% or less). In embodiments, the thickness is measurably thicker on silicon (Si) or silicon germanium (SiGe) than on other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In embodiments, the film composition includes approximately 0.5% Cl (or less than 1%) as an impurity, with essentially no other observed impurities. In embodiments, the deposition process enables metal coverage on non-line-of-sight surfaces, such as those hidden from view by sputter deposition. The embodiments described herein can be implemented to improve transistor device drive by reducing the external resistance to current driven through the source and drain contacts.

[0434] According to an embodiment of the present disclosure, the substrate is characterized by exposing a source or drain contact trench of a semiconductor source or drain structure. The titanium layer (or other high-purity metal-containing layer) is a conductive contact layer for the semiconductor source or drain structure. Figure 41A 、 41B , 42, 43A-43C and 44 to describe exemplary embodiments of such an embodiment.

[0435] Figure 41A A cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to an embodiment of the present disclosure is illustrated.

[0436] refer to Figure 41A , semiconductor structure 4100 includes a gate structure 4102 over a substrate 4104. Gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. Source region 4108 and drain region 4110 are on opposite sides of gate structure 4102. Source or drain contacts 4112 are electrically connected to source region 4108 and drain region 4110 and are spaced apart from gate structure 4102 by one or both of an interlayer dielectric layer 4114 and a gate dielectric spacer 4116. Source region 4108 and drain region 4110 are regions of substrate 4104.

[0437] In an embodiment, the source or drain contact 4112 includes a high-purity metal-containing layer 4112A, such as described above, and a conductive trench fill material 4112B. In one embodiment, the high-purity metal-containing layer 4112A has a total atomic composition comprising 98% or more titanium. In one such embodiment, the total atomic composition of the high-purity metal-containing layer 4112A further comprises 0.5-2% chlorine. In an embodiment, the high-purity metal-containing layer 4112A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 4112B is composed of a conductive metal, such as, but not limited to, Cu, Al, W, or alloys thereof.

[0438] Figure 41B A cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region according to an embodiment of the present disclosure is illustrated.

[0439] refer to Figure 41B, semiconductor structure 4150 includes a gate structure 4152 above substrate 4154. Gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. Source region 4158 and drain region 4160 are on opposite sides of gate structure 4152. Source or drain contacts 4162 are electrically connected to source region 4158 and drain region 4160 and are spaced apart from gate structure 4152 by one or both of an interlayer dielectric layer 4164 and a gate dielectric spacer 4166. Source region 4158 and drain region 4160 are epitaxial or embedded material regions formed in the etched away areas of substrate 4154. As depicted, in an embodiment, source region 4158 and drain region 4160 are raised source and drain regions. In certain such embodiments, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

[0440] In an embodiment, the source or drain contact 4162 includes a high-purity metal-containing layer 4162A, such as described above, and a conductive trench fill material 4162B. In one embodiment, the high-purity metal-containing layer 4162A has a total atomic composition comprising 98% or more titanium. In one such embodiment, the total atomic composition of the high-purity metal-containing layer 4162A further comprises 0.5-2% chlorine. In an embodiment, the high-purity metal-containing layer 4162A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 4162B is composed of a conductive metal, such as, but not limited to, Cu, Al, W, or alloys thereof.

[0441] Therefore, in the embodiments, reference is made to Figure 41A and 41B , the integrated circuit structure includes a feature having a surface (source or drain contact trench exposing the semiconductor source or drain structure). A high-purity metal-containing layer 4112A or 4162A is on the surface of the source or drain contact trench. It is to be understood that the contact formation process may involve consumption of the exposed silicon or germanium or silicon-germanium material in the source or drain region. Such consumption can degrade device performance. In contrast, according to embodiments of the present disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure below the source or drain contact trench is not eroded or consumed, or is substantially not eroded or consumed. In one such embodiment, this non-consumption or non-erosion results from the low-temperature deposition of the high-purity metal-containing contact layer.

[0442] Figure 42 A plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is illustrated.

[0443] refer to Figure 42 , a plurality of active gate lines 4204 are formed over the plurality of semiconductor fins 4200. Dummy gate lines 4206 are at the ends of the plurality of semiconductor fins 4200. The spaces 4208 between the gate lines 4204 / 4206 are where trench contacts can be formed as conductive contacts to source or drain regions, such as source or drain regions 4251, 4252, 4253, and 4254.

[0444] Figures 43A-43C The present invention illustrates various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Figure 42 A cross-sectional view taken along the a-a' axis.

[0445] refer to Figure 43A A plurality of active gate lines 4304 are formed above semiconductor fins 4302, which are formed above substrate 4300. Dummy gate lines 4306 are located at the ends of semiconductor fins 4302. A dielectric layer 4310 is located between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. Embedded source or drain structures 4308 are located within semiconductor fins 4302, between the active gate lines 4304, and between the dummy gate lines 4306 and the active gate lines 4304. The active gate lines 4304 include a gate dielectric layer 4312, a work function gate electrode portion 4314, a fill gate electrode portion 4316, and a gate electrode capping layer 4318. Dielectric spacers 4320 line the sidewalls of the active gate lines 4304 and the dummy gate lines 4306.

[0446] refer to Figure 43B , portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 are removed to provide openings 4330 in locations where trench contacts are to be formed. Removal of the portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 may cause erosion of the embedded source or drain structure 4308 to provide an eroded embedded source or drain structure 4332, which may have an upper saddle-shaped morphology, such as Figure 43B As described in .

[0447] refer to Figure 43C Trench contacts 4334 are formed in the openings 4330 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304. Each of the trench contacts 4334 may include a metal-containing contact layer 4336 and a conductive fill material 4338.

[0448] Figure 44 The invention illustrates an embodiment of the present invention for an integrated circuit structure. Figure 42 A cross-sectional view taken along the b-b' axis.

[0449] refer to Figure 44 , fin 4402 is depicted above substrate 4404. The lower portion of fin 4402 is surrounded by trench isolation material 4404. The upper portion of fin 4402 has been removed to enable growth of embedded source and drain structures 4406. Trench contacts 4408 are formed in openings in dielectric layer 4410 that expose embedded source and drain structures 4406. The trench contacts include a metal-containing contact layer 4412 and a conductive fill material 4414. It will be appreciated that, in accordance with an embodiment, the metal-containing contact layer 4412 extends to the top of the trench contacts 4408, as shown. Figure 44 However, in another embodiment, the metal-containing contact layer 4412 does not extend to the top of the trench contact 4408, but is slightly recessed within the trench contact 4408, for example, similar to Figure 43C Depiction of the metal-containing contact layer 4336 in FIG.

[0450] Therefore, the common reference Figure 42 、 43A-43C and 44, according to an embodiment of the present disclosure, an integrated circuit structure includes a semiconductor fin (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fin (4200, 4302, 4402) has a top and sidewalls. A gate electrode (4204, 4304) is above the top of the semiconductor fin (4200, 4302, 4402) and adjacent to a sidewall of a portion of the semiconductor fin (4200, 4302, 4402). The gate electrode (4204, 4304) defines a channel region in the semiconductor fin (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is located at a first end of the channel region on a first side of the gate electrode (4204, 4304), the first semiconductor source or drain structure (4251, 4332, 4406) having an uneven topography. A second semiconductor source or drain structure (4252, 4332, 4406) is located at a second end of the channel region on a second side of the gate electrode (4204, 4304), the second end being opposite the first end and the second side being opposite the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has an uneven topography. A metal-containing contact material (4336, 4412) is directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metal-containing contact material (4336, 4412) conforms to the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conforms to the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In an embodiment, the metal-containing contact material (4336, 4412) has a total atomic composition comprising 95% or more of a single metal species. In one such embodiment, the metal-containing contact material (4336, 4412) has a total atomic composition comprising 98% or more of titanium. In a specific such embodiment, the total atomic composition of the metal-containing contact material (4336, 4412) further comprises 0.5-2% chlorine. In an embodiment, the metal-containing contact material (4336, 4412) has a thickness variation of 30% or less along the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0452] In an embodiment, the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a raised central portion and lower side portions, e.g. Figure 44 In an embodiment, the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include saddle-shaped portions, such as Figure 43C As described in .

[0453] In an embodiment, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both include silicon. In an embodiment, the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) both further include germanium, for example, in the form of silicon germanium.

[0454] In an embodiment, the metal-containing contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) is further above the first semiconductor source or drain structure (4251, 4332, 4406) along the sidewalls of a trench in the dielectric layer (4320, 4410), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal-containing contact material (4336) decreases along the sidewalls of the trench from 4336A at the first semiconductor source or drain structure (4332) to a position (4336B) above the first semiconductor source or drain structure (4332). Figure 43C An example of this is illustrated in In an embodiment, the conductive fill material (4338, 4414) is on the metal-containing contact material (4336, 4412) within the trench, as Figure 43C and 44 As described in .

[0455] In an embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (e.g., Figure 42The upper fins 4200, 4302, 4402 of the second semiconductor fin are provided. A gate electrode (4204, 4304) is further located above the top of the second semiconductor fin and adjacent to a sidewall of a portion of the second semiconductor fin, the gate electrode defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is located at a first end of the channel region of the second semiconductor fin on a first side of the gate electrode (4204, 4304), the third semiconductor source or drain structure having an uneven topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is located at a second end of the channel region of the second semiconductor fin on a second side of the gate electrode (4204, 4304), the second end being opposite the first end, the fourth semiconductor source or drain structure (4254, 4332, 4406) having an uneven topography. The metal-containing contact material (4336, 4412) is directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406), the metal-containing contact material (4336, 4412) conforming to the uneven topography of the third semiconductor source or drain structure (4253, 4332, 4406) and conforming to the uneven topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In an embodiment, the metal-containing contact material (4336, 4412) is continuous between the first semiconductor source or drain structure (4251, 4332, 4406 on the left) and the third semiconductor source or drain structure (4253, 4332, 4406 on the right), and is continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0456] In another aspect, the hard mask material serves to preserve (inhibit erosion) and may remain over the dielectric material in trench line locations where the conductive trench contacts are interrupted (eg, in contact plug locations). Figure 45A and 45B A plan view and a corresponding cross-sectional view are respectively illustrated of an integrated circuit structure including a trench contact plug having a hard mask material thereon according to an embodiment of the present disclosure.

[0457] refer to Figure 45A and 45BIn an embodiment, an integrated circuit structure 4500 includes a fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are located above the fin 4502A. Each gate structure in the gate structures 4506 is oriented in a direction 4508 orthogonal to the fin 4502A and has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of a first pair of gate structures 4506A / 4506B in the gate structures 4506. A contact plug 4514B is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of a second pair of gate structures 4506B / 4506C in the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hardmask material 4518.

[0458] In an embodiment, the lower dielectric material 4516 of the contact plug 4516B includes silicon and oxygen, such as silicon oxide or silicon dioxide, and the upper hard mask material 4518 of the contact plug 4516B includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0459] In an embodiment, trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on lower conductive structure 4520. In one embodiment, dielectric cap 4522 of trench contact structure 4512 has an upper surface that is coplanar with an upper surface of upper hard mask material 4518 of contact plug 4514B, as depicted.

[0460] In an embodiment, each gate structure in the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each gate structure in the plurality of gate structures 4506 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514B, as depicted. In an embodiment, although not depicted, a thin oxide layer, such as a thermally or chemically oxidized silicon or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0461] Reference again Figure 45A and 45BIn an embodiment, an integrated circuit structure 4500 includes a plurality of fins 4502, such as silicon fins. Each fin in the plurality of fins 4502 is oriented along a first direction 4504. A plurality of gate structures 4506 are disposed over the plurality of fins 4502. Each gate structure in the plurality of gate structures 4506 is disposed along a second direction 4508 orthogonal to the first direction 4504. Each gate structure in the plurality of gate structures 4506 has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is disposed over a first fin 4502A in the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures in the gate structure 4506. A contact plug 4514A is disposed over a second fin 4502B in the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures in the gate structure 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518 .

[0462] In an embodiment, the lower dielectric material 4516 of the contact plug 4516A includes silicon and oxygen, such as silicon oxide or silicon dioxide, and the upper hard mask material 4518 of the contact plug 4516A includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0463] In an embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as depicted.

[0464] In an embodiment, each gate structure in the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each gate structure in the plurality of gate structures 4506 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as depicted. In an embodiment, although not depicted, a thin oxide layer, such as a thermally or chemically oxidized silicon or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0465] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process can be implemented to form contact structures for use in semiconductor structure fabrication (e.g., for integrated circuit fabrication). In one embodiment, the contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve an additional photolithography process combined with a selective contact etch to closely align the photolithographic contact pattern to the existing gate pattern. For example, another process can include patterning a poly (gate) grid, where the contacts and contact plugs are patterned separately.

[0466] According to one or more embodiments described herein, a contact formation method involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, the method enables the use of inherently highly selective wet etching (e.g., compared to dry etching or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plug photolithography operation. In one such embodiment, the method enables the elimination of the need for critical photolithography operations that would otherwise be used to generate the contact pattern as used in other methods. In an embodiment, the trench contact grid is not patterned separately, but rather is formed between the aggregate (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0467] Figures 46A-46D Illustrated are cross-sectional views representing various operations in a method including fabricating an integrated circuit structure having a trench contact plug having a hard mask material thereon, in accordance with an embodiment of the present disclosure.

[0468] refer to Figure 46A A method of fabricating an integrated circuit structure includes forming a plurality of fins, each fin 4602 of the plurality of fins being oriented along a first direction 4604. Each fin 4602 of the plurality of fins may include a diffusion region 4606. A plurality of gate structures 4608 are formed above the plurality of fins. Each gate structure of the plurality of gate structures 4508 is oriented along a second direction 4610 orthogonal to the first direction 4604 (e.g., direction 4610 into and out of the page). A sacrificial material structure 4612 is formed between a first pair of gate structures 4608. A contact plug 4614 is formed between a second pair of gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask material 4618 is formed on the lower dielectric material 4616.

[0469] In an embodiment, gate structure 4608 includes a sacrificial gate stack or dummy gate stack and dielectric spacers 4609. The sacrificial gate stack or dummy gate stack may be composed of polysilicon or silicon nitride pillars or some other sacrificial material, which may be referred to as gate dummy material.

[0470] refer to Figure 46B ,from Figure 46A The sacrificial material structure 4612 is removed to form an opening 4620 between the first pair of gate structures 4608.

[0471] refer to Figure 46C , forming a trench contact structure 4622 in the opening 4620 between the first pair of gate structures 4608. Additionally, in an embodiment, as part of forming the trench contact structure 4622, Figure 46A and 46B The hard mask 4618 is planarized. The final contact plug 4614 ′ includes a lower dielectric material 4616 and an upper hard mask material 4624 formed from the hard mask material 4618 .

[0472] In one embodiment, the lower dielectric material 4616 of each of the contact plugs 4614′ includes silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614′ includes silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614′.

[0473] refer to Figure 46D , in a replacement gate process scheme, the sacrificial gate stack or dummy gate stack of the gate structure 4608 is replaced. In such a scheme, the dummy gate material, such as polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried out from an earlier process.

[0474] Thus, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Additionally, in an embodiment, a top portion of the permanent gate structure 4630 is removed, for example, by an etching process, and replaced with a dielectric cap 4636. In an embodiment, the dielectric cap 4636 of each gate structure in the permanent gate structure 4630 has an upper surface that is coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614′.

[0475] Reference again Figures 46A-46DIn an embodiment, the replacement gate process is performed after forming the trench contact structure 4622 , as depicted. However, according to other embodiments, the replacement gate process is performed before forming the trench contact structure 4622 .

[0476] In another aspect, contact-on-active-gate (COAG) structures and processes are described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to methods of fabricating a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The methods described herein can be used to reduce the standard cell area by enabling gate contact formation over an active gate area. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure.

[0477] In technologies where space and layout constraints are somewhat relaxed compared to current generation space and layout constraints, a contact to the gate structure may be made by making a contact to a portion of the gate electrode disposed over an isolation region. As an example, Figure 47A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is illustrated.

[0478] refer to Figure 47A , semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed in substrate 4702 and within isolation region 4706. One or more gate lines (also referred to as polylines), such as gate lines 4708A, 4708B, and 4708C, are disposed over diffusion or active region 4704 and over a portion of isolation region 4706. Source or drain contacts (also referred to as trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contact to trench contacts 4710A and 4710B, respectively. A separate gate contact 4714 and an overlying gate contact via 4716 provide contact to gate line 4708B. Compared to the source or drain trench contacts 4710A or 4710B, from a plan view perspective, the gate contact 4714 is disposed over the isolation region 4706 and not over the diffusion or active region 4704. Furthermore, neither the gate contact 4714 nor the gate contact via 4716 is disposed between the source or drain trench contacts 4710A and 4710B.

[0479] Figure 47BA cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is illustrated. Figure 47B , semiconductor structure or device 4700B (e.g., Figure 47A A non-planar version of device 4700A) includes a non-planar diffusion or active region 4704C (e.g., a fin structure) formed from substrate 4702 and within isolation region 4706. A gate line 4708B is disposed over the non-planar diffusion or active region 4704B and over a portion of isolation region 4706. As shown, gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752 along with a dielectric cap layer 4754. Also seen from this view is a gate contact 4714 and an overlying gate contact via 4716, as well as an overlying metal interconnect 4760, all of which are disposed in an interlayer dielectric stack or layer 4770. Also seen from this view is a gate contact 4714 and an overlying gate contact via 4716, as well as an overlying metal interconnect 4760, all of which are disposed in an interlayer dielectric stack or layer 4770. Figure 47B From the perspective of FIG, the gate contact 4714 is disposed above the isolation region 4706 but not above the non-planar diffusion or active region 4704B.

[0480] Reference again Figure 47A and 47B , the arrangement of semiconductor structures or devices 4700A and 4700B, respectively, places a gate contact above the isolation region. Such an arrangement wastes layout space. However, placing a gate contact above an active area would require an extremely tight registration budget, or the gate size would have to be increased to provide sufficient space for the gate contact to land. Furthermore, historically, contacting the gate above a diffusion region has been avoided due to the risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address the aforementioned issues by providing a feasible method for fabricating a contact structure, and the resulting structure, that contacts a portion of a gate electrode formed above a diffusion or active region.

[0481] As an example, Figure 48A A plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated. Figure 48A, semiconductor structure or device 4800A includes a diffusion or active region 4804 disposed in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffusion or active region 4804 and over a portion of the isolation region 4806. Source or drain trench contacts, such as trench contacts 4810A and 4810B, are disposed over the source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contact to trench contacts 4810A and 4810B, respectively. A gate contact via 4816, without an intervening separate gate contact layer, provides contact to gate line 4808B. Figure 47A In contrast, from a plan view perspective, the gate contact 4816 is disposed over the diffusion or active region 4804 and between the source or drain contacts 4810A and 4810B.

[0482] Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated. Figure 48B , semiconductor structure or device 4800B (e.g., Figure 48A A non-planar version of device 4800A (e.g., a fin structure) includes a non-planar diffusion or active region 4804B (e.g., a fin structure) formed from substrate 4802 and within isolation region 4806. A gate line 4808B is disposed over the non-planar diffusion or active region 4804B and over a portion of isolation region 4806. As shown, gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852 along with a dielectric cap layer 4854. Also seen from this view is a gate contact via 4816, as well as an overlying metal interconnect 4860, both of which are disposed in an interlayer dielectric stack or layer 4870. Also seen from this view is a gate contact via 4816, as well as an overlying metal interconnect 4860, both of which are disposed in an interlayer dielectric stack or layer 4870. Figure 48B From the perspective of FIG, the gate contact via 4816 is disposed above the non-planar diffusion or active area 4804B.

[0483] Therefore, refer again to Figure 48A and 48B In an embodiment, the trench contact vias 4812A, 4812B and the gate contact via 4816 are formed in the same layer and are substantially coplanar. Figure 47A and 47B In contrast, the contact to the gate line will additionally comprise an additional gate contact layer, which may, for example, run perpendicular to the corresponding gate line. Figure 48A and 48BIn the described structure(s), structures 4800A and 4800B are fabricated so that contacts directly from the metal interconnect layer can be landed on the active gate portion without shorting to the adjacent source or drain regions. In embodiments, such an arrangement provides a significant area reduction in circuit layout by eliminating the need to extend the transistor gate over the isolation to form a reliable contact. As used throughout, in embodiments, reference to the active portion of a gate refers to that portion of a gate line or structure that is disposed above the active or diffusion region of the underlying substrate (as viewed in plan). In embodiments, reference to the inactive portion of a gate refers to that portion of a gate line or structure that is disposed above the isolation region of the underlying substrate (as viewed in plan).

[0484] In an embodiment, semiconductor structure or device 4800 is a non-planar device, such as, but not limited to, a fin FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of and formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 4808A-4808C surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is formed as a discrete three-dimensional body, such as in a gate-all-around device. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C each completely surround the channel region.

[0485] More generally, one or more embodiments relate to methods for landing gate contact vias directly on active transistor gates and structures formed by landing gate contact vias directly on active transistor gates. Such methods can eliminate the need to extend gate lines over isolation for contact purposes. Such methods can also eliminate the need for a separate gate contact (GCN) layer for directing signals from the gate lines or structures. In one embodiment, this elimination is achieved by recessing the contact metal in the trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) into the process flow. This additional dielectric material is included as a trench contact dielectric cap layer that has different etching characteristics than the gate dielectric material cap layer (e.g., GILA) already used for trench contact alignment in a gate-aligned contact process (GAP) processing scheme.

[0486] As an exemplary fabrication scheme, Figures 49A-49D Illustrated are cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present disclosure.

[0487] refer to Figure 49A, a semiconductor structure 4900 is provided after trench contacts (TCN) are formed. It is to be appreciated that this particular arrangement of structure 4900 is for illustrative purposes only, and a wide variety of possible layouts may benefit from embodiments of the disclosure described herein. The semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E, disposed above a substrate 4902. The gate stack structure may include a gate dielectric layer and a gate electrode. Trench contacts—e.g., contacts to diffusion regions of the substrate 4902, such as trench contacts 4910A-4910C—are also included in the structure 4900 and are spaced apart from the gate stack structures 4908A-4908E by dielectric spacers 4920. An insulating cap layer 4922 may be disposed on the gate stack structures 4908A-4908E (e.g., GILA), as also shown in FIG. Figure 49A As also described in Figure 49A As depicted in FIG, contact stop regions or “contact plugs” fabricated from an interlayer dielectric material, such as region 4923, may be included in areas where contact formation is to be prevented.

[0488] In an embodiment, providing structure 4900 involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, the method enables the use of inherently highly selective wet etching (e.g., as opposed to dry etching or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plug photolithography operation. In one such embodiment, the method enables the elimination of the need for critical photolithography operations that would otherwise be used to generate the contact pattern as used in other methods. In an embodiment, the trench contact grid is not patterned separately, but rather is formed between the polymer (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0489] In addition, the gate stack structures 4908A-4908E can be manufactured by a replacement gate process. In such an embodiment, dummy gate materials such as polysilicon or silicon nitride pillar materials can be removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to being carried out from an earlier process. In an embodiment, the dummy gates are removed by a dry etch or a wet etch process. In one embodiment, the dummy gates are composed of polysilicon or amorphous silicon and are removed using a dry etch process including SF6. In another embodiment, the dummy gates are composed of polysilicon or amorphous silicon and are removed using a wet etch process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gates are composed of silicon nitride and are removed using a wet etch including aqueous phosphoric acid.

[0490] In an embodiment, one or more of the methods described herein generally contemplates a dummy gate and replacement gate process in conjunction with a dummy contact and replacement contact process to implement structure 4900. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal is performed on at least a portion of the permanent gate structure at a temperature greater than approximately 600 degrees Celsius, such as after forming the gate dielectric layer. The anneal is performed before forming the permanent contact.

[0491] refer to Figure 49B The trench contacts 4910A-4910C of the structure 4900 are recessed within the spacers 4920 to provide recessed trench contacts 4911A-4911C having a height lower than the top surfaces of the spacers 4920 and the insulating capping layer 4922. An insulating capping layer 4924 (e.g., TILA) is then formed over the recessed trench contacts 4911A-4911C. According to an embodiment of the present disclosure, the insulating capping layer 4924 over the recessed trench contacts 4911A-4911C is composed of a material having different etching characteristics than the insulating capping layer 4922 over the gate stack structures 4908A-4908E. As will be seen in subsequent processing operations, this difference can be exploited to selectively etch one of the trench contacts 4922 / 4924 from the other.

[0492] The trench contacts 4910A-4910C can be recessed by a process that is selective for the materials of the spacers 4920 and the insulating capping layer 4922. For example, in one embodiment, the trench contacts 4910A-4910C are recessed by an etching process, such as a wet etching process or a dry etching process. The insulating capping layer 4924 can be formed by a process suitable for providing a conformal and sealing layer over the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulating capping layer 4924 is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. This conformal layer is then planarized, for example by chemical mechanical polishing (CMP), to provide the insulating capping layer 4924 material only over the trench contacts 4910A-4910C and the newly exposed spacers 4920 and insulating capping layer 4922.

[0493] Regarding suitable material composition for the insulating cap layers 4922 / 4924, in one embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other is composed of silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other is composed of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of carbon-doped silicon nitride and the other is composed of silicon carbide.

[0494] refer to Figure 49C , forming an interlayer dielectric (ILD) 4930 and a hard mask 4932 stack and patterning them to provide, for example, Figure 49B Patterned metal (0) trench 4934 above the structure.

[0495] The interlayer dielectric (ILD) 4930 may be composed of a material suitable for electrically isolating metal features ultimately formed therein while maintaining a robust structure between front-end and back-end processing. Furthermore, in an embodiment, the composition of the ILD 4930 is selected to be consistent with the via etch selectivity used for trench contact dielectric cap patterning, as described below in connection with Figure 49DAs described in more detail below. In one embodiment, ILD 4930 is composed of a single or multiple silicon oxide layers or a single or multiple carbon-doped oxide (CDO) material layers. However, in other embodiments, ILD 4930 has a dual-layer composition, where the top portion is composed of a different material than the bottom portion below ILD 4930. Hardmask layer 4932 can be composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, hardmask layer 4932 is substantially composed of carbon, for example, as a cross-linked organic polymer layer. In other embodiments, silicon nitride or carbon-doped silicon nitride is used as hardmask 4932. The interlayer dielectric (ILD) 4930 and hardmask 4932 stack can be patterned through photolithography and etching processes.

[0496] refer to Figure 49D , forming a via opening 4936 (eg, VCT) in the interlayer dielectric (ILD) 4930 that extends from the metal (0) trench 4934 to one or more of the recessed trench contacts 4911A-4911C. For example, in Figure 49D , via openings are formed to expose the recessed trench contacts 4911A and 4911C. Forming via opening 4936 includes etching respective portions of the interlayer dielectric (ILD) 4930 and the corresponding insulating capping layer 4924. In one such embodiment, a portion of the insulating capping layer 4922 is exposed during patterning of the interlayer dielectric (ILD) 4930 (e.g., the portion of the insulating capping layer 4922 above the gate stacks 4908B and 4908E). In this embodiment, the insulating capping layer 4924 is etched selectively relative to the insulating capping layer 4922 (i.e., without significantly etching or affecting the insulating capping layer 4922) to form the via opening 4936.

[0497] In one embodiment, the via opening pattern is ultimately transferred to insulating capping layer 4924 (i.e., trench contact insulating capping layer) by an etching process that does not etch insulating capping layer 4922 (i.e., gate insulating capping layer). Insulating capping layer 4924 (TILA) can be composed of any of the following or a combination thereof: silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides and silicates, including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof. This layer can be deposited using any of the following techniques: CVD, ALD, PECVD, PVD, HDP, assisted CVD, and low-temperature CVD. Corresponding plasma dry etching has been developed as a combination of chemical and physical sputtering mechanisms. Simultaneous polymer deposition can be used to control material removal rate, etch profile, and film selectivity. The dry etch is typically generated using a gas mixture including NF3, CHF3, C4F8, HBr, and O2, typically at a pressure in the range of 30-100 mTorr and a plasma bias of 50-1000 W. The dry etch can be designed to achieve significant etch selectivity between the cap layer 4924 (TILA) and the 4922 (GILA) layer to minimize loss of 4922 (GILA) during the dry etch of 4924 (TILA) used to form contacts to the source and drain regions of the transistor.

[0498] Reference again Figure 49D , it is to be appreciated that a similar approach can be implemented to produce a via opening pattern that is ultimately transferred to the insulating capping layer 4922 (ie, the trench contact insulating capping layer) by an etching process that does not etch the insulating capping layer 4924 (ie, the gate insulating capping layer).

[0499] To further illustrate the concept of Contact on Active Gate (COAG) technology, Figure 50 Illustrated are a plan view and corresponding cross-sectional views of an integrated circuit structure having a trench contact with an overlying insulating cap layer according to an embodiment of the present disclosure.

[0500] refer to Figure 50 , an integrated circuit structure 5000 includes a gate line 5004 over a semiconductor substrate or fin 5002, such as a silicon fin. The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating capping layer 5006 on the gate stack 5005. Dielectric spacers 5008 are along sidewalls of the gate stack 5005, and in an embodiment, along sidewalls of the gate insulating capping layer 5006, as depicted.

[0501] Trench contacts 5010 abut sidewalls of gate lines 5004 with dielectric spacers 5008 between them. Each of trench contacts 5010 includes a conductive contact structure 5011 and a trench contact insulating capping layer 5012 thereon.

[0502] Reference again Figure 50 , a gate contact via 5014 is formed in the opening of the gate insulating capping layer 5006, and the gate contact via 5014 electrically contacts the gate stack 5005. In an embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a location above the semiconductor substrate or fin 5002 and laterally between the trench contacts 5010, as depicted. In one such embodiment, the trench contact insulating capping layer 5012 on the conductive contact structure 5011 prevents a gate-to-source short or a gate-to-drain short through the gate contact via 5014.

[0503] Reference again Figure 50 , trench contact vias 5016 are formed in the openings of the trench contact insulating capping layer 5012, and the trench contact vias 5016 electrically contact the corresponding conductive contact structures 5011. In an embodiment, the trench contact vias 5016 electrically contact the corresponding conductive contact structures 5011 at locations above the semiconductor substrate or fin 5002 and laterally adjacent to the gate stack 5005 of the gate line 5004, as depicted. In one such embodiment, the gate insulating capping layer 5006 on the gate stack 5005 prevents source-to-gate shorting or drain-to-gate shorting through the trench contact vias 5016.

[0504] It is to be appreciated that different structural relationships between the insulating gate cap layer and the insulating trench contact cap layer can be produced. As an example, Figures 51A-51F Illustrated are cross-sectional views of various integrated circuit structures each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer according to embodiments of the present disclosure.

[0505] refer to Figure 51A 、 51B5100A, 5100B, and 5100C, respectively, include a fin 5102, such as a silicon fin. Although depicted as a cross-sectional view, it should be understood that the fin 5102 has a top 5102A and sidewalls (into and out of the page as viewed from the perspective shown). First and second gate dielectric layers 5104 and 5106 are over the top 5102A of the fin 5102 and laterally abut the sidewalls of the fin 5102. First and second gate electrodes 5108 and 5110 are over the first and second gate dielectric layers 5104 and 5106, respectively, which are over the top 5102A of the fin 5102 and laterally abut the sidewalls of the fin 5102. Each of the first and second gate electrodes 5108 and 5110 includes a conformal conductive layer 5109A, such as a work function setting layer, and a conductive fill material 5109B over the conformal conductive layer 5109A. The first and second gate electrodes 5108 and 5110 both have a first side 5112 and a second side 5114 opposite the first side 5112. The first and second gate electrodes 5108 and 5110 also each have an insulating cap 5116 having a top surface 5118.

[0506] A first dielectric spacer 5120 abuts a first side 5112 of the first gate electrode 5108. A second dielectric spacer 5122 abuts a second side 5114 of the second gate electrode 5110. A semiconductor source or drain region 5124 abuts the first and second dielectric spacers 5120 and 5122. A trench contact structure 5126 is over the semiconductor source or drain region 5124 and abuts the first and second dielectric spacers 5120 and 5122.

[0507] The trench contact structure 5126 includes an insulating cap 5128 overlying the conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has a top surface 5129 that is substantially coplanar with the top surface 5118 of the insulating cap 5116 of the first and second gate electrodes 5108 and 5110. In one embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into the recess 5132 in the first and second dielectric spacers 5120 and 5122. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 overhangs the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recess 5132 in the first and second dielectric spacers 5120 and 5122 and, therefore, does not overhang the conductive structure 5130 of the trench contact structure 5126.

[0508] It is to be appreciated that the conductive structure 5130 of the trench contact structure 5126 may not be rectangular, e.g. Figures 51A-51CFor example, the conductive structure 5130 of the trench contact structure 5126 may have a similar structure to that described in Figure 51A The cross-sectional geometry of the conductive structure 5130A illustrated in the projection of is shown or is the same as the cross-sectional geometry.

[0509] In an embodiment, the insulating cap 5128 of the trench contact structure 5126 has a different composition than the insulating cap 5116 of the first and second gate electrodes 5108 and 5110. In one such embodiment, the insulating cap 5128 of the trench contact structure 5126 includes a carbide material, such as a silicon carbide material, while the insulating cap 5116 of the first and second gate electrodes 5108 and 5110 includes a nitride material, such as a silicon nitride material.

[0510] In an embodiment, the insulating caps 5116 of the first and second gate electrodes 5108 and 5110 both have bottom surfaces 5117A below the bottom surface 5128A of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG. Figure 51A In another embodiment, the insulating caps 5116 of the first and second gate electrodes 5108 and 5110 both have bottom surfaces 5117B that are substantially coplanar with the bottom surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG. Figure 51B In another embodiment, the insulating caps 5116 of the first and second gate electrodes 5108 and 5110 both have bottom surfaces 5117C above the bottom surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG. Figure 51C As described in .

[0511] In an embodiment, the conductive structure 5130 of the trench contact structure 5128 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 above and over the entire U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. The insulating cap 5128 of the trench contact structure 5126 is located on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 include titanium, and the T-shaped metal layer 5136 includes cobalt. In a specific such embodiment, the T-shaped metal layer 5136 further includes carbon.

[0512] In an embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicide layer 5140 comprises titanium and silicon. In a specific such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 comprises nickel, platinum, and silicon. In a specific such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In another specific such embodiment, the metal silicide layer further comprises germanium.

[0513] In the examples, reference Figure 51D , the conductive via 5150 is over and electrically connected to a portion of the first gate electrode 5108 above the top 5102A of the fin 5102. The conductive via 5150 is in an opening 5152 in the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is over a portion of the insulating cap 5128 of the trench contact structure 5126 but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular such embodiment, the conductive via 5150 is in an eroded portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0514] In the examples, reference Figure 51E , the conductive via 5160 is over and electrically connected to a portion of the trench contact structure 5126. The conductive via is in an opening 5162 of the insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is over a portion of the insulating cap 5116 of the first and second gate electrodes 5108 and 5110 but is not electrically connected to the first and second gate electrodes 5108 and 5110. In a particular such embodiment, the conductive via 5160 is in an eroded portion 5164 of the insulating cap 5116 of the first and second gate electrodes 5108 and 5110.

[0515] Reference again Figure 51E In an embodiment, the conductive via 5160 is Figure 51D The second conductive via 5160 is of the same structure as the conductive via 5150. In one such embodiment, the second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, the second conductive via 5160 is fused with the conductive via 5150 to form an electrical shorting contact 5170, as shown in FIG. Figure 51F As described in .

[0516] The methods and structures described herein can enable the formation of other structures or devices that are impossible or difficult to manufacture using other methods. In a first example, Figure 52A FIG2 illustrates a plan view of another semiconductor device having a gate contact via disposed above an active portion of a gate according to another embodiment of the present disclosure. Figure 52A , a semiconductor structure or device 5200 includes a plurality of gate structures 5208A-5208C interdigitated with a plurality of trench contacts 5210A and 5210B (these features are disposed above an active area of ​​a substrate, not shown). Gate contact vias 5280 are formed on active portions of gate structures 5208B. Gate contact vias 5280 are further disposed on active portions of gate structure 5208C, thereby coupling gate structures 5208B and 5208C. It will be appreciated that the intervening trench contacts 5210B can be isolated from the contacts 5280 by using a trench contact isolation capping layer (e.g., TILA). Figure 52A The contact configuration may provide a method for more easily strapping adjacent gate lines in a layout without routing the strapping through upper metallization layers, thereby enabling a smaller cell area or a less complex wiring scheme, or both.

[0517] In the second example, Figure 52B FIG2 illustrates a plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts according to another embodiment of the present disclosure. Figure 52B , a semiconductor structure or device 5250 includes a plurality of gate structures 5258A-5258C interdigitated with a plurality of trench contacts 5260A and 5260B (these features are disposed above an active area of ​​a substrate, not shown). Trench contact vias 5290 are formed above the trench contacts 5260A. Trench contact vias 5290 are further disposed above the trench contacts 5260B, thereby coupling the trench contacts 5260A and 5260B. It will be appreciated that the intervening gate structures 5258B can be isolated from the trench contact vias 5290 by using a gate isolation capping layer (e.g., by a GILA process). Figure 52B The contact configuration may provide a method for more easily bundling adjacent trench contacts into a layout without routing the bundling through upper metallization layers, thereby enabling a smaller cell area or a less complex routing scheme, or both.

[0518] Several deposition operations may be used to fabricate the insulating capping layer for the gate electrode, and as a result, the insulating capping layer may comprise the product of a multi-deposition fabrication process. As an example, Figures 53A-53EIllustrated are cross-sectional views representing various operations in a method of fabricating ...

Claims

1. An integrated circuit structure comprising: a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction; a first isolation structure over a first end of the fin, wherein a portion of the first isolation structure is located over a top portion and a first portion of a sidewall of the fin, and wherein a top surface of the first isolation structure is located above the top portion of the fin; a gate structure comprising a gate electrode over a top portion of the fin and laterally adjacent to a sidewall of a region of the fin, wherein the gate structure is spaced apart from a first isolation structure along the direction; as well as a second isolation structure over a second end of the fin, the second end opposite the first end, wherein a portion of the second isolation structure is located over a top portion and a second portion of a sidewall of the fin, spacing the second isolation structure from the gate structure along the direction, wherein a top surface of the second isolation structure is located over the top portion of the fin, and wherein both the first isolation structure and the second isolation structure include a first dielectric material laterally surrounding a recessed second dielectric material different from the first dielectric material, the recessed second dielectric material laterally surrounding at least a portion of a third dielectric material different from the first and second dielectric materials.

2. The integrated circuit structure according to claim 1, wherein: Both the first isolation structure and the second isolation structure further include a fourth dielectric material laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material.

3. The integrated circuit structure according to claim 2, wherein: A fourth dielectric material is further on the upper surface of the second dielectric material.

4. The integrated circuit structure according to claim 2, wherein: The fourth dielectric material has an approximately vertical central seam.

5. The integrated circuit structure according to claim 2, wherein: The fourth dielectric material has no seams.

6. The integrated circuit structure according to claim 1, wherein: The third dielectric material has an upper surface that is coplanar with an upper surface of the second dielectric material.

7. The integrated circuit structure according to claim 1, wherein: The third dielectric material has an upper surface lower than an upper surface of the second dielectric material.

8. The integrated circuit structure of claim 1, wherein the third dielectric material has an upper surface that is higher than an upper surface of the second dielectric material, and wherein the third dielectric material is further above the upper surface of the second dielectric material.

9. The integrated circuit structure according to claim 1, wherein: The first and second isolation structures induce compressive stress on the fin.

10. The integrated circuit structure according to claim 9, wherein: The gate electrode is a P-type gate electrode.

11. The integrated circuit structure according to claim 1, wherein: The first isolation structure has a width along the direction, the gate structure has the width along the direction, and the second isolation structure has the width along the direction.

12. The integrated circuit structure according to claim 11, wherein: A center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the direction, and a center of the second isolation structure is spaced apart from a center of the gate structure by the pitch along the direction.

13. The integrated circuit structure according to claim 1, wherein: The first and second isolation structures are both in corresponding trenches in the interlayer dielectric layer.

14. The integrated circuit structure according to claim 1, further comprising: a first source or drain region between the gate structure and the first isolation structure; as well as A second source or drain region is between the gate structure and the second isolation structure.

15. The integrated circuit structure according to claim 14, wherein: The first and second source or drain regions are embedded source or drain regions including silicon and germanium.

16. The integrated circuit structure according to claim 1, wherein: The gate structure further includes a high-k dielectric layer between the gate electrode and the fin and along sidewalls of the gate electrode.

17. A method of manufacturing an integrated circuit structure, the method comprising: forming a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction; a first isolation structure formed over a first end of the fin, wherein a portion of the first isolation structure is located over a top portion and a first portion of a sidewall of the fin, and wherein a top surface of the first isolation structure is located above the top portion of the fin; forming a gate structure including a gate electrode over a top portion of the fin and laterally adjacent to a sidewall of a region of the fin, wherein the gate structure is spaced apart from a first isolation structure along the direction; as well as a second isolation structure formed over a second end of the fin, the second end opposite the first end, wherein a portion of the second isolation structure is located over a top portion and a second portion of a sidewall of the fin, spacing the second isolation structure from the gate structure along the direction, wherein a top surface of the second isolation structure is located above the top portion of the fin, and wherein both the first isolation structure and the second isolation structure include a first dielectric material laterally surrounding a recessed second dielectric material different from the first dielectric material, the recessed second dielectric material laterally surrounding at least a portion of a third dielectric material different from the first and second dielectric materials.

18. The method according to claim 17, wherein Both the first isolation structure and the second isolation structure further include a fourth dielectric material laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material.

19. The method according to claim 18, wherein A fourth dielectric material is further on the upper surface of the second dielectric material.

20. The method according to claim 17, wherein The first isolation structure has a width along the direction, the gate structure has the width along the direction, and the second isolation structure has the width along the direction.

21. An apparatus for manufacturing an integrated circuit structure, the apparatus comprising: means for forming a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction; means for forming a first isolation structure over a first end of the fin, wherein a portion of the first isolation structure is located over a top portion and a first portion of a sidewall of the fin, and wherein a top surface of the first isolation structure is located above the top portion of the fin; means for forming a gate structure comprising a gate electrode over a top portion of the fin and laterally adjacent to a sidewall of a region of the fin, wherein the gate structure is spaced apart from a first isolation structure along the direction; as well as means for forming a second isolation structure over a second end of the fin, the second end being opposite the first end, wherein a portion of the second isolation structure is located over a top portion and a second portion of a sidewall of the fin, spacing the second isolation structure from the gate structure along the direction, wherein a top surface of the second isolation structure is located over the top portion of the fin, and wherein both the first isolation structure and the second isolation structure comprise a first dielectric material laterally surrounding a recessed second dielectric material different from the first dielectric material, the recessed second dielectric material laterally surrounding at least a portion of a third dielectric material different from the first and second dielectric materials.

22. The device according to claim 21, wherein Both the first isolation structure and the second isolation structure further include a fourth dielectric material laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on an upper surface of the third dielectric material.

23. The device according to claim 22, wherein A fourth dielectric material is further on the upper surface of the second dielectric material.

24. The apparatus according to claim 21, wherein The first isolation structure has a width along the direction, the gate structure has the width along the direction, and the second isolation structure has the width along the direction.

25. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 17 to 20.

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