Semiconductor device with integrated PN diode temperature sensor

Abstract

A semiconductor device includes: a semiconductor substrate having a first region with one or more transistor cells and a second region without transistor cells; a first dielectric material on the first region and the second region of the semiconductor substrate; a second dielectric material on the first dielectric material; a pn diode formed in the first dielectric material on the second region of the semiconductor substrate; a plurality of first contacts extending from the pn diode and extending into a p-type region of the pn diode such that the p-type region abuts a sidewall of each first contact; and a plurality of second contacts extending from the pn diode and extending into an n-type region of the pn diode such that the n-type region abuts a sidewall of each second contact.

Description

Background Art

[0001] Micropatterned trench (MPT) cell design technology provides sub-micron mesas and is used to implement insulated gate bipolar transistors (IGBTs) and other types of power transistors to achieve high voltage (e.g., 1200V) devices with reduced overall power losses. Temperature sensors are often integrated in power transistor dies (chips) to provide accurate temperature information. An integrated temperature sensor for MPT power transistor technology is needed. Summary of the invention

[0002] According to an embodiment of a semiconductor device, the semiconductor device includes: a semiconductor substrate having a first region with one or more transistor cells and a second region without transistor cells; a first dielectric material above the first region and the second region of the semiconductor substrate; a second dielectric material above the first dielectric material; a pn diode formed in the first dielectric material above the second region of the semiconductor substrate; a plurality of first contacts extending from the pn diode and extending into a p-type region of the pn diode so that the p-type region abuts a side wall of each first contact; and a plurality of second contacts extending from the pn diode and extending into an n-type region of the pn diode so that the n-type region abuts a side wall of each second contact.

[0003] According to an embodiment of a method for manufacturing a semiconductor device, the method includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region without transistor cells; forming a first dielectric material above the first region and the second region of the semiconductor substrate; forming a second dielectric material above the first dielectric material; forming a pn diode in the first dielectric material above the second region of the semiconductor substrate; forming a plurality of first contacts extending from the pn diode and extending into a p-type region of the pn diode so that the p-type region abuts a side wall of each first contact; and forming a plurality of second contacts extending from the pn diode and extending into an n-type region of the pn diode so that the n-type region abuts a side wall of each second contact.

[0004] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and are detailed in the following description.

[0006] Figure 1A A partial cross-sectional view of an embodiment of an integrated pn diode temperature sensor is illustrated.

[0007] Figure 1B A partial top view of an integrated pn diode temperature sensor is shown.

[0008] Figures 2A to 2E An embodiment of fabricating a semiconductor device including an integrated pn diode temperature sensor is illustrated.

[0009] Figures 3A to 3H Another embodiment of fabricating an integrated pn diode temperature sensor is shown.

[0010] Figure 4 A partial cross-sectional view of an alternative embodiment is shown in which a mask is formed over the pn diode structure after forming the diode contact recesses and before the common body contact implant process.

[0011] Figure 5 A partial cross-sectional view of an alternative embodiment is shown in which the cathode region of the pn diode is formed after forming a second dielectric material over the diode structure.

[0012] Figure 6 A hybrid circuit schematic illustrating an embodiment of a temperature sensor circuit implemented using four of the integrated pn diodes.

[0013] Figures 7A to 7C Respective top views of different placement embodiments for an integrated pn diode temperature sensor in a semiconductor die are illustrated. DETAILED DESCRIPTION

[0014] Embodiments described herein provide a semiconductor device with an integrated pn diode temperature sensor and a corresponding method of manufacturing. The pn diode temperature sensor is formed inside a standard dielectric material provided as part of the device, which can be implemented as a polycrystalline or amorphous silicon pn diode. In the case of MPT technology, the resulting IGBT or power MOSFET obtains temperature sensing capabilities without any changes to the basic technology or performance.

[0015] Figure 1A A cross-sectional view of an embodiment of an integrated pn diode temperature sensor formed over a region of a semiconductor substrate that is free of transistor cells is shown. An isolation dielectric 100, such as LOCOS (local oxidation of silicon), covers the region of the substrate that is free of transistor cells to provide isolation from adjacent regions that contain one or more transistor cells, such as IGBT or power MOSFET cells. The isolation dielectric 100 is over the region of the substrate that is free of transistor cells but not over the region that contains one or more transistor cells, wherein standard dielectric material is separated from the semiconductor substrate by the isolation dielectric 100. For ease of illustration, no isolation dielectric 100 is shown over the region of the substrate that is free of transistor cells but not over the region that contains one or more transistor cells. Figure 1A The semiconductor substrate is shown in FIG.

[0016] Figure 1B The picture is Figure 1A A partial top-down plan view of an integrated pn diode temperature sensor is shown in FIG.

[0017] A pn diode 101 is formed in a first interlayer dielectric material 102 above a region of a semiconductor substrate without transistor cells. The first interlayer dielectric material 102 includes a lower layer 104 and an upper layer 106 above the lower layer 104. The upper layer 106 directly contacts the lower layer 104 above a region of the semiconductor substrate containing one or more transistor cells. The pn diode 101 is formed between the lower layer 104 and the upper layer 106 of the first interlayer dielectric material 102 above the region of the semiconductor substrate without transistor cells. In one embodiment, the lower layer 104 of the first interlayer dielectric material 102 is thicker than the upper layer 106. For example, in the case of USG (undoped silicate glass) as the first interlayer dielectric material 102, the lower layer 104 may have a thickness of about 50 to 60 nm and the upper layer 106 may have a thickness of about 90 to 100 nm. Other layer thicknesses are possible, and the upper layer 106 may be thicker than the lower layer 104 as an alternative.

[0018] A second interlayer dielectric material 108 is formed above the first interlayer dielectric material 102, above both the region of the semiconductor substrate containing one or more transistor cells and the region of the semiconductor substrate without transistor cells. In one embodiment, the first interlayer dielectric material 102 includes USG, the second interlayer dielectric material 108 includes borophosphosilicate glass (BPSG), and the pn diode 101 includes polycrystalline or amorphous silicon. In the case of polycrystalline or amorphous silicon, the pn diode 101 can have a thickness between 200nm and 950nm. Other pn diode thicknesses are possible.

[0019] A plurality of first contacts 110 extend from the pn diode 101 and into a p-type region 112 of the pn diode 101 such that the p-type region 112 abuts a sidewall 114 of each first contact 110. A plurality of second contacts 116 extend from the pn diode 101 and into an n-type region 118 of the pn diode 101 such that the n-type region 118 abuts a sidewall 120 of each second contact 116. In one embodiment, the plurality of first contacts 110 extend through the p-type region 112 of the pn diode 101 and into a lower layer 104 of a first interlayer dielectric material 102 disposed between the pn diode 101 and an underlying semiconductor substrate. Likewise, the plurality of second contacts 116 extend through the n-type region 118 of the pn diode 101 and into the lower layer 104 of the first interlayer dielectric material 102. As in Figure 1AAs shown in the figure, the first interlayer dielectric material 102 and the second interlayer dielectric material 108 can be etched back around the perimeter of each first contact 110 and each second contact 116 so that the pn diode 101 is not covered by the first interlayer dielectric material 102 or the second interlayer dielectric material 108 in each area where the first interlayer dielectric material 102 and the second interlayer dielectric material 108 are etched back. Figure 1A The second ILD material 108 is shown having more etch back than the first ILD material 102 , which may be attributed to the difference in dielectric material type and associated etch rates (eg, BPSG for the second ILD material 108 and USG for the first ILD material 102 ).

[0020] A plurality of first contacts 110 may be formed in a row 122 of first contacts 110 extending substantially parallel to one another. Similarly, a plurality of second contacts 116 may be formed in a row 124 of second contacts 116 extending substantially parallel to one another. Figure 1B As shown in FIG. 1 , the first contacts 110 may be arranged in a first checkerboard pattern 126 and the second contacts 116 may be arranged in a second checkerboard pattern 128 .

[0021] In some embodiments, and as described in more detail later herein, the first contact 110 and the second contact 116 are formed as part of a common contact formation process. During the common contact formation process, a plurality of third contacts (in the region of the semiconductor substrate having one or more transistor cells) are formed simultaneously with the first contact 110 and the second contact 116. Figure 1A and Figure 1B1). The common contact formation process is photolithographically focused on the region of the semiconductor substrate having one or more transistor cells, rather than on the pn diode 101. According to these embodiments, the plurality of first contacts 110 are spaced apart from a first edge 130 of the pn diode 101 by a minimum distance (d_min), for example, of at least 50 μm, along which a row 122 of the first contacts 110 runs in parallel. Similarly, the plurality of second contacts 116 are spaced apart from a second edge 132 of the pn diode 101 by the same or different minimum distance, along which a row 124 of the second contacts 116 runs in parallel. With such a minimum spacing, contacts 110, 116 to the p-type and n-type regions 112, 118 of the pn diode 101 are reliably formed, even if the pn diode 101 is formed at a different level than the focus of the photolithographic process used to form contacts to the region of the semiconductor substrate having one or more transistor cells. In this way, the contacts 110 , 116 to the pn diode 101 and the contacts to the transistor cell(s) may be formed simultaneously using a common contact formation process.

[0022] Figures 2A to 2E Illustration manufacturing included in Figure 1A and 1B A partial cross-sectional view of an embodiment of a method for integrating a semiconductor device with a pn diode temperature sensor is shown in FIG.

[0023] Figure 2A A semiconductor substrate 200 is shown having a cell region in which one or more transistor cells are to be formed, a diode adjacent to the cell region. The substrate 200 may include any type of semiconductor material, such as a single element semiconductor (e.g., Si, Ge, etc.), silicon on insulator, a binary semiconductor (e.g., SiC, GaN, GaAs, etc.), a ternary semiconductor, etc., with or without epitaxial layer(s). Oxide and nitride are deposited on the top surface of the semiconductor substrate 200. The semiconductor substrate 200 is etched through the openings formed in the oxide / nitride material.

[0024] Field oxide regions 202 (such as LOCOS) provide isolation between the cell region and the diode region of the substrate 200. A trench 204 is formed in the cell region of the semiconductor substrate 200. The trench 204 in the cell region may include a gate trench 206 and a field plate trench 208, and define a submicron semiconductor mesa 210. The trench 204 is filled with an electrode material 212 (such as doped polysilicon). The electrode material 212 in each trench 204 is separated from the surrounding semiconductor material by a dielectric material 214 such as a standard gate oxide. The dielectric material 214 may be thicker than in the gate trench 206 and / or include a different material in the field plate trench 208 than in the gate trench 206.

[0025] Figure 2B Shown in Figure 1A and 1B After the lower and upper layers 104, 106 of the first interlayer dielectric material 102 shown in FIG. 1 are formed on the semiconductor substrate 200, and after Figure 1A and 1B The integrated pn diode 101 shown in FIG. 1 is formed after the semiconductor substrate 200 is formed between lower and upper layers 104, 106 of a first interlayer dielectric material 102 above a diode region of the semiconductor substrate 200 without transistor cells. Various embodiments for forming the pn diode 101 are described in more detail later herein.

[0026] Figure 2C The semiconductor substrate 200 is shown after body and source / emitter regions 216, 218 are formed in a cell region of the substrate 200. Any standard implantation process may be used to form the oppositely doped body and source / emitter regions 216, 218 (p-body, n-source / emitter; or n-body, p-source / emitter).

[0027] Figure 2D Shown in Figure 1A and 1B 1 and 2 , after the second interlayer dielectric material 108 is formed on the upper layer 106 of the first interlayer dielectric material 102, and after the common contact groove forming process. During the common contact groove forming process, a plurality of contact grooves 220 extending into the cell region of the semiconductor substrate 200 are formed simultaneously with a plurality of first contact grooves 222 extending into the p-type region 112 of the integrated pn diode 101 and a plurality of second contact grooves 224 extending into the n-type region 118 of the integrated pn diode 101. The common contact forming process is photolithographically focused on the cell region of the semiconductor substrate 200, rather than on the pn diode 101.

[0028] To ensure proper contact formation to the pn diode 101, the plurality of first contact recesses 222 are spaced apart by a minimum distance, such as at least 50 μm, from a first edge 226 of the pn diode 101 along which the first contact recesses 222 extend in parallel. Likewise, the plurality of second contact recesses 224 are spaced apart by the same or different minimum distances from a second edge 228 of the pn diode 101 along which the second contact recesses 224 extend in parallel. With such minimum spacing, the contact recesses 222, 224 extending into the pn diode 101 are reliably formed even if the pn diode 101 is formed at a different level from the focus of a photolithography process used to form the contact recess 220 to the cell region of the semiconductor substrate 200. In this way, the contact recesses 222, 224 to the pn diode 101 and the contact recess 220 to the cell region of the substrate 200 can be simultaneously formed using a common contact recess formation process.

[0029] Some of the contact grooves 220 in the cell region extend into the electrode 212 disposed in the field plate trench 208, while other of the contact grooves 220 in the cell region extend into the body region through the adjacent source / emitter region 218 to form corresponding gate and source / body contact grooves in the cell region. Figure 2D The contact groove to the electrode 212 disposed in the gate trench 206 in the cell region is not visible.

[0030] according to Figure 2D , the thickness (TD) of the diode 101 is less than the contact recess etch depth. As such, the common contact trench etch extends through the entire pn diode 101 and stops at or enters the lower layer 104 of the first dielectric material 102 disposed between the pn diode 101 and the semiconductor substrate 200. Thus, the plurality of first diode contact trenches 222 extend through the p-type region 112 of the pn diode 101 and into the lower layer 104 of the first dielectric material 102. Similarly, the plurality of second diode contact trenches 224 extend through the n-type region 118 of the pn diode 101 and into the lower layer 104 of the first dielectric material 102.

[0031] Figure 2EThe semiconductor substrate 200 is shown after performing a p-type implant to provide an ohmic contact to the body region, followed by depositing a conductive material 230 (such as a metal) on the semiconductor substrate 200 to fill the various contact recesses 220, 222, 224 and patterning them to form corresponding electrodes of the semiconductor device. For example, the electrodes may include drain / collector (D), source / emitter (S) and gate (G) electrodes of one or more power transistors (such as IGBTs or power MOSFETs) formed in the cell region of the semiconductor substrate 200, and anode (A) and cathode (K) electrodes of an integrated pn diode 101 formed on the diode region of the substrate 200.

[0032] The p-type implant described above and performed prior to the deposition of the conductive material 230 filling the various contact recesses 220, 222, 224 increases the doping concentration of the body region in the region where the contact recesses 220 enter the body region. The resulting highly doped region (also referred to as the body contact region) provides a good ohmic contact between the body region and the conductive material 230 filling the contact recesses 220 extending into the body region. In one embodiment, after implanting the p-type body contact dopant and before filling the contact recesses 220, 222, 224 with the conductive material 230, the second dielectric material 108 and the upper layer 106 of the first dielectric material 102 are etched back around the perimeter of each diode contact recess 222, 224 so that the pn diode 101 is not covered by the second dielectric material 108 or the upper layer 106 of the first dielectric material 102 in each region where the second dielectric material 108 and the upper layer 106 of the first dielectric material 102 are etched back.

[0033] Figure 2D The diode contact recess arrangement shown in FIG. 1 , in which the diode contact recesses 222, 224 extend through the pn diode 101 and into the lower layer 104 of the first dielectric material 102, can be beneficial in limiting the amount of p-type dopant that enters the n-type region 118 of the pn diode 101 during the body contact implant process. The p-type dopant species should primarily pass through the contact recesses 224 in the n-type region 118 of the pn diode 101 and enter the lower layer 104 of the first dielectric material 102 without penetrating into the n-type diode region 118. For thicker pn diodes, in which the diode contact recesses 222, 224 do not extend completely through the diode 101 and into the lower layer 104 of the first dielectric material 102, the contact recesses 224 that penetrate the n-type region 118 of the diode 101 can be masked prior to the p-type body contact implant process to prevent the p-type dopant from entering the n-type region 118 of the diode 101.

[0034] Figures 3A to 3H Picture made in Figure 1A and1B A partial cross-sectional view of another embodiment of a method for integrating a pn diode temperature sensor is shown in FIG. Figures 3A to 3H The underlying semiconductor substrate is shown in FIG.

[0035] Figure 3A A blanket layer of polycrystalline or amorphous silicon 300 is shown formed on the lower layer 104 of the first dielectric material 102 and implanted with a p-type dopant species 302 .

[0036] Figure 3B A cathode implant region 304 of a pn diode is shown formed by an n-type dopant species 306 implanted through an opening in a mask 308 .

[0037] Figure 3C An anode implant region 310 of a pn diode is shown formed by a p-type dopant species 312 implanted through an opening in a mask 314. Figure 3C 3. The cathode and anode implant regions 304, 310 are shown separated by a distance d_s of, for example, about 1 μm. However, the p-type anode implant 312 may overlap into the cathode implant region 304 so that no gap exists between the anode and cathode implant regions 304, 310.

[0038] Figure 3D The structure is shown after patterning a layer 300 of polycrystalline or amorphous silicon into a pn diode 314 disposed just above an area of ​​the semiconductor substrate without transistor cells, and after forming an upper layer 106 of a first dielectric material 102 over the pn diode 314 and over a lower layer 104 of the first dielectric material 102 outside the diode area.

[0039] Figure 3E The structure is shown after forming the second dielectric material 108 over the first dielectric material 102 , and after diffusing and activating the cathode and anode implants to form respective anode and cathode regions 316 , 318 of the pn diode 314 .

[0040] Figure 3F The structure is shown after forming an opening 320 in the second dielectric material 108 and in the upper layer 106 of the first dielectric material 102 .

[0041] Figure 3GThe structure is shown after contact recesses 322, 324 are etched through the upper layer 106 of the first dielectric material 102 and the opening 320 in the second dielectric material 108 and extend into the p-type and n-type regions 316, 318 of the pn diode 314. According to this embodiment, the thickness of the polycrystalline or amorphous silicon 300 is greater than the contact recess etch depth. As such, the common contact recess etch does not enter the lower layer 104 of the first dielectric material 102 disposed between the pn diode 314 and the underlying semiconductor substrate. Therefore, each anode contact recess 322 terminates in the p-type region 316 of the pn diode 314 before reaching the lower layer 104 of the first dielectric material 102. Similarly, each cathode contact recess 324 terminates in the n-type region 318 of the pn diode 314 before reaching the lower layer 104 of the first dielectric material 102.

[0042] Figure 3H Shown above combined with cross-substrate execution Figure 2D and 2E The common body contact implantation process described herein is to implant a transistor in the body region of the semiconductor substrate (in the Figure 3H Because the diode contact recesses 322, 324 do not extend all the way through the polycrystalline or amorphous silicon 300, according to this embodiment, both the anode region 316 and the cathode region 318 of the pn diode 314 include the P+ contact region 326. The contact recesses 322, 324 are then filled with a conductive material such as a metal, for example as previously described herein in conjunction with Figure 2E As described.

[0043] Figure 4 A partial cross-sectional view of an alternative embodiment is shown in which a mask 400 is formed on the pn diode structure after forming the diode contact recesses 322, 324 and before the common body contact implant process. According to this embodiment, the mask 400 blocks the p-type body contact implant from entering the cathode region 318 of the pn diode. The mask 400 is removed after the common body contact implant process.

[0044] Figure 5 A partial cross-sectional view of an alternative embodiment is shown in which the cathode implant region 304 of the pn diode is formed after the second dielectric material 108 is formed over the diode structure. According to this embodiment, an opening is formed in the second dielectric material 102 and in the upper layer 106 of the first dielectric material 102 to expose the cathode implant region 304 of the diode. An n-type dopant species 500 is then implanted through the openings in the second dielectric material 108 and the upper layer 106 of the first dielectric material 102 and into the polycrystalline or amorphous silicon 300. The n-type dopant 500 is then diffused and activated to form the cathode region of the pn diode.

[0045] In addition to or as an alternative to the above embodiments, it is possible to use Figure 3A The n-type dopant species in the blanket implant polycrystalline or amorphous silicon layer 300 replaces the p-type dopant species. The diode structure can then be masked and implanted with the p-type dopant species to define the anode region of the diode.

[0046] In addition to or as an alternative to the above embodiments, the Figure 3C 322. Alternatively, the anode region of the diode may be defined by a common p-type body contact implantation process described herein, whereby p-type dopant species enter the polycrystalline or amorphous silicon 300 through a previously formed anode contact recess 322. During the common p-type body contact implantation process, the anode region is formed by subsequent diffusion / activation of the p-type dopant species implanted through the anode contact recess 322.

[0047] In addition or as an alternative to the above described embodiments, a mask may be applied to the anode contact recess 322 so that the common p-type body contact implant is partially or even completely blocked in the anode region 316 of the pn diode.

[0048] In addition or as an alternative to the above-described embodiments, implant activation for the cathode and anode implant regions 304, 310 of the pn diode temperature sensor may be achieved using a base technology source diffusion drive that occurs after the pn diode temperature sensor fabrication steps.

[0049] Figure 6 A hybrid circuit schematic of a temperature sensor circuit 600 implemented with four of the integrated pn diodes 101 described herein is illustrated. Two of the pn diodes 101 are electrically connected in series in a 'PN' configuration, and the other two pn diodes 101 are electrically connected in series in a 'NP' configuration. The two chains of serially connected diodes are connected at one end to a first terminal 602 of a semiconductor device, and at the other end to a second terminal 604 of the device. An optional anti-parallel ESD (electrostatic discharge) blocking diode 606 is connected between the terminals 602, 604 of the temperature sensor circuit 600.

[0050] The temperature sensor circuit 600 may be located at Fig. 7A The center of the unit area 702 of the semiconductor die (chip) 700 shown in FIG. Figure 7B On the periphery / edge of the cell area 702 of the die 700 shown in FIG. Figure 7C7. The edge termination region 704 is an area of ​​the die 700 that has no fully-functional transistor cells and provides a transition area between the physical edge of the die 700 and the cell area. Other diode placement options are also contemplated.

[0051] Spatially relative terms such as "below," "under," "below," "above," "on," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the figures. In addition, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0052] As used herein, the terms "having," "containing," "including," "comprising," and the like are introductory terms indicating the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0053] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A semiconductor device, comprising: a semiconductor substrate having a first region with one or more transistor cells and a second region without transistor cells; a first dielectric material overlying the first and second regions of the semiconductor substrate; a second dielectric material overlying the first dielectric material; a pn diode formed in the first dielectric material overlying the second region of the semiconductor substrate; a plurality of first contacts extending from over the pn diode and into a p-type region of the pn diode such that the p-type region abuts a sidewall of each first contact; as well as a plurality of second contacts extending from over the pn diode and into an n-type region of the pn diode such that the n-type region abuts a sidewall of each second contact, Wherein the plurality of first contacts are spaced apart from a first edge of the pn diode by at least 50 μm, and the plurality of first contacts extend in parallel along the first edge, and wherein the plurality of second contacts are spaced apart from a second edge of the pn diode by at least 50 μm, and the plurality of second contacts extend in parallel along the second edge, so that contacts to the pn diode and contacts to the transistor unit can be simultaneously formed using a common contact formation process.

2. The semiconductor device of claim 1 , wherein the first dielectric material comprises a lower layer and an upper layer above the lower layer, the plurality of first contacts extend through a p-type region of the pn diode and extend into the lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein the plurality of second contacts extend through an n-type region of the pn diode and extend into the lower layer of the first dielectric material.

3. The semiconductor device of claim 1 , wherein the first dielectric material comprises a lower layer and an upper layer above the lower layer, the plurality of first contacts terminate in a p-type region of the pn diode before reaching the lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein the plurality of second contacts terminate in an n-type region of the pn diode before reaching the lower layer of the first dielectric material. 4 . The semiconductor device of claim 1 , wherein the first dielectric material comprises a first layer and a second layer over the first layer, and wherein a pn diode is formed between the second layer and the first layer over the second region of the semiconductor substrate. 5 . The semiconductor device of claim 4 , wherein the first layer of the first dielectric material is thicker than the second layer of the first dielectric material. 6 . The semiconductor device of claim 1 , wherein the plurality of first contacts comprises rows of first contacts extending substantially parallel to one another, and wherein the plurality of second contacts comprises rows of second contacts extending substantially parallel to one another. 7 . The semiconductor device of claim 1 , wherein the plurality of first contacts are arranged in a first checkerboard pattern, and wherein the plurality of second contacts are arranged in a second checkerboard pattern. 8 . The semiconductor device of claim 1 , further comprising a third dielectric material on the second region of the semiconductor substrate but not on the first region, wherein the first dielectric material is separated from the semiconductor substrate by the third dielectric material.

9. The semiconductor device of claim 1, wherein the pn diode comprises polycrystalline or amorphous silicon having a thickness between 300 nm and 950 nm.

10. The semiconductor device of claim 1, wherein the first dielectric material comprises undoped silicate glass (USG), wherein the second dielectric material comprises borophosphosilicate glass (BPSG), and wherein the pn diode comprises polycrystalline or amorphous silicon.

11. The semiconductor device of claim 1 , wherein the first dielectric material and the second dielectric material are etched back around a perimeter of each first contact and each second contact so that the pn diode is not covered by the first dielectric material or the second dielectric material in each region where the first dielectric material and the second dielectric material are etched back.

12. A method for manufacturing a semiconductor device, the method comprising: forming one or more transistor cells in a first region of a semiconductor substrate having a second region without transistor cells; forming a first dielectric material over the first and second regions of the semiconductor substrate; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region of the semiconductor substrate; etching a first contact recess into a p-type region of a pn diode, etching a second contact recess into an n-type region of the pn diode, and etching a third contact recess into a first region of a semiconductor substrate, simultaneously etching the first contact recess, the second contact recess, and the third contact recess using a common contact forming process; photolithographically focusing a common contact forming process on the first region of the semiconductor substrate and not on the pn diode; The first contact groove is spaced at least 50 μm apart from a first edge of the pn diode, and the first contact groove extends parallel to the first edge; The second contact groove is spaced at least 50 μm apart from a second edge of the pn diode, and the second contact groove extends parallel to the second edge; and The first contact recess, the second contact recess, and the third contact recess are filled with a conductive material.

13. The method of claim 12, wherein the first dielectric material includes a lower layer and an upper layer above the lower layer, etching the first contact groove includes etching the first contact groove through the p-type region of the pn diode and into the lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein etching the second contact groove includes etching the second contact groove through the n-type region of the pn diode and into the lower layer of the first dielectric material.

14. The method of claim 12, wherein the first dielectric material comprises a lower layer and an upper layer above the lower layer, etching the first contact groove comprises etching the first contact groove so that the first contact groove terminates in a p-type region of the pn diode before reaching the lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein etching the second contact groove comprises etching the second contact groove so that the second contact groove terminates in an n-type region of the pn diode before reaching the lower layer of the first dielectric material.

15. The method of claim 12, wherein the first dielectric material includes a lower layer and an upper layer above the lower layer, the first contact groove extends through a second dielectric material, through the upper layer of the first dielectric material covering the pn diode and into a p-type region of the pn diode, wherein a second contact groove extends through the second dielectric material, through the upper layer of the first dielectric material, and into an n-type region of the pn diode, and wherein a third contact groove extends through the second dielectric material, through the first dielectric material and into the first region of the semiconductor substrate.

16. The method according to claim 12, further comprising: Before filling the first contact groove, the second contact groove, and the third contact groove with a conductive material, a p-type dopant is implanted into the first contact groove, the second contact groove, and the third contact groove.

17. The method according to claim 16, further comprising: After implanting the p-type dopant and before filling the first contact groove, the second contact groove and the third contact groove with a conductive material, the first dielectric material and the second dielectric material are etched back around the perimeter of each first contact groove and each second contact groove so that the pn diode is not covered by the first dielectric material or the second dielectric material in each area, wherein the first dielectric material and the second dielectric material are etched back.

18. The method of claim 12, wherein forming the first dielectric material and forming the pn diode comprises: forming a first layer of a first dielectric material over the first and second regions of the semiconductor substrate; forming polysilicon on the first layer of the first dielectric material over the second region of the semiconductor substrate but not over the first region; forming a second layer of a first dielectric material on the first layer over the first region of the semiconductor substrate and on the polysilicon over the second region of the semiconductor substrate; and A pn diode is formed in the polysilicon between the first layer and the second layer.

19. The method of claim 12, wherein forming the first dielectric material and forming the pn diode comprises: forming a first layer of a first dielectric material over the first and second regions of the semiconductor substrate; forming amorphous silicon on the first layer of the first dielectric material over the second region of the semiconductor substrate but not over the first region; forming a second layer of a first dielectric material on the first layer over the first region of the semiconductor substrate and on the amorphous silicon over the second region of the semiconductor substrate, and A pn diode is formed in the amorphous silicon between the first layer and the second layer.

20. The method of claim 12, wherein the first contact grooves are arranged in rows extending substantially parallel to each other, and wherein the second contact grooves are arranged in rows extending substantially parallel to each other.

21. The method of claim 12, wherein the first contact recesses are arranged in a first checkerboard pattern, and wherein the second contact recesses are arranged in a second checkerboard pattern.

22. The method of claim 12, further comprising: A third dielectric material is formed over the second region but not the first region of the semiconductor substrate, wherein the first dielectric material is separated from the semiconductor substrate by the third dielectric material.

23. The method of claim 12, wherein the pn diode comprises polycrystalline or amorphous silicon having a thickness between 300 nm and 950 nm.

24. The method of claim 12, wherein the first dielectric material comprises undoped silicate glass (USG), wherein the second dielectric material comprises borophosphosilicate glass (BPSG), and wherein the pn diode comprises polycrystalline or amorphous silicon.

25. The method of claim 12, wherein a first group of third contact recesses extend into an electrode disposed in a field plate trench formed in a first region of the semiconductor substrate, and wherein a second group of third contact recesses extend into a body region of one or more transistor cells in the first region of the semiconductor substrate.

26. The method of claim 12, further comprising: The conductive material is patterned to form electrodes for one or more transistor cells formed in the first region of the semiconductor substrate and to form anode and cathode electrodes for a pn diode formed above the second region of the semiconductor substrate.

27. The method of claim 12, wherein a p-type region of a pn diode abuts a sidewall of each first contact, wherein an n-type region of a pn diode abuts a sidewall of each second contact, and wherein each third contact extends into a doped region or electrode of one or more transistor cells in the first region of the semiconductor substrate.

28. A method for manufacturing a semiconductor device, the method comprising: forming one or more transistor cells in a semiconductor substrate having a first region with the one or more transistor cells and a second region without transistor cells; forming a pn diode in the dielectric material overlying the second region of the semiconductor substrate; etching a first contact recess into a p-type region of a pn diode, etching a second contact recess into an n-type region of the pn diode, and etching a third contact recess into a first region of a semiconductor substrate, simultaneously etching the first contact recess, the second contact recess, and the third contact recess using a common contact forming process; photolithographically focusing a common contact formation process on a first region of the semiconductor substrate and not on the pn diode; The first contact groove is spaced at least 50 μm apart from a first edge of the pn diode, and the first contact groove extends parallel to the first edge; The second contact groove is spaced at least 50 μm apart from a second edge of the pn diode, and the second contact groove extends parallel to the second edge; and The first contact recess, the second contact recess, and the third contact recess are filled with a conductive material.

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