Driving circuit, semiconductor device including the driving circuit, and control method of the driving circuit

Abstract

Embodiments of the present disclosure relate to a drive circuit, a semiconductor device including the drive circuit, and a control method of the drive circuit. According to one embodiment, a word line driver includes: a first inverter driven by a first power supply voltage and inverting and outputting a decoding signal; a second inverter driven by a second power supply voltage and inverting and outputting a decoding signal; a first PMOS transistor controlled to be turned on or off based on an output signal of the second inverter; a first NMOS transistor controlled to be turned on or off based on an output signal of the first inverter; and a second PMOS transistor disposed between a power supply voltage terminal provided with the second power supply voltage and a gate of the first PMOS transistor, and temporarily turned on in synchronization with a fall of the decoding signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2017-231556 filed on December 1, 2017 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a drive circuit, a semiconductor device including the drive circuit, and a control method for the drive circuit, and to a drive circuit, a semiconductor device including the drive circuit, and a control method for the drive circuit, which are suitable for improving reliability without increasing power consumption, for example. Background Art

[0004] Generally, a word line driver for driving a word line of a memory cell array is configured using a CMOS gate which excels in high-speed operation and low power consumption.

[0005] Here, in the case of driving a word line of a DRAM (dynamic random access memory), a nonvolatile memory, or the like, a word line driver needs to apply as high a voltage as possible to the word line in order to accurately read data stored in a memory cell. Therefore, in the case of driving a word line of a DRAM, a nonvolatile memory, or the like, the word line driver applies a high voltage to the word line by driving it with a power supply voltage higher than a rated voltage.

[0006] However, in a word line driver using a CMOS gate configuration, a high voltage is stably applied to a plurality of specific MOS transistors, and thus these MOS transistors may suffer from dielectric breakdown. Therefore, there is a problem that the reliability of a semiconductor device equipped with a word line driver is deteriorated.

[0007] A solution to this problem is disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713. The driver disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713 includes an output stage inverter, a first inverter driven by a high voltage VDH to output an inverted signal of an input signal Vin to a gate of a PMOS transistor provided in the output stage inverter, and a second inverter driven by a low voltage VDL (< high voltage VDH) to output an inverted signal of an input signal Vin to a gate of an NMOS transistor provided in the output stage inverter.

[0008] Here, since the second inverter is driven by the low voltage VDL, a high voltage is not stably applied to each MOS transistor configuring the second inverter. Therefore, the possibility of each MOS transistor configuring the second inverter suffering from dielectric breakdown is low. Therefore, the reliability of the driver disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713 can be improved because the number of MOS transistors suffering from dielectric breakdown can be reduced. Summary of the invention

[0009] However, in the driver disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713, the driving voltage (high voltage VDH) of the first inverter is different from the driving voltage (low voltage VDL) of the second inverter. Therefore, the time period required for the output signal of the first inverter to rise is different from the time period required for the output signal of the second inverter to rise. Therefore, the PMOS transistor and the NMOS transistor configuring the output stage inverter are unintentionally turned on at the same time. Therefore, there is a problem of increased through current, resulting in increased power consumption.

[0010] Other problems and novel features will become clear from the description of the specification and the accompanying drawings.

[0011] According to one embodiment, a driving circuit includes: a first inverter, which is driven by a first power supply voltage and inverts and outputs a first input signal; a second inverter, which is driven by a second power supply voltage higher than the first power supply voltage and inverts and outputs the first input signal; a first PMOS transistor, which controls a current flowing from a power supply voltage terminal supplied with the second power supply voltage to an external output terminal based on an output signal of the second inverter; a first NMOS transistor, which controls a current flowing from the external output terminal to a reference voltage terminal based on the output signal of the first inverter; and a second PMOS transistor, which is provided between the power supply voltage terminal supplied with the second power supply voltage and a gate of the first PMOS transistor and is temporarily turned on in synchronization with a fall of the first input signal.

[0012] According to another embodiment, a control method of a driving circuit includes the following steps: inverting and outputting a first input signal using a first inverter driven by a first power supply voltage; inverting and outputting the first input signal using a second inverter driven by a second power supply voltage higher than the first power supply voltage; controlling a current flowing in a first PMOS transistor arranged between a power supply voltage terminal provided with the second power supply voltage and an external output terminal based on an output signal of the second inverter; controlling a current flowing in a first NMOS transistor arranged between the external output terminal and a reference voltage terminal based on an output signal of the first inverter; and temporarily turning on a second PMOS transistor arranged between a power supply voltage terminal provided with the second power supply voltage and a gate of the first PMOS transistor in synchronization with a falling edge of the first input signal.

[0013] According to the above-described embodiments, a driving circuit capable of improving reliability without increasing power consumption, a semiconductor device including the driving circuit, and a control method of the driving circuit can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram for showing a configuration example of a semiconductor device according to a first embodiment;

[0015] Figure 2 It is used to show Figure 1 A circuit diagram showing a specific configuration example of a pulse signal generating unit shown;

[0016] Figure 3 It is used to show Figure 1 A timing diagram of the operation of the pulse signal generating unit shown;

[0017] Figure 4 It is used to show Figure 1 A circuit diagram showing a specific configuration example of a word line driver provided in the semiconductor device shown;

[0018] Figure 5 It is used to show Figure 4 A timing diagram of the operation of the word line driver is shown;

[0019] Figure 6 is a circuit diagram for showing a specific configuration example of a word line driver provided in the semiconductor device according to the second embodiment;

[0020] Figure 7 It is used to show Figure 6 A timing diagram of the operation of the word line driver is shown;

[0021] Figure 8 is a block diagram for showing a configuration example of a semiconductor device according to a third embodiment;

[0022] Fig. 9 It is used to show Figure 8 A diagram showing an example of a configuration of an address decoder provided in a semiconductor device shown in FIG.

[0023] Fig.10 is a circuit diagram for showing a specific configuration example of a word line driver provided in a semiconductor device according to a fourth embodiment;

[0024] Fig.11 is a diagram for illustrating a configuration example of a bias generating circuit;

[0025] Fig.12 is a block diagram for showing a configuration example of a semiconductor device according to an idea before producing the embodiment;

[0026] Fig.13 It is used to show Fig.12 A circuit diagram showing a specific configuration example of a word line driver provided in the semiconductor device shown;

[0027] Fig.14 It is used to show Fig.13 A timing diagram of the operation of the word line driver is shown;

[0028] Fig.15 is a circuit diagram for illustrating a specific configuration example of a word line driver provided in a semiconductor device according to an idea prior to producing the embodiment; and

[0029] Fig.16 It is used to show Fig.15 A timing diagram of the operation of the word line driver is shown. DETAILED DESCRIPTION

[0030] In order to make the explanation clear, the following description and drawings are appropriately omitted and simplified. In addition, each element shown in the drawings as a functional block for performing various processes can be configured as hardware using a CPU, a memory or other circuits, and can be implemented by a program loaded into the memory as software, etc. Therefore, it can be understood by those skilled in the art that these functional blocks can be implemented in various forms, such as hardware only, software only or a combination thereof, and are not limited to any of these. It should be noted that the same element is followed by the same symbol in each drawing, and its repeated description is appropriately omitted.

[0031] In addition, the above-mentioned program can be stored and provided to the computer using various types of non-transient computer-readable media. Non-transient computer-readable media include various types of tangible recording media. Examples of non-transient computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, or hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memories), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs), flash ROMs, or RAMs (random access memories)). In addition, the program can be provided to the computer via various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. The program can be provided to the computer by a transient computer-readable medium via a wired communication path (such as an electric wire or optical fiber, etc.) or a wireless communication path.

[0032] <Previous Considerations of the Inventor>

[0033] Before describing the details of the semiconductor device according to the first embodiment, a semiconductor device previously considered by the inventors will be described.

[0034] Fig.12 1 is a block diagram showing a configuration example of a semiconductor device 5 according to an idea before the embodiment is produced. The semiconductor device 5 is, for example, a DRAM, a nonvolatile memory, etc., and reads and outputs data stored in a memory cell at an address specified by an address signal in a memory cell configuring a memory cell array.

[0035] Specifically, the semiconductor device 5 includes at least an address decoder 51, n (n is a natural number) word line drivers 52 provided in association with the word lines WL1 to WLn in n rows, a memory cell array 53, and a sense amplifier 54. It should be noted that in the following description, the n word line drivers 52 are also referred to as word line drivers 52_1 to 52_n.

[0036] The address decoder 51 decodes the address signal AD1 to generate n decoded signals D1 to Dn. The word line drivers 52_1 to 52_n drive the decoded signals D1 to Dn and output them to the word lines WL1 to WLn, respectively. Hereinafter, the signals output to the word lines WL1 to WLn are referred to as word line signals W1 to Wn.

[0037] The memory cell array 53 is configured using a plurality of memory cells arranged in a matrix manner, for example, with n rows and m columns (n ​​and m are natural numbers). When reading data, a word line designated by the address signal AD1 among the n word lines WL1 to WLn is activated (i.e., indicates an H level). In addition, all other word lines are disabled (i.e., indicates an L level). Therefore, the data piece stored in the memory cell in the m column set in association with the activated word line is propagated through the m bit lines.

[0038] The sense amplifier 54 amplifies data propagating through a bit line designated (selected) by the address signal AD1 among data propagating through the m bit lines, and outputs the amplified data as read data.

[0039] (Specific Configuration Example of Word Line Driver 52)

[0040] Fig.13 is a circuit diagram for showing a specific configuration example of the word line driver 52 . Fig.13 The case where the word line driver 52 is the word line driver 52_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 52_2 to 52_n.

[0041] like Fig.13 As shown, the word line driver 52_1 is configured using a CMOS gate which is excellent in high-speed operation and low power consumption. Here, in order to accurately read data stored in a memory cell of a DRAM, a nonvolatile memory, etc., a higher voltage needs to be applied to the word line. Therefore, since the word line driver 52_1 is driven by a power supply voltage VDD2 higher than a power supply voltage VDD1 (VDD1 is a rated voltage), the word line driver 52_1 applies a high voltage to the word line WL1.

[0042] Specifically, the word line driver 52_1 includes PMOS transistors MP0 and MP3 and NMOS transistors MN0 and MN3. The inverter of the previous stage is configured using transistors MP0 and MN0. The inverter of the next stage is configured using transistors MP3 and MN3.

[0043] In transistor MP0, the source is coupled to a power supply voltage terminal (hereinafter referred to as power supply voltage terminal VDD2) provided with the power supply voltage VDD2, the drain is coupled to the node N51, and the gate is coupled to the input terminal IN1, and the input terminal IN1 is provided with a decoding signal D1 indicating a voltage range between the reference voltage VSS and the power supply voltage VDD1.

[0044] In the transistor MN0 , a source is coupled to a reference voltage terminal (hereinafter referred to as a reference voltage terminal VSS) supplied with a reference voltage VSS, a drain is coupled to a node N51 , and a gate is coupled to the input terminal IN1 .

[0045] In transistor MP3, the source is coupled to the power supply voltage VDD2, the drain is coupled to the output terminal OUT1, and the voltage of the node N51 (i.e., the output of the inverter of the previous stage) is applied to the gate. In transistor MN3, the source is coupled to the reference voltage VSS, the drain is coupled to the output terminal OUT1, and the voltage of the node N51 (i.e., the output of the inverter of the previous stage) is applied to the gate. In addition, the voltage of the output terminal OUT1 is output as the word line signal W1.

[0046] As described above, the word line driver 52_1 is driven by the power supply voltage VDD2 higher than the power supply voltage VDD1. Therefore, when the word line driver 52_1 activates the word line signal W1 in response to the activation of the decoding signal D1, the word line driver 52_1 can apply the power supply voltage VDD2 higher than the power supply voltage VDD1 as the word line signal W1 to the word line WL1.

[0047] (Operation of Word Line Driver 52)

[0048] Fig.14 is a timing diagram for illustrating the operation of the word line driver 52 . Fig.14 The case where the word line driver 52 is the word line driver 52_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 52_2 to 52_n.

[0049] In the case of performing a data read operation, one of the n decode signals D1 to Dn output from the address decoder 51 rises. Fig.14 In the example of , the decoding signal D1 rises (time t51). Therefore, the word line signal W1 is activated. That is, the word line signal W1 rises (time t52). When the data read operation is completed, the decoding signal D1 falls (time t53). Therefore, the word line signal W1 is disabled. That is, the word line signal W1 falls (time t54). It should be noted that the transistor MP0 is not completely turned off during the period (time t51 to t53) when the decoding signal D1 is activated, because the potential difference between the gate and the source corresponds to the difference between VDD2 and VDD1. Therefore, some through-current flows into the transistors MP0 and MN0. However, if the power supply voltage VDD2 is equal to or less than the voltage value obtained by adding the threshold voltage (absolute value) of the PMOS transistor to the power supply voltage VDD1, the through-current becomes smaller. In addition, the through-current is limited during the period when the decoding signal D1 is activated. Therefore, it is assumed in the present embodiment that the through-current is negligibly small.

[0050] Here, the word line driver 52 needs to have high reliability as well as high-speed operation and low power consumption. Hereinafter, factors affecting each of high-speed operation, low power consumption and high reliability will be described in detail.

[0051] First, there are two factors that affect high-speed operation: the delay caused by the word line driver of the selected activated word line and the delay caused by the word line driver of the selected disabled word line. The former affects the access time to the memory cell array (the time required from transmitting an access signal such as an address signal or a clock signal to reading the stored data) and the access cycle (the time required from transmitting a specific access signal to transmitting the next access signal), and the latter affects the access cycle to the memory cell array.

[0052] Next, there are two main factors that affect low power consumption: the current that charges or discharges the load capacitance of the word line by the selected word line driver, and the through current generated in the selected word line driver.

[0053] In addition, TDDB (time-dependent dielectric breakdown) is a factor that affects high reliability. TDDB is a dielectric breakdown phenomenon of a transistor provided in a non-selected word line driver caused by stably applying a high voltage to the transistor. TDDB is likely to occur due to a rise in the applied voltage and an increase in the size of the transistor to which the high voltage is applied.

[0054] Here, in the transistors MP0 and MN3 of each word line driver 52 provided on the non-selected word line, the high power supply voltage VDD2 is stably applied between the gate and the source of each transistor, and therefore the possibility of TDDB occurring is high. As a result, there is a problem of degradation in the reliability of the semiconductor device 5. As the value of the power supply voltage VDD2 increases in order to increase the memory cell current or enhance the driving capability of the word line driver 52, the problem becomes significant.

[0055] It should be noted that if the sizes of the transistors MP0 and MN3 are reduced, the occurrence of TDDB is suppressed. However, the delay time required to disable the word line in the active state increases, and thus the data read cycle becomes longer.

[0056] In order to solve such a problem, the inventors next considered the word line driver 62 .

[0057] (Specific Configuration Example of Word Line Driver 62)

[0058] Fig.15 is a circuit diagram for showing a specific configuration example of the word line driver 62 provided in the semiconductor device 6 according to the concept before the embodiment was produced. Fig.15 The case where the word line driver 62 is the word line driver 62_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 62_2 to 62_n.

[0059] like Fig.15As shown, the word line driver 62_1 includes PMOS transistors MP1 to MP3 and NMOS transistors MN1 to MN3. The inverter INV1 is configured using transistors MP1 and MN1. The inverter INV2 is configured using transistors MP2 and MN2.

[0060] In the transistor MP1 configuring the inverter INV1, the source is coupled to a power supply voltage terminal (hereinafter referred to as the power supply voltage terminal VDD1) supplied with the power supply voltage VDD1, the drain is coupled to the node N61, and the gate is coupled to the input terminal IN1 supplied with the decoding signal D1. In the transistor MN1, the source is coupled to the reference voltage terminal VSS, the drain is coupled to the node N61, and the gate is coupled to the input terminal IN1.

[0061] In transistor MP2 configuring inverter INV2, the source is coupled to power supply voltage terminal VDD2, the drain is coupled to node N62, and the gate is coupled to input terminal IN1. In transistor MN2, the source is coupled to reference voltage terminal VSS, the drain is coupled to node N62, and the gate is coupled to input terminal IN1.

[0062] The transistor MP3 is a pull-up element and controls the current flowing from the power supply voltage terminal VDD2 to the output terminal OUT1 based on the output voltage of the inverter INV2. Specifically, in the transistor MP3, the source is coupled to the power supply voltage terminal VDD2, the drain is coupled to the output terminal OUT1, and the gate is coupled to the output of the inverter INV2.

[0063] The transistor MN3 is a pull-down element and controls the current flowing from the output terminal OUT1 to the reference voltage terminal VSS based on the output voltage of the inverter INV1. Specifically, in the transistor MN3, the source is coupled to the reference voltage terminal VSS, the drain is coupled to the output terminal OUT1, and the gate is coupled to the output of the inverter INV1.

[0064] Here, as described above, TDDB may occur in the two transistors MP0 and MN3 in the word line driver 52. In contrast, since the inverter INV1 is driven by the power supply voltage VDD1 in the word line driver 62, the power supply voltage VDD2 is stably applied between the gate and source of only the transistor MP2 in the non-selected state. That is, TDDB may occur only in the transistor MP2 in the word line driver 62, and the transistor MN3 is excluded. Therefore, the occurrence of TDDB in the word line driver 62 can be reduced compared with the case of the word line driver 52.

[0065] In addition, the size of the gate of transistor MN3 is generally three times the size of the gate of transistor MP2. Therefore, by excluding transistor MN3 from the target of TDDB occurrence, the probability of TDDB occurrence in word line driver 62 can be significantly reduced. As a result, the reliability of semiconductor device 6 can be improved.

[0066] It should be noted that, since the occurrence probability of TDDB is reduced, by setting the value of the power supply voltage VDD2 to be larger than that in the case of the word line driver 52 , the driving capability of the word line driver 62 can be improved.

[0067] However, since the driving voltage supplied to the inverter INV1 is different from the driving voltage supplied to the inverter INV2 in the word line driver 62, the time period required for the output signal of the inverter INV1 to rise is different from the time required for the output signal of the inverter INV2 to rise. Therefore, the transistor MP3 and the transistor MN3 provided at the output stage are unintentionally turned on at the same time. Therefore, there is a problem of increased through current, resulting in increased power consumption.

[0068] (Operation of Word Line Driver 62)

[0069] Fig.16 is a timing diagram for illustrating the operation of the word line driver 62 . Fig.16 The case where the word line driver 62 is the word line driver 62_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 62_2 to 62_n.

[0070] In the data read operation, the decoding signal D1 first rises (time t61). Therefore, the output signal of each of the inverters INV1 and INV2 falls (time t62). Therefore, the transistor MP3 is turned on, and the transistor MN3 is turned off. Therefore, the word line signal W1 is activated. That is, the word line signal W1 rises (time t63).

[0071] Thereafter, when the data read operation is completed, the decoding signal D1 falls (time t64). Therefore, the output signal of each of the inverters INV1 and INV2 starts to rise (time t65). When the output signal of each of the inverters INV1 and INV2 rises (time t66 and time t67), the transistor MP3 is turned off, and the transistor MN3 is turned on. Therefore, the word line signal W1 is disabled. That is, the word line signal W1 falls (time t68).

[0072] Here, the inverter INV1 is driven by the power supply voltage VDD1, and the inverter INV2 is driven by the power supply voltage VDD2 which is higher than the power supply voltage VDD1. Therefore, the time (time t67) at which the output signal of the inverter INV2 rises to the level of the power supply voltage VDD2 is later than the time (time t66) at which the output signal of the inverter INV1 rises to the level of the power supply voltage VDD1. Therefore, the transistor MN3 is fully turned on before the transistor MP3 is turned off. Therefore, since the transistors MP3 and MN3 are turned on at the same time in the period (time t66 to t67) from the time at which the transistor MN3 is fully turned on after the output signal of the inverter INV1 rises to the level of the power supply voltage VDD1 to the time at which the transistor MP3 is turned off after the output signal of the inverter INV2 rises to the level of the power supply voltage VDD2, the through current increases, resulting in increased power consumption.

[0073] It should be noted that if the size of transistor MP2 is increased, the time when transistor MP3 is turned off (time t67) can be advanced to about the time when transistor MN3 is fully turned on (time t66). Therefore, the increase in through current is suppressed. However, if the size of transistor MP2 is increased, the probability of TDDB occurring in transistor MP2 becomes high.

[0074] Alternatively, if the size of transistor MP1 is reduced, the time when transistor MN3 is fully turned on (time t66) can be delayed to about the time when transistor MP3 is turned off (time t67). Therefore, the increase of through current is suppressed. However, if the size of transistor MP1 is reduced, the operation speed of word line driver 62 becomes slower.

[0075] As a result, the inventors have found the semiconductor device 1 according to the first embodiment, which can improve reliability while suppressing an increase in power consumption.

[0076] <First Embodiment>

[0077] Figure 1 1 is a block diagram showing a configuration example of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is, for example, a DRAM, a nonvolatile memory, etc., and reads and outputs data stored in a memory cell at an address specified by an address signal in a memory cell configuring a memory cell array.

[0078] Specifically, the semiconductor device 1 includes at least an address decoder 11, n (n is a natural number) word line drivers 12, a memory cell array 13, a sense amplifier 14, and n pulse signal generating units 15. The n word line drivers 12 and the n pulse signal generating units 15 are provided in association with the word lines WL1 to WLn in the n rows. In the following description, the n word line drivers 12 are also referred to as word line drivers 12_1 to 12_n. In addition, the n pulse signal generating units 15 are also referred to as pulse signal generating units 15_1 to 15_n.

[0079] The address decoder 11 decodes the address signal AD1 to generate n decoded signals D1 to Dn.

[0080] The pulse signal generating units 15_1 to 15_n respectively generate pulse signals P1 to Pn which temporarily fall in association with the fall of the decode signals D1 to Dn. These pulse signals P1 to Pn are respectively supplied to the word line drivers 12_1 to 12_n.

[0081] (Specific Configuration of Pulse Signal Generating Unit 15)

[0082] Figure 2 is a circuit diagram for illustrating a specific configuration example of the pulse signal generating unit 15 . Figure 2 The case where the pulse signal generating unit 15 is the pulse signal generating unit 15_1 in the first row is illustrated. However, the same applies to the case of the pulse signal generating units 15_2 to 15_n.

[0083] like Figure 2 As shown, the pulse signal generating unit 15_1 includes a delay element 151 and an OR circuit 152. The delay element 151 outputs an inverted signal of the decoded signal D1. The OR circuit 152 outputs a logical sum of the decoded signal D1 and the output signal of the delay element 151 as a pulse signal P1.

[0084] Figure 3 is a timing chart for illustrating the operation of the pulse signal generating unit 15_1.

[0085] like Figure 3 As shown in FIG. 1 , when the decoded signal D1 rises (time t21), the output signal of the delay element 151 falls thereafter (time t22). At this time, the pulse signal P1 is kept at the H level. Thereafter, when the decoded signal D1 falls (time t23), the output signal of the delay element 151 rises thereafter (time t25). At this time, the pulse signal P1 falls according to the fall of the decoded signal D1 (time t24), and rises according to the rise of the output signal of the delay element 151 (time t26). That is, the pulse signal P1 temporarily falls (time t24 to t26).

[0086] Will refer to it again Figure 1 Continue with the explanation.

[0087] The word line drivers 12_1 to 12_n drive the decoded signals D1 to Dn to be output to the word lines WL1 to WLn, respectively. Hereinafter, the signals output to the word lines WL1 to WLn are referred to as word line signals W1 to Wn.

[0088] The memory cell array 13 is configured using a plurality of memory cells arranged in a matrix manner, for example, with n rows and m columns (n ​​and m are natural numbers). When reading data, a word line designated by the address signal AD1 among the n word lines WL1 to WLn is activated (indicating an H level), and all other word lines are disabled (indicating an L level). Therefore, a piece of data stored in a memory cell in the m columns set in association with the activated word line is propagated through the m bit lines.

[0089] The sense amplifier 14 amplifies data propagating through a bit line designated (selected) by the address signal AD1 among data propagating through the m bit lines, and outputs the amplified data as read data.

[0090] (Specific Configuration of Word Line Driver 12)

[0091] Figure 4 is a circuit diagram for showing a specific configuration example of the word line driver 12 . Figure 4 The case where the word line driver 12 is the word line driver 12_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 12_2 to 12_n.

[0092] like Figure 4 As shown, the word line driver 12_1 includes PMOS transistors MP1 to MP4 and NMOS transistors MN1 to MN3. The inverter INV1 is configured using transistors MP1 and MN1. The inverter INV2 is configured using transistors MP2 and MN2.

[0093] In the transistor MP1 configuring the inverter INV1, the source is coupled to the power supply voltage terminal VDD1, the drain is coupled to the node N11, and the gate is coupled to the input terminal IN1 supplied with the decoding signal D1. In the transistor MN1, the source is coupled to the reference voltage terminal VSS, the drain is coupled to the node N11, and the gate is coupled to the input terminal IN1.

[0094] In transistor MP2 configuring inverter INV2, the source is coupled to power supply voltage terminal VDD2, the drain is coupled to node N12, and the gate is coupled to input terminal IN1. In transistor MN2, the source is coupled to reference voltage terminal VSS, the drain is coupled to node N12, and the gate is coupled to input terminal IN1.

[0095] The transistor MP3 is a pull-up element and controls the current flowing from the power supply voltage terminal VDD2 to the output terminal OUT1 based on the output voltage of the inverter INV2. Specifically, in the transistor MP3, the source is coupled to the power supply voltage terminal VDD2, the drain is coupled to the output terminal OUT1, and the gate is coupled to the output of the inverter INV2.

[0096] The transistor MN3 is a pull-down element and controls the current flowing from the output terminal OUT1 to the reference voltage terminal VSS based on the output voltage of the inverter INV1. Specifically, in the transistor MN3, the source is coupled to the reference voltage terminal VSS, the drain is coupled to the output terminal OUT1, and the gate is coupled to the output of the inverter INV1.

[0097] The transistor MP4 is a pull-up element for accelerating the turn-off operation of the transistor MP3, and is temporarily turned on by the pulse signal P1 that temporarily falls in synchronization with the fall of the decoding signal D1. Specifically, in the transistor MP4, the source is coupled to the power supply voltage terminal VDD2, the drain is coupled to the gate of the transistor MP3, and the gate is coupled to the input terminal IN2 supplied with the pulse signal P1.

[0098] Here, since the inverter INV1 is driven by the power supply voltage VDD1 in the word line driver 12_1, the power supply voltage VDD2 is stably applied between the gate and source of only the transistor MP2 in the non-selection state. That is, TDDB may occur only in the transistor MP2 in the word line driver 12_1, and the transistor MN3 is excluded. Therefore, the occurrence of TDDB in the word line driver 12_1 can be reduced compared with the case of the word line driver 52_1.

[0099] In addition, the size of the gate of the transistor MN3 is generally three times the size of the gate of the transistor MP2. Therefore, by excluding the transistor MN3 from the target of TDDB occurrence, the probability of TDDB occurrence in the word line driver 12_1 can be significantly reduced. As a result, the reliability of the semiconductor device 1 can be improved.

[0100] It should be noted that, since the occurrence probability of TDDB is reduced, by setting the value of the power supply voltage VDD2 to be greater than that in the case of the word line driver 52_1 , the driving capability of the word line driver 12_1 can be improved.

[0101] (Operation of Word Line Driver 12)

[0102] Figure 5 is a timing chart for illustrating the operation of the word line driver 12 . Figure 5The case where the word line driver 12 is the word line driver 12_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 12_2 to 12_n.

[0103] In the case of performing a data read operation, one of the n decode signals D1 to Dn output from the address decoder 11 rises. Figure 5 In the example of , the decoding signal D1 rises (time t11). Therefore, the output signal of each of the inverters INV1 and INV2 falls (time t12). Therefore, the transistor MP3 is turned on, and the transistor MN3 is turned off. Therefore, the word line signal W1 is activated. That is, the word line signal W1 rises (time t13).

[0104] Thereafter, when the data read operation is completed, the decoding signal D1 falls (time t14). Therefore, the output signal of each of the inverters INV1 and INV2 begins to rise (time t15). When the output signal of each of the inverters INV1 and INV2 rises (time t16), the transistor MP3 is turned off, and the transistor MN3 is turned on. Therefore, the word line signal W1 is disabled. That is, the word line signal W1 falls (time t17). It should be noted that during the period (time t11 to t14) when the decoding signal D1 is activated, the transistors MP4 and MP2 are not completely turned off, because the potential difference between the gate and the source of each transistor corresponds to the difference between VDD2 and VDD1. Therefore, some through current flows into each of the transistors MP4 and MN2 and the transistors MP2 and MN2. However, if the power supply voltage VDD2 is equal to or less than the voltage value obtained by adding the threshold voltage (absolute value) of the PMOS transistor to the power supply voltage VDD1, the through current becomes smaller. In addition, the period during which the decoding signal D1 is activated is limited. Therefore, it is assumed in the present embodiment that the through current is negligibly small. In addition, even after the word line signal W1 is disabled (after time t17), the transistor MP4 is not completely turned off. However, at this time, since the transistor MP2 is turned on and the gate voltage of the transistor MP3 (the voltage of the node 12) rises to the level of the power supply voltage VDD2, there is no problem even if the transistor MP4 is not completely turned off.

[0105] Here, the inverter INV1 is driven by the power supply voltage VDD1, and the inverter INV2 is driven by the power supply voltage VDD2 which is higher than the power supply voltage VDD1. Therefore, if no measures are taken, the time (time t16') at which the output signal of the inverter INV2 rises to the level of the power supply voltage VDD2 is later than the time (time t16) at which the output signal of the inverter INV1 rises to the level of the power supply voltage VDD1. Therefore, the transistor MN3 is fully turned on before the transistor MP3 is turned off. Therefore, since the transistors MP3 and MN3 are turned on at the same time in the period (time t16 to t16') from the time when the transistor MN3 is fully turned on to the time when the transistor MP3 is turned off, the through current increases, resulting in increased power consumption.

[0106] Therefore, in the word line driver 12_1 according to the present embodiment, the transistor MP4 is temporarily turned on by the pulse signal P1 that temporarily falls in synchronization with the fall of the decoding signal D1. Therefore, the charge is quickly accumulated from the power supply voltage terminal VDD2 to the gate of the transistor MP3 through the transistor MP4, and the gate voltage of the transistor MP3 rises quickly. Therefore, the transistor MP3 is immediately switched from on to off.

[0107] Therefore, the time when the transistor MP3 is turned off can be advanced to about the time when the transistor MN3 is fully turned on (time t16). Therefore, the period from the time when the transistor MN3 is fully turned on to the time when the transistor MP3 is turned off can be shortened (ideally eliminated). Therefore, the increase of the through current is suppressed, and as a result, the increase of the power consumption is suppressed.

[0108] It should be noted that after the gate voltage of the transistor MP3 is sufficiently increased, the pulse signal P1 changes from the L level to the H level (the level of the power supply voltage VDD1). Therefore, the power supply voltage VDD2 can be prevented from being stably applied between the gate and the source of the transistor MP4. As a result, TDDB can be prevented from occurring in the transistor MP3.

[0109] In addition, the time when the pulse signal P1 falls is preferably as close as possible to (ideally matching) the time when the decoding signal D1 falls. For example, if the time when the pulse signal P1 falls becomes much faster than the time when the decoding signal D1 falls, the transistor MP4 is turned on before the transistor MN2 is turned off. Therefore, the through current flowing in the transistors MP4 and MN2 increases. On the other hand, if the time when the pulse signal P1 falls becomes much slower than the time when the decoding signal D1 falls, the transistor MP cannot be turned off immediately. Therefore, the through current flowing in the transistors MP3 and MN3 increases.

[0110] It should be noted that since the increase in through current is suppressed, it is not necessary to increase the size of the transistor MP2 or to reduce the size of the transistor MP1. Therefore, high reliability and high-speed operation can be maintained.

[0111] As described above, in the semiconductor device 1 according to the embodiment, each word line driver includes a transistor MP4, which is provided between the power supply voltage terminal VDD2 and the gate of the transistor MP3 in the output stage and is temporarily turned on in synchronization with the fall of the decoding signal. Therefore, since the transistor MP3 in the output stage can be turned off immediately in the semiconductor device 1 according to the embodiment, the period during which the transistors MP3 and MN3 in the output stage are turned on at the same time can be shortened. As a result, the increase in the through current flowing in the transistors MP3 and MN3 in the output stage can be suppressed. That is, the reliability of the semiconductor device 1 according to the embodiment can be improved without increasing power consumption.

[0112] <Second Embodiment>

[0113] Figure 6 2 is a diagram for showing a configuration example of a word line driver 22 provided in the semiconductor device 2 according to the second embodiment. It should be noted that the word line driver 22 corresponds to the word line driver 12 of the semiconductor device 1. Figure 6 The case where the word line driver 22 is the word line driver 22_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 22_2 to 22_n.

[0114] like Figure 6 As shown, the word line driver 22_1 further includes an N-channel MOS transistor MN4 compared to the word line driver 12_1. The other configuration of the word line driver 22_1 is the same as that of the word line driver 12_1, and thus the description thereof will be omitted.

[0115] The transistor MN4 is a pull-down element for accelerating the charge extraction of the output terminal OUT1, and is temporarily turned on by the pulse signal P1b that temporarily rises in synchronization with the fall of the decoding signal D1. The pulse signal P1b is, for example, an inverted signal of the pulse signal P1. Specifically, in the transistor MN4, the source is coupled to the reference voltage terminal VSS, the drain is coupled to the output terminal OUT1, and the gate is coupled to the input terminal IN3 supplied with the pulse signal P1b.

[0116] It should be noted that the size ratio of the transistor MN4 to the transistor MN3 is not particularly limited, but the size of the transistor MN3 is ideally smaller than that of the transistor MN4. Specifically, the size of the transistor MN3 is approximately one-third of the size of the transistor MN4.

[0117] (Operation of Word Line Driver 22)

[0118] Figure 7 2 is a timing chart for illustrating the operation of the word line driver 22 . Figure 7The case where the word line driver 22 is the word line driver 22_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 22_2 to 22_n.

[0119] In the case of performing a data read operation, one of the n decode signals D1 to Dn output from the address decoder 11 rises. Figure 7 In the example of , the decoding signal D1 rises (time t31). Therefore, the output signal of each of the inverters INV1 and INV2 falls (time t32). Therefore, the transistor MP3 is turned on, and the transistor MN3 is turned off. Therefore, the word line signal W1 is activated. That is, the word line signal W1 rises (time t33).

[0120] Thereafter, when the data read operation is completed, the decoding signal D1 falls (time t34). Therefore, the output signal of each of the inverters INV1 and INV2 starts to rise (time t35). When the output signal of each of the inverters INV1 and INV2 rises (time t36), the transistor MP3 is turned off, and the transistor MN3 is turned on. Therefore, the word line signal W1 is disabled. That is, the word line signal W1 falls (time t37).

[0121] Here, in the word line driver 22_1 according to the present embodiment, the transistor MP4 is temporarily turned on by the pulse signal P1 which temporarily falls in synchronization with the fall of the decoding signal D1. Therefore, the charge is quickly accumulated from the power supply voltage terminal VDD2 to the gate of the transistor MP3 through the transistor MP4, and the gate voltage of the transistor MP3 rises quickly. Therefore, the transistor MP3 is immediately switched from on to off.

[0122] Therefore, the time when the transistor MP3 is turned off can be advanced to about the time when the transistor MN3 is fully turned on (time t36). Therefore, the period from the time when the transistor MN3 is fully turned on to the time when the transistor MP3 is turned off can be shortened (ideally eliminated). Therefore, the increase of the through current is suppressed, and as a result, the increase of the power consumption is suppressed.

[0123] It should be noted that in some cases, it is actually difficult to completely match the time when the transistor MP3 is turned off with the time when the transistor MN3 is fully turned on. Therefore, in the word line driver 22_1 according to the present embodiment, the transistor MN4 is temporarily turned on by the pulse signal P1b that temporarily rises in synchronization with the fall of the decoding signal D1. Therefore, the charge of the output terminal OUT1 is extracted not only through the transistor MN3 but also through the transistor MN4. Therefore, since the size of the transistor MN3 in which the through current flows can be reduced, the through current is reduced. For example, in the case where the size of the transistor MN3 is one-third of the size of the transistor MN4, the through current is reduced to about one-quarter.

[0124] <Third Embodiment>

[0125] Figure 8 1 is a block diagram showing a configuration example of a semiconductor device 3 according to a third embodiment. The semiconductor device 3 is different from the semiconductor device 1 in the structure of an address decoder and the number of pulse signal generating units 15. Hereinafter, the third embodiment will be described in detail.

[0126] Specifically, the semiconductor device 3 includes at least an address decoder 31 , n word line drivers 12 , a memory cell array 13 , a sense amplifier 14 , and p (p is a natural number smaller than n) pulse signal generating units 15 .

[0127] In the following description, the p pulse signal generating units 15 are also referred to as pulse signal generating units 15_1 to 15_p. In addition, the q (q is n / p) word line drivers 12 provided with the pulse signal Pi from the pulse signal generating unit 15_i (i is a natural number from 1 to p) among the n word line drivers 12 are also referred to as word line drivers 12_i_1 to 12_i_q. It should be noted that the word line driver 12_1_1 corresponds to the word line driver 12_1, and the word line driver 12_p_q corresponds to the word line driver 12_n.

[0128] (Specific Configuration Example of Address Decoder 31)

[0129] Fig. 9 31 is a diagram for illustrating a specific configuration example of the address decoder 31. It should be noted that Fig. 9 P pulse signal generating units 15_1 to 15 — p are shown except for the address decoder 31 .

[0130] like Fig. 9 As shown, the address decoder 31 includes pre-decoders 311 and 312 and p AND circuit groups 313_1 to 313_p.

[0131] The predecoder 311 decodes an address signal configured, for example, using high-order bits among a plurality of bits configuring the address signal AD1 (hereinafter referred to as a high-order address signal), and outputs predecode signals Dh_1 to Dh_p. The predecoder 312 decodes an address signal configured, for example, using the remaining low-order bits among the bits configuring the address signal AD1 (hereinafter referred to as a low-order address signal), and outputs predecode signals Dl_1 to Dl_q.

[0132] Each of the AND circuit groups 313_1 to 313_p is configured using q AND circuits. The AND circuit group 313_i (where i is a natural number from 1 to p) multiplies the pre-decoded signal Dh_i output from the pre-decoder 311 by the pre-decoded signals Dl_1 to Dl_q output from the pre-decoder 312, and outputs the results as decoded signals D1_i_1 to D1_i_q. It should be noted that the decoded signal D1_1_1 corresponds to the decoded signal D1, and the decoded signal D1_p_q corresponds to the decoded signal Dn.

[0133] The pre-decoded signals Dh_1 to Dh_p output from the pre-decoder 311 are respectively supplied to the pulse signal generation units 15_1 to 15_p.

[0134] Reference will be made again Figure 8 Continue the description.

[0135] The pulse signal generation units 15_1 to 15_p respectively output pulse signals P1 to Pp that temporarily drop in synchronization with the falling edges of the pre-decoded signals Dh_1 to Dh_p. The pulse signal Pi (where i is a natural number from 1 to p) is supplied to the q word line drivers 12_i_1 to 12_i_q.

[0136] The word line drivers 12_i_1 to 12_i_q respectively drive the decoded signals D1_i_1 to D1_i_q for output to the word lines WL1_i_1 to WL1_i_q. It should be noted that the word line WL1_1_1 corresponds to the word line WL1, and the word line WL1_p_q corresponds to the word line WLn.

[0137] The other configurations of the semiconductor device 3 are the same as those of the semiconductor device 1, and thus the description thereof will be omitted.

[0138] As described above, the semiconductor device 3 according to the present embodiment generates the pulse signals P1 to Pp having a p-bit width (p < n) based only on the pre-decoded signals having a p-bit width generated by decoding the high-order address signal, rather than generating the n pulse signals P1 to Pn based on the n decoded signals generated by decoding the address signal AD1. Therefore, the semiconductor device 3 according to the present embodiment can reduce the number of pulse signal generation units 15, and thus the increase in the circuit scale can be suppressed.

[0139] The semiconductor device 3 according to the present embodiment generates each of the decoded signals D1 to Dn and the pulse signals P1 to Pp based on the pre-decoded signals having a p-bit width generated by decoding the high-order address signal. Therefore, it is possible to easily align the falling timings of the decoded signals D1 to Dn and the falling timings of the pulse signals P1 to Pp, and thus the increase in the direct current flowing through the transistors MP3 and MN3 provided in each word line driver 12 can be suppressed.

[0140] In the present embodiment, the case where the semiconductor device 3 includes the word line drivers 12_1 to 12_n is described as an example. However, the present invention is not limited thereto, but the semiconductor device 3 may include the word line drivers 22_1 to 22_n.

[0141] <Fourth Embodiment>

[0142] Fig.10 4 is a diagram for showing a configuration example of a word line driver 42 provided in the semiconductor device 4 according to the fourth embodiment. It should be noted that the word line driver 42 corresponds to the word line driver 12 of the semiconductor device 1. Fig.10 The case where the word line driver 42 is the word line driver 42_1 in the first row is illustrated. However, the same applies to the case of the word line drivers 42_2 to 42_n.

[0143] like Fig.10 As shown, compared with the word line driver 12_1, the word line driver 42_1 includes an inverter INV2a instead of the inverter INV2. In the inverter INV2a, the gate of the transistor MP2 is coupled to the input terminal IN4 supplied with the bias signal B1. The other configurations of the inverter INV2a are the same as those of the inverter INV2, and therefore the description thereof will be omitted.

[0144] For example, in the case where the internal power supply circuit is started when the standby mode is switched to the normal operation mode, the bias signal B1 is activated.

[0145] Fig.11 FIG. 1 is a diagram for illustrating a configuration example of the bias generating circuit BG1. It should be noted that the inverter INV2a is also provided in Fig.11 Shown in.

[0146] like Fig.11 As shown, the bias generating circuit BG1 includes a P-channel MOS transistor MP5 and a constant current source I1. In the transistor MP5, the source is coupled to the power supply voltage terminal VDD2, and the drain and the gate are coupled to the output terminal of the bias generating circuit BG1. The input terminal of the constant current source I1 is coupled to the output terminal of the bias generating circuit BG1, and the output terminal of the constant current source I1 is coupled to the reference voltage terminal VSS.

[0147] Here, the transistor MP5 provided in the bias generating circuit BG1 and the transistor MP2 provided in the inverter INV2a are coupled to each other in a current mirror manner. Therefore, a current proportional to the current flowing between the source and drain of the transistor MP5 (the current flowing in the constant current source I1) always flows between the source and drain of the transistor MP2.

[0148] On the contrary, the current flowing between the source and drain of the transistor MN2 is different depending on the voltage level of the input signal D1. For example, in the case where the input signal D1 is activated to indicate the H level, a constant current flows between the source and drain of the transistor MN2. At this time, the node N12 (the gate of the transistor MP3) is discharged by the transistor MN2, and therefore the L level is indicated. It should be noted that in order to maintain stable operation and high-speed operation, the current flowing between the source and drain of the transistor MP2 is adjusted so as to be substantially smaller than the current flowing between the source and drain of the transistor MN2.

[0149] On the other hand, when the input signal D1 is disabled to indicate the L level, the current flowing between the source and drain of the transistor MN2 stops. At this time, the node N12 (the gate of the transistor MP3) is charged by the transistor MP4 having a large driving capability, and thus the H level is indicated. It should be noted that although the transistor MP4 is turned off after the charging of the node N12 is completed, the node N12 remains at the H level because the transistor MP3 is turned on with a high resistance.

[0150] Here, the threshold voltage of the transistor MP5 is applied only between the gate and source of the transistor MP5 provided in the bias generation circuit BG1, and the high power supply voltage VDD2 is applied unstably. Likewise, the threshold voltage of the transistor MP5 is applied only between the gate and source of the transistor MP2 provided in the inverter INV2a of each word line driver, and the high power supply voltage VDD2 is applied unstably. Therefore, the occurrence of TDDB in the transistors MP5 and MP2 is suppressed.

[0151] It should be noted that the bias generating circuit BG1 can be shared by the word line drivers and therefore does not greatly affect the increase in current consumption.

[0152] As described above, in each of the semiconductor devices 1 to 4 according to the above-mentioned first to fourth embodiments, each word line driver includes a transistor MP4, which is provided between the power supply voltage terminal VDD2 and the gate of the transistor MP3 in the output stage and is temporarily turned on in synchronization with the fall of the decoding signal. Therefore, in each of the semiconductor devices 1 to 4 according to the above-mentioned first to fourth embodiments, the transistor MP3 in the output stage can be turned off immediately, and thus the period during which the transistors MP3 and MN3 in the output stage are turned on at the same time can be shortened. As a result, the increase in the through current flowing in the transistors MP3 and MN3 in the output stage can be suppressed. That is, in each of the semiconductor devices 1 to 4 according to the above-mentioned first to fourth embodiments, the reliability can be improved without increasing the power consumption.

[0153] At this time, it is not necessary to increase the size of the transistor MP2 or to reduce the size of the transistor MP1 to suppress the increase in the through current. Therefore, high reliability and high-speed operation of each of the semiconductor devices 1 to 3 can be maintained.

[0154] The invention achieved by the inventors has been specifically described above based on the embodiments. However, it is clear that the present invention is not limited to the above-described embodiments and various changes can be made without departing from the scope thereof.

[0155] For example, each semiconductor device according to the above-described embodiments may be configured to reverse the conductivity type (p-type or n-type) of a semiconductor substrate, a semiconductor layer, a diffusion layer (diffusion region), etc. Therefore, in the case where one conductivity type of the n-type and the p-type is the first conductivity type and the other is the second conductivity type, the first conductivity type may be the p-type and the second conductivity type may be the n-type. Conversely, the first conductivity type may be the n-type and the second conductivity type may be the p-type.

Claims

1. A driving circuit, comprising: a first inverter driven by a first power supply voltage and inverting and outputting a first input signal; a second inverter driven by a second power supply voltage higher than the first power supply voltage and inverting and outputting the first input signal; a first PMOS transistor that controls a current flowing from a power supply voltage terminal supplied with the second power supply voltage to an external output terminal based on an output signal of the second inverter; a first NMOS transistor that controls a current flowing from the external output terminal to a reference voltage terminal based on an output signal of the first inverter; a second PMOS transistor provided between the power supply voltage terminal supplied with the second power supply voltage and a gate of the first PMOS transistor; and a signal generating circuit having an output terminal coupled to a gate of the second PMOS transistor, wherein the gate of the second PMOS transistor receives a second input signal, and The signal generating circuit is configured to generate the second input signal in synchronization with a falling edge of the first input signal.

2. The driving circuit according to claim 1, wherein the signal generating circuit comprises: a delay circuit that delays and outputs an inverted signal of the first input signal; and An OR circuit outputs a logical sum of the first input signal and the output signal of the delay circuit as the second input signal. 3 . The driving circuit according to claim 1 , further comprising a second NMOS transistor which is provided in parallel with the first NMOS transistor and is temporarily turned on in synchronization with a falling edge of the first input signal.

4. The driving circuit according to claim 3, The size of the first NMOS transistor is smaller than that of the second NMOS transistor.

5. The driving circuit according to claim 3, A third input signal which temporarily rises in synchronization with a fall of the first input signal is supplied to the gate of the second NMOS transistor.

6. The driving circuit according to claim 1, The first inverter comprises: a third PMOS transistor provided between the power supply voltage terminal supplied with the second power supply voltage and the output terminal of the first inverter, a gate of the third PMOS transistor being supplied with a predetermined bias signal; as well as A third NMOS transistor is provided between the reference voltage terminal and the output terminal of the first inverter, and a gate of the third NMOS transistor is supplied with the first input signal.

7. A semiconductor device comprising: an address decoder that decodes the address signal to generate a plurality of decoded signals; The driving circuit according to claim 1, which drives the decoded signal as the first input signal to be output to a plurality of word lines; as well as A memory cell array in which data stored in a memory cell at a designated address is read based on an activation state of each of the word line and a plurality of bit lines.

8. The semiconductor device according to claim 7, further comprising a plurality of signal generating circuits generating the second input signal, Each of the signal generating circuits has: a delay circuit that delays and outputs an inverted signal of the decoded signal; and An OR circuit outputs a logical sum of the decoded signal and the output signal of the delay circuit as the second input signal.

9. The semiconductor device according to claim 7, Each of the driving circuits includes a second NMOS transistor that is arranged in parallel with the first NMOS transistor and is temporarily turned on in synchronization with a falling edge of the first input signal.

10. The semiconductor device according to claim 9, The size of the first NMOS transistor is smaller than that of the second NMOS transistor.

11. The semiconductor device according to claim 9, A plurality of third input signals which temporarily rise in synchronization with the falling of the decode signal are supplied to the gates of the second NMOS transistors respectively provided in the drive circuit.

12. The semiconductor device according to claim 7, The address decoder has: a first predecoder that decodes a high-order address signal represented by a high-order bit among bits configuring the address signal to generate a plurality of first predecoded signals; a second pre-decoder that decodes a low-order address signal represented by the remaining bits of the bits configuring the address signal to generate a plurality of second pre-decoded signals; as well as a decoding signal generating unit, which generates the decoding signal based on the first pre-decoding signal and the second pre-decoding signal, wherein the semiconductor device further comprises a plurality of signal generating circuits that generate a plurality of second input signals that temporarily fall in synchronization with a fall of the first pre-decoding signal, and The common second input signal is input to the driving circuit, and the decoded signal generated based on the common first pre-decoded signal is input to the driving circuit.

13. A control method for a driving circuit, comprising the following steps: inverting and outputting a first input signal using a first inverter driven by a first power supply voltage; inverting and outputting the first input signal using a second inverter driven by a second power supply voltage higher than the first power supply voltage; controlling a current flowing in a first PMOS transistor provided between a power supply voltage terminal supplied with the second power supply voltage and an external output terminal based on an output signal of the second inverter; controlling a current flowing in a first NMOS transistor based on an output signal of the first inverter, the first NMOS transistor being disposed between the external output terminal and a reference voltage terminal; as well as temporarily turning on a second PMOS transistor based on a second input signal supplied to a gate of the second PMOS transistor, the second PMOS transistor being provided between the power supply voltage terminal supplied with the second power supply voltage and the gate of the first PMOS transistor, The second input signal is generated by a signal generating circuit in synchronization with a falling edge of the first input signal.

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