Digital input circuit for receiving digital input signal from signal generator

Abstract

The present invention relates to a digital input circuit for receiving a digital input signal of a signal generator, comprising: an input terminal; a first subcircuit, which has a current stabilizing element and a voltage stabilizing element, and the first subcircuit has a non-ideal current output characteristic at least in the second state; a second subcircuit, which has a current stabilizing element and a voltage stabilizing element, and the second subcircuit has a non-ideal current output characteristic at least in the second state, wherein the first and second subcircuits are designed and interconnected so that at least in the second state or at least in a part of the second state, the current flowing through the voltage stabilizing element of the first subcircuit is composed of the stable current of the second subcircuit, and the current flowing through the voltage stabilizing element of the second subcircuit is composed of the stable current of the first subcircuit, so that the non-ideal current output characteristic of the first subcircuit and the non-ideal current output characteristic of the second subcircuit are basically compensated at least in the second state.

Description

Technical Field

[0001] The present invention relates to a digital input circuit for receiving a digital input signal of a signal generator, comprising: an input end, via which an input signal can be transmitted to the input circuit, when the input signal reaches or falls below a lower threshold, the input circuit occupies a first state, and when the input signal reaches or exceeds an upper threshold, the input circuit occupies a second state; a first subcircuit, the first subcircuit having at least one current stabilization element with a control loop and at least one voltage stabilization element, wherein the first subcircuit has a non-ideal current output characteristic at least in the second state; and a second subcircuit, the second subcircuit having at least one current stabilization element with a control loop and at least one voltage stabilization element, wherein the second subcircuit has a non-ideal current output characteristic at least in the second state. Background Art

[0002] A trend that can be observed in technology today is the miniaturization of devices and device components, in particular also electrical and electronic devices and device components, which is constantly being developed. This trend towards miniaturization is usually accompanied by a simultaneous increase in the functional scope of the device or device component. As a result, for example, in switching devices or safety switching devices, which are provided for safety-related applications, in particular in automation technology installations, the number of inputs for receiving analog or digital input signals from different signal generators increases. The analog or digital input signals originate, for example, from sensor devices or signaling devices, such as emergency-off buttons, emergency-stop buttons, safety doors, switch mats, two-hand switches, limit switches and other position switches.

[0003] The digital input signal is a binary signal and is characterized by two defined states, which can be defined, for example, by two static potentials. The binary states are characterized by different voltage states, with a first state if a defined voltage threshold is reached or below. This is a so-called low state. If a defined voltage threshold is reached or exceeded, a second state is present. This is a so-called high state.

[0004] Digital input circuits of the type mentioned above for receiving digital input signals of a signal generator by means of at least one input are known from the prior art in very different embodiments. In current-sinking digital input circuits, which are usually operated with an operating voltage of 24 V (DC), a distinction is made according to the standard EN 61131-2:2007 between three different types (Type 1, Type 2 and Type 3). These three types of digital input circuits differ from one another in particular in their high level, their low level and their current consumption.

[0005] The digital input circuit of type 1 must compulsorily recognize the high level at the latest when the input voltage is 15 V. In practice, the high level is therefore already detected when the input voltage is <15V. The digital input circuit of type 1 must also recognize the high level in the total input voltage range of 15V to 30V. The current consumption is in the high level range of ≥2mA and can be up to 15 mA. The digital input circuit of type 1 (and types 2 and 3 mentioned below) must also be able to recognize the low level in the total range from -3V to 5V for this purpose. Therefore, in practice, the low level has been detected when the input voltage is >5V. In the range from -3V to 5V, the input current is allowed to be between 0mA and 15mA. When the input voltage is between 5V and 15V, it is important that the current limit is 0.5mA. In this range, if the input current is ≤0.5mA, the input terminal must also recognize the low level. This type of digital input circuit is particularly used for electromechanical switching devices, such as buttons or relay contacts, or also for 3-conductor sensor devices. A typical application example for a Type 1 digital input circuit is an emergency shutdown switch device.

[0006] For example, a type 2 digital input circuit is suitable for 2-conductor sensor devices and for semiconductor sensors that require a relatively high quiescent current for their operation. The current consumption in the high-level range between 11 V and 30 V is typically ≥ 6 mA and can be up to 30 mA.

[0007] The digital input circuit of type 3 is characterized, in particular at high voltage, by lower power consumption and waste heat compared to the digital input circuit of type 2, so that more digital input circuits can be combined into one digital input module compared to the digital input circuit of type 2. The digital input circuit of type 3 must recognize a high level in the input voltage range between 11 V and 30 V. The current consumption is usually ≥2mA in the high level range between 12 V and 30 V and can be up to 15 mA. In the input voltage range between -3 V and 5 V, the digital input circuit of type 3 must recognize a low level when the permissible current consumption is between 0 mA and 15 mA. In addition, a low level must be recognized when the input voltage is between 5V and 11V and the input current is ≤1.5mA.

[0008] The trend towards miniaturization already mentioned above requires, in addition to the use of increasingly smaller components, a continuous reduction in the power loss of the components and circuits used, as the number of functions increases. This also applies in particular to digital input circuits, which are required, for example, for processing signals of signaling devices or sensor signals. Therefore, the goal in these digital input circuits is to keep the input current as low as possible at the input voltage corresponding to the second state (i.e. the logical high level). This is particularly important in the range where the maximum input voltage occurs, because then the maximum current usually also flows, and thus the maximum power loss also occurs. However, at the same time, a minimum input current is usually required, which must not be exceeded when an upper threshold is reached, which defines the beginning of the high level range.

[0009] The digital input circuit which is optimal in terms of its minimum power consumption has an input current-input voltage characteristic curve such as Figure 1 This figure shows the input current I of the digital input circuit. IN According to the input voltage U IN The low level range is controlled by the input voltage U IN ≤U Low,max And through the input current I IN ≤I Low,max The high level range is limited by the input voltage U High,min ≤U IN ≤U High,max and through the input current I IN =I High,min There is a limit between the low level range and the high level range, which is located at the input voltage U IN > U Low,max and U IN High,min The transition region between the input current I Low,max IN High,min As mentioned above, in practical applications, high and low states have been detected at the input voltage in the transition region. A basic feature of this idealized characteristic curve variation is the constant input current I in the high range of the digital input circuit. IN = I High,min This means that, despite the input voltage U IN increases, but ideally, the input current I IN Will not improve further.

[0010] In contrast, Figure 2 ​​​The change of the input current-input voltage characteristic curve of a real digital input circuit is shown, which has a non-optimal power consumption due to the non-ideal current consumption characteristics in the second state (high level range). The input current I IN According to the input voltage U IN changes. Figure 2 As shown in Figure 1 The difference from the idealized characteristic curve shown in FIG. 1 is that the input current I IN Also in the high level range further (to a greater or lesser extent) increases. Therefore, with the input voltage U IN Getting bigger and bigger, applicable: I IN > I High,min The input current I IN The resulting boost ΔI increases with increasing input voltage U IN , and as in Figure 1 Compared to the case in which the characteristic curve of the ideal digital input circuit shown in FIG. 1 changes, this leads to a significantly stronger increase in the electrical power loss.

[0011] In the prior art, in order to stabilize the input current of the digital input circuit, for example, a Figure 3 The circuit arrangement shown in the figure. The circuit arrangement of the digital input circuit 100' has a very simple constructed voltage regulator, which includes a bipolar transistor (npn transistor) T1', a Zener diode Z1' and a series resistor R2' for the Zener diode Z1'. With the help of the Zener diode Z1', voltage limitation can be achieved. In order for the output voltage of the voltage regulator constructed in this way to have good stability, it is necessary that the Zener diode Z1' is operated in its stable region (ie, with a small differential resistance) or at least in the vicinity thereof. However, for this purpose, the series resistor R2' of the Zener diode Z1' of the voltage regulator must be selected to be sufficiently small. However, this has a negative impact on the input voltage (U in > U High,min ) has the following disadvantages: the current flowing through the series resistor R2' and the Zener diode Z1' and the resulting input current of the digital input circuit 100' itself further increases significantly. Therefore, the current increase ΔI in the high level range cannot be kept very small in any case. Therefore, the desired good stability of the output voltage of the voltage regulator in the case of an increase in the input voltage causes a significant increase in the voltage regulator's own current demand.

[0012] On the other hand, however, if the series resistor R2' increases, the stability of the output voltage of the voltage regulator deteriorates to the same extent as the series resistor R2' increases. The operating point of the Zener diode Z1' for stabilizing the output voltage can then move very quickly into the stop band of the Zener diode Z1'. In this stop band, the differential resistance of the Zener diode Z1' is known to be very large. This has the disadvantage that the actual output voltage of the voltage regulator depends not only relatively strongly on the input voltage U IN , and also strongly depends on the type of Zener diode Z1' used. This in turn can cause the output voltage of the voltage regulator (at least at the input voltage U IN =U High,min ) does not reach the minimum value required for detecting the high state. Therefore, the digital input circuit only IN >U High,min In extreme cases, the high voltage state is not even recognized.

[0013] In addition to the lack of reliability of the input circuit 100' configured in this way, although the series resistor R2' of the Zener diode Z1' is relatively large, the input current I IN With input voltage U IN If multiple digital input circuits must be accommodated in a single housing with limited power dissipation capacity to form a digital input module, particular attention should be paid to the input current I IN With input voltage U IN increases with the rise of .

[0014] In other digital input circuits known from the prior art, the input current is stabilized by means of a single current source. Even when using a typical real current source, the above-mentioned disadvantages of the circuit arrangement occur (i.e., as in Figure 2 An example of such an embodiment is known from EP 1 906 533 A1. In this document, an additional current source for setting the quiescent current in the low-level range is used to connect the proximity switch.

[0015] In order to obtain a digital input circuit with the lowest possible electrical power loss, the digital input circuit should ideally have an input current-input voltage characteristic curve in the logic high level range that is as close as possible to the input current-input voltage characteristic curve in the logic high level range. Figure 1 The characteristic curve shown in the figure changes. Therefore, basically: in the input current-input voltage characteristic curve, at the input voltage U IN > U High,min When increasing, it will be based on Figure 2The increase in the input current ΔI shown is minimized as much as possible. In addition, the minimum input current I in the high level range IN It should also be as close as possible to at least the required input current I High,min A further object was to realize the digital input circuit as simply as possible and thus also cost-effectively. Summary of the invention

[0016] The object of the present invention is therefore to provide a digital input circuit of the type mentioned at the outset, which enables reliable recognition of high and low state of the input signal and particularly low-loss operation in the high level range and which is designed in a simple and cost-effective manner.

[0017] The solution to the object provides a digital input circuit for receiving a digital input signal of a signal generator, the digital input circuit comprising:

[0018] an input terminal, via which an input signal can be supplied to a digital input circuit, wherein the digital input circuit occupies a first state when the input signal reaches or falls below a lower threshold value, and the digital input circuit occupies a second state when the input signal reaches or exceeds an upper threshold value;

[0019] a first subcircuit, the first subcircuit having at least one current stabilization element with a control loop and having at least one voltage stabilization element, wherein the first subcircuit has a non-ideal current output characteristic at least in a second state; and

[0020] a second subcircuit, the second subcircuit having at least one current stabilization element with a control loop and at least one voltage stabilization element, wherein the second subcircuit has a non-ideal current output characteristic at least in a second state,

[0021] It is characterized in that the first subcircuit and the second subcircuit are designed and interconnected so that at least in the second state or at least in a part of the second state, the current flowing through the voltage stabilizing element of the first subcircuit is basically composed of the stabilized current of the second subcircuit, and the current flowing through the voltage stabilizing element of the second subcircuit is basically composed of the stabilized current of the first subcircuit, so that the non-ideal current output characteristics of the first subcircuit and the non-ideal current output characteristics of the second subcircuit are basically compensated at least in the second state, the digital input circuit has a high-ohmic resistor, the first subcircuit is directly connected to the ground via the high-ohmic resistor, and the resistance value of the high-ohmic resistor is ≥750kΩ.

[0022] The digital input circuit according to the invention is characterized in that the first subcircuit and the second subcircuit are designed and interconnected so that at least in the second state or at least in a part of the second state, the current flowing through the voltage stabilizing element of the first subcircuit is substantially composed of the stabilized current of the second subcircuit, and the current flowing through the voltage stabilizing element of the second subcircuit is substantially composed of the stabilized current of the first subcircuit, so that the non-ideal current output characteristics of the first subcircuit and the non-ideal current output characteristics of the second subcircuit are substantially compensated at least in the second state. Therefore, the circuit architecture of the digital input circuit according to the invention is characterized in that at least two subcircuits are used, which form a current source, wherein the subcircuits are preferably connected in sequence in a cross-shaped manner, so that at least for input signals in the high level range (or at least in a part of the high level range) (the high level range defines the second state of the digital input circuit), the current flowing through the voltage stabilizing element of the first subcircuit is substantially composed of the stabilized current of the second subcircuit, and the current flowing through the voltage stabilizing element of the second subcircuit is substantially composed of the stabilized current of the first subcircuit. It is thereby achieved that in the region of the first and second subcircuits, two parallel constant or substantially constant currents flow. By means of this circuit architecture, a digital input circuit can be realized in an unexpectedly simple and cost-effective manner, the input current-input voltage characteristic curve of which has approximately the same characteristic curve as that of the second state formed by the high level range. Figure 1 The current of the two control loops in the second state (high level range) only accounts for a small part of the current of the two sub-circuits. IN > U High,min When, according to Figure 2 The current increase ΔI also tends to zero, so that the electrical damage power in the second state of the digital circuit device according to the invention can be minimized in an advantageous manner. The digital input circuit according to the invention is also suitable for the following digital input module, which includes a plurality of digital input circuits arranged in a single housing with limited power loss capacity.

[0023] In a preferred embodiment, it is proposed that the voltage stabilizing elements of the first and second subcircuits are Zener diodes, which operate in a stable region in the second state. The circuit architecture enables, when the Zener diodes are used for the first subcircuit and the second subcircuit, their specific dimensions can be selected very simply so that, at least for input signals in the high level range, a sufficiently large current flows through the two Zener diodes so that the two Zener diodes operate in their stable region or at least close to this temperature region. In this circuit architecture, the good mutual stability of the currents of the two subcircuits (and thus the total input current) is based on the fact that the current of the Zener diodes and therefore the voltage of the Zener diodes remain stable. The mutual stability of the currents of the two subcircuits is maximum when the Zener diodes are in their stable region. This is achieved in an advantageous manner without the need to significantly increase the input current I in the high level range, which is disadvantageous. IN , as in Figure 3 This is the case in the case of digital input circuit 100 ′ and when the Zener diode Z1 ′ of the voltage regulator arranged therein is operated in the stable region.

[0024] As an alternative to the Zener diode, other voltage stabilizing elements are also possible in principle, for example conventional diodes, light-emitting diodes or reference diodes (one or more diodes which are connected in series or in series with, for example, one or more Zener diodes). Figure 2 Even with conventional diodes, the current increase ΔI can be limited almost as well as with Zener diodes, since the differential resistance of the diode in the passband can have a similar value to some Zener diodes in the stable region after reaching the breakdown voltage. The scatter of the diode voltage at a specific current is usually greater than in the case of Zener diodes. It follows from this that the scatter of the absolute current is usually smaller in subcircuits in which Zener diodes are used as voltage stabilization elements.

[0025] In a particularly preferred embodiment, the digital input circuit has the possibility of having a high-ohmic resistor, via which the first subcircuit is connected to ground and whose resistance value is preferably ≥750 kΩ, in particular ≥1 MΩ. It has been shown that another advantage of operating the Zener diodes of the first subcircuit and the second subcircuit in their stable region is that their influence on component-related tolerances of the current of the first subcircuit and the second subcircuit is also minimized. Therefore, the current increase ΔI is minimal when the Zener diodes of the two subcircuits are operated in their respective stable regions and have a resistance as high as possible (for example, in this embodiment, ≥1 MΩ, for example). In particular, the high-ohmic resistor has the function of ensuring that at the input voltage U INWhen the voltage is increased (from 0 V), the current can even flow into the input. Therefore, the resistor acts as a "starting resistor" or "starting resistor" to a certain extent. Specifically, the resistor allows the current to flow in the control loop of the current stabilization element of the first subcircuit in the "on phase". The current is in turn a prerequisite for the first subcircuit to be able to provide current. The current is a prerequisite for the current flow in the control loop of the current stabilization element of the second subcircuit, and the current flow ultimately enables the current to flow into the second subcircuit.

[0026] In a particularly preferred embodiment, it can be provided that the balancing element of the first subcircuit is formed by a bipolar transistor, in particular a pnp transistor, which has a base, an emitter and a collector. This allows the balancing element of the first subcircuit to be realized relatively simply and cost-effectively.

[0027] The current balancing element of the second subcircuit can preferably be formed by a bipolar transistor, in particular an npn transistor, which has a base, an emitter and a collector. This measure can also realize the current balancing element of the second subcircuit relatively simply and cost-effectively.

[0028] In an advantageous embodiment, it is provided that the first and second subcircuits are interconnected in such a way that the base of the bipolar transistor of the first subcircuit is connected to the collector of the bipolar transistor of the second subcircuit.

[0029] In a further advantageous embodiment, the first and second subcircuit can be interconnected such that the base of the bipolar transistor of the second subcircuit is connected to the collector of the bipolar transistor of the first subcircuit.

[0030] In a preferred embodiment, it can be proposed that the digital input circuit has a third subcircuit, which is set up for identifying the logical state of the digital input circuit, and the third subcircuit is connected to an output terminal, via which the output signal can be output. In another embodiment, it is also feasible that the third subcircuit is placed in a separate device unit in a submerged manner. However, the third subcircuit is not mandatory. Therefore, the digital input circuit can be used to optically display the logical state of the input signal, for example. The display can be integrated into the second subcircuit in particular, in that, for this purpose, for example, a Zener diode is replaced by an LED or by a diode that is connected in series with a Zener diode or in series with a normal diode.

[0031] In a particularly preferred embodiment, the following feasibility exists: the third subcircuit has a coupling element and a threshold element connected in parallel therewith, the coupling element is set up for coupling the input end with the output end, wherein the threshold element is configured to provide a switching threshold for the coupling element and is particularly configured as a resistor. With the help of the coupling element and the threshold element, it is possible to check whether the digital input circuit is in the first state (in the low level range) or in the second state (in the high level range). Preferably, the coupling element can be configured so that only when the digital input circuit is in the second state (in the high level range), the coupling element is conductive and couples the input end with the output end. The coupling element can be configured in particular as an optical coupler to promote the current separation of the primary side of the digital input circuit including the input end and the secondary side including the output end. The current separation has the following advantages: the output end or the component connected thereto can be protected from damage and the errors caused thereby in the case of overvoltage. The threshold element, which is preferably designed as a resistor, ensures the required switching threshold for the coupling element and limits it to the high level range, and on the other hand limits the current through the light-emitting diode of the optocoupler, which preferably forms the coupling element, to a value for which the optocoupler is designed (e.g. 1 mA). Finally, the current flowing through the resistor also helps the input circuit to operate at an input current I of 1.5 mA. IN According to the IEC 61131-2 standard, this is required for DC 24V type 3 inputs as long as the input voltage is between 5V and 11V.

[0032] In an alternative embodiment, it is also possible, for example, to design the coupling element as a transistor stage. This provides a digital input circuit in a non-potentially isolated embodiment.

[0033] It has been shown that the temperature influence of the input current can be minimized by a suitable design of the first subcircuit and the second subcircuit. In a particularly advantageous embodiment, it is provided that the Zener diodes of the first and second subcircuits have a negative temperature coefficient. If such a Zener diode with a negative temperature coefficient is used, then the Zener diode can at least partially offset the likewise negative temperature coefficient of the base-emitter voltage of the transistor. In other words, this means that the temperature-dependent voltage changes of the Zener diode and the base-emitter voltage of the transistors of the two subcircuits can be relatively well compensated.

[0034] The significant advantages of the above circuit architecture are in particular:

[0035] - simple and low-cost realizability,

[0036] - its applicability to all types of digital input circuits 100 according to IEC61131-2 (Types 1, 2 and 3),

[0037] - its suitability for digital input circuits 100 that sink and source current,

[0038] - its applicability to digital input circuits 100 with and without potential separation, and

[0039] - their suitability for safety-related applications, in particular in safety switching devices for fail-safe disconnection of technical installations or in I / O modules.

[0040] The digital input circuit having the above-described circuit architecture can be realized in particular by means of discrete components. Alternatively, the digital input circuit having the circuit architecture can also be realized by an integrated circuit in an IC, in particular in an ASIC.

[0041] The digital input circuit described here is not itself very low-loss. The actual size of the electrical power loss is ultimately related to the specific size of the circuit. The specific size can minimize the power loss (especially in the high-level range, of course). It is also possible to select the specific size to cause a larger or large power loss. In a digital input circuit of type 2, the standard IEC61131-2 requires, for example, a minimum current of 6mA for a DC 24V input terminal in the high-level range, and then three times the size (at least 2mA) in a digital input circuit of type 1 or type 3. Accordingly, in a digital input circuit of type 2, the power loss in the high-level region is at least three times the size in a digital input circuit of type 1 or type 3. However, even in a digital input circuit of type 2, the power loss is of course kept to a minimum by means of the circuit architecture described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other features and advantages of the present invention will become apparent with the help of the following description of preferred embodiments with reference to the accompanying drawings. In the drawings:

[0043] Figure 1 shows the idealized variation of the input current-input voltage characteristic curve of a digital input circuit;

[0044] Figure 2 Shows the actual change of the input current-input voltage characteristic curve of the digital input circuit;

[0045] Figure 3 A digital input circuit according to the prior art is shown;

[0046] Figure 4 A digital input circuit constructed according to a preferred embodiment of the present invention is shown. DETAILED DESCRIPTION

[0047] Next, refer to Figure 4 The structure of a digital input circuit 100 according to a preferred embodiment of the present invention is explained in detail. The digital input circuit 100 has an input terminal 1, by means of which the digital input circuit 100 can be connected to a signal generator. The signal generator that can provide a digital input signal to the input circuit can in particular include a sensor device or a signal device, such as an emergency shutdown button, an emergency stop button, a protective door, a switch pad, a two-hand switch, a limit switch or a position switch. The signal device can also work in a contactless manner and can, for example, be configured as a grating or a light barrier or include the grating or the light barrier. The digital input signal provided by the signal generator is a binary signal and is characterized by two defined states, which can in particular be given by two static potentials. As mentioned above, the two states are characterized by different voltage levels. This is a first state, in which the input voltage U IN is below a defined threshold value and the first state is often also referred to as a low level state, and relates to a second state in which the input voltage U IN The low level range is characterized by the input voltage U IN ≤U Low,max And the input current I IN ≤I Low,max The high level range is controlled by the input voltage U High,min ≤U IN ≤U High,max and input current I IN ≥I High,min To limit.

[0048] From a functional point of view, the circuit structure of the digital input circuit 100 proposed here can be roughly divided into three subcircuits 3 , 4 , 5 , which will be explained in more detail below.

[0049] The digital input circuit 100 comprises an input filter mechanism 6 which is connected to the input terminal 1 on the one hand and to the first subcircuit 3 on the other hand. The input filter mechanism 6 comprises a resistor R1 and a capacitor C1 connected downstream thereof, one electrode of which is connected to the ground GND1. The capacitor C1 is used in particular to make the input voltage U IN smoothing and also improving the electromagnetic compatibility of the digital input circuit 100. For example, the resistor R1 of the input filter mechanism 6 can have a resistance value of 1.5 kΩ.

[0050] The first subcircuit 3 includes: a first transistor T1, which forms a first current stabilization element of the digital input circuit 100 and has a control loop A1; and a first Zener diode Z1, which forms a first voltage stabilization element of the digital input circuit 100. In the embodiment shown here, the first transistor T1 is configured as a pnp transistor. In addition, the first subcircuit 3 has a resistor R2, which is arranged between the emitter of the first (pnp) transistor T1 and the input filter mechanism 6, and is thus connected to the input terminal 1 of the digital input circuit 100. For example, the resistor R2 can have a resistance value of 1.1 kΩ. The first subcircuit 3 has a non-ideal current output characteristic. Therefore, the first subcircuit does not provide a constant output current (at least) in the second state (in the high level state), but provides the following output current, which changes with the input voltage U IN The increase in the input current I IN increase.

[0051] The second subcircuit 4 includes: a second transistor T2, which forms a second current stabilization element of the digital input circuit 100 and has a control loop A2; and a second Zener diode Z2, which forms a second voltage stabilization element of the digital input circuit 100. In the embodiment shown here, the second transistor T2 is designed as an npn transistor. In addition, the second subcircuit 4 has a resistor R5, which connects the emitter of the second (npn) transistor T1 to the ground GND1. For example, the resistor R5 can have a resistance value of 1.1 kΩ, so that it is dimensioned like the resistor R2 of the first subcircuit 3. The second subcircuit 4 also has a non-ideal current output characteristic. Therefore, the second subcircuit (at least) also does not provide a constant output current in the second state (high level state), but provides the following output current, which changes with the input voltage U IN The increase in the input current I IN increase.

[0052] The digital input circuit 100 further comprises a high-ohmic resistor R3, via which the first subcircuit 3 is connected to the ground GND1, and whose resistance value is preferably ≥ 1 MΩ. In the present embodiment, the high-ohmic resistor R3 connecting the first subcircuit 3 to the ground GND1 has the following function, which ensures that (from 0 V) ​​at the input voltage U INWhen the resistor R3 is increased, the current can flow into the input terminal as a whole. Therefore, the resistor R3 is used as a "starting resistor" or "starting resistor". Specifically, the resistor R3 allows in this "on phase": the current can flow in the control loop A1 of the first transistor T1 as a whole. The current is in turn a prerequisite for the first subcircuit 3 to be able to provide current (via the collector of the first transistor T1). The current is in turn a prerequisite for the current to flow in the control loop A2 of the second transistor T2, which ultimately allows the current to flow into the second subcircuit 4 (via the collector-emitter path of the second transistor T2). Therefore, the resistor R3 is for the Figure 4 Although leakage currents can ensure that current flows in the control loop A1 of the first transistor T1 in the above-mentioned “on phase” even without the resistor R3 , this is usually unreliable and therefore not feasible in practice.

[0053] In the present case, the third subcircuit 5 is designed to determine the logic state of the input signal, which is supplied to the digital input circuit 100 via the input 1 and thus also determines the logic state of the digital input circuit 100. The third subcircuit 5 of the input circuit 100 is connected to the output 2, via which the output voltage U OUT Output. The third subcircuit 5 includes a first resistor R4 and a second resistor R6, wherein the first resistor is connected to the collector of the first transistor T1. The second resistor R6 has a first terminal connected to the output terminal 2 and a second terminal connected to the ground GND2. In addition, the third subcircuit 5 includes a coupling element 7 to separate the first subcircuit 3, the second subcircuit 4 and the resistor R4 of the third subcircuit 5 from the resistor R6 and the output terminal 2. In the embodiment shown here, the coupling element 7 is set up to cause a complete current separation (that is, potential separation) between the first subcircuit 3, the second subcircuit 4 and the first resistor R4 of the third subcircuit 5 on one side and the second resistor R6 of the third subcircuit 5 and the output terminal 2 on the other side. Therefore, the first subcircuit 3, the second subcircuit 4 and the first resistor R4 of the third subcircuit 5 are formed on the primary side of the digital input circuit 100, while the output terminal 2 and the second resistor R6 are arranged on the secondary side of the digital input circuit 100.

[0054] In the exemplary embodiment shown here, the coupling element 7, which enables a signal transmission from the primary side to the secondary side, is designed as an optocoupler, which has a light-emitting diode 70 on the primary side and a phototransistor 71 on the secondary side. The phototransistor 71 has an emitter in a manner known per se, which is connected to the ground GND2 via a resistor R6 and is also connected to the output 2 of the digital input circuit 100.

[0055] In this case, the first resistor R4 of the third subcircuit 5 ensures, on the one hand, the required switching threshold of the coupling element 7, which is in the form of an optocoupler, and, on the other hand, limits the current through the light-emitting diode 70 of the optocoupler (in the high-level range) to the value for which the optocoupler is designed (e.g., to a current of 1 mA). Finally, the current flowing through the resistor R4 also contributes to the fact that the digital input circuit 100 is capable of switching at an input current I of 1.5 mA. IN According to the IEC 61131-2 standard, this is required for DC 24V type 3 inputs as long as the input voltage is between 5V and 11V.

[0056] The input voltage U IN The identification of being in the low level range (first state of the digital input circuit 100) or in the high level range (second state of the digital input circuit 100) is achieved by means of the coupling element 7 and the resistor R4 connected in parallel therewith, which from a functional point of view forms a threshold element. From a functional point of view, the Zener diode Z2 of the second subcircuit 4 and the resistor R4 together form a voltage divider, wherein the Zener diode Z2 provides the voltage reference. The resistor R4 is dimensioned so that if for the input voltage U IN Applicable: U IN ≥U High,min , then the current flows through the light-emitting diode 70 of the coupling element 7 which is currently designed as an optocoupler. For example, the resistor R4 can have a resistance value of 2 kΩ. IN = U High,min To ensure this, in practice, the U IN < U High,min The high state is already recognized when (ie in the transition region). Then, the collector-emitter path of the phototransistor 71 becomes conductive, so that the corresponding output signal U can be provided at the output terminal 2. OUT , the output signal indicates the second state (high level state). Otherwise, the corresponding output signal U is provided at the output terminal 2. OUT , the output signal represents the first state (low level state).

[0057] The galvanic separation described above has the advantage that the output 2 or the components connected thereto can be protected from damage and errors caused thereby in the event of an overvoltage. In an alternative embodiment, it is also possible, for example, to replace the coupling element 7, which is currently designed as an optocoupler, with a transistor pole. This provides a digital input circuit 100 in a non-potentially separated embodiment.

[0058] The first and second subcircuits 3, 4 form two current sources (the second subcircuit 4 can also be referred to as a current sink), which are designed and interconnected in such a way that the non-ideal current output characteristics of the first subcircuit 3 and the non-ideal current output characteristics of the second subcircuit 4 can at least partially compensate each other in the second state (i.e. in the high level range or at least in a part of the high level range). The first subcircuit 3 and the second subcircuit 4 are connected in a cross-connected manner in this case. Here, the base of the transistor T1 of the first subcircuit 3 (forming part of the control loop A1 of the transistor T1) is connected to the collector of the bipolar transistor T2 of the second subcircuit 4. In addition, the base of the bipolar transistor T2 of the second subcircuit 4 (forming part of the control loop A2 of the transistor T2) is connected to the collector of the bipolar transistor T1 of the first subcircuit 3 via a resistor R4.

[0059] During operation of the digital input circuit 100 and receipt of an input signal in the high level range or at least in a part of the high level range, the current flows from the first subcircuit 3 to the third subcircuit 5, by means of which the input signal U IN logical state. Compensation of the non-ideal current output characteristics of the two sub-circuits 3 and 4 is achieved in the following manner: the current flowing through the first Zener diode Z1 is essentially composed of the stabilized current of the second sub-circuit 4, and the current flowing through the second Zener diode Z2 is essentially composed of the stabilized current of the first sub-circuit 3. The good mutual stability of the currents of the two sub-circuits 3 and 4 and thus the total input current of the input circuit 100 is based in this circuit architecture: the currents of the Zener diodes Z1 and Z2 and thus also the voltages of the Zener diodes Z1 and Z2 remain stable. If the Zener diodes Z1 and Z2 are located in their respective stable regions, the mutual stability of the currents of the two sub-circuits 3 and 4 is maximum. The currents of the two control loops A1 and A2 only account for a small part of the currents of the two sub-circuits 3 and 4 in the second state (high level range). The transistor T2 of the second sub-circuit 4 can control the base current I of the transistor T1 of the first sub-circuit 3 in the low level range. B,T1 On the contrary, the transistor T1 of the first sub-circuit 3 can control the base current I of the transistor T2 of the second sub-circuit 4 in the low level range. B,T2 In the high level range, the transistors T1 , T2 control in particular the current through the Zener diodes Z1 , Z2 of the respective other subcircuit 3 , 4 .

[0060] In the logic high level range that characterizes the second state of the digital input circuit 100, the Zener diode Z1 of the first subcircuit 3 and the Zener diode Z2 of the second subcircuit 4 respectively operate in their stable regions. This means that the current of the first subcircuit 3 basically flows through the Zener diode Z2 of the second subcircuit 4 in this state. If the resistor R3 is selected to be large enough, the current flowing through the Zener diode Z1 of the first subcircuit 3 almost completely flows into the second subcircuit 4 in this state. For example, the resistor R3 can have a resistance value of 1 MΩ. However, before the two Zener diodes Z1 and Z2 operate in their respective stable regions, especially in the transition section of the Zener diodes Z1 and Z2 from the resistance band to the conduction region, the current of the two subcircuits 3 and 4 has almost completely flowed through the Zener diodes Z1 and Z2 of the corresponding other subcircuit 3 and 4. By connecting the first subcircuit 3 and the second subcircuit 4 in sequence in a cross-connection, at least when the input signal U IN In the high level range (the second state of the digital input circuit 100 ), a substantially constant current of the respective other subcircuit 3 , 4 flows through the two Zener diodes Z1 , Z2 of the first and second subcircuit 3 , 4 , respectively. IN This measure makes it possible to minimize the current increase ΔI in the high-level range, so that an input current-input voltage characteristic curve change of the digital input circuit 100 can be obtained, which approximately corresponds to the input current-input voltage characteristic curve according to Figure 1 By minimizing the current increase ΔI in the high-level range, which preferably tends to zero with the circuit architecture described here, the power loss of the digital input circuit can be minimized in an advantageous manner.

[0061] An important advantage of the circuit architecture described here is that when Zener diodes Z1, Z2 are used for the first subcircuit 3 and the second subcircuit 4, their dimensions can be selected very simply so that at least for an input signal U in the high level range IN In terms of the current flowing through the two Zener diodes Z1, Z2, a sufficiently large current flows so that the two Zener diodes can be operated in their stable region or at least close to the region. The Zener diodes do not need to significantly increase the input current I in the high level range. IN This is achieved in the case of Figure 3 This is the case in the case of the digital input circuit 100 ′ and the Zener diode Z1 ′ of the voltage regulator provided therein when operated in the stable region.

[0062] Another advantage of operating the Zener diodes Z1, Z2 of the first subcircuit 3 and the second subcircuit 4 in their stable region is that their influence on the current of the first subcircuit 3 and the second subcircuit 4 due to component-related tolerances is also minimized. If the Zener diodes Z1, Z2 of the two subcircuits 3, 4 are operated in their stable region and the series resistor R3 of the Zener diode Z1 of the first subcircuit 3 is selected to be as large as possible (for example R3=1 MΩ as described above), the current increase ΔI is therefore minimal. For example, the two Zener diodes Z1, Z2 can have a breakdown voltage of 2.7V.

[0063] Input current I IN The temperature influence of can be minimized by a suitable design of the first subcircuit 3 and the second subcircuit 4. For example, for this purpose, Zener diodes Z1, Z2 with a negative temperature coefficient can be used, so that the Zener diodes at least partially offset the likewise negative temperature coefficient of the base-emitter voltage of the transistors T1, T2. In other words, this means that the temperature-dependent voltage changes of the Zener diodes Z1, Z2 and the base-emitter voltages of the transistors T1, T2 of the first and second subcircuits 3, 4 can be relatively well compensated.

[0064] Alternatively, it is also possible to achieve an equalization of the temperature coefficients of the base-emitter voltages of the transistors T1 , T2 by adding a respective conventional diode in series to the Zener diode Z1 of the first subcircuit 3 and the Zener diode Z2 of the second subcircuit 4 .

[0065] The significant advantages of the circuit architecture described here are in particular:

[0066] - simple and low-cost realizability,

[0067] - its applicability to all types of digital input circuits 100 according to IEC61131-2 (Types 1, 2 and 3),

[0068] - its suitability for digital input circuits 100 that sink and source current,

[0069] - its applicability to digital input circuits 100 with and without potential separation, and

[0070] - their suitability for safety-related applications, in particular in safety switching devices for fail-safe disconnection of technical installations or in I / O modules.

[0071] The digital input circuit 100 implemented by means of discrete components has been described above. Alternatively, the digital input circuit 100 having this circuit architecture can also be implemented by an integrated circuit in an IC, in particular an ASIC.

[0072] In another embodiment, it is also possible to provide for detecting the input signal U IN The third subcircuit 5 of the logic state can also be accommodated in a recessed manner in a separate device unit.

Claims

1. A digital input circuit (100) for receiving a digital input signal of a signal generator, the digital input circuit comprising: An input terminal (1), via which an input signal can be supplied to a digital input circuit (100), wherein when the input signal reaches or falls below a lower threshold, the digital input circuit (100) occupies a first state, and when the input signal reaches or exceeds an upper threshold, the digital input circuit (100) occupies a second state; A first subcircuit (3), the first subcircuit having at least one current stabilization element with a control loop (A1) and having at least one voltage stabilization element, wherein the first subcircuit (3) has a non-ideal current output characteristic at least in a second state; and A second subcircuit (4), the second subcircuit having at least one current stabilization element with a control loop (A2) and at least one voltage stabilization element, wherein the second subcircuit (4) has a non-ideal current output characteristic at least in a second state, The invention is characterized in that the first subcircuit (3) and the second subcircuit (4) are designed and interconnected so that at least in the second state or at least in a part of the second state, the current flowing through the voltage stabilizing element of the first subcircuit (3) is substantially composed of the stabilized current of the second subcircuit (4), and the current flowing through the voltage stabilizing element of the second subcircuit (4) is substantially composed of the stabilized current of the first subcircuit (3), so that the non-ideal current output characteristics of the first subcircuit (3) and the non-ideal current output characteristics of the second subcircuit (4) are substantially compensated at least in the second state, and the digital input circuit (100) has a high-ohmic resistor (R3), the first subcircuit (3) is directly connected to the ground (GND1) via the high-ohmic resistor, and the resistance value of the high-ohmic resistor is ≥750 kΩ.

2. The digital input circuit (100) according to claim 1, characterized in that: The Zener diodes (Z1, Z2) of the first subcircuit (3) and the second subcircuit (4) are operated in their stable region in the second state.

3. The digital input circuit (100) according to claim 1 or 2, characterized in that: The resistance value of the high ohm resistor is ≥ 1MΩ.

4. The digital input circuit (100) according to claim 1 or 2, characterized in that: The current stabilizing element of the first subcircuit (3) is formed by a bipolar transistor (T1), which has a base, an emitter and a collector.

5. The digital input circuit (100) according to claim 4, characterized in that: The current stabilizing element of the first subcircuit (3) is formed by a pnp transistor.

6. The digital input circuit (100) according to claim 4, characterized in that: The current stabilizing element of the second subcircuit (4) is formed by a bipolar transistor (T2) having a base, an emitter and a collector.

7. The digital input circuit (100) according to claim 6, characterized in that: The current stabilizing element of the second subcircuit (4) is formed by an npn transistor.

8. The digital input circuit (100) according to claim 6, characterized in that: The first and second subcircuits (3, 4) are interconnected such that the base of the bipolar transistor (T1) of the first subcircuit (3) is connected to the collector of the bipolar transistor (T2) of the second subcircuit (4).

9. The digital input circuit (100) according to claim 6, characterized in that: The first and second subcircuits (3, 4) are interconnected such that the base of the bipolar transistor (T2) of the second subcircuit (4) is connected to the collector of the bipolar transistor (T1) of the first subcircuit (3).

10. The digital input circuit (100) according to claim 1 or 2, characterized in that: The digital input circuit (100) has a third subcircuit (5), which is designed to identify the logic state of the digital input circuit (100) and is connected to an output terminal (2), via which an output signal can be output.

11. The digital input circuit (100) according to claim 10, characterized in that: The third subcircuit (5) has a coupling element (7) which is designed to couple the input (1) to the output (2) and a threshold value element which is connected in parallel therewith and is designed to provide a switching threshold value for the coupling element (7).

12. The digital input circuit (100) according to claim 11, characterized in that: The threshold element is configured as a resistor (R4).

13. The digital input circuit (100) according to claim 1 or 2, characterized in that: The Zener diodes (Z1, Z2) of the first and second subcircuits (3, 4) have a negative temperature coefficient.

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