Reverse engineering data analysis system, integrated circuit component data processing tool and method

Abstract

Various embodiments of a reverse engineering data analysis system, an integrated circuit component data processing tool and methods thereof are described herein. In one such embodiment, an integrated circuit (IC) reverse engineering data management system for processing IC component data extracted from a target IC is described, the system comprising: a data storage device operable to store a data structure comprising a plurality of extracted IC component data nodes, the IC component data nodes representing a plurality of IC components of a corresponding target IC and connectivity between the plurality of IC components; a graphical user interface (GUI); and a digital data processor operable on the data structure: to present a dynamic graph of the data nodes via the GUI; to graphically migrate at least some of the data nodes on the dynamic graph according to their connectivity with other nodes, wherein the connected nodes are attractively displaced relative to each other, so that the migrated nodes gradually aggregate with related nodes to define different IC component clusters, the different IC component clusters representing different groups of related IC components of the target IC, and the unconnected nodes are repulsively displaced to gradually distance themselves from the unconnected nodes. Various related methods, processes, systems and computer-readable media are also described.

Description

Technical Field

[0001] The present disclosure relates to reverse engineering (RE) tools and systems, and more particularly to reverse engineering data analysis systems, integrated circuit (IC) component data processing tools and methods thereof. Background Art

[0002] Understanding the functionality of an integrated circuit (IC) (e.g., a digital IC) starting from a finished device can be challenging. For example, modern digital IC designs are often created using highly automated processes. For example, modern digital IC designs are often designed by writing a high-level description of their functionality in a hardware description language, and then synthesizing the high-level description to a logic gate level. This approach, along with the increasing use of libraries of previously designed circuit sub-blocks (e.g., hard and / or soft "macros"), can enable the routine creation of a variety of gate designs.

[0003] Highly automated processing (also known as auto-routing) typically includes software programs that automatically place electronic components in a space-efficient manner, which may not necessarily result in a logically ordered or visually intuitive circuit layout. As a result, circuit components representing the same functional block can have different layouts.

[0004] While IC reverse engineering techniques have been developed to reconstruct the low-level netlist (also known as gate, raw or cell-level netlist) of an IC with a reasonable degree of automation and accuracy, organizing and analyzing these netlists into functional, modular and / or hierarchical blocks currently still largely relies on the efforts of a large number of expert personnel, which is not only time-consuming but also cost-inefficient.

[0005] This background information is provided to reveal information that the applicant believes may be relevant. No admission or interpretation is made that any of the foregoing information constitutes prior art or forms part of the common general knowledge in the relevant field. Summary of the invention

[0006] The following presents a brief summary of the general inventive concepts described herein to provide a basic understanding of some aspects of the present disclosure. This summary does not describe the present disclosure in detail. This document is not intended to limit the important and core components of the embodiments of the present disclosure or to define the scope except as explicitly or implicitly described in the following description and claims.

[0007] There is a need for a reverse engineering data analysis system, integrated circuit component data processing tool and method thereof that overcomes some of the shortcomings of the known techniques, or at least provides a useful alternative thereto. Some aspects of the present disclosure provide examples of such systems and methods. For example, in some embodiments, a system and method are provided to facilitate computational organization, analysis and / or classification of IC components of an IC into functional, modular and / or hierarchical blocks.

[0008] According to one aspect, an integrated circuit (IC) reverse engineering data management system for processing IC component data extracted from a target IC is provided, the system comprising: a data storage device operable to store a data structure comprising a plurality of extracted IC component data nodes, the IC component data nodes representing a plurality of IC components of a corresponding target IC and connectivity between the plurality of IC components; a graphical user interface (GUI); and a digital data processor operable on the data structure to: present a dynamic graph of the data nodes via the GUI; and to graphically migrate at least some of the data nodes on the dynamic graph according to their connectivity with other nodes, wherein connected nodes are attractively displaced relative to each other so that the migrated nodes gradually aggregate with related nodes to define different IC component clusters, the different IC component clusters representing different groups of related IC components of the target IC, while unconnected nodes are repulsively displaced to gradually distance the unconnected nodes from each other.

[0009] In one embodiment, the data structure also associates an initial physical position of each of the extracted IC component data nodes based on the extracted physical IC layout of the target IC; wherein the dynamic graph is initially presented based on each of the initial physical positions based on the extracted physical IC layout; and wherein at least some of the data nodes are initially migrated from their respective initial physical positions in a graphical manner.

[0010] In one embodiment, the digital data processor is further operable to graphically migrate the at least some of the data nodes as a function of distances between the data nodes.

[0011] In one embodiment, the distance function comprises a linear attraction function for connected nodes.

[0012] In one embodiment, the distance function comprises a logarithmic attraction function for connected nodes.

[0013] In one embodiment, the attraction function is inverted within the halo distance from any of the connected nodes to reduce node overlap.

[0014] In one embodiment, the distance function further comprises a repulsive force component applied between each of the at least some data nodes within a threshold repulsive distance to gradually distance any of the unconnected nodes within the threshold repulsive distance.

[0015] In one embodiment, the digital processor is operable to graphically migrate the at least some of the data nodes based on a damped force directed process.

[0016] In one embodiment, the data structure comprises a netlist.

[0017] In one embodiment, the digital processor is further operable to graphically present the connectivity for selection of the node by visually presenting cluster connections of a selected cluster of IC components.

[0018] In one embodiment, different IC component clusters represent different IC functional groups.

[0019] In one embodiment, the system further comprises an IC component extraction tool that automatically extracts the extracted IC component data nodes from one or more digital images of the target IC.

[0020] In one embodiment, the system further comprises an IC imaging device for imaging the target IC and generating the one or more digital images.

[0021] In one embodiment, the digital data processor is further operable to present the dynamic graph as an interactive map of the nodes and implement a digital input representation of a selected node through the map based on the clusters to update the data structure accordingly.

[0022] According to another aspect, a non-temporary computer-readable medium for managing extracted integrated circuit (IC) reverse engineering (RE) data and having computer executable instructions stored thereon is provided: to access a stored data structure, the stored data structure including a plurality of extracted IC component data nodes, the IC component data nodes representing a plurality of IC components of a corresponding target IC and connectivity between the plurality of IC components; presenting a dynamic graph of the data nodes through a graphical user interface (GUI); and iteratively calculating the displacement of at least some of the data nodes based on their connectivity with other nodes, wherein connected nodes are attractively displaced relative to each other, and unconnected nodes are repulsively displaced relative to each other; and graphically migrating at least some of the data nodes on the dynamic graph based on the iterative calculation, so that the migrated nodes gradually aggregate with related nodes to define different IC component clusters, the different IC component clusters representing different groups of related IC components of the target IC.

[0023] In one embodiment, the stored data structure also associates an initial physical position of each of the extracted IC component data nodes based on an extracted physical IC layout of the target IC; wherein the dynamic graph is initially presented based on each of the initial physical positions based on the extracted physical IC layout; and wherein at least some of the data nodes are initially migrated from their respective initial physical positions in a graphical manner.

[0024] In one embodiment, the computer readable medium further comprises instructions to calculate the attractive displacement of the at least some of the data nodes as a function of the distance between the data nodes.

[0025] In one embodiment, the distance function comprises a linear attraction function for connected nodes.

[0026] In one embodiment, the distance function comprises a logarithmic attraction function for connected nodes.

[0027] In one embodiment, the attraction function is inverted within the halo distance from any of the connected nodes to reduce node overlap.

[0028] In one embodiment, the distance function further comprises a repulsive force component applied between each of the at least some data nodes within a threshold repulsive distance to gradually distance any of the unconnected nodes within the threshold repulsive distance.

[0029] In one embodiment, the computer readable medium further comprises instructions to iteratively calculate the displacement based on an iterative damping force vectoring process applied between the at least some of the nodes.

[0030] In one embodiment, the data structure comprises a netlist.

[0031] In one embodiment, the computer readable medium further comprises instructions to graphically present the connectivity for selection of the node by visually presenting cluster connections of a selected IC component cluster.

[0032] In one embodiment, different IC component clusters represent different IC functional groups.

[0033] In one embodiment, the computer readable medium further comprises instructions for extracting the extracted IC component data nodes from one or more digital images of the target IC.

[0034] In one embodiment, the computer readable medium further comprises instructions to present the dynamic graph as an interactive map of the nodes and to implement a digital input representation of a selected node through the map based on the clusters to update the data structure accordingly.

[0035] According to another aspect, a computer-implemented process for managing integrated circuit (IC) reverse engineering (RE) data is provided, the process comprising: accessing a stored data structure comprising a plurality of extracted IC component data nodes, the IC component data nodes representing a plurality of IC components of a corresponding target IC and connectivity between the plurality of IC components; presenting an interactive graph of the data nodes through a graphical user interface (GUI), wherein the data stored for each of the data nodes can be graphically accessed and edited through the interactive graph; iteratively calculating the displacement of at least some of the data nodes based on their connectivity with other nodes, wherein connected nodes are attractively displaced relative to each other, and unconnected nodes are repulsively displaced relative to each other; graphically migrating the at least some of the data nodes on the interactive graph based on the iterative calculation, so that the migrated nodes gradually aggregate with related nodes to define different IC component data node clusters, the different IC component data node clusters representing different groups of related IC components of the target IC; and receiving selective data node edits for a given group of related IC components by digitally selecting a given data node cluster on the interactive graph.

[0036] In one embodiment, the stored data structure also associates an initial physical position of each of the extracted IC component data nodes based on an extracted physical IC layout of the target IC; wherein the dynamic graph is initially presented based on each of the initial physical positions based on the extracted physical IC layout; and wherein at least some of the data nodes are initially migrated from their respective initial physical positions in a graphical manner.

[0037] In one embodiment, iteratively calculating comprises calculating said displacement of said at least some of the data nodes as a function of distances between the data nodes.

[0038] In one embodiment, the distance function comprises at least one of a linear attraction function or a logarithmic attraction function for connected nodes.

[0039] In one embodiment, the data structure comprises a netlist.

[0040] In one embodiment, different IC component clusters represent different IC functional groups.

[0041] Other aspects, features and / or advantages will become more apparent from a reading of the non-limiting description of specific embodiments of the invention given by way of example only with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] By way of example only, several embodiments of the present disclosure will be provided with reference to the accompanying drawings, in which:

[0043] Figure 1 is a schematic diagram of a reverse engineering data analysis system, integrated circuit (IC) component data presentation and its organization tool according to one embodiment;

[0044] Figure 2 is an exemplary screen shot of an initially extracted IC circuit layout image representing the IC circuit layout image that will be Figure 1 The system handles reverse engineering of IC components to physical IC layout;

[0045] Figure 3A and 3B yes Figure 2 illustrative screenshots of various portions of an extracted IC circuit layout image of FIG. 1 , showing inter-component connections (eg, flying wires) between a relatively small number and a large number of manually selected components, respectively;

[0046] Figure 4A , 4B and 4C are exemplary screen shots showing the execution of Figure 1 10, 50 and 150 iterations of the system's automatic visual IC component aggregation tool Figure 2 Sequential evolution of the extracted IC component images;

[0047] Figure 5A and 5B is from Figure 4C An exemplary close-up screenshot taken in the lower portion of the screenshot of provides a close-up view of various clusters that were automatically migrated to the area with the aid of the clustering tool, wherein Figure 5B Further shown are the aggregated inter-component connections, which exhibit enhanced local connectivity;

[0048] Figure 6 Once by Figure 1 The system from Figure 2 An exemplary screenshot of the initial IC layout of FIG. 1 , the IC buffer (shown within the selection box) and the associated XOR gate clusters connected thereto;

[0049] Figure 7 Once by Figure 1 The system from Figure 2 An exemplary screenshot of a cluster group of 397 combinatorial logic instances with only 8 inputs and 8 outputs, clustering an initial IC layout of FIG.

[0050] Figure 8 is an exemplary screen shot of a user interface that can be used to modify Figure 1 Different functional parameters of the system's automatic visual IC component clustering tool.

[0051] For simplicity and clarity, elements in several of the drawings are shown and are not necessarily drawn to scale. For example, to facilitate understanding of the various presently disclosed embodiments, the dimensions of some elements in the drawings may be emphasized relative to other components. Moreover, common and well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted to more clearly observe these different embodiments of the present disclosure. DETAILED DESCRIPTION

[0052] Various implementations and aspects of the specification will be described with reference to the details discussed below. The following description and accompanying drawings are intended to illustrate the specification and should not be construed as limiting the specification. Many specific details are described to fully understand the various implementations of the specification. However, in some cases, well-known or conventional details are not described to briefly discuss the implementation of the specification.

[0053] Various devices and processes will be described below to provide examples of implementations of the systems disclosed herein. The implementations described below do not limit any claimed implementations and any claimed implementations may cover processes or devices different from those described below. The claimed implementations are not limited to devices and processes having all the features of any one device or process described below, or are not limited to features common to all devices or processes described below. The devices or processes described below may not be implementations of any claimed subject.

[0054] In addition, numerous specific details are set forth to provide a comprehensive understanding of the implementations described herein. However, those skilled in the relevant art will appreciate that the implementations described herein may be practiced without these specific details. In other cases, well-known methods, processes, and components are not described in detail to avoid obscuring the implementations described herein.

[0055] In this specification, an element may be described as being "configured to" perform one or more functions or "configured for" such functions. Generally, an element configured to perform or configured for performing a function is capable of performing the function, or is suitable for performing the function, or is adapted to perform the function, or is operable to perform such a function, or is capable of performing the function.

[0056] It should be understood that for the purposes of this specification, the language of "at least one of X, Y, and Z" and "one or more of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items X, Y, and Z (e.g., XYZ, XY, YZ, ZZ, etc.). Similar logic can be applied to two or more items in any occurrence of the language of "at least one of..." and "one or more of...".

[0057] According to various embodiments, the systems and methods described herein provide various examples of reverse engineering data analysis systems and integrated circuit (IC) component data processing tools and methods thereof. For example, the systems and methods described herein include various computing tools and functions that, when used alone or in combination, can facilitate, accelerate and / or improve the laborious and time-intensive tasks of analyzing, characterizing, classifying and / or interpreting reverse engineering images of a target integrated circuit or portion thereof, for reconstructing the layout or design of such functional, hierarchical, structural and / or similar targets for further analysis, reporting and / or replication, for example. As will be further described below, the embodiments contemplated herein call for certain computing tools and processes that, when operating on extracted IC component data, such as operating on low-level netlists or similar data structures, can be used to effectively visually aggregate interrelated data nodes on various IC component graphs, facilitating identification of functional IC component groups and / or subgroups, related or similarly operable or interconnected IC component types and / or features, or similar graph node aggregations. When such data nodes are visually aggregated through an automatic IC component data node aggregation or grouping process, data node annotation, analysis, and / or classification can be more conveniently and / or accurately achieved, so that in some embodiments, for example, their interconnections can be easily observed, analyzed, and / or characterized. As will be readily appreciated by those skilled in the art, these and other uses, functions, and / or advantages of the systems and methods described herein will be further detailed below.

[0058] Now refer to Figure 1 An exemplary reverse engineering data analysis system is described according to some embodiments, and the system is generally represented by the number 100 herein. In this embodiment, the system generally includes a digital data processing system 102 having one or more digital data processors (not shown) for processing RE IC component data, such as RE IC data set 104. For example, the system 100 can be configured to access, interfere with, or directly obtain RE data through an IC imaging device or system 106. IC imaging devices that are readily understood in the art include, but are not limited to, scanning electron microscopes (SEMs), transmission electron microscopes (TEMs), focused and / or broad ion beam (FIB) imaging devices, atomic force microscopes (ATMs), optical microscopes, or similar devices.

[0059] The image data acquired and / or accessed from these imaging devices 106 can then be processed by an automatic IC data extraction tool 108, for example, resulting in the automatic extraction of low-level IC component data, wherein the low-level IC component data represents the imaged IC components and identifies such components by type, structure, connection and interconnection or similar qualifiers. In one such embodiment, the IC data extraction tool 108 can result in the compilation of the REIC data set 104, for example in the form of a low-level netlist or other similar data structure, wherein the other similar data structure represents each extracted IC component as a series of interconnected IC component data nodes, each IC component data node having an initial IC layout position associated therewith and layout connection information consistent with the imaged IC layout. Other related, extracted and / or progressively acquired or derived layout and IC component information can be stored in or associated with such data structures, for example, to identify different IC component functions, interactions, functional groups, features, etc. These data structures are very familiar to those skilled in the art and therefore do not need to be further described here.

[0060] In one embodiment, the system 100 is then configured to read and process an input data set 104, which will typically contain low-level information representing the target reverse engineering IC, such as a netlist. Similarly, the data set can be generated by an integrated circuit extraction verification system or a similar extraction tool 108. For example, the data set can at least partially contain, for example, extracted component layouts (placement / position of each component), their types, and interconnections between the pins of each component. As will be appreciated by those skilled in the art, different RE IC data set types, formats, and / or structures can also be considered, just as different information can be included for each data set node or some data set nodes from direct extraction and / or by manual input during the extraction and preliminary analysis / characterization process. As will be described in detail below, using the techniques described herein, for example, further RE IC component characterizations can be effectively and accurately generated through automated component data clustering techniques and dynamic and / or interactive data presentation and editing tools associated therewith.

[0061] In this regard and in accordance with one embodiment, an initial input graph may be constructed from an IC dataset, where the IC dataset is rendered to an engine 110 from information contained in the input dataset 104. This initial input graph may then be presented on an integrated or interface graphical user interface 112, where each vertex or node in the graph generally represents a component in a source IC, and in some implementations, the initial layout of the nodes in the graph is taken from the component layout in the source IC. It should be noted that while an initial graph rendering corresponding to known physical IC layout locations may be preferred in some implementations, other implementations may start with a randomized graph, or again from some other preset or specified initial rendering configuration, which is expected to provide better component visibility, aggregation efficiency, and / or information during visualization of subsequent graph iterations / component migrations. In other examples, the actual component locations on the target IC may not be known or stored in the accessed data structure, making it difficult to easily access an accurate physical depiction of the extracted IC layout.

[0062] In some examples, the connectivity of each node can also be extracted using information about the presence of interconnections between the pins of each component (e.g., stored in a connection table). In some embodiments, global networks are automatically excluded when building the connection table because the action of connecting to the same power supply does not generally indicate any type of functional relationship between two components. In addition, some chips have many different power domains. In this case, it is conceivable that the power supply connection can predict the functional relationship between the two components. In order to speed up the calculation of the connections between nodes, some embodiments store the node connections in an "adjacency matrix" implemented as a sparse table.

[0063] exist Figure 1 In the illustrated embodiment, the input graph is visualized in a window (or digital canvas) 114 located within the interactive user interface 112. Each node may be graphically represented on the canvas 114 by an icon or other visual identifier indicating the component type, including but not limited to an alphanumeric code, a label, an icon, a graphic, or a similar digital graphical identifier. Figure 2 An exemplary screen shot of an initially extracted IC circuit layout image representing the physical IC layout of a reverse engineered IC component to be processed by the system 100 is provided.

[0064] As mentioned above, connections between nodes may also be graphically represented by straight (colored) lines (also called "flight lines"). For example, colored flight lines may be colored according to the type of connection between components (i.e., input or output, power connection, etc.). Figure 3A and 3B Provided Figure 200143] Exemplary screenshots of various portions of an extracted IC circuit layout image of FIG. 10, showing, for example, inter-component connections (eg, flying wires) between a relatively small number and a large number of manually selected components, respectively.

[0065] like Figure 2 , 3A and 3B, the graphical user interface 112 of the system 100 can provide not only a graphical visualization of the extracted input graphics, but also dynamically and / or selectively (e.g., via interactive tool 120) access to extracted or exported IC layout data, such as flight line data as described above, and interactive access to stored IC component node data through a supplementary data set visualization window or portal, which provides access to various stored node information, such as node type, location, identification number, name, function, relationship to other nodes and / or identified functional groups, power connections, etc. As will be readily appreciated by those skilled in the art, other data types may be considered or alternatively considered without departing from the overall scope and nature of the present disclosure.

[0066] Continue to refer Figure 1 , the presented IC data set is then selectively processed through an IC data node aggregation process, which is generally referred to herein as a force-directed or similar process 116, to gradually migrate all of the selected IC data nodes from their respective initial physical positions on the graph based on their connectivity with other nodes. For example, in one embodiment, connected nodes are attractively displaced relative to each other, while unconnected nodes are repulsively displaced relative to each other, so that the migrated nodes are gradually aggregated with related nodes to define different IC component clusters representing different groups of related IC components of the target IC. Therefore, the IC component connection data allows the extracted IC data nodes to migrate from their initial positions (usually defined by their initial positions on the target IC) to be aggregated based on their actual physical IC component connections, so that in most cases, they are consistent with the functional or relationship attributes between the components.

[0067] In one example, if Figure 1 As shown, the layout of nodes within the graph is iteratively modified at 118 using a force-directed process 116 operating on the processing system 102. For example, the iterative process 118 can recalculate the layout of the initial graph using only information contained in the structure of the graph itself without relying on domain-specific knowledge to facilitate visualization, ultimate analysis, and / or classification of the extracted IC component data with little or no user intervention. Figure 4A , 4B and 4C respectively provide the results of performing, for example, 10, 50 and 150 iterations of the force-directed IC component data node aggregation process. Figure 2 Exemplary screenshots of the sequential evolution of an extracted IC component image.

[0068] The force-directed process as described herein can be used to efficiently aggregate related IC component data nodes for graph aggregation. Therefore, the force-directed process as described herein can be used to extract a list of functionally related IC components 122, or to present these functionally related IC components on the digital canvas 114 in a graphical manner at least, for interactive processing through, for example, a GUI tool 120. That is, these interactive tools 120 can be used to interactively process batch IC component data node characterization and / or classification, for example, by dynamically selecting aggregation or otherwise aggregating IC component nodes on an iterative graph presented on the canvas 114 and operating batch character assignment or similar functions of the GUI. As will be readily understood by those skilled in the art, other batch or aggregation-specific processing, classification and / or characterization tools may also be considered or considered alternatively. In this case, the RE IC data set 104 can be gradually updated and / or improved by iterative aggregation and / or operator analysis and / or interaction via the GUI 112, ultimately producing, for example, a more complete and comprehensive data set for further processing, analysis and / or assignment.

[0069] Known design layout optimization techniques common to IC design solutions generally seek to maximize circuit performance by minimizing the path lengths interconnecting various circuit elements, while ensuring that all networks are routed and while complying with imposed size and performance constraints. The final result can then be viewed and tested for compliance, and reset by adjusting certain layout parameters. In sharp contrast, the proposed embodiment involves the opposite problem, wherein, in reverse engineering, the initial placement of a set of components (a low-level netlist or similar IC data component data structure) of a target IC is known from data extraction using different imaging techniques, but the common group and item-by-item functionality of each component is previously unknown. Therefore, a force-directed drawing process as described herein is performed to at least partially automate and facilitate the analysis of these netlists into functionalized, modular and / or hierarchical blocks, thereby more clearly seeing and accessing the various IC layout operations, functions and features of the target IC. In this case, not only is the downstream aggregation of migrated IC component data nodes generally very beneficial to the extracted layout and the functional aspects of its components, but also how such data nodes are iterated on dynamic graphs and / or interactive graphs about other nodes and or clusters. To this end, the evolution of the force-directed process can provide valuable information beyond that provided by static endpoint graphs. Other optional interactive tools, such as single or bulk IC data component node pinning, displacement and / or reallocation, can dynamically influence the evolution of the migration graph and help to gain a deep understanding of the functional properties of the various IC components represented by the migrated IC component data nodes.

[0070] In some embodiments, and as described above, the space containing the graph (e.g., digital canvas 114) can be a 2-D Cartesian space, where each position is represented using a pair of numbers. For example, 32-bit integers can be used to represent positions in the graph to increase the speed of the clustering process described below, but more precise data types can also be used. In some embodiments, the space can be infinite and continuous; in other embodiments, the space can be a finite space in which periodic boundary conditions are used. In some other embodiments, a space with higher dimensions than a 2-D space can be used. For example, in a 2-D space, as further discussed below in an exemplary embodiment, a node on one side of a large, tightly converging group of nodes may encounter some difficulty in passing and opening up a path when it is necessary to reach the other side of the group. For example, expanding the dimensionality of the space to three or more dimensions will allow such nodes to more easily slide through tight clusters (slide behind or in front of tight clusters). Those skilled in the art will understand that these and other such considerations fall within the general scope and essence of the present disclosure.

[0071] In this Cartesian space, in some embodiments, each component can be associated with a given size, for example, 30 to 50 units in width and height. As will be readily appreciated by those skilled in the art, other relative size and / or dimension considerations may be addressed depending on the specific implementation of the graphics rendering and processing technology employed.

[0072] Typically, as described above, each pair of nodes in the connected extracted IC data structure will experience an attraction between them. For example, the attraction may be linear or logarithmic relative to the (graph) distance between the two nodes, but other functional forms may also be used. For example, using a logarithmic function may have the advantage of limiting the high accelerations and oscillations experienced by the component at the very beginning of the iteration. For example, this may be useful because the initial positions of the nodes (relative to the average size of the representative components) are usually spread out over a longer distance. For example, the initial node positions may be associated with the extracted node positions on the target IC layout and initially presented as such. In other embodiments and / or implementations of the same embodiment, the initial IC component data nodes may be associated and presented according to different sets of positions, for example, intentionally and / or randomly associated with them during or after the data extraction process, or again, applied to other structured but non-position-specific data structures or netlists, from a few examples. Therefore, although the initial dynamic graph may visually represent the physical layout of the target IC, other implementations may remove such representations, or may again not have ready access to such physical location information, and still perform the data note migration and aggregation techniques described herein.

[0073] In some embodiments, each node can also be excluded from all its local neighbors. The repulsive force can be a linear function of the distance between the nodes, but other functional forms can also be used. In such an embodiment, any node that is less than a specific threshold distance from another node is considered a "local neighbor". In some embodiments, the threshold distance can be 2000 units (as defined by the Cartesian graph environment), and can be, for example, user-adjustable. Using a distance threshold can speed up calculations because there is no need to calculate the repulsive force of nodes far away from each other (because the force is a function of the distance between the nodes, and the magnitude of the force experienced at a far distance can be ignored). It is observed that using such a threshold tends to reduce the amount of residual slow "drift" that can be observed at the end of the minimization process, for example. For example, other repulsive force options can be considered, in which non-connected node pairs are specifically identified and repel each other. Although this can effectively separate non-connected pairs at the beginning, the threshold repulsive distance, or the repulsive force function related to the distance that is quickly reduced again can avoid the rapid drift of unconnected components. Other features (such as graphic pinning or anchoring) as described below can solve some of these problems.

[0074] As described below, further optimizations or customizations may be included in the force-directed process. For example, in digital ICs, a network typically has one "driver" and many "drive" pins. The driver component outputs signals onto the network, and the drive component receives the output signals. Given this input / output asymmetry, in some embodiments, force calculations may also be asymmetric by having nodes representing driver components strongly attract nodes representing their drive components, but having drive instances weakly attract other drive instances on the same network. This can help break up large homogeneous clusters where the connections between nodes do not follow a regular pattern, for example.

[0075] In some embodiments, global scale parameters and offset parameters can also be used to apply linear transformations to all attractive and repulsive forces. For example, if attractive forces increase, the nodes will tend to be pulled tightly toward the center of gravity of the system. On the other hand, if repulsive forces increase, the system will tend to "explode" and the nodes will move quickly away from each other.

[0076] Thus, user-adjusted force parameters and customizations, such as those described above and / or other similar adjustments, may be interactively applied or adjusted (eg, via interactive tool 120) to increase the aggregation efficiency and speed at which a particular extracted IC layout may be processed.

[0077] As described above, the force-directed process can treat each node as occupying only a single point in space, although each node is typically drawn with a specific length and width on the screen canvas, which may cause nodes to overlap. Of course, when the operator is docked with the interactive canvas, it may be difficult to identify individual nodes and select individual nodes with a mouse or other interactive tool. To alleviate this situation, in some embodiments, a circular "halo" area can be defined around each node. In the example currently described, this area can be a default circle of 200 units in diameter, but the size can be user-adjustable. Using this method, when calculating the attractive force between connected nodes, if the remote connected node is within the defined halo distance, the sign of the calculated force will become negative (effectively causing repulsion rather than attraction), and, in a specific embodiment, the sign of the calculated force can be effectively changed from a logarithmic attraction function to an inverse (repulsive) linear function. Therefore, although the counterforce is still a function of distance, in this embodiment, the counterforce can become stronger (e.g., in an inverse linear manner rather than logarithmic, with a large multiplicative constant). Therefore, two nodes should not be so close as to overlap. In reality, most connected nodes will reach equilibrium somewhere inside the halo distance (depending on the number of connections) where the attractive and repulsive forces are locally balanced.

[0078] In an illustrative embodiment, a force-directed system is minimized using a damped dynamics approach that works by accelerating the system in the direction of the force. For example, in some embodiments, a "virtual" mass can be assigned to each particle (IC data node) and a force is applied to these particles according to Newton's second law of mechanics. In some embodiments, all components have unit mass, but other mass values ​​can be used for different components. For example, a component with a higher relative mass will experience less acceleration than a component with a smaller relative mass, which may be beneficial when seeking to customize a specific graphical target. For example, some target components can be attributed to a heavier relative mass, so the connecting node is preferably migrated thereto, and the heavier node experiences reduced relative motion. At one extreme, some nodes, groups or clusters can be effectively fixed on the graph (more or less equal to infinite mass) to avoid further migration of these nodes. This may be particularly useful when some nodes or clusters are accurately identified and annotated and do not need to be further migrated, thereby reducing the possibility that their further migration will affect or adversely interfere with the migration of a slower force-balanced cluster. These and other such functions and attributes can be easily considered in this context.

[0079] Using a damped dynamics approach, the applied forces drive changes in the acceleration of these "particles" as a function of "time", which in turn changes their velocities and their positions. The "time" variable here has no physical meaning in itself, it is just the quantity used to numerically solve the differential equations of motion, but rather represents the number of iterative steps taken by the process. After many iterations, the positions of these particles will tend to converge to an equilibrium or near-equilibrium clustered configuration. To simplify the force calculations, the position of each node is the point located at the center of the area of ​​the icon, marker, or identifier used to represent the position on the screen. Effectively, even though the nodes are displayed with areas, they are treated as if they were single point particles by the calculation process.

[0080] In this embodiment, each node is also subject to friction (or damping force or resistance), hence the term "damped dynamics", to limit the high velocities that some nodes can achieve during the minimization process. For example, friction can be modeled as a small force whose magnitude is proportional to the velocity of the node, but in the opposite direction of its velocity. Other damping functions can be considered, as will be readily appreciated by those skilled in the art.

[0081] The damped dynamics minimization process typically works by computing all the forces at all nodes in the graph and then solving Newton's equations of motion for each node. The standard procedure for solving these coupled differential equations on a computer is to break time into discrete intervals and then iteratively solve the equations of motion over these intervals.

[0082] In some embodiments, as described above, position updating is performed by numerically solving Newton's second law. First, vector summation is performed for all forces and used to calculate the acceleration of each component. Acceleration is integrated over time to generate the velocity of each component, and velocity is integrated over time to generate the position of each component. All methods of algorithms for integrating Newton's equations of motion (referred to as integrators) can be used. For example, these methods include but are not limited to Euler's algorithm, Verlet integrator (including Velocity Verlet algorithm), Leapfrog integrator, Runge-Kutta integrator, etc. It will be appreciated by those skilled in the art that these algorithms have different advantages and disadvantages, and more accurate or more stable algorithms may require more CPU resources. The correct balance between accuracy and efficiency may vary according to user requirements.

[0083] During each iteration of the force-directed minimization process, the force calculation and position update steps are iterated in a loop until the user determines that acceptable clustering has been achieved. Otherwise, if satisfactory results cannot be achieved, the iterative process can be stopped and restarted using different execution parameters. Alternatively, different iteration branches or paths can be implemented sequentially or simultaneously using different parameters, for example, once certain clusters are formed (and optionally fixed on the graph), while other clusters remain in active migration, and because of active migration, alternative parameters can produce more certain results.

[0084] That is, in some embodiments, the parameters that influence the computation may be updated at any time, even while the algorithm is looping. The parameter changes are then taken into account in the next full loop. In some embodiments, the program may run on a conventional CPU or a GPU, with the GPU potentially offering advantages in processing speed given the highly parallel GPU architecture.

[0085] For some configurations, the vector sum of the attractive forces will not be zero. The system can then gain momentum and continue to drift in one direction, even after the appropriate amount of clustering. There may also be persistent local oscillations, and groups of components orbiting each other. One way to mitigate these effects is to increase the magnitude of the friction forces. Other ways to account for these effects are to eliminate the center of mass drift at each iteration (or to sum the forces at each iteration and, if the sum is not zero, apply a small bias force to each component so that the sum becomes zero). Other methods of producing a fixed center of mass may also be employed.

[0086] Other optimization techniques may also be applied, such as, but not limited to, adaptive step size, using particle neighbor lists (i.e., Verlet lists), dividing the space into cells (i.e., using quadtrees (2D) or octrees (3D), etc.), or similar. Those skilled in the art will appreciate that a wide variety of optimization techniques may be applied to the described embodiments without changing the general nature of the present disclosure.

[0087] In some embodiments, the method can automatically make small random changes to force parameters to increase the probability that a node will find an equilibrium state. In other embodiments, a small random force can be added to each node to increase the probability that the system will find a lower local minimum. By adding and subtracting small random forces (i.e., equivalent to heating and quenching a physical system), a simulated annealing algorithm, for example, can be applied.

[0088] As will be appreciated by those skilled in the art, other techniques may be applied to cluster or migrate data nodes to more informative graph states. For example, the nodes in the graph may be moved as described in detail above to minimize the "energy" function represented by the forces experienced by each node. For example, different numerical minimization / optimization techniques may be used on the "energy" function depending on its characteristics. Local minimization methods may be used, including but not limited to methods such as steepest descent (SD), conjugate gradient (CG), quasi-Newton (QN) (i.e., BFGS, L-BFGS), etc. Global minimization methods may also be used, such as methods using similar stochastic optimization algorithms such as simulated annealing, to name just a few examples.

[0089] In some embodiments, the interactive user interface 112 may be similar to the interface of a movie playback application. For example, a large portion of the screen may be used to display nodes representing IC components and their locations. As the method continues to improve, it may also be updated in real time (or updated again for each defined number of iterations). In some embodiments, there may be "play" and "pause" buttons. Pressing the pause button temporarily stops screen updates and / or dynamic node migration iterations. Similarly, a button may be included to advance the minimization process through N iterations and automatically pause. In some embodiments, the user may control the camera lens, allowing the display to be panned or zoomed in or out at any time, even while the program is running. In some embodiments, a "jump back" feature is also provided, allowing the user to return to a previous state. In this case, in some embodiments, the user may change parameters and resume the program from any previous point in "time" (i.e., the previous "iteration"). Doing so may create a new "branch" state. The application may track branches and allow the user to switch to any branch on command. In some embodiments, the user may also choose to control the screen refresh rate. At this point, the screen will only refresh every N iterations, thereby increasing the speed at which the algorithm advances (in real time). These and other similar visualization and dynamic control functions and features may be considered without departing from the general scope and essence of the present disclosure.

[0090] In some embodiments, the user can select and move any number of nodes with the mouse at any time, even while the program is running. This immediately changes the absolute positions of the nodes. In the next iteration, the new positions are used in force calculations as usual. With this feature, the user can "pull apart" large homogeneous clusters of nodes to see if smaller clusters form.

[0091] In some embodiments, any number of nodes can be "pinned" or "unpinned" from the canvas at any time, even while the program is running. Pinned nodes participate in force calculations as usual, but their positions are not updated at all. This gives the impression that the pinned nodes are fixed to the canvas, while the unpinned nodes can move freely around them. This feature is useful if the user knows (perhaps through previous analysis) the function of one or more nodes. These nodes can be placed on the canvas away from other components and then pinned there. Those unpinned nodes that are related to functions in the pinned group tend to move quickly towards the pinned group, which makes them easy to spot.

[0092] In some embodiments, the canvas may be projected to the user using a virtual reality headset. Using a more inclusive viewing environment that provides this technology may make it easier to locate subtle clusters where a 2D screen projection may obscure them.

[0093] Example

[0094] Reference below Figures 2 to 8 An illustrative embodiment of an IC RE data management system as generally described above is described in which an exemplary RE IC data set is processed through an integrated GUI.

[0095] refer to Figure 2 , and an exemplary starting configuration of an input graph is shown according to an exemplary embodiment. The initial position of each node is taken from the layout of a previously imaged digital circuit schematic. As described above, the initial graphic position may or may not be directly related to its actual physical position on the corresponding IC layout. For example, this information may not be easily available in some implementations (e.g., when working from a netlist of components and their connections), or may not be suitable for informational presentations (e.g., multi-layer devices often result in illegible 2D maps), or again, random or other specified initial graphic options can result in faster convergence and / or provide greater cluster visibility during graph node migration, to name just a few examples. As will be readily appreciated by those skilled in the art, these and other such examples should be considered to fall within the general scope and nature of the present disclosure.

[0096] refer to Figure 3A and 3B , and according to an exemplary embodiment, a flight line showing the connection between the selected node and the rest of the circuit is shown. It can be easily observed that while the connected nodes generally represent functionally related IC components, they are not necessarily initially close to each other based on the input IC layout. Figure 3A Neutralizes a large selection of components Figure 3B This can be clearly seen in .

[0097] refer to Figures 4A to 4C , and according to an exemplary embodiment, in 10 iterations ( Figure 4A ), 50 iterations ( Figure 4C ) and 150 iterations ( Figure 4C ) is shown later Figure 2 The evolution of the position of the starting node.

[0098] refer to Figure 5A and 5B , and according to an exemplary embodiment, the connectivity between nodes of a series of clusters is shown. Figure 5A Shows Figure 4C A close-up of the bottom of the configuration shown in Figure 5B The connectivity between nodes is shown. It is observed that the clusters have high local connectivity.

[0099] refer to Figure 6 , and according to an exemplary embodiment, a cluster consisting of nodes representing XOR gates is shown, which is close to nodes representing buffers (boxed components) connected thereto.

[0100] Similarly, Figure 7 A large group of 397 connected nodes representing a component of combinatorial logic is shown. It is easy to observe that this group has a total of 8 inputs and 8 outputs, which can be efficiently drawn using different color-coded flight lines.

[0101] refer to Figure 8 , and according to an exemplary embodiment, a user interface 800 for changing the operating parameters of the method is shown. In the case where the computer has more than one available GPU, the platform parameter 802 controls the graphics processing unit (GPU) on which the program is executed. The redraw skip frame count parameter 804 controls the number of iterations to be run before refreshing the screen. The parameter set 806 (attractive / repulsive force table and attractive / repulsive force bias) adjusts parameters related to the bias and strength of attractive and repulsive forces. As described above, the halo parameter 808 sets the distance from the center of a component to its halo. The repulsive distance threshold parameter 810 sets a distance within which the repulsive force is set to zero between two components. The damping coefficient parameter 812 sets the friction coefficient that controls the amount of friction. The net fanout limit coefficient parameter 814 sets the minimum number of fanouts that a network may have before being excluded when building the connection table (global and local). Finally, the AF driver / drive weight parameter 816 linearly controls how strong the bias of the attractive force between the driver to the driven component and the driven to the driven component is. (Between 0 and 1. At 0, slave-to-slave connections are strongly attracted, at 0.5, there is no difference between driver-to-slave and slave-to-slave connections, and at 1.0, there is no attraction at all for driver-to-slave connections.)

[0102] As will be appreciated by those skilled in the art, while some exemplary screenshots of systems and methods in operation according to the embodiments described herein are provided above, other features, parameters, and visual attributes may be considered herein without departing from the overall scope and nature of the present disclosure.

[0103] That is, although various embodiments are described in the present disclosure for illustrative purposes, such description is not intended to be limited to these embodiments. On the contrary, the applicant's teachings described and illustrated herein encompass various substitutions, modifications, and equivalents without departing from the overall scope defined in the embodiments and the appended claims. No particular order of steps or stages of the methods or processes described in this disclosure is intended or implied, except to the extent necessary or inherent to the process itself. In many cases, the order of the processing steps can be changed without changing the purpose, effect, or input of the described method.

[0104] The information shown and described in detail herein is fully capable of achieving the above-mentioned purpose of the present disclosure, i.e., the current preferred embodiment of the present disclosure, and therefore represents the subject matter of the present invention's broad consideration. The scope of the present disclosure fully encompasses other embodiments that may become apparent to those skilled in the art, and is therefore limited only by the appended claims, wherein unless explicitly stated, reference to an element in the singular is not intended to mean "one and only one", but "one or more". All structural and functional equivalents of the components of the above-mentioned preferred embodiments and additional embodiments considered by those of ordinary skill in the art are expressly incorporated by reference herein and are intended to be covered by the present claims. In addition, there is no requirement that a system or method solve every problem that the present disclosure seeks to solve, because these problems are included in the present claims. In addition, regardless of whether an element, component, or method step is explicitly stated in a claim, the elements, components, or method steps in the present disclosure are not intended to be dedicated to the public. However, without departing from the spirit and scope of the present disclosure as set forth in the appended claims, various changes and modifications may be made to the form, material, workpiece, and manufacturing material details, which are obvious to those skilled in the art and are also included in the present disclosure.

Claims

1. An integrated circuit reverse engineering data management system for processing integrated circuit component data extracted from a target integrated circuit, the system comprising: a data storage device operable to store a data structure comprising a plurality of extracted integrated circuit component data nodes, the integrated circuit component data nodes representing a plurality of integrated circuit components of a corresponding target integrated circuit and connectivity between the plurality of integrated circuit components; A graphical user interface; as well as a digital data processor operable on the data structure to: present a dynamic graph of the data nodes via the graphical user interface; At least some of the data nodes on the dynamic graph are graphically migrated based on connectivity between the data nodes and other nodes, wherein connected nodes are attractively displaced relative to each other so that the migrated data nodes are clustered with related nodes to define different integrated circuit component clusters, wherein the different integrated circuit component clusters represent different groups of related integrated circuit components of a target integrated circuit, and unconnected nodes are repulsively displaced to distance themselves from the unconnected nodes.

2. The system according to claim 1, characterized in that The data structure also associates an initial physical location of a data node of each extracted integrated circuit component based on an extracted physical integrated circuit layout of a target integrated circuit; wherein the dynamic graph is initially presented based on each of the initial physical locations based on the extracted physical integrated circuit layout; and wherein at least some of the data nodes are initially migrated from their respective initial physical locations in a graphical manner.

3. The system according to claim 1 or 2, characterized in that: The digital data processor is further operable to graphically migrate the at least some of the data nodes as a function of distances between the data nodes.

4. The system according to claim 3, characterized in that The distance function includes a linear attraction function for connecting nodes.

5. The system according to claim 3, characterized in that The distance function includes a logarithmic attraction function for connecting nodes.

6. The system according to claim 4 or 5, characterized in that: The attraction function is inverted within a halo distance from any of the connected nodes to reduce node overlap.

7. The system according to claim 3, characterized in that The distance function also includes a repulsive force component applied between each of the at least some data nodes within a threshold repulsive distance to distance any of the unconnected nodes within the threshold repulsive distance.

8. The system according to claim 1, characterized in that The digital data processor is operable to graphically migrate the at least some of the data nodes based on a damped force directed process.

9. The system according to claim 1, characterized in that The data structure includes a netlist.

10. The system according to claim 1, characterized in that The digital data processor is further operable to graphically present the connectivity for selection of the node by visually presenting cluster connections of a selected cluster of integrated circuit components.

11. The system according to claim 1, characterized in that The different integrated circuit component clusters represent different integrated circuit functional groups.

12. The system according to claim 1, characterized in that The system further includes an IC component extraction tool that automatically extracts the extracted IC component data nodes from one or more digital images of the target IC.

13. The system according to claim 12, characterized in that The system further includes an integrated circuit imaging device for imaging the target integrated circuit and generating the one or more digital images.

14. The system according to claim 1, characterized in that The digital data processor is further operable to present the dynamic graph as an interactive map of the nodes and implement a digital input representation of a selected node through the map based on the integrated circuit component cluster to update the data structure accordingly.

15. A non-transitory computer readable medium for managing extracted integrated circuit reverse engineering data and having computer executable instructions stored thereon to: accessing a stored data structure, the stored data structure comprising a plurality of extracted integrated circuit component data nodes, the integrated circuit component data nodes representing a plurality of integrated circuit components of a corresponding target integrated circuit and connectivity between the plurality of integrated circuit components; Presenting a dynamic graph of the data nodes through a graphical user interface; as well as iteratively calculating displacements of at least some of said data nodes according to their connectivity with other nodes, wherein connected nodes are attractively displaced relative to each other and unconnected nodes are repulsively displaced relative to each other; The at least some data nodes on the dynamic graph are graphically migrated based on the iterative calculations such that the migrated nodes are clustered with related nodes to define different integrated circuit component clusters representing different groups of related integrated circuit components of a target integrated circuit.

16. The non-transitory computer readable medium of claim 15, wherein: The stored data structure also associates an initial physical location of each of the extracted integrated circuit component data nodes based on an extracted physical integrated circuit layout of the target integrated circuit; wherein the dynamic graph is initially presented based on each of the initial physical locations based on the extracted physical integrated circuit layout; and wherein at least some of the data nodes are initially migrated from their respective initial physical locations in a graphical manner.

17. The non-transitory computer readable medium according to claim 15 or 16, wherein: Also included are instructions to calculate attractive displacements of the at least some of the data nodes as a function of distances between the data nodes.

18. The non-transitory computer readable medium of claim 17, wherein: The distance function includes a linear attraction function for connecting nodes.

19. The non-transitory computer readable medium of claim 17, wherein: The distance function includes a logarithmic attraction function for connecting nodes.

20. The non-transitory computer readable medium according to claim 18 or 19, wherein: The attraction function is inverted within a halo distance from any of the connected nodes to reduce node overlap.

21. The non-transitory computer readable medium of claim 16, wherein: The distance function also includes a repulsive force component applied between each of the at least some of the data nodes within a threshold repulsive distance to distance any of the unconnected nodes within the threshold repulsive distance.

22. The non-transitory computer readable medium of claim 16, wherein: The instructions iteratively calculate the displacement based on an iterative damping force vectoring process applied between the at least some of the data nodes.

23. The non-transitory computer readable medium of claim 16, wherein: The data structure includes a network list.

24. The non-transitory computer readable medium of claim 16, wherein: The computer-readable medium also includes instructions to graphically present the connectivity for selection of the node by visually presenting cluster connections of a selected cluster of integrated circuit components.

25. The non-transitory computer readable medium of claim 16, wherein: The different integrated circuit component clusters represent different integrated circuit functional groups.

26. The non-transitory computer readable medium of claim 16, wherein: The computer-readable medium further includes instructions for extracting the extracted integrated circuit component data nodes from one or more digital images of the target integrated circuit.

27. The non-transitory computer readable medium of claim 16, wherein: The computer-readable medium further includes instructions to present the dynamic graph as an interactive map of the nodes and to implement a digital input representation of a selected node through the map based on the clusters to update the data structure accordingly.

28. A computer-implemented process for managing integrated circuit reverse engineering data, the process comprising: accessing a stored data structure, the stored data structure comprising a plurality of extracted integrated circuit component data nodes, the integrated circuit component data nodes representing a plurality of integrated circuit components of a corresponding target integrated circuit and connectivity between the plurality of integrated circuit components; presenting a dynamic graph of the data nodes via a graphical user interface, wherein data stored for each of the data nodes can be graphically accessed and edited via an interactive graph; iteratively calculating displacements of at least some of said data nodes according to their connectivity with other nodes, wherein connected nodes are attractively displaced relative to each other and unconnected nodes are repulsively displaced relative to each other; graphically migrating the at least some of the data nodes on the interactive graph based on the iterative calculations such that the migrated nodes are clustered with related nodes to define different integrated circuit component data node clusters, the different integrated circuit component data node clusters representing different groups of related integrated circuit components of a target integrated circuit; as well as Selective data node edits for a given set of related integrated circuit components are received by numerically selecting a given cluster of data nodes on the interactive graph.

29. The computer-implemented process of claim 28, wherein: The stored data structure also associates an initial physical location of each of the extracted integrated circuit component data nodes according to an extracted physical integrated circuit layout of the target integrated circuit; wherein the dynamic graph is initially presented based on each of the initial physical locations according to the extracted physical integrated circuit layout; and wherein at least some of the data nodes are initially migrated from their respective initial physical locations in a graphical manner.

30. The computer-implemented process of claim 28 or 29, wherein: The iterative calculation includes calculating the displacement of the at least some of the data nodes as a function of the distance between the data nodes.

31. The computer-implemented process of claim 30, wherein: The distance function includes at least one of a linear attraction function or a logarithmic attraction function for connecting nodes.

32. The computer-implemented process of claim 28, wherein: The data structure includes a network list.

33. The computer-implemented process of claim 28, wherein: The different integrated circuit component data node clusters represent different integrated circuit functional groups.

Images