Fast lidar data classification

Abstract

A fast lidar data classification method is described. The controller includes a communication interface for receiving a lidar dataset comprising multiple intensity measurement data points; and a processing circuitry for implementing an iterative process to determine a second and fourth central moment of at least a portion of the intensity measurement data point dataset, using the second and fourth central moments to determine the kurtosis of at least a portion of the intensity measurement data point dataset, identifying the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset, and removing the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset from the dataset until the kurtosis converges to a predetermined value.

Description

Background Technology

[0001] The topics described in this article generally relate to the field of electronic devices, and more specifically to systems and methods for rapid optical detection and ranging (LiDAR) data classification.

[0002] LiDAR (Light Detection and Ranging) is a detection system that uses lasers to measure the distance between objects and sensors, thereby producing highly accurate measurements. The output of a LiDAR system is a high-resolution three-dimensional (3D) map of a geographic area. LiDAR can be used in a variety of applications across different technological fields. Currently, LiDAR is being applied to autonomous vehicles in the field of high-definition (HD) mapping of geographic areas surrounding vehicles.

[0003] LiDAR generates massive point cloud datasets that can be managed, visualized, and analyzed (i.e., used for object detection). Because LiDAR algorithms generate datasets containing a very large number (e.g., millions) of data points to be analyzed, developing a suitable, fast, and easily mapped-to-hardware-implementation data sorting algorithm can be challenging.

[0004] Therefore, systems and methods for achieving rapid lidar data classification can be useful, for example, in HD mapping of autonomous vehicles. Attached Figure Description

[0005] The specific implementation method is described with reference to the accompanying drawings.

[0006] Figure 1 These are illustrative examples of environments used to implement rapid lidar data classification for autonomous vehicles.

[0007] Figure 2 This is a high-level schematic illustration of an exemplary architecture for implementing rapid lidar data classification for autonomous vehicles, based on some examples.

[0008] Figure 3 This is a flowchart illustrating operations in a method for implementing rapid lidar data classification for autonomous vehicles, based on some examples.

[0009] Figure 4 This is a diagram illustrating the components in an architecture used to implement rapid lidar data classification for autonomous vehicles, based on some examples.

[0010] Figure 5 It is a graphical depiction of segmented point clouds based on some examples of fast lidar data classification for autonomous vehicles.

[0011] Figure 6-10 This is a schematic example of an electronic device that can be classified based on fast lidar data applicable to autonomous vehicles, using some examples. Detailed Implementation

[0012] This document describes examples of fast lidar data classification, which in some cases can be used in autonomous vehicles. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be implemented without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring specific examples.

[0013] This paper describes techniques for processing LiDAR data, and more specifically, for classifying LiDAR data. In some examples, a specific adaptation of the kurtosis of the intensity values ​​in the dataset is used to analyze the LiDAR dataset (or subset thereof). The controller implements an iterative process: determining the kurtosis of the dataset, and then removing data points with the largest intensity values ​​from the dataset until the kurtosis of the dataset converges to a value of 3. The remaining data points in the dataset can be classified as planes, such as a ground plane or another surface plane. This process can be repeated across different locations represented by the dataset to aid in the classification of features of the image represented by the dataset. This paper also describes a specific implementation of a processing circuit system for performing the computations necessary to calculate the kurtosis of the dataset in a manner easily implemented in digital logic.

[0014] In one aspect, the controller includes a communication interface for receiving a lidar dataset comprising a plurality of intensity measurement data points; and a processing circuitry for implementing an iterative process for determining a second central moment and a fourth central moment of at least a portion of the intensity measurement data point dataset, using the second central moment and the fourth central moment to determine the kurtosis of at least a portion of the intensity measurement data point dataset, identifying the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset, and removing the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset from the at least a portion of the dataset until the kurtosis converges to a predetermined value.

[0015] On the other hand, the autonomous vehicle includes a lidar system for generating lidar data comprising multiple intensity measurement data points; a controller including a communication interface for receiving the lidar dataset; and a processing circuit system for implementing an iterative process for determining a second central moment and a fourth central moment of at least a portion of the intensity measurement data point dataset, using the second central moment and the fourth central moment to determine the kurtosis of at least a portion of the intensity measurement data point dataset, identifying the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset, and removing the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset from the dataset until the kurtosis converges to a predetermined value.

[0016] The subject matter described herein can be advantageously used in conjunction with motorized vehicles. As used herein, the term "vehicle" should be interpreted broadly to include automobiles, trucks, ships, airplanes, spacecraft, trains, buses, or any form of transport. References will be made below. Figure 1-10 Describe further details of the structure and operation.

[0017] Figure 1 This is a schematic illustration of an environment for rapid lidar data classification for autonomous vehicles, based on several examples. See also Figure 1 In some examples, environment 100 includes one or more cloud-based vehicle management systems 110, which are communicatively coupled to a communication network 120, which is capable of transmitting information from the vehicle management system 110 to one or more autonomous vehicles (such as helicopter 130, airplane 132, or car vehicle 134).

[0018] In some examples, the vehicle management system 110 may include one or more processor-based devices, such as servers including computer-readable storage that stores software updates for one or more devices communicatively coupled to one or more autonomous vehicles.

[0019] Network 120 may be embodied as a public communications network (such as, for example, the Internet) or a private communications network (such as, a cellular network) or a combination thereof. In one or more examples, network 120 may comply with the Global Microwave Interconnection Access (WiMAX) standard or future generations of WiMAX, and in a particular example may operate in accordance with a standard based on IEEE 802.16 (e.g., IEEE 802.16e) or a standard based on IEEE 802.11 (e.g., IEEE 802.11a / b / g / n standards). In one or more alternative examples, network 900 may comply with the 3GPP LTE, 3GPP2 AIE, and / or 3GPP LTE-Advanced standards. Typically, Network 900 may include any type of wireless network based on Orthogonal Frequency Division Multiple Access (OFDMA), such as WiMAX-compliant networks, Wi-Fi Alliance-compliant networks, Digital Subscriber Line (DSL) networks, Asymmetric Digital Subscriber Line (ADSL) networks, Ultra-Wideband (UWB)-compliant networks, Wireless Universal Serial Bus (USB)-compliant networks, 4th Generation (4G) networks, etc., and the scope of the claimed subject matter is not limited to these aspects.

[0020] Figure 2 This is a high-level schematic illustration of an exemplary architecture for implementing rapid LiDAR data classification for autonomous vehicles, based on some examples. See also... Figure 2 In some examples, the autonomous vehicle management system may include one or more vehicle management algorithms 212, which may include software and / or firmware for managing devices on one or more autonomous vehicles. The vehicle management system 110 may include one or more neural networks 214 for managing devices on one or more autonomous vehicles. The vehicle management system 110 may further include one or more databases for managing data associated with devices on one or more autonomous vehicles.

[0021] The autonomous vehicle management system 110 is communicatively coupled to one or more controllers 230 via communication networks 220, which are sometimes referred to as electronic control units (ECUs). The networks 220 may be embodied as public communication networks (such as, for example, the Internet) or private communication networks (such as, cellular networks) or combinations thereof.

[0022] Controller 230 may be incorporated into or communicatively coupled to an autonomous vehicle. Controller 230 may be embodied as a general-purpose processor, such as those available from Intel Corporation in Santa Clara, California. Core 2 Processor. As used herein, the term "processor" means any type of computing element, such as, but not limited to, a microprocessor, microcontroller, Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or any other type of processor or processing circuit. Alternatively, controller 230 may be embodied as a low-power controller, such as a Field Programmable Gate Array (FPGA), etc.

[0023] The controller 230 may include a communication interface 232 for managing communications via network 220, a local memory 234, a vehicle management module 236, and a data classification module 238. The communication interface 232 may include or be coupled to an RF transceiver, which may establish a communication connection via a protocol conforming to network 120 as described above or using a local communication protocol such as an Ethernet connection.

[0024] In some examples, local memory module 236 may include random access memory (RAM) and / or read-only memory (ROM). Other memory types, such as dynamic RAM (DRAM) and synchronous DRAM (SDRAM), may be used to implement memory 236. Memory 234 may include one or more applications, including vehicle management module 236 and data classification module 238, which may be implemented as logical instructions (e.g., software or firmware) executable on controller 230, or may be simplified to hardwired logic circuitry.

[0025] The controller 230 may be coupled to one or more devices 240 on the autonomous vehicle. For example, the device 240 may include one or more sensors (e.g., radar, lidar, camera) 242, actuators 244, or position sensors 246 (e.g., GPS, inertial sensors, etc.).

[0026] Various structural components have been described as examples of architectures for rapid lidar data classification of autonomous vehicles, and will be referenced. Figure 3-4 Describe the operations implemented by the system. In some examples, Figure 3 Some or all of the operations described herein can be implemented by the data classification module 238 executed on the controller 230.

[0027] See Figure 3-4 At operation 310, a lidar dataset is received. For example, controller 230 may receive the lidar dataset from lidar device 242 via communication interface 232. The lidar dataset may include a large number of data points, each of which represents the intensity of a laser beam reflected from an object at a specific point in time, similar to a pixel map collected by a digital camera.

[0028] At operation 315, the kurtosis of the probability density function of the dataset (or a subset thereof) is calculated. For example, data classification module 238 may select a subset of the dataset corresponding to a region of a pixel map represented by the dataset, and may calculate the kurtosis of the data points in the subset representing the region. Those skilled in the art will recognize that the kurtosis of the dataset representing a surface plane (e.g., a plane of the ground or the surface of an object) will have a measurement of 3. The presence of data points reflected from objects above or below the surface screen in the region will cause the kurtosis of the dataset to tend to be greater than 3.

[0029] At operation 320, if the kurtosis of the data points in a subset of the region is greater than 3, control is passed to operation 325. At operation 325, the data points in the dataset with the highest intensity value are identified and classified as objects. At operation 330, the data points in the dataset with the highest intensity value are removed from the dataset. Control is then passed back to operation 315 and the kurtosis of the dataset is recalculated. Conversely, if the kurtosis of the dataset is 3 at operation 320, the remaining points in the dataset are classified as surface planes.

[0030] therefore, Figure 3 The operation describes an iterative process: determine the kurtosis of the dataset, then remove data points with the highest intensity values ​​from the dataset until the kurtosis converges to a value of 3. The remaining data points in the dataset can then be classified as planes, such as a ground plane or another surface plane. This process can be repeated across different locations in the dataset to help classify the features of the image represented by the dataset.

[0031] In some examples, the process described in this paper employs a specific definition of kurtosis that allows for rapid implementation in digital logic. Given a univariate random variable 'Y' with a mean μy and finite moments, the kurtosis of the data is defined as the normalized fourth moment of the dataset, as shown in Equation 1:

[0032] Formula 1

[0033] Where 'E' is the expectation. The kurtosis can be rewritten based on the central moments. The definition of the central moments of the distribution f(n) of length N+1 about the point n=N is given by equation (2):

[0034] Formula 2

[0035] Applying the binomial theorem, we get:

[0036] Formula 3

[0037] Equation (3) above gives the relationship between the central moments of interest and the original moments, the relationship between the second central moments and the fourth central moments, and is given by the following equation:

[0038]

[0039]

[0040] And the kurtosis K is then given by the following formula:

[0041] Formula 4

[0042] To calculate kurtosis, the central moment must be calculated, and to calculate the central moment, the original moments must first be calculated. An efficient architecture for the original moments can be achieved by using an infinite impulse response (IIR) recursive filter.

[0043] See Figure 4 To calculate the original moments, a cascaded single-pole IIR filter 410 can be used. The general formula for an a(p+1) cascaded all-pole filter is as follows:

[0044] Formula 5

[0045] For p = 0, the following Z-transform pairs are generated:

[0046] Formula 6

[0047] The output of the filter responding to f(n) of length N+1 is:

[0048] Formula 7

[0049] Estimate the output when n = N+1:

[0050] Formula 8

[0051] This is the zeroth moment of f(n) with respect to N. Next, for the case of p = 2, we obtain...

[0052]

[0053] Generates using the differential properties of the Z-transform:

[0054]

[0055] From the above, the relationship between the impulse responses of first-order and second-order all-pole filters can be derived as follows:

[0056]

[0057] The output of this filter will be:

[0058]

[0059] When n = N + 2, the estimated output will be a linear combination of the first two moments of f(n):

[0060]

[0061] In the same manner, linear combinations of higher moments can be computed. The transformation matrix up to the fourth moment is given by M = A·Y:

[0062] Formula 9

[0063] Figure 4 An example is shown: a circuit architecture for calculating the original moments using the output of a single-pole IIR cascaded filter (output 410). For example... Figure 4 As illustrated, the raw moments are routed through adder 415, multiplier 420, and divider 425 to calculate kurtosis. For example... Figure 4 As illustrated, the raw moment output generated by the single-pole IIR filter 415 is directed to adder 415 to generate the central moment M. N 0 To M N 4 Note that a single-pole IIR filter is simply an accumulator with feedback delay that can be implemented using a flip-flop.

[0064] therefore, Figure 4 The circuit system depicted can be used to perform the necessary calculations to efficiently determine the digital logic. Figure 3 The kurtosis of the dataset (or a subset thereof) required for operation 315. Figure 5 It is a graphical depiction of segmented point clouds based on examples of rapid lidar data classification for autonomous vehicles. For example... Figure 5 As illustrated, this method can quickly classify LiDAR data into objects and planes.

[0065] As described above, in some examples, controller 230 may be embodied as a computer system. Figure 6 The diagram illustrates a block diagram of a computing system 600 according to an example. The computing system 600 may include one or more central processing units 602 or processors that communicate via an interconnect network (or bus) 604. The processor 602 may include a general-purpose processor, a network processor (which processes data transmitted via a computer network 603), or other types of processors (including Reduced Instruction Set Computer (RISC) processors or Complex Instruction Set Computer (CISC) processors). Furthermore, the processor 602 may have a single-core or multi-core design. A processor 602 with a multi-core design may integrate different types of processor cores onto the same integrated circuit (IC) die. Additionally, a processor 602 with a multi-core design may be implemented as a symmetric or asymmetric multiprocessor.

[0066] Chipset 606 may also communicate with interconnect network 604. Chipset 606 may include memory control hub (MCH) 608. MCH 608 may include memory controller 610 communicating with memory 612. Memory 612 may store data, including sequences of instructions executable by processor 602 or any other device included in computing system 600. In one example, memory 612 may include one or more volatile storage (or memory) devices, such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Non-volatile memory, such as hard disk, may also be utilized. Additional devices, such as multiple processors and / or multiple system memories, may communicate via interconnect network 604.

[0067] MCH 608 may also include a graphics interface 614 for communicating with the display device 616. In one example, the graphics interface 614 may communicate with the display device 616 via an Accelerated Graphics Port (AGP). In this example, the display 616 (such as a flat panel display) may communicate with the graphics interface 614 via, for example, a signal converter that converts a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display 616. The display signals generated by the display device may pass through various control devices before being interpreted by the display and subsequently displayed on the display 616.

[0068] Central interface 618 allows communication between MCH 608 and ICH 620. ICH 620 provides an interface to I / O devices communicating with computing system 600. ICH 620 can communicate with bus 622 via peripheral bridge (or controller) 624, such as a Peripheral Component Interconnect (PCI) bridge, Universal Serial Bus (USB) controller, or other types of peripheral bridges or controllers. Bridge 624 provides a data path between processor 602 and peripheral devices. Other types of topologies can be utilized. Additionally, multiple buses can communicate with ICH 620, for example, via multiple bridges or controllers. Moreover, in various examples, other peripheral devices communicating with ICH 620 may include Integrated Drive Electronics (IDE) or (multiple) Small Computer System Interface (SCSI) hard drives, (multiple) USB ports, keyboard, mouse, (multiple) parallel ports, (multiple) serial ports, (multiple) floppy disk drives, digital output support (e.g., Digital Video Interface (DVI)), or other devices.

[0069] Bus 622 can communicate with audio device 626, one or more disk drives 628, and network interface device 630 (which communicates with computer network 603). Other devices can communicate via bus 622. Furthermore, in some examples, components (such as network interface device 630) can communicate with MCH 608. Additionally, processor 602 and one or more other components discussed herein can be combined to form a single chip (e.g., for providing a system-on-a-chip (SOC)). Furthermore, in other examples, graphics accelerator 616 may be included within MCH 608.

[0070] In addition, the computing system 600 may include volatile and / or non-volatile memory (or storage). For example, non-volatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable ROM (EPROM), electrically RPROM (EEPROM), disk drive (e.g., 628), floppy disk, compact disk ROM (CD-ROM), digital multifunction disk (DVD), flash memory, magneto-optical disk, or other types of non-volatile machine-readable media capable of storing electronic data (e.g., including instructions).

[0071] Figure 7 The figure illustrates a block diagram of a computing system 700 according to an example. System 700 may include one or more processors 702-1 to 702-N (collectively referred to herein as “processors 702” or “processor 702”). Processors 702 may communicate via an interconnect network or bus 704. Each processor may include various components; for clarity, some of these components are discussed with reference only to processor 702-1. Accordingly, each of the remaining processors 702-2 to 702-N may include the same or similar components discussed with reference to processor 702-1.

[0072] In the example, processor 702-1 may include one or more processor cores 706-1 to 706-M (referred to herein as "cores 706" or more generally as "core 706"), a shared cache 708, a router 710, and / or processor control logic or unit 720. Processor core 706 may be implemented on a single integrated circuit (IC) chip. Furthermore, the chip may include one or more shared and / or private caches (such as cache 708), buses or interconnects (such as bus or interconnect network 712), memory controllers, or other components.

[0073] In one example, router 710 can be used to enable communication between components of processor 702-1 and / or system 700. Furthermore, processor 702-1 may include more than one router 710. Additionally, numerous routers 710 can communicate to enable data routing between components internal to or external to processor 702-1.

[0074] Shared cache 708 may store data (e.g., instructions) used by one or more components of processor 702-1, such as core 706. For example, shared cache 708 may locally cache data stored in memory 714 for faster access by components of processor 702. In this example, cache 708 may include intermediate caches (such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache), last-level cache (LLC), and / or combinations thereof. Furthermore, components of processor 702-1 may communicate directly with shared cache 708 via a bus (e.g., bus 712) and / or a memory controller or hub. Figure 7 As shown, in some examples, one or more of the cores 706 may include a Level 1 (L1) cache 716-1 (generally referred to herein as "L1 cache 716").

[0075] Figure 8 The diagram shows a block diagram of the processor core 706 and other components of a computing system according to an example. In one example, Figure 8 The arrows shown illustrate the flow of instructions through core 706. One or more processor cores (such as processor core 706) can be implemented in, for example, reference... Figure 7 On the single integrated circuit chip (or die) under discussion. Furthermore, the chip may include one or more shared and / or private caches (e.g., Figure 7 708 cache), interconnect (e.g., Figure 7 Interconnection 704 and / or 112), control unit, memory controller or other components.

[0076] like Figure 8 As illustrated, processor core 706 may include a fetch unit 802 to fetch instructions (including instructions with conditional branches) for core 706 to execute. These instructions may be fetched from any storage device, such as memory 714. Core 706 may also include a decode unit 804 to decode the fetched instructions. For example, decode unit 804 may decode the fetched instructions into multiple uops (micro-operations).

[0077] Furthermore, core 706 may include a scheduling unit 806. The scheduling unit 806 may perform various operations associated with decoded instructions stored (e.g., received from decoding unit 804) until these instructions are ready for dispatch, for example, until all source values ​​of the decoded instructions become available. In one example, the scheduling unit 806 may schedule and / or issue (or dispatch) decoded instructions to execution unit 808 for execution. Execution unit 808 may execute the dispatched instructions after they have been decoded (e.g., by decoding unit 804) and dispatched (e.g., by scheduling unit 806). In this example, execution unit 808 may include more than one execution unit. Execution unit 808 may also perform various arithmetic operations such as addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In this example, a coprocessor (not shown) may be combined with execution unit 808 to perform various arithmetic operations.

[0078] Furthermore, execution unit 808 can execute instructions out of order. Therefore, in one example, processor core 706 can be an out-of-order processor core. Core 706 may also include a retirement unit 810. This retirement unit 810 can retire the instructions after they have been committed. In the example, retiring the executed instructions may result in: committing the processor state based on the execution of these instructions; deallocating the physical registers used by these instructions, etc.

[0079] Core 706 may also include bus unit 714 to enable the processor core 706 to connect with other components (such as references) via one or more buses (e.g., buses 804 and / or 812). Figure 8 Communication between the components discussed. Core 706 may also include one or more registers 816 to store data (such as values ​​related to power state settings) accessed by the various components of core 706.

[0080] Furthermore, even Figure 7 The diagram shows that the control unit 720 is coupled to the core 706 via interconnect 812, but in various examples, the control unit 720 may be located elsewhere, such as inside the core 706, coupled to the core via bus 704, etc.

[0081] In some examples, one or more of the components discussed in this article may be embodied as a system-on-a-chip (SOC) device. Figure 9 The diagram illustrates a block diagram of a SoC package based on an example. (See diagram for example.) Figure 9As illustrated, the SOC 902 includes one or more processor cores 920, one or more graphics processor cores 930, an input / output (I / O) interface 940, and a memory controller 942. The components of the SOC package 902 can be coupled to interconnects or buses such as those discussed herein with reference to other figures. Additionally, the SOC package 902 may include more or fewer components, such as those discussed herein with reference to other figures. Further, each component of the SOC package 902 may include one or more other components, such as those discussed herein with reference to other figures. In one example, the SOC package 902 (and its components) is provided on one or more integrated circuit (IC) dies, for example, it is packaged into a single semiconductor device.

[0082] like Figure 9 As illustrated, the SOC package 902 is coupled to the memory 960 (which may be similar to or the same as the memory discussed herein with reference to other figures) via a memory controller 942. In this example, the memory 960 (or a portion thereof) may be integrated onto the SOC package 902.

[0083] I / O interface 940 may be coupled to one or more I / O devices 970, for example, via interconnects and / or buses as discussed herein with reference to other figures. The I / O devices 970 may include one or more of a keyboard, mouse, touchpad, display, image / video capture device (such as a camera or camcorder / video recorder), touch surface, speaker, etc.

[0084] Figure 10 The diagram illustrates a computing system 1000 arranged in a point-to-point (PtP) configuration according to an example. Specifically, Figure 10 This illustrates a system in which the processor, memory, and input / output devices are interconnected via several point-to-point interfaces. For example... Figure 10 As illustrated in the diagram, system 1000 may include several processors, of which only two, 1002 and 1004, are shown for clarity. Processors 1002 and 1004 may each include a local memory controller hub (MCH) 1006 and 1008 to enable communication with memories 1010 and 1012.

[0085] In the example, processors 1002 and 1004 can be references. Figure 7One of the processors 702 under discussion. Processors 1002 and 1004 can exchange data via point-to-point (PtP) interface 1014 using point-to-point (PtP) interface circuits 1016 and 1018, respectively. Additionally, processors 1002 and 1004 can exchange data with chipset 1020 via PtP interfaces 1022 and 1024, respectively, using point-to-point interface circuits 1026, 1028, 1030, and 1032, respectively. Chipset 1020 can further exchange data with high-performance graphics circuit 1034 via high-performance graphics interface 1036, for example, using PtP interface circuit 1037.

[0086] Chipset 1020 can communicate with bus 1040 using PtP interface circuitry 1041. Bus 1040 may have one or more devices communicating with it, such as bus bridge 1042 and I / O devices 1043. Bus bridge 1043 can communicate with other devices such as keyboard / mouse 1045, communication devices 1046 (such as modems, network interface devices, or other communication devices that can communicate with computer network 1003), audio I / O devices, and / or data storage device 1048 via bus 1044. Data storage device 1048 (which may be a hard disk drive or a NAND flash-based solid-state drive) can store code 1049 that can be executed by processor 1004.

[0087] The following examples provide further examples.

[0088] Example 1 is the backbone of lidar data classification, comprising multiple sensors including a communication interface for receiving a lidar dataset comprising multiple intensity measurement data points; and a processing circuit system for implementing an iterative process for: determining a second central moment and a fourth central moment of at least a portion of the intensity measurement data point dataset; using the second central moment and the fourth central moment to determine the kurtosis of at least a portion of the intensity measurement data point dataset; identifying the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset; and removing the intensity measurement data point with the highest intensity in at least a portion of the intensity measurement data point dataset from the at least a portion of the dataset until the kurtosis converges to a predetermined value.

[0089] In Example 2, the subject of Example 1 may optionally include a processing circuit system for classifying at least a portion of a dataset into a plane.

[0090] In Example 3, the subject of any of Examples 1-2 may optionally include an arrangement in which the controller includes a processing circuitry for performing matrix multiplication transformations to compute the original set of moments for at least a portion of the dataset of intensity measurement data points.

[0091] In Example 4, the subject of any of Examples 1-3 may optionally include an arrangement in which the controller includes a processing circuit system for calculating a second central moment and a fourth central moment from a raw set of moments for at least a portion of a dataset of intensity measurement data points.

[0092] In Example 5, the subject of any of Examples 1-4 may optionally include an arrangement in which the controller includes a processing circuit system for using the formula To determine the kurtosis of at least a portion of the dataset of intensity measurement data points, where: It is the second central moment; and It is the fourth central moment.

[0093] In Example 6, the subject of any of Examples 1-5 may optionally include an arrangement in which matrix multiplication transformations compute the following:

[0094]

[0095] in:

[0096] It is the zeroth primitive moment;

[0097] It is the first primitive moment;

[0098] It is the second primitive moment;

[0099] It is the third primitive moment; and

[0100] It is the fourth primitive moment.

[0101] In Example 7, the subject of any of Examples 1-6 may optionally include an arrangement in which the processing circuitry system for computing matrix multiplication transformations includes a series of single-pole infinite impulse response filters, wherein each single-pole infinite impulse response filter includes an accumulator and a feedback delay.

[0102] In Example 8, the subject of any of Examples 1-7 may optionally include an arrangement in which the remote communication device includes a vehicle alarm.

[0103] In Example 9, the subject of any one of Examples 1-8 may optionally include an arrangement in which the controller includes, wherein the processing circuitry system for calculating the matrix multiplication transformation includes: a first series of multipliers and adders for calculating the second central moment; and a second series of multipliers and adders for calculating the fourth central moment.

[0104] In Example 10, the subject of any one of Examples 1-9 may optionally include an arrangement in which the controller includes a processing circuit system for calculating the matrix multiplication transformation, which includes a divider for dividing the fourth central moment by the second central moment.

[0105] Example 11 is an autonomous vehicle including a lidar system for generating lidar data comprising multiple intensity measurement data points; a controller including a communication interface for receiving the lidar dataset; and a processing circuitry system for implementing an iterative process to determine a second central moment and a fourth central moment of at least a portion of the dataset of intensity measurement data points, using the second central moment and the fourth central moment to determine the kurtosis of at least a portion of the dataset of intensity measurement data points, identifying the intensity measurement data point with the highest intensity in at least a portion of the dataset of intensity measurement data points, and removing the intensity measurement data point with the highest intensity in at least a portion of the dataset of intensity measurement data points from the dataset until the kurtosis converges to a predetermined value.

[0106] In Example 12, the subject of Example 11 may optionally include a processing circuit system for classifying at least a portion of a dataset into a plane.

[0107] In Example 13, the subject of any of Examples 11-12 may optionally include an arrangement in which the controller includes a processing circuitry for performing matrix multiplication transformations to compute the original set of moments for at least a portion of the dataset of intensity measurement data points.

[0108] In Example 14, the subject of any of Examples 11-13 may optionally include an arrangement in which the controller includes a processing circuitry for calculating a second central moment and a fourth central moment from a raw set of moments for at least a portion of a dataset of intensity measurement data points.

[0109] In Example 15, the subject of any of Examples 11-14 may optionally include an arrangement in which the controller includes a processing circuit system for using the formula To determine the kurtosis of at least a portion of the dataset of intensity measurement data points, where: It is the second central moment; And it is the fourth central moment.

[0110] In Example 16, the subject of any of Examples 11-15 may optionally include an arrangement in which matrix multiplication transformations compute the following:

[0111]

[0112] in:

[0113] It is the zeroth primitive moment;

[0114] It is the first primitive moment;

[0115] It is the second primitive moment;

[0116] It is the third primitive moment; and

[0117] It is the fourth primitive moment.

[0118] In Example 17, the subject of any of Examples 11-16 may optionally include an arrangement in which the processing circuitry system for computing matrix multiplication transformations includes a series of single-pole infinite impulse response filters, wherein each single-pole infinite impulse response filter includes an accumulator and a feedback delay.

[0119] In Example 18, the subject of any of Examples 11-17 may optionally include an arrangement in which the remote communication device includes a vehicle alarm.

[0120] In Example 19, the subject of any one of Examples 11-18 may optionally include an arrangement in which the controller includes, wherein the processing circuitry system for calculating the matrix multiplication transformation includes: a first series of multipliers and adders for calculating the second central moment; and a second series of multipliers and adders for calculating the fourth central moment.

[0121] In Example 20, the subject of any one of Examples 1-9 may optionally include an arrangement in which the controller includes a processing circuit system for calculating the matrix multiplication transformation, which includes a divider for dividing the fourth central moment by the second central moment.

[0122] The term "logical instruction" as used in this application refers to an expression that can be understood by one or more machines to perform one or more logical operations. For example, a logical instruction may include instructions that can be interpreted by a processor compiler to perform one or more operations on one or more data objects. However, these are merely examples of machine-readable instructions, and the examples are not limited to this.

[0123] The term "computer-readable medium" as used herein refers to a medium capable of maintaining an expression perceptible to one or more machines. For example, a computer-readable medium may include one or more storage devices for storing computer-readable instructions or data. Such storage devices may include storage media such as, for example, optical, magnetic, or semiconductor storage media. However, these are merely examples of computer-readable media, and the examples are not limited to this.

[0124] The term "logic" as used herein refers to a structure for performing one or more logical operations. For example, logic may include circuitry that provides one or more output signals based on one or more input signals. Such circuitry may include a finite state machine that receives digital inputs and provides digital outputs, or circuitry that provides one or more analog output signals in response to one or more analog input signals. Such circuitry can be provided in the form of application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Additionally, logic may include machine-readable instructions stored in memory, which, in combination with processing circuitry, are executed. However, these are merely examples of structures that can provide logic, and the examples are not limited to this aspect.

[0125] Some of the methods described herein can be embodied as logical instructions on a computer-readable medium. When executed on a processor, these logical instructions cause the processor to be programmed as a dedicated machine to implement the described methods. When configured by the logical instructions to execute the methods described herein, the processor constitutes a structure for executing the described methods. Alternatively, the methods described herein can be simplified to logic on top of, for example, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.

[0126] In the specification and claims, the terms coupled and connected, and their derivatives, may be used. In certain examples, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact with each other. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but can still cooperate or interact with each other.

[0127] References to "an example" or "some examples" in this specification mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one implementation. The phrase "in an example" appearing in various places in this specification may all refer to the same example or may not all refer to the same example.

[0128] Although examples have been described using language specific to structural features and / or methodological actions, it should be understood that the claimed subject matter may not be limited to the specific features or actions described. Instead, specific features and actions are disclosed as sample forms of implementing the claimed subject matter.

Claims

1. A system for classifying lidar data, comprising: A communication interface for receiving a lidar dataset that includes multiple intensity measurement data points; An infinite impulse response (IIR) recursive filter, comprising cascaded single-pole IIR filters, is used to generate the original moment set of the plurality of intensity measurement data points; and Processing circuitry system for implementing an iterative process, the iterative process being used for: Determine the second and fourth central moments of at least a portion of the dataset of strength measurement data points; The second central moment and the fourth central moment are used to determine the kurtosis of at least a portion of the dataset of intensity measurement data points; The intensity measurement data point that has the highest intensity in at least a portion of the dataset of intensity measurement data points; as well as Remove the intensity measurement data point with the highest intensity in the intensity measurement data point from the at least portion of the dataset until the kurtosis converges to a predetermined value.

2. The system as described in claim 1, characterized in that, Includes a processing circuit system for: Classify at least a portion of the dataset into a plane.

3. The system as described in claim 1, characterized in that, Includes a processing circuit system for: Perform a matrix multiplication transformation to compute the original set of moments for at least a portion of the dataset of intensity measurement data points.

4. The system as described in claim 3, characterized in that, Includes a processing circuit system for: The second central moment and the fourth central moment are calculated from the original set of moments of at least a portion of the dataset of intensity measurement data points.

5. The system as described in claim 4, characterized in that, Includes a processing circuit system for: Use formula To determine the kurtosis of at least a portion of the dataset of intensity measurement data points, wherein: It is the second central moment; and It is the fourth central moment.

6. The system as described in claim 3, characterized in that, The matrix multiplication transformation calculates the following: in: It is the zeroth primitive moment; It is the first primitive moment; It is the second primitive moment; It is the third primitive moment; and It is the fourth primitive moment.

7. The system as described in claim 6, characterized in that, The processing circuit system for calculating the matrix multiplication transformation includes: A series of single-pole infinite impulse response (IOR) filters, wherein each single-pole IOR filter includes an accumulator and a feedback delay.

8. The system as described in claim 7, characterized in that, The matrix multiplication transformation calculates the following:

9. The system as described in claim 8, characterized in that, The processing circuit system for calculating the matrix multiplication transformation includes: A first series of multipliers and adders is used to calculate the second central moment; and A second series of multipliers and adders are used to calculate the fourth central moment.

10. The system as described in claim 9, characterized in that, The processing circuit system for calculating the matrix multiplication transformation includes: A divider is used to divide the fourth central moment by the second central moment.

11. An autonomous vehicle, comprising: A lidar system used to generate lidar datasets that include multiple intensity measurement data points; as well as The controller includes: A communication interface is provided for receiving the LiDAR dataset. An infinite impulse response (IIR) recursive filter, comprising cascaded single-pole IIR filters, is used to generate the original moment set of the plurality of intensity measurement data points; and Processing circuitry system for implementing an iterative process, the iterative process being used for: Determine the second and fourth central moments of at least a portion of the dataset of strength measurement data points; The second central moment and the fourth central moment are used to determine the kurtosis of at least a portion of the dataset of intensity measurement data points; The intensity measurement data point that has the highest intensity in at least a portion of the dataset of intensity measurement data points; and Remove the intensity measurement data point with the highest intensity in the intensity measurement data point from the at least portion of the dataset until the kurtosis converges to a predetermined value.

12. The autonomous transportation vehicle as described in claim 11, characterized in that, Includes a processing circuit system for: Classify at least a portion of the dataset into a plane.

13. The autonomous transportation vehicle as described in claim 11, characterized in that, Includes a processing circuit system for: Perform a matrix multiplication transformation to compute the original set of moments for at least a portion of the dataset of intensity measurement data points.

14. The autonomous transportation vehicle as described in claim 13, characterized in that, Includes a processing circuit system for: The second central moment and the fourth central moment are calculated from the original set of moments of at least a portion of the dataset of intensity measurement data points.

15. The autonomous transportation vehicle as described in claim 14, characterized in that, Includes a processing circuit system for: Use formula To determine the kurtosis of at least a portion of the dataset of intensity measurement data points, wherein: It is the second central moment; and It is the fourth central moment.

16. The autonomous transportation vehicle as described in claim 13, characterized in that, The matrix multiplication transformation calculates the following: in: It is the zeroth primitive moment; It is the first primitive moment; It is the second primitive moment; It is the third primitive moment; and It is the fourth primitive moment.

17. The autonomous transportation vehicle as described in claim 16, characterized in that, The processing circuit system for calculating the matrix multiplication transformation includes: A series of single-pole infinite impulse response (IOR) filters, wherein each single-pole IOR filter includes an accumulator and a feedback delay.

18. The autonomous transportation vehicle as described in claim 17, characterized in that, The matrix multiplication transformation calculates the following:

19. The autonomous transportation vehicle as described in claim 18, characterized in that, The processing circuit system for calculating the matrix multiplication transformation includes: A first series of multipliers and adders is used to calculate the second central moment; and A second series of multipliers and adders are used to calculate the fourth central moment.

20. The autonomous transportation vehicle as described in claim 19, characterized in that, The processing circuit system for calculating the matrix multiplication transformation includes: A divider is used to divide the fourth central moment by the second central moment.

Images