A signal isolation transmission circuit based on capacitance

Abstract

A signal isolation transmission circuit based on capacitors, wherein an isolation capacitor group is respectively connected to a first signal transmission circuit and a second signal transmission circuit, wherein the first signal transmission circuit and the second signal transmission circuit respectively include a signal input module and a signal output module, wherein when the first signal transmission circuit works in an input mode, the second signal transmission circuit works in an output mode, and when the second signal transmission circuit works in an input mode, the first signal transmission circuit works in an output mode, wherein when working in the input mode, only the signal input module works, and when working in the output module, only the signal output module works, the signal input module performs duty cycle modulation on the input signal, and outputs a modulated signal of a fixed frequency, wherein the isolation capacitor group realizes signal isolation transmission, and the signal output module demodulates the modulated signal. The present invention performs signal transmission through special duty cycle modulation and demodulation, and realizes signal isolation transmission by using capacitors as signal isolation devices.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit signal processing, and in particular to a capacitor-based signal isolation transmission circuit. Background Art

[0002] In electronic systems in different voltage domains, it is often necessary to isolate signals to ensure system reliability and safety. Common digital signal isolation is achieved through devices such as transformers, optocouplers, and Hall devices, but the isolation and conversion of analog signals is very difficult. It is usually necessary to convert analog signals into digital signals and then transmit them through digital isolation devices. This method requires multiple isolation devices to achieve the analog signal isolation and conversion function. Considering factors such as cost, reliability, and device size, optocouplers are currently the most popular signal isolation devices, which achieve electrical isolation between two voltage domains through optical transmission. However, due to the poor temperature characteristics of optocouplers, high power consumption, short aging cycle, and difficulty in semiconductor process integration, optocouplers face many application bottlenecks. Summary of the invention

[0003] The present invention provides a capacitor-based signal isolation transmission circuit, which performs signal transmission through special duty cycle modulation and demodulation, and uses capacitors as signal isolation devices to achieve signal isolation transmission.

[0004] In order to achieve the above-mentioned object, the present invention provides a capacitor-based signal isolation transmission circuit, comprising: a first signal transmission circuit and a second signal transmission circuit with completely identical structures, and an isolation capacitor group respectively connected to the first signal transmission circuit and the second signal transmission circuit;

[0005] The first signal transmission circuit and the second signal transmission circuit each include a signal input module and a signal output module, and the first signal transmission circuit and the second signal transmission circuit can respectively work in an input mode and an output mode, when working in the input mode, only the signal input module works, and the signal output module does not work, and when working in the output module, only the signal output module works, and the signal input module does not work;

[0006] When the first signal transmission circuit works in the input mode, the second signal transmission circuit works in the output mode; when the second signal transmission circuit works in the input mode, the first signal transmission circuit works in the output mode;

[0007] The signal input module performs duty cycle modulation on the input signal and outputs a modulated signal with a fixed frequency;

[0008] The isolation capacitor group realizes signal isolation transmission;

[0009] The signal output module demodulates the modulated signal.

[0010] The signal input module is a modulation circuit, which converts the high level of the input signal into a clock cycle of a first duty cycle, and converts the low level of the input signal into a clock cycle of a second duty cycle.

[0011] The first duty cycle is 75% and the second duty cycle is 25%; or the first duty cycle is 25% and the second duty cycle is 75%.

[0012] The modulation circuit comprises:

[0013] A signal modulation circuit, whose input terminal inputs a signal SIG_INL and a reference clock signal CK0, and whose output terminal outputs a modulation signal SIGX, which is used to perform duty cycle modulation on the signal;

[0014] The glitch filtering circuit has an input terminal that inputs a modulation signal SIGX, and an output terminal that outputs two mutually inverted fixed-frequency modulation signals SIG_ML and SIG_MLB, which are used to filter signal glitches.

[0015] The signal modulation circuit comprises:

[0016] A frequency division trigger, an AND gate, an inverter, a 4-input AND-OR gate, and an OR gate. The reference clock signal CK0 generates a divided clock signal CK1 after passing through the frequency division trigger. The reference clock signal CK0 and the divided clock signal CK1 are input to the AND gate and then output the signal CK_AND. The reference clock signal CK0 and the divided clock signal CK1 are input to the OR gate and output the signal CK_OR. The input signal SIG_INL is input to the inverter and outputs the signal SIG_INB. The signal CK_AND, the signal CK_OR, the signal SIG_INL and the signal SIG_INB are input to the 4-input AND-OR gate together. The signal CK_AND is ANDed with the signal SIG_INB, the signal CK_OR is ANDed with the signal SIG_INL, and the results of the two are ORed together to obtain the signal SIGX. The signal SIGX is the transition modulation signal.

[0017] The burr filtering circuit comprises:

[0018] A delay circuit, an XOR gate, a glitch filter trigger, and a three-state buffer. The reference clock signal CK0 is input into the XOR gate together with the reference clock signal CK0 after passing through the delay circuit. The XOR gate outputs a trigger signal TRIG. The trigger signal TRIG is connected to the clock signal end of the glitch filter trigger. The modulation signal SIGX is input into the data end of the glitch filter trigger. The falling edge of the trigger signal TRIG samples the state of the modulation signal SIGX. The positive output end of the glitch filter trigger outputs a signal SIG_ML_BUF to the three-state buffer, and the reverse output end outputs a signal SIG_MLB_BUF to the three-state buffer. The high-impedance output signal SIG_ML and the high-impedance output signal SIG_MLB are output through the three-state buffer.

[0019] The signal output module includes a detection circuit and a demodulation circuit. The input end of the detection circuit is connected to the isolation capacitor group, and the output end of the detection circuit is connected to the input end of the demodulation circuit. The detection circuit converts the charge signal SIG_MR coupled from the isolation capacitor group into a voltage signal SIG_MRD, and the demodulation circuit demodulates the voltage signal SIG_MRD to obtain a demodulation signal SIG_OUTR.

[0020] The isolation capacitor group includes a first isolation capacitor, which couples the modulated fixed frequency signal SIG_ML to form a charge signal SIG_MR.

[0021] The detection circuit comprises:

[0022] A hysteresis comparator, whose positive input stage is connected to the first isolation capacitor, whose positive input stage inputs the charge signal SIG_MR, and whose output terminal outputs the voltage signal SIG_MRD, and the hysteresis comparator is used to restore the timing information of the signal before coupling;

[0023] a first resistor, one end of which is connected to the power supply and the other end of which is connected to the positive input stage of the hysteresis comparator;

[0024] a second resistor, one end of which is connected to the positive input stage of the hysteresis comparator and the other end of which is grounded;

[0025] a third resistor, one end of which is connected to the power supply and the other end of which is connected to the negative input stage of the hysteresis comparator;

[0026] A fourth resistor has one end connected to the negative input stage of the hysteresis comparator and the other end grounded.

[0027] The detection circuit comprises:

[0028] A hysteresis comparator, whose positive input stage is connected to the first isolation capacitor, whose positive input stage inputs the charge signal SIG_MR, and whose output terminal outputs the voltage signal SIG_MRD, and the hysteresis comparator is used to restore the timing information of the signal before coupling;

[0029] a fifth resistor, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the positive input stage of the hysteresis comparator;

[0030] A sixth resistor has one end connected to the bias voltage signal VREFX, and the other end connected to the negative input stage of the hysteresis comparator.

[0031] The isolation capacitor group includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor couples the modulated fixed frequency signal SIG_ML to form a charge signal SIG_MR. The second isolation capacitor couples the modulated fixed frequency signal SIG_MLB to form a charge signal SIG_MRB.

[0032] The detection circuit comprises:

[0033] A hysteresis comparator, wherein the positive input stage is connected to the first isolation capacitor, the positive input stage inputs the charge signal SIG_MR, the negative input stage is connected to the second isolation capacitor, the negative input stage inputs the charge signal SIG_MRB, and the output terminal outputs the voltage signal SIG_MRD;

[0034] a first resistor, one end of which is connected to the power supply and the other end of which is connected to the positive input stage of the hysteresis comparator;

[0035] a second resistor, one end of which is connected to the positive input stage of the hysteresis comparator and the other end of which is grounded;

[0036] a third resistor, one end of which is connected to the power supply and the other end of which is connected to the negative input stage of the hysteresis comparator;

[0037] A fourth resistor has one end connected to the negative input stage of the hysteresis comparator and the other end grounded.

[0038] The detection circuit comprises:

[0039] A hysteresis comparator, wherein the positive input stage is connected to the first isolation capacitor, the positive input stage inputs the charge signal SIG_MR, the negative input stage is connected to the second isolation capacitor, the negative input stage inputs the charge signal SIG_MRB, and the output terminal outputs the voltage signal SIG_MRD;

[0040] a fifth resistor, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the positive input stage of the hysteresis comparator;

[0041] A sixth resistor has one end connected to the bias voltage signal VREFX, and the other end connected to the negative input stage of the hysteresis comparator.

[0042] The demodulation circuit comprises:

[0043] A high-level time-to-voltage circuit, whose input terminal inputs a delayed voltage signal SIG_MRD_DLY, and whose output terminal outputs a high-level time-converted voltage signal VH, and the high-level time-to-voltage circuit is used to convert a high-level time quantity into a voltage quantity VH;

[0044] A low-level time-to-voltage circuit, whose input terminal inputs a delayed voltage signal SIG_MRD_DLY, and whose output terminal outputs a low-level time-converted voltage signal VL, and the low-level time-to-voltage circuit is used to convert a low-level time quantity into a voltage quantity VL;

[0045] The demodulation trigger circuit has an input terminal inputting a high-level time-converted voltage signal VH and a low-level time-converted voltage signal VL, and an output terminal outputting a demodulation signal SIG_OUTR.

[0046] The high level time-to-voltage conversion circuit comprises:

[0047] A current source transistor, whose source is connected to the power supply, the gate is connected to the bias voltage IBIAS, and the drain is connected to the source of the switching transistor;

[0048] A switch transistor, whose source is connected to the drain of the current source transistor, whose gate is connected to the output end of the inverter, and whose drain is connected to the high-level time conversion voltage signal VH;

[0049] A discharge transistor, whose source is connected to the high-level time conversion voltage signal VH, whose gate is connected to the discharge signal DISC, and whose drain is grounded;

[0050] A capacitor, one end of which is connected to the high-level time conversion voltage signal VH, and the other end is grounded;

[0051] The inverter has an input end connected to the delayed voltage signal SIG_MRD_DLY output by the delay circuit, and an output end connected to the gate of the switching transistor.

[0052] The low level time-to-voltage conversion circuit comprises:

[0053] A current source transistor, whose source is connected to the power supply, the gate is connected to the bias voltage IBIAS, and the drain is connected to the source of the switching transistor;

[0054] A switch transistor, whose source is connected to the drain of the current source transistor, whose gate is connected to the delayed voltage signal SIG_MRD_DLY output by the delay circuit, and whose drain is connected to the low-level time conversion voltage signal VL;

[0055] A discharge transistor, whose source is connected to the low-level time conversion voltage signal VL, whose gate is connected to the discharge signal DISC, and whose drain is grounded;

[0056] A capacitor, one end of which is connected to the low-level time conversion voltage signal VL, and the other end is grounded.

[0057] The described demodulation trigger circuit includes:

[0058] A comparator, whose positive input terminal is connected to the high-level time conversion voltage signal VH output by the high-level time-to-voltage circuit, whose negative input terminal is connected to the low-level time conversion voltage signal VL output by the low-level time-to-voltage circuit, and whose output terminal outputs a comparison signal DAT to the flip-flop; when VH > VL, the comparison signal DAT is at a high level, and when VH < VL, the comparison signal DAT is at a low level;

[0059] A flip-flop, whose data input terminal D is connected to the output terminal of the comparator, whose trigger clock terminal C is connected to the voltage signal SIG_MRD, and whose output terminal Q outputs a demodulation signal SIG_OUTR.

[0060] The present invention performs signal transmission through special duty cycle modulation and demodulation, and uses a capacitor as a signal isolation device to achieve signal isolation transmission. Using a capacitor as the isolation device, the stable, low-cost, low-power, and easy-to-integrate characteristics of the capacitor make the present invention have very good practicability. Brief Description of the Drawings

[0061] Figure 1 is a circuit diagram of the first embodiment of a capacitor-based signal isolation transmission circuit provided by the present invention.

[0062] Figure 2 is Figure 1 the signal transmission circuit diagram when the first signal transmission circuit in [reference] works in the input mode and the second signal transmission circuit works in the output mode.

[0063] Figure 3 is Figure 1 the signal transmission circuit diagram when the first signal transmission circuit in [reference] works in the output mode and the second signal transmission circuit works in the input mode.

[0064] Figure 4 is a circuit diagram of the second embodiment of a capacitor-based signal isolation transmission circuit provided by the present invention.

[0065] Figure 5 is Figure 4 the signal transmission circuit diagram when the first signal transmission circuit in [reference] works in the input mode and the second signal transmission circuit works in the output mode.

[0066] Figure 6 is Figure 4 the signal transmission circuit diagram when the first signal transmission circuit in [reference] works in the output mode and the second signal transmission circuit works in the input mode.

[0067] Figure 7 is the working waveform diagram of the modulation circuit of the present invention.

[0068] Figure 8 It is a typical circuit diagram of the modulation circuit of the present invention.

[0069] Fig. 9 It is a typical internal working waveform diagram of the modulation circuit of the present invention.

[0070] Fig.10 is a circuit diagram of a first embodiment of a detection circuit of the present invention.

[0071] Fig.11 1 is a working waveform diagram of the first embodiment of the detection circuit of the present invention.

[0072] Fig.12 is a circuit diagram of a second embodiment of a detection circuit of the present invention.

[0073] Fig.13 is a circuit diagram of a third embodiment of a detection circuit of the present invention.

[0074] Fig.14 is a circuit diagram of a fourth embodiment of a detection circuit of the present invention.

[0075] Fig.15 It is a typical internal circuit of the demodulation circuit of the present invention.

[0076] Fig.16 It is a demodulation waveform diagram of the demodulation circuit of the present invention.

[0077] Fig.17 It is a typical internal working waveform diagram of the demodulation circuit of the present invention. DETAILED DESCRIPTION

[0078] The following is based on Figure 1 to Figure 17 , specifically describe the preferred embodiments of the present invention.

[0079] like Figure 1 As shown, the present invention provides a capacitor-based signal isolation transmission circuit, comprising: a first signal transmission circuit 101, a second signal transmission circuit 102, and a first isolation capacitor 103 respectively connected to the first signal transmission circuit 101 and the second signal transmission circuit 102.

[0080] The first signal transmission circuit 101 and the second signal transmission circuit 102 respectively include a signal input module and a signal output module, and the first signal transmission circuit 101 and the second signal transmission circuit 102 can respectively work in input mode and output mode, that is, the first signal transmission circuit 101 and the second signal transmission circuit 102 are both a half-duplex working mode, and the relationship between the first signal transmission circuit 101 and the second signal transmission circuit 102 is equivalent to the relationship between the host and the slave, the host can send information to the slave, and the slave can also send information to the host, thereby realizing the interaction of information between the host and the slave. When working in input mode, only the signal input module works, and the signal output module does not work; when working in output mode, only the signal output module works, and the signal input module does not work; the first signal transmission circuit 101 and the second signal transmission circuit 102 do not work in input mode or output mode at the same time, but are staggered, that is, when the first signal transmission circuit 101 works in input mode, the second signal transmission circuit 102 works in output mode, realizing isolated transmission of signals from the first signal transmission circuit 101 to the second signal transmission circuit 102; when the first signal transmission circuit 101 works in output mode, the second signal transmission circuit 102 works in input mode, realizing isolated transmission of signals from the second signal transmission circuit 102 to the first signal transmission circuit. By default, both the first signal transmission circuit 101 and the second signal transmission circuit 102 are in output mode, and no signal is transmitted until the first signal transmission circuit 101 or the second signal transmission circuit 102 enters input mode and starts signal transmission.

[0081] Specifically, the first signal transmission circuit 101 includes a signal input module and a signal output module;

[0082] The signal input module comprises: a first modulation circuit 108, whose input end is connected to the input signal SIG_INL, and whose output end is connected to the first isolation capacitor 103, and is used to convert the input signal SIG_INL into an output signal SIG_ML with a fixed frequency, and the first modulation circuit 108 converts the high level of the input signal SIG_INL into a clock cycle of a first specific duty cycle, and converts the low level of the input signal SIG_INL into a clock cycle of a second specific duty cycle;

[0083] The signal output module comprises:

[0084] A first detection circuit 104, whose input end is connected to the first isolation capacitor 103, and whose output end is connected to the first demodulation circuit 107, is used to convert the charge signal SIG_ML coupled from the first isolation capacitor 103 into a voltage signal SIG_MLD;

[0085] The first demodulation circuit 107 has an input end connected to the first detection circuit 104 and an output end outputting a demodulation signal SIG_OUTL, and is used for demodulating the voltage signal SIG_MLD output by the first detection circuit 104 to obtain a demodulation signal SIG_OUTL.

[0086] Similarly, the second signal transmission circuit 102 includes a signal input module and a signal output module;

[0087] The signal input module comprises: a second modulation circuit 109, whose input end is connected to the input signal SIG_INR, and whose output end is connected to the first isolation capacitor 103, and is used to convert the input signal SIG_INR into an output signal SIG_MR with a fixed frequency, and the second modulation circuit 109 converts the high level of the input signal SIG_INR into a clock cycle of a first specific duty cycle, and converts the low level of the input signal SIG_INR into a clock cycle of a second specific duty cycle;

[0088] The signal output module comprises:

[0089] A second detection circuit 106, whose input end is connected to the first isolation capacitor 103, and whose output end is connected to the second demodulation circuit 105, is used for converting the charge signal SIG_MR coupled from the first isolation capacitor 103 into a voltage signal SIG_MRD;

[0090] The second demodulation circuit 105 has an input end connected to the second detection circuit 106 and an output end outputting a demodulation signal SIG_OUTR, and is used for demodulating the voltage signal SIG_MRD output by the second detection circuit 106 to obtain a demodulation signal SIG_OUTR.

[0091] like Figure 2As shown, it is a unidirectional isolation transmission circuit from the first signal transmission circuit 101 to the second signal transmission circuit 102. The first signal transmission circuit 101 is in input mode, and only the first modulation circuit 108 is working. The second signal transmission circuit 102 is in output mode, and only the second detection circuit 106 and the second demodulation circuit 105 are working. The first modulation circuit 108 converts the input signal SIG_INL into a signal SIG_ML with a fixed frequency, and converts the high level of the input signal SIG_INL into a clock cycle of a first specific duty cycle, and converts the low level of the input signal SIG_INL into a clock cycle of a second specific duty cycle. The first isolation capacitor 103 is used to achieve signal isolation, which couples the modulated fixed frequency signal SIG_ML into a charge signal SIG_MR and inputs it into the second signal transmission circuit 102. The second detection circuit 106 converts the charge signal SIG_MR coupled through the first isolation capacitor 103 into a voltage signal SIG_MRD. The voltage signal SIG_MRD is input to the second demodulation circuit 105. The second demodulation circuit 105 demodulates the voltage signal SIG_MRD and outputs a demodulation signal SIG_OUTR.

[0092] like Figure 3 As shown, it is a unidirectional isolation transmission circuit from the second signal transmission circuit 102 to the first signal transmission circuit 101. The second signal transmission circuit 102 is in input mode, and only the second modulation circuit 109 works. The first signal transmission circuit 101 is in output mode, and only the first detection circuit 104 and the first demodulation circuit 107 work. The second modulation circuit 109 converts the input signal SIG_INR into a signal SIG_MR with a fixed frequency, and converts the high level of the input signal SIG_INR into a clock cycle of a first specific duty cycle, and converts the low level of the input signal SIG_INR into a clock cycle of a second specific duty cycle. The first isolation capacitor 103 is used to achieve signal isolation, which couples the modulated fixed frequency signal SIG_MR into a charge signal SIG_ML and inputs it into the first signal transmission circuit 101. The first detection circuit 104 converts the charge signal SIG_ML coupled through the first isolation capacitor 103 into a voltage signal SIG_MLD. The voltage signal SIG_MLD is input to the first demodulation circuit 107. The first demodulation circuit 107 demodulates the voltage signal SIG_MLD and outputs a demodulation signal SIG_OUTL.

[0093] from Figure 2 and Figure 3 It can be seen that the signal isolation transmission from the first signal transmission circuit 101 to the second signal transmission circuit 102 is completely consistent with the signal isolation transmission from the second signal transmission circuit 102 to the first signal transmission circuit 101 .

[0094] The invention can transmit any pulse signal and is a universal half-duplex signal isolation transmission circuit.

[0095] like Figure 4 As shown, in another embodiment of the present invention, Figure 1 A second isolation capacitor 110 is added on the basis of the embodiment. When the first signal transmission circuit 101 is in input mode, the first modulation circuit 108 outputs two fixed frequency modulation signals SIG_ML and SIG_MLB, SIG_ML and SIG_MLB are a pair of complementary signals, that is, SIG_MLB is the inversion of the SIG_ML signal, the first isolation capacitor 103 couples the modulated fixed frequency modulation signal SIG_ML to become a charge signal SIG_MR and inputs it to the second signal transmission circuit 102, and the second isolation capacitor 110 couples the modulated fixed frequency modulation signal SIG_MLB to become a charge signal SIG_MRB and inputs it to the second signal transmission circuit 102. When the second signal transmission circuit 102 is in input mode, the second modulation circuit 109 outputs two fixed frequency modulation signals SIG_MR and SIG_MRB, SIG_MR and SIG_MRB are a pair of complementary signals, that is, SIG_MRB is the inversion of the SIG_MR signal, the first isolation capacitor 103 couples the modulated fixed frequency modulation signal SIG_MR into a charge signal SIG_ML and inputs it to the first signal transmission circuit 101, and the second isolation capacitor 110 couples the modulated fixed frequency modulation signal SIG_MRB into a charge signal SIG_MLB and inputs it to the first signal transmission circuit 101. The isolated transmission of signals is realized between the first signal transmission circuit 101 and the second signal transmission circuit 102 through two isolation capacitors, because the detection circuit detects the differential potential of the two-way signal, so the dual-way isolation capacitor solution helps the stability and safety of signal detection.

[0096] like Figure 5 As shown, it is a unidirectional isolation transmission circuit from the first signal transmission circuit 101 to the second signal transmission circuit 102. Figure 2 A second isolation capacitor 110 is added on the basis of the circuit to form a dual-capacitor isolation signal transmission circuit. Figure 5 and Figure 2 The circuit functions are the same.

[0097] like Figure 6 As shown, it is a unidirectional isolation transmission circuit from the second signal transmission circuit 102 to the first signal transmission circuit 101. Figure 3 A second isolation capacitor 110 is added on the basis of the circuit to form a dual-capacitor isolation signal transmission circuit. Figure 6 and Figure 3 The circuit functions are the same.

[0098] like Figure 7As shown, taking the unidirectional isolation transmission circuit from the first signal transmission circuit 101 to the second signal transmission circuit 102 as an example, the time period of the first specific duty cycle is 75% as an example, and the time period of the second specific duty cycle is 25% as an example. When the input signal SIG_INL is a 100% high-level signal, the input frequency of the modulation signal SIG_ML is fixed and the duty cycle is constant at 75% of the clock cycle. When the input signal SIG_INL is a pulse signal, the high-level area of ​​SIG_INL is modulated into a clock cycle with a duty cycle of 75%, and the low-level area of ​​SIG_INL is modulated into a clock cycle with a duty cycle of 25%. In order to perfectly modulate the input signal SIG_INL, the high-level time and low-level time of SIG_INL are required to be integer multiples of the modulation clock cycle. When the input signal SIG_INL is a 100% low-level signal, the input frequency of the modulation signal SIG_ML is fixed and the duty cycle is constant at 25% of the clock cycle.

[0099] like Figure 8 As shown, the modulation circuit (the first modulation circuit 108 or the second modulation circuit 109) includes:

[0100] The signal modulation circuit 500 has an input terminal that receives a signal SIG_INL and a reference clock signal CK0, and an output terminal that outputs a modulation signal SIGX, which is used to perform duty cycle modulation on the signal;

[0101] The glitch filtering circuit 506 has an input terminal that inputs the modulation signal SIGX and an output terminal that outputs two fixed frequency modulation signals SIG_ML and SIG_MLB, which are used to filter signal glitches.

[0102] Further, the signal modulation circuit 500 includes: a frequency division trigger 501, an AND gate 502, an inverter 503, a 4-input AND-OR gate 504, and an OR gate 505. The reference clock signal CK0 generates a frequency division clock signal CK1 after passing through the frequency division trigger 501. The reference clock signal CK0 and the frequency division clock signal CK1 are input to the AND gate 502 to output the signal CK_AND. The reference clock signal CK0 and the frequency division clock signal CK1 are input to the OR gate 505 to output the signal CK_OR. The input signal SIG_INL is input to the inverter 503 to output the signal SIG_INB. The signal CK_AND, the signal CK_OR, the signal SIG_INL and the signal SIG_INB are input to the 4-input AND-OR gate 504 together, wherein the signal CK_AND is ANDed with the signal SIG_INB, the signal CK_OR is ANDed with the signal SIG_INL, and the results of the two are ORed to obtain the signal SIGX, which is the transition modulation signal. Since the signal modulation circuit 500 is a combinational logic circuit, a glitch will be generated in the transition modulation signal SIGX at the edge of the clock, so the modulation signal SIGX is input into the glitch filtering circuit 506 .

[0103] The glitch filtering circuit 506 comprises: a delay circuit 507, an XOR gate 508, a glitch filtering trigger 509, and tri-state buffers 510 and 511. The reference clock signal CK0 passes through the delay circuit 507 and is input to the XOR gate 508 together with the reference clock signal CK0. The XOR gate 508 outputs a trigger signal TRIG. The trigger signal TRIG is connected to the clock signal end of the glitch filtering trigger 509. The modulation signal SIGX is input to the data end of the glitch filtering trigger 509. The falling edge of the trigger signal TRIG samples the state of the modulation signal SIGX, thereby filtering the glitches. The positive output end of the glitch filter trigger 509 outputs the signal SIG_ML_BUF to the three-state buffer 510, and the reverse output end outputs the signal SIG_MLB_BUF to the three-state buffer 511. The signal SIG_ML_BUF outputs the signal SIG_ML through the three-state buffer 510, and the signal SIG_MLB_BUF outputs the signal SIG_MLB through the three-state buffer 511. The three-state buffer can enable the first signal transmission circuit 101 and the second signal transmission circuit 102 to set the output end of the modulation circuit to a high-impedance output when in the input mode.

[0104] like Fig. 9 As shown, Figure 8The working waveform diagram of the modulation circuit in the figure, the first specific duty cycle is 75% as an example, and the second specific duty cycle is 25% as an example. Among them, CK0 is the reference clock of the entire modulation circuit, and CK1 is the two-frequency signal of the clock signal CK0. After CK0 and CK1 are ANDed, the CK_AND signal is obtained, which is a 25% duty cycle. After CK0 and CK1 are ORed, the CK_OR signal is obtained, which is a 75% duty cycle. Through the selection of the AND-OR gate 504, when SIG_INL is high, SIGX=CK_OR, that is, a 75% duty cycle signal is input; when SIG_INL is low, SIGX=CK_AND, that is, a 25% duty cycle signal is output. Therefore, SIGX realizes 25%-75% modulation of SIG_INL signal. Since SIGX signal is generated by logic circuit, it is easy to generate burrs at the jumping edge of clock signal. Therefore, SIGX signal glitch filtering is realized by glitch filtering circuit 506, wherein delay circuit 507 and XOR gate 508 generate trigger signal TRIG. Using the falling edge of TRIG signal as trigger signal, trigger 509 samples SIGX signal and outputs glitch-free 25%-75% modulation signals SIG_ML and SIG_MLB.

[0105] like Fig.10 As shown in FIG. 1 , a first embodiment of a detection circuit (a first detection circuit 104 or a second detection circuit 106) is shown. The detection circuit is suitable for Figure 1 In the single isolation capacitor solution shown in FIG. 1 , the detection circuit includes:

[0106] A hysteresis comparator 701, whose positive input stage is connected to the first isolation capacitor 103, whose positive input stage inputs a charge signal SIG_MR, and whose output terminal outputs a voltage signal SIG_MRD. The hysteresis comparator 701 is used to restore the timing information of the signal before coupling;

[0107] A first resistor 702, one end of which is connected to the power supply, and the other end of which is connected to the positive input stage of the hysteresis comparator 701;

[0108] A second resistor 703, one end of which is connected to the positive input stage of the hysteresis comparator 701, and the other end of which is grounded;

[0109] A third resistor 704, one end of which is connected to the power supply, and the other end of which is connected to the negative input stage of the hysteresis comparator 701;

[0110] The fourth resistor 705 has one end connected to the negative input stage of the hysteresis comparator 701 and the other end grounded.

[0111] The first resistor 702 and the second resistor 703 provide a default voltage level VX for the positive input terminal of the hysteresis comparator 701 , and the third resistor 704 and the fourth resistor 705 provide a default voltage level VY for the negative input terminal of the hysteresis comparator 701 , VX=VY.

[0112] like Fig.11 As shown, Fig.10 The working waveform of the detection circuit in the figure shows that the rising edge of SIG_ML will couple the charge to the SIG_MR side, causing the voltage of SIG_MR to rise, and then the voltage is restored through the two pull-up and pull-down resistors connected to SIG_MR. The falling edge of SIG_ML will couple the charge to the SIG_MR side, causing the voltage of SIG_MR to drop, and then the voltage is restored through the two pull-up and pull-down resistors connected to SIG_MR, thereby Fig.11 The SIG_MR voltage waveform shown in FIG. 1 restores the frequency duty cycle and other timing information of SIG_ML at the output terminal SIG_MRD of the hysteresis comparator 701 through the voltage comparison function of the hysteresis comparator 701 .

[0113] like Fig.12 As shown in FIG. 1 , a second embodiment of the detection circuit is shown. The detection circuit is suitable for Figure 1 In the single isolation capacitor solution shown in FIG. 1 , the detection circuit includes:

[0114] A hysteresis comparator 901, whose positive input stage is connected to the first isolation capacitor 103, whose positive input stage inputs a charge signal SIG_MR, and whose output terminal outputs a voltage signal SIG_MRD. The hysteresis comparator 901 is used to restore the timing information of the signal before coupling;

[0115] a fifth resistor 902, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the positive input stage of the hysteresis comparator 901;

[0116] The sixth resistor 903 has one end connected to the bias voltage signal VREFX, and the other end connected to the negative input stage of the hysteresis comparator 901 .

[0117] The fifth resistor 902 and the sixth resistor 903 are simultaneously connected to the bias voltage signal VREFX, so that the positive input terminal and the negative input terminal of the hysteresis comparator 901 are equal to the reference voltage VREFX under default conditions.

[0118] like Fig.13 As shown, it is a third embodiment of the detection circuit, which is suitable for Figure 4 In the dual isolation capacitor solution shown in FIG. 1 , the detection circuit includes:

[0119] A hysteresis comparator 701, whose positive input stage is connected to the first isolation capacitor 103, the positive input stage inputs the charge signal SIG_MR, whose negative input stage is connected to the second isolation capacitor 110, the negative input stage inputs the charge signal SIG_MRB, and whose output terminal outputs the voltage signal SIG_MRD;

[0120] A first resistor 702, one end of which is connected to the power supply, and the other end of which is connected to the positive input stage of the hysteresis comparator 701;

[0121] A second resistor 703, one end of which is connected to the positive input stage of the hysteresis comparator 701, and the other end of which is grounded;

[0122] A third resistor 704, one end of which is connected to the power supply, and the other end of which is connected to the negative input stage of the hysteresis comparator 701;

[0123] The fourth resistor 705 has one end connected to the negative input stage of the hysteresis comparator 701 and the other end grounded.

[0124] The first resistor 702 and the second resistor 703 provide a default voltage level VX for the positive input terminal of the hysteresis comparator 701 , and the third resistor 704 and the fourth resistor 705 provide a default voltage level VY for the negative input terminal of the hysteresis comparator 701 , VX=VY.

[0125] like Fig.14 As shown, it is a fourth embodiment of the detection circuit, which is suitable for Figure 4 In the dual isolation capacitor solution shown in FIG. 1 , the detection circuit includes:

[0126] A hysteresis comparator 901, whose positive input stage is connected to the first isolation capacitor 103, the positive input stage inputs the charge signal SIG_MR, whose negative input stage is connected to the second isolation capacitor 110, the negative input stage inputs the charge signal SIG_MRB, and whose output terminal outputs the voltage signal SIG_MRD;

[0127] a fifth resistor 902, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the positive input stage of the hysteresis comparator 901;

[0128] The sixth resistor 903 has one end connected to the bias voltage signal VREFX, and the other end connected to the negative input stage of the hysteresis comparator 901 .

[0129] The fifth resistor 902 and the sixth resistor 903 are simultaneously connected to the bias voltage signal VREFX, so that the positive input terminal and the negative input terminal of the hysteresis comparator 901 are equal to the reference voltage VREFX under default conditions.

[0130] like Fig.15 As shown, the demodulation circuit (the first demodulation circuit 107 or the second demodulation circuit 105) includes:

[0131] A high-level time-to-voltage circuit 1111, whose input terminal inputs a delayed voltage signal SIG_MRD_DLY, and whose output terminal outputs a high-level time-converted voltage signal VH, and the high-level time-to-voltage circuit 1111 is used to convert a high-level time quantity into a voltage quantity VH;

[0132] A low level time to voltage circuit 1112, whose input terminal inputs the delayed voltage signal SIG_MRD_DLY, and whose output terminal outputs the low level time conversion voltage signal VL, and the low level time to voltage circuit 1112 is used to convert the low level time quantity into the voltage quantity VL;

[0133] The demodulation trigger circuit 1113 has an input terminal inputting a high-level time-converted voltage signal VH and a low-level time-converted voltage signal VL, and an output terminal outputting a demodulation signal SIG_OUTR.

[0134] Furthermore, the high level time-to-voltage conversion circuit 1111 comprises:

[0135] A current source transistor 1101, whose source is connected to a power supply, whose gate is connected to a bias voltage IBIAS, and whose drain is connected to a source of a switch transistor 1102;

[0136] A switch transistor 1102, whose source is connected to the drain of the current source transistor 1101, whose gate is connected to the output end of the inverter 1114, and whose drain is connected to the high-level time conversion voltage signal VH;

[0137] A discharge transistor 1103, whose source is connected to the high-level time conversion voltage signal VH, whose gate is connected to the discharge signal DISC, and whose drain is grounded;

[0138] A capacitor 1104, one end of which is connected to the high-level time conversion voltage signal VH, and the other end is grounded;

[0139] The inverter 1114 has an input terminal connected to the delayed voltage signal SIG_MRD_DLY output by the delay circuit, and an output terminal connected to the gate of the switch transistor 1102 .

[0140] The low level time to voltage conversion circuit 1112 comprises:

[0141] A current source transistor 1105, whose source is connected to the power supply, whose gate is connected to the bias voltage IBIAS, and whose drain is connected to the source of the switch transistor 1106;

[0142] A switch transistor 1106, whose source is connected to the drain of the current source transistor 1105, whose gate is connected to the delayed voltage signal SIG_MRD_DLY output by the delay circuit, and whose drain is connected to the low-level time conversion voltage signal VL;

[0143] A discharge transistor 1107, whose source is connected to the low-level time conversion voltage signal VL, whose gate is connected to the discharge signal DISC, and whose drain is grounded;

[0144] The capacitor 1108 has one end connected to the low-level time conversion voltage signal VL and the other end grounded.

[0145] The described demodulation trigger circuit 1113 includes:

[0146] A comparator 1109, whose positive input terminal is connected to the high-level time conversion voltage signal VH output by the high-level time-to-voltage circuit 1111, whose negative input terminal is connected to the low-level time conversion voltage signal VL output by the low-level time-to-voltage circuit 1112, and whose output terminal outputs a comparison signal DAT to the flip-flop 1110; when VH > VL, the comparison signal DAT is at a high level, and when VH < VL, the comparison signal DAT is at a low level;

[0147] A flip-flop 1110, whose data input terminal D is connected to the output terminal of the comparator 1109, whose trigger clock terminal C is connected to the voltage signal SIG_MRD, and whose output terminal Q outputs a demodulation signal SIG_OUTR.

[0148] As Fig.16 shown, the modulated signal SIG_MRD is restored to SIG_OUTR by the demodulation circuit. Among them, the clock cycle with a duty ratio of 75% is restored to a high level, and the clock cycle with a duty ratio of 25% is restored to a low level. Since the determination of the duty ratio of the current modulation chip by the demodulation circuit will be expressed in the next cycle, there will be a delay of one modulation clock cycle from SIG_MRD to SIG_OUTR, that is, there will be a delay of one modulation clock cycle for SIG_OUTR relative to SIG_INL.

[0149] As Fig.17As shown, the modulation signal SIG_MRD generates a modulation signal SIG_MRD_DLY after a delay of T0. The rising edge of SIG_MRD_DLY generates a pulse signal DISC with a pulse width of T1. During the high level period of SIG_MRD_DLY, the switching transistor 1102 is turned on, and the current source transistor 1101 charges the capacitor 1104, causing the VH voltage to rise and the switching transistor 1106 to turn off, and the VL voltage to be maintained; during the low level period of SIG_MRD_DLY, the switching transistor 1106 is turned on, and the current source transistor 1105 charges the capacitor 1108, causing the VL voltage to rise and the switching transistor 1102 to turn off, and the VH voltage to be maintained; when the SIG_MRD_DLY signal has a 25% duty cycle, after one clock cycle of charging, VH < VL, the comparator 1109 outputs DAT as low, and the rising edge of SIG_MRD samples the DAT signal, and SIG_OUTR outputs low. When the SIG_MRD_DLY signal has a 75% duty cycle, after one clock cycle of charging, VH > VL, the comparator 1109 outputs DAT as high, and the rising edge of SIG_MRD samples the DAT signal, and SIG_OUTR outputs high. Thus, the demodulation of the SIG_MRD signal is achieved. Since the demodulation signal SIG_OUTR demodulates the SIG_MRD signal of the previous cycle, there is a one-cycle lag relative to the original input signal SIG_INL.

[0150] The present invention performs signal transmission through special duty cycle modulation and demodulation, and uses a capacitor as a signal isolation device to achieve signal isolation transmission. Using a capacitor as the isolation device, the stable, low-cost, low-power, and easy-to-integrate characteristics of the capacitor make the present invention have very good practicability.

[0151] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and substitutions to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A capacitor-based signal isolation transmission circuit, characterized in that: It comprises: a first signal transmission circuit and a second signal transmission circuit with completely identical structures, and an isolation capacitor group respectively connected to the first signal transmission circuit and the second signal transmission circuit; The first signal transmission circuit and the second signal transmission circuit each include a signal input module and a signal output module, and the first signal transmission circuit and the second signal transmission circuit can respectively work in an input mode and an output mode, when working in the input mode, only the signal input module works, and the signal output module does not work, and when working in the output module, only the signal output module works, and the signal input module does not work; When the first signal transmission circuit works in the input mode, the second signal transmission circuit works in the output mode; when the second signal transmission circuit works in the input mode, the first signal transmission circuit works in the output mode; The signal input module is a modulation circuit, which converts the high level of the input signal into a clock cycle of a first duty cycle, and converts the low level of the input signal into a clock cycle of a second duty cycle, wherein the first duty cycle is 75% and the second duty cycle is 25%; or the first duty cycle is 25% and the second duty cycle is 75%; the modulation circuit comprises: A signal modulation circuit, whose input terminal inputs a signal SIG_INL and a reference clock signal CK0, and whose output terminal outputs a modulation signal SIGX, which is used to perform duty cycle modulation on the signal; A glitch filtering circuit, whose input terminal inputs a modulation signal SIGX, and whose output terminal outputs two mutually inverted fixed frequency modulation signals SIG_ML and SIG_MLB, which are used to filter signal glitches; The isolation capacitor group realizes signal isolation transmission, and the isolation capacitor group couples the modulated fixed frequency signal into a charge signal; The signal output module includes a detection circuit and a demodulation circuit. The input end of the detection circuit is connected to the isolation capacitor group, and the output end of the detection circuit is connected to the input end of the demodulation circuit. The detection circuit converts the charge signal coupled from the isolation capacitor group into a voltage signal, and the demodulation circuit demodulates the voltage signal to obtain a demodulation signal.

2. The capacitor-based signal isolation transmission circuit according to claim 1, characterized in that: The signal modulation circuit comprises: A frequency division trigger, an AND gate, an inverter, a 4-input AND-OR gate, and an OR gate. The reference clock signal CK0 generates a frequency division clock signal CK1 after passing through the frequency division trigger. The reference clock signal CK0 and the divided clock signal CK1 are input to the AND gate and then the output signal CK_AND is input. The reference clock signal CK0 and the divided clock signal CK1 are input to the OR gate and the output signal CK_OR is input. The input signal SIG_INL is input to the inverter and the output signal SIG_INB is input. The signal CK_AND and the signal CK_OR, signal SIG_INL and signal SIG_INB are input to a 4-input AND-OR gate, where signal CK_AND is ANDed with signal SIG_INB, and signal CK_OR is ANDed with signal SIG_INL is ANDed, and the results of the two are ORed to obtain the signal SIGX, which is the transitional modulation signal.

3. The capacitor-based signal isolation transmission circuit according to claim 2, characterized in that: The burr filtering circuit comprises: A delay circuit, an XOR gate, a glitch filter trigger, and a tri-state buffer. The reference clock signal CK0 is input to the XOR gate together with the reference clock signal CK0 after passing through the delay circuit. The XOR gate outputs a trigger signal TRIG. The trigger signal TRIG is connected to the clock signal end of the glitch filter trigger. The modulation signal SIGX is input to the data end of the glitch filter trigger. The falling edge of the trigger signal TRIG samples the state of the modulation signal SIGX. The positive output end of the glitch filter trigger outputs a signal SIG_ML_BUF to the tri-state buffer, and the negative output end outputs a signal SIG_MLB_BUF is given to the tri-state buffer, and the tri-state buffer outputs a high-impedance output signal SIG_ML and high-impedance output signal SIG_MLB.

4. The capacitor-based signal isolation transmission circuit according to claim 1, characterized in that: The isolation capacitor group includes a first isolation capacitor, which couples the modulated fixed frequency signal SIG_ML to form a charge signal SIG_MR.

5. The capacitor-based signal isolation transmission circuit according to claim 4, characterized in that: The detection circuit comprises: A hysteresis comparator, whose positive input stage is connected to the first isolation capacitor, whose positive input stage inputs the charge signal SIG_MR, and whose output terminal outputs the voltage signal SIG_MRD, and the hysteresis comparator is used to restore the timing information of the signal before coupling; a first resistor, one end of which is connected to the power supply and the other end of which is connected to the positive input stage of the hysteresis comparator; a second resistor, one end of which is connected to the positive input stage of the hysteresis comparator and the other end of which is grounded; a third resistor, one end of which is connected to the power supply and the other end of which is connected to the negative input stage of the hysteresis comparator; A fourth resistor has one end connected to the negative input stage of the hysteresis comparator and the other end grounded.

6. The capacitor-based signal isolation transmission circuit according to claim 4, characterized in that: The detection circuit comprises: A hysteresis comparator, whose positive input stage is connected to the first isolation capacitor, whose positive input stage inputs the charge signal SIG_MR, and whose output terminal outputs the voltage signal SIG_MRD, and the hysteresis comparator is used to restore the timing information of the signal before coupling; a fifth resistor, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the positive input stage of the hysteresis comparator; A sixth resistor has one end connected to the bias voltage signal VREFX, and the other end connected to the negative input stage of the hysteresis comparator.

7. The capacitor-based signal isolation transmission circuit according to claim 1, characterized in that: The isolation capacitor group includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor couples the modulated fixed frequency signal SIG_ML to form a charge signal SIG_MR. The second isolation capacitor couples the modulated fixed frequency signal SIG_MLB to form a charge signal SIG_MRB.

8. The capacitor-based signal isolation transmission circuit according to claim 7, characterized in that: The detection circuit comprises: A hysteresis comparator, wherein the positive input stage is connected to the first isolation capacitor, the positive input stage inputs the charge signal SIG_MR, the negative input stage is connected to the second isolation capacitor, the negative input stage inputs the charge signal SIG_MRB, and the output terminal outputs the voltage signal SIG_MRD; a first resistor, one end of which is connected to the power supply and the other end of which is connected to the positive input stage of the hysteresis comparator; a second resistor, one end of which is connected to the positive input stage of the hysteresis comparator and the other end of which is grounded; a third resistor, one end of which is connected to the power supply and the other end of which is connected to the negative input stage of the hysteresis comparator; A fourth resistor has one end connected to the negative input stage of the hysteresis comparator and the other end grounded.

9. The capacitor-based signal isolation transmission circuit according to claim 7, characterized in that: The detection circuit comprises: A hysteresis comparator, whose positive input stage is connected to a first isolation capacitor, and the positive input stage inputs a charge signal SIG_MR. Its negative input stage is connected to a second isolation capacitor, and the negative input stage inputs a charge signal SIG_MRB. Its output terminal outputs a voltage signal SIG_MRD; A fifth resistor, one end of which is connected to a bias voltage signal VREFX, and the other end is connected to the positive input stage of the hysteresis comparator; A sixth resistor, one end of which is connected to a bias voltage signal VREFX, and the other end is connected to the negative input stage of the hysteresis comparator.

10. The capacitor-based signal isolation transmission circuit according to any one of claims 5, 6, 8, and 9, characterized in that: The described demodulation circuit includes: A high-level time-to-voltage circuit, whose input terminal inputs a delayed voltage signal SIG_MRD_DLY, and its output terminal outputs a high-level time conversion voltage signal VH. This high-level time-to-voltage circuit is used to convert the high-level time quantity into a voltage quantity VH; A low-level time-to-voltage circuit, whose input terminal inputs a delayed voltage signal SIG_MRD_DLY, and its output terminal outputs a low-level time conversion voltage signal VL. This low-level time-to-voltage circuit is used to convert the low-level time quantity into a voltage quantity VL; A demodulation trigger circuit, whose input terminal inputs a high-level time conversion voltage signal VH and a low-level time conversion voltage signal VL, and its output terminal outputs a demodulation signal SIG_OUTR.

11. The capacitor-based signal isolation transmission circuit according to claim 10, characterized in that: The described high-level time-to-voltage circuit includes: A current source transistor, whose source is connected to the power supply, the gate is connected to a bias voltage IBIAS, and the drain is connected to the source of a switching transistor; A switching transistor, whose source is connected to the drain of the current source transistor, the gate is connected to the output terminal of an inverter, and the drain is connected to the high-level time conversion voltage signal VH; A discharging transistor, whose source is connected to the high-level time conversion voltage signal VH, the gate is connected to a discharging signal DISC, and the drain is grounded; A capacitor, one end of which is connected to the high-level time conversion voltage signal VH, and the other end is grounded; An inverter, whose input terminal is connected to the delayed voltage signal output by a delay circuit SIG_MRD_DLY, and its output terminal is connected to the gate of the switching transistor.

12. The capacitor-based signal isolation transmission circuit according to claim 10, characterized in that: The described low-level time-to-voltage circuit includes: A current source transistor, whose source is connected to the power supply, the gate is connected to a bias voltage IBIAS, and the drain is connected to the source of a switching transistor; A switching transistor, whose source is connected to the drain of the current source transistor, the gate is connected to the delayed voltage signal SIG_MRD_DLY output by the delay circuit, and the drain is connected to the low-level time conversion voltage signal VL; A discharging transistor, whose source is connected to the low-level time conversion voltage signal VL, the gate is connected to a discharging signal DISC, and the drain is grounded; A capacitor, one end of which is connected to the low-level time conversion voltage signal VL, and the other end is grounded.

13. The capacitor-based signal isolation transmission circuit according to claim 11 or 12, characterized in that: The described demodulation trigger circuit includes: A comparator, whose positive input terminal is connected to the high-level time conversion voltage signal VH output by the high-level time-to-voltage circuit, its negative input terminal is connected to the low-level time conversion voltage signal VL output by the low-level time-to-voltage circuit, and its output terminal outputs a comparison signal DAT to a flip-flop; when VH > VL, the comparison signal DAT is at a high level, and when VH < VL, the comparison signal DAT is at a low level; A trigger, whose data input terminal D is connected to the output terminal of the comparator, whose trigger clock terminal C is connected to the voltage signal SIG_MRD, and whose output terminal Q outputs the demodulated signal SIG_OUTR.

Images