Memory system that changes operation of memory controller according to internal state

Abstract

A memory system includes a memory device and a memory controller. The memory device outputs data in response to a read command. The memory device includes a first functional circuit, which performs a first operation based on data stored in the memory device in response to the read command to generate first processed data. The memory controller provides the read command to the memory device in response to a read request received from a host. The memory controller receives status information associated with performing the first operation. The memory controller includes a second functional circuit, which performs a second operation based on the first processed data to generate second processed data. The manner of the second operation changes according to the status information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2017-0170426 filed on December 12, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices, and more particularly, to the configuration and operation of a memory system that stores and outputs data. Background Art

[0004] In recent years, various electronic devices are being used. The electronic device performs its own function according to the operation of the electronic circuit included in the electronic device. The memory system may include various electronic circuits for storing data and outputting the stored data, and may be implemented on a single electronic device or on multiple electronic devices.

[0005] The memory system can perform various operations on the data to be stored or the data to be output. For example, the memory system can perform operations for encrypting / decrypting, compressing / decompressing and converting data, and detecting and correcting data errors. Based on such operations, the memory system can store and output data suitable for user requests.

[0006] Meanwhile, with the widespread use of various electronic devices and the increase in the amount of data and information, various requirements for memory systems are required. For example, the scale of semiconductor manufacturing processes has become smaller to store a large amount of data in a memory device on a small circuit area, and various functions need to be implemented for stable and reliable data processing.

[0007] In addition, users may use electronic devices in various situations, so it may be necessary to provide a memory system that operates flexibly. A memory system with a rigid configuration may not provide appropriate functions under certain circumstances or may perform erroneous operations. Therefore, it may be an important issue to implement a memory system that operates flexibly according to circumstances or states. Summary of the invention

[0008] Exemplary embodiments of the present disclosure may provide a memory system configured to flexibly change an operation of a memory controller according to an internal state of a memory device.

[0009] In some exemplary embodiments, a memory system may include a memory device and a memory controller. The memory device may output data in response to a read command. The memory device may include a first functional circuit. The first functional circuit may perform a first operation based on data stored in the memory device in response to the read command to generate first processed data. The memory controller may provide a read command to the memory device in response to a read request received from a host so that data is output to the memory device. The memory controller may receive status information associated with performing the first operation. The memory controller may include a second functional circuit. The second functional circuit may perform a second operation based on the first processed data to generate second processed data. The manner of the second operation may vary according to the status information.

[0010] In some exemplary embodiments, a memory system may include a memory device and a memory controller. The memory device may perform a first error handling operation based on data stored in the memory device to generate first processed data. The memory controller may receive status information associated with performing the first error handling operation. The memory controller may perform a second error handling operation based on the first processed data to generate second processed data. The maximum number of errors detected by the second error handling operation with respect to the first processed data may be greater than the maximum number of errors detected by the first error handling operation with respect to the stored data. The manner of the second error handling operation may vary according to the status information.

[0011] In some exemplary embodiments, a memory system may include a memory device and a memory controller. The memory device may perform a first operation based on data stored in the memory device to generate first processed data. The memory controller may receive state information associated with performing the first operation. The memory controller may perform a second operation based on the first processed data to generate second processed data. The first processed data may be generated differently in the memory device in association with a change in the state information. The manner of the second operation may vary according to the state information. The second processed data may be generated differently in the memory controller according to the change in the state information.

[0012] In some exemplary embodiments, the memory system may include a memory device and a memory controller. The memory controller may perform functional operations based on data received from the memory device to generate processed data. The memory controller may receive state information associated with operations performed in the memory device. The memory controller may perform functional operations in a manner selected based on the state information in different ways. As the state information changes, the data received in the memory controller may be changed.

[0013] In some exemplary embodiments, a memory system includes a memory device and a memory controller. The memory controller: (1) receives first data and status information from the memory device, wherein the first data represents second data stored by the memory device, (2) performs a first operation on the first data in response to determining that the status information indicates the first status, (3) performs a second operation different from the first operation on the first data in response to determining that the status information indicates the second status, and (4) communicates processed data to an external host, wherein the processed data represents the second data and has no error information or a report indicating error information.

[0014] According to some exemplary embodiments, the memory system can operate differently according to the condition or state, and can perform operations to be suitable for a given condition or state. In some exemplary embodiments, undetectable errors and uncorrectable errors can be prevented from occurring, and operating performance and power consumption can be managed. Therefore, the stability, reliability and flexibility of the operation of the memory system can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects and features of the present disclosure will become apparent from the following description with reference to the accompanying drawings.

[0016] Figure 1 is a block diagram illustrating an exemplary configuration of an electronic system according to some exemplary embodiments.

[0017] Figure 2 is shown with Figure 1 A block diagram of an exemplary configuration associated with a storage device.

[0018] Figure 3 is a block diagram illustrating an exemplary configuration of a memory system according to some exemplary embodiments.

[0019] Figure 4 It is shown Figure 3 A block diagram of an exemplary configuration of a memory device.

[0020] Figure 5 is shown with Figure 3 A block diagram of an exemplary configuration associated with a memory system.

[0021] Figure 6 is used to describe Figure 5 A table of error handling operations performed in a memory system.

[0022] Figure 7 is shown with Figure 3 A block diagram of an exemplary configuration associated with a memory system.

[0023] Figure 8 is used to describe the use of Figure 7 A block diagram of an exemplary operation of a memory device to store and output data with parity checking.

[0024] Fig. 9 and Fig.10 is a block diagram for describing an exemplary operation of a memory controller based on Figure 7 The state information in the memory system changes.

[0025] Fig.11 It is shown Figure 7 A block diagram of an exemplary configuration of a variable error correction code (ECC) circuit.

[0026] Fig.12 is shown with Figure 3 A block diagram of an exemplary configuration associated with a memory system.

[0027] Fig.13 and Fig.14 is a block diagram for describing an exemplary operation of a memory controller based on Fig.12 The state information in the memory system changes.

[0028] Fig.15 It is shown Fig.12 00140] A block diagram of an exemplary configuration of a variable decompressor circuit.

[0029] Figures 16 to 18 is used to transfer status information from Figure 3 A block diagram of an exemplary configuration of a memory controller is provided to a memory system.

[0030] Fig.19 Is a description and Figure 3 A flowchart of exemplary operations associated with a memory system. DETAILED DESCRIPTION

[0031] Hereinafter, some exemplary embodiments will be described in detail and clearly with reference to the accompanying drawings so that those skilled in the art can easily realize the present disclosure.

[0032] Figure 1 is a diagram showing an exemplary configuration of an electronic system 1000 according to some exemplary embodiments.

[0033] The electronic system 1000 may include a main processor 1101, a working memory 1200, a storage device 1300, a communication block 1400, a user interface 1500, and a bus 1600. For example, the electronic system 1000 may be one of electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a workstation, one or more servers, an electric vehicle, a home appliance, a medical device, etc.

[0034] The main processor 1101 may control the overall operation of the electronic system 1000. For example, the main processor 1101 may be implemented with a general-purpose processor, a dedicated processor, or an application processor, and the main processor includes one or more processor cores.

[0035] The working memory 1200 may store data used in the operation of the electronic system 1000. For example, the working memory 1200 may temporarily store data processed or to be processed by the main processor 1101. For example, the working memory 1200 may include a volatile memory (such as a static random access memory (SRAM), a dynamic RAM (DRAM), and / or a synchronous DRAM (SDRAM)) and / or a nonvolatile memory (such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), and / or a ferroelectric RAM (FRAM)).

[0036] For example, the working memory 1200 may include one or more memory devices 1210 and a controller 1230. The memory device 1210 may include a memory element for storing or outputting data. The number of the memory device 1210 may be variously changed or modified to suit the requirements of the electronic system 1000.

[0037] The controller 1230 may control the memory device 1210 so that the memory device 1210 stores or outputs data. The controller 1230 may perform various functional operations based on data to be stored in the memory device 1210 and data output from the memory device 1210.

[0038] The storage device 1300 may store data regardless of the power supplied. For example, the storage device 1300 may include a nonvolatile memory device such as a flash memory, a PRAM, an MRAM, a ReRAM, a FRAM, etc. For example, the storage device 1300 may include a storage medium such as a solid state drive (SSD), a memory card, an embedded storage device, etc.

[0039] The communication block 1400 may support at least one of various wireless / wired protocols to communicate with external devices / systems of the electronic system 1000. The user interface 1500 may include various input / output interfaces to arbitrate communication between a user and the electronic system 1000.

[0040] The bus 1600 may provide a communication path between components of the electronic system 1000. The components of the electronic system 1000 may exchange data with each other according to the bus format of the bus 1600. For example, the bus format may include one or more of various interface protocols, such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Mobile PCIe (M-PCIe), Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Double Data Rate (DDR), Low Power DDR (LPDDR), etc.

[0041] Figure 2 It is shown Figure 1 1300 is a block diagram of an exemplary configuration of a storage device 1300.

[0042] As reference Figure 1 As described above, the main processor 1101 can communicate with the working memory 1200 and the storage device 1300 through the bus 1600. In the present disclosure, an object capable of accessing components of the electronic system 1000 (e.g., the working memory 1200, the storage device 1300, etc.) may be referred to as a "host" (e.g., the host 1100). The main processor 1101 may be an example of an object capable of operating as the host 1100. However, the present disclosure is not limited thereto.

[0043] The host 1100 may exchange data DAT with the storage device 1300. The storage device 1300 may provide storage services to the host 1100 in response to a command CMD received from the host 1100.

[0044] For example, the host 1100 may provide a command CMD including a write request and data DAT including write data to the storage device 1300. The storage device 1300 may store the requested write data in response to the write request. For example, the host 1100 may provide a command CMD including a read request to the storage device 1300. The storage device 1300 may output the requested read data to the host 1100 in response to the read request.

[0045] The storage device 1300 may include one or more memory devices 1311 and 1319, a storage controller 1330, and one or more buffer memories 1351 and 1359. For example, Figure 2 Two memory devices 1311 and 1319 and two buffer memories 1351 and 1359 are shown, but the number of memory devices and the number of buffer memories included in the memory device 1300 may be variously changed or modified.

[0046] Each of the memory devices 1311 and 1319 may store or output data requested by the host 1100. To this end, each of the memory devices 1311 and 1319 may include a storage area for storing data.

[0047] The storage area may be identified based on a value referred to as an “address.” The host 1100 may provide an address ADDR to the storage device 1300 to exchange data DAT associated with a particular storage area of ​​the memory devices 1311 and 1319. Write data may be stored in the storage area identified by the address ADDR, and read data may be output from the storage area identified by the address ADDR.

[0048] The buffer memories 1351 and 1359 may buffer data used in the operation of the memory device 1300. For example, the buffer memories 1351 and 1359 may store address conversion information that is referred to in order to perform conversion between an address ADDR provided from the host 1100 and a physical address on the memory devices 1311 and 1319. For example, the buffer memories 1351 and 1359 may store error correction code (ECC) information that is referred to in order to detect and correct errors of data output from the memory devices 1311 and 1319. To this end, the buffer memories 1351 and 1359 may include a volatile memory (such as SRAM, DRAM, SDRAM, etc.) and / or a nonvolatile memory (such as PRAM, MRAM, ReRAM, FRAM, etc.).

[0049] The memory controller 1330 may control the overall operation of the memory device 1300. To this end, for example, the memory controller 1330 may include a non-volatile memory (NVM) controller 1331, a host interface circuit 1333, a buffer controller 1335, one or more processor cores 1337, an internal buffer 1338, and an on-chip bus 1339.

[0050] The nonvolatile memory controller 1331 may provide an interface with the memory devices 1311 and 1319. The nonvolatile memory controller 1331 may control the memory devices 1311 and 1319 so that the memory devices 1311 and 1319 store or output data. The nonvolatile memory controller 1331 may perform various functional operations based on data to be stored in the memory devices 1311 and 1319 and data output from the memory devices 1311 and 1319.

[0051] The host interface circuit 1333 may provide an interface with the host 1100. The host interface circuit 1333 may perform appropriate conversion between the formats of commands CMD, data DAT, and addresses ADDR received from the host 1100 and the formats managed / used in the memory controller 1330.

[0052] The buffer controller 1335 may provide an interface with the buffer memories 1351 and 1359. The buffer controller 1335 may control the buffer memories 1351 and 1359 so that the buffer memories 1351 and 1359 store or output data. The buffer controller 1335 may perform various functional operations based on data to be stored in the buffer memories 1351 and 1359 and data output from the buffer memories 1351 and 1359.

[0053] The components of the storage controller 1330 may include one or more hardware components (eg, analog circuits, logic circuits, etc.) configured to perform the operations described above and to be described below.

[0054] In addition, the storage controller 1330 may include one or more processor cores 1337. The operations of the components of the storage controller 1330 described above and to be described below may be implemented with a program code of software and / or firmware, and the processor core 1337 may execute an instruction set of the program code. The processor core 1337 may process various arithmetic / logical operations to execute the instruction set.

[0055] The internal buffer 1338 may store data processed or to be processed by the processor core 1337. The internal buffer 1338 may temporarily store data DAT, commands CMD, and addresses ADDR received from the host 1100. The internal buffer 1338 may temporarily store data output from the memory devices 1311 and 1319. For example, the internal buffer 1338 may include a volatile memory (such as SRAM, DRAM, SDRAM, etc.) and / or a non-volatile memory (such as PRAM, MRAM, ReRAM, FRAM, etc.).

[0056] The on-chip bus 1339 may provide a communication path between components of the memory controller 1330. To this end, the on-chip bus 1339 may support one or more interface protocols and may enable physical signals to be transmitted through conductive materials.

[0057] Figure 3 is a block diagram illustrating an exemplary configuration of a memory system 2000 according to some exemplary embodiments.

[0058] The memory system 2000 may include one or more memory devices 2100 and a memory controller 2300 . Figure 3 Three memory devices 2110 , 2120 , and 2190 are shown, but the number of memory devices included in the memory system 2000 may be variously changed or modified.

[0059] The memory system 2000 may be implemented on a single electronic device. Alternatively, the memory system 2000 may be implemented on a plurality of electronic devices, or may be implemented using a plurality of chips.

[0060] For example, the memory system 2000 may be used Figure 1 The working memory 1200 is implemented, and the memory devices 2110, 2120 and 2190 and the memory controller 2300 may correspond to Figure 1 1210 and controller 1230. In some cases, the memory system 2000 may be Figure 2 For example, the memory devices 2110, 2120, and 2190 and the memory controller 2300 may correspond to Figure 2 1310 and 1319 and the nonvolatile memory controller 1331. For example, the memory devices 2110, 2120, and 2190 and the memory controller 2300 may correspond to Figure 2 Buffer memories 1351 and 1359 and buffer controller 1335.

[0061] The above examples describe some possible example implementations for better understanding and are not intended to limit the present disclosure. The memory system 2000 can be implemented in any configuration including one or more memory devices for storing data and a memory controller for controlling the memory devices. Below, some example implementations will be described with respect to a specific type of memory (e.g., DRAM or flash memory), but it can be easily understood that these example implementations can be used for any type of memory.

[0062] Each of the memory devices 2110, 2120, and 2190 may store data. In response to a read command received from the memory controller 2300, each of the memory devices 2110, 2120, and 2190 may output the stored data. The memory controller 2300 may provide a read command to a memory device in response to a command CMD of a read request received from the host 1100, storing the requested data in the memory device. Therefore, the requested data may be output from the corresponding memory device. Each of the memory devices 2110, 2120, and 2190 may be implemented on one semiconductor memory chip or die.

[0063] The memory devices 2110, 2120, and 2190 may include internal functional circuits 2111, 2121, and 2191, respectively. The internal functional circuits 2111, 2121, and 2191 may be provided within the memory devices 2110, 2120, and 2190, respectively. In the present disclosure, each of the internal functional circuits 2111, 2121, and 2191 may also be referred to as a "first functional circuit."

[0064] The internal function circuits 2111, 2121, and 2191 may perform a first operation based on data stored in the respective memory devices 2110, 2120, and 2190. Each of the internal function circuits 2111, 2121, and 2191 may perform the first operation in response to a read command received from the memory controller 2300. The memory devices 2110, 2120, and 2190 may perform the first operation through the internal function circuits 2111, 2121, and 2191 to generate first processed data mDAT.

[0065] The first operation may include one or more of various types of operations, and the function of each of the internal functional circuits 2111, 2121, and 2191 may be determined according to the type of the first operation. For example, the first operation may include all or some of an error handling operation (e.g., an error detection operation, an error correction operation, etc.), an encryption / decryption operation, a compression / decompression operation, an encoding / decoding operation, etc. The functions of the internal functional circuits 2111, 2121, and 2191 may be the same as or different from each other.

[0066] The memory controller 2300 may control the memory devices 2110, 2120, and 2190 so that the memory devices 2110, 2120, and 2190 store or output data. To this end, the memory controller 2300 may perform various operations. For example, the memory controller 2300 may include an external variable function circuit 2310. The external variable function circuit 2310 may be provided outside the memory devices 2110, 2120, and 2190. In the present disclosure, the external variable function circuit 2310 may also be referred to as a "second function circuit."

[0067] The memory controller 2300 may receive first processed data mDAT from the memory devices 2110, 2120, and 2190. The external variable function circuit 2310 may perform a second operation based on the first processed data mDAT. The memory controller 2300 may perform a second operation through the external variable function circuit 2310 to generate second processed data pDAT.

[0068] The second operation may include one or more of various types of operations, and the function of the external variable function circuit 2310 may be determined according to the type of the second operation. For example, the second operation may include all or some of an error handling operation (e.g., an error detection operation, an error correction operation, etc.), an encryption / decryption operation, a compression / decompression operation, an encoding / decoding operation, etc.

[0069] The function of the external variable function circuit 2310 may be the same as or different from the functions of the internal function circuits 2111, 2121, and 2191. In other words, the type of the second operation may be the same as or different from the type of the first operation.

[0070] When the type of the second operation is the same as the type of the first operation, the capability of the external variable function circuit 2310 may be different from the capability of each of the internal function circuits 2111, 2121, and 2191. For example, the circuit area of ​​each of the memory devices 2110, 2120, and 2190 may be smaller than the circuit area of ​​the memory controller 2300, and thus the capability of each of the internal function circuits 2111, 2121, and 2191 may be lower than the capability of the external variable function circuit 2310. For example, when the first operation and the second operation include error detection operations, the maximum number of errors detected by each of the internal function circuits 2111, 2121, and 2191 may be smaller than the maximum number of errors detected by the external variable function circuit 2310.

[0071] When a read request is received from the host 1100, the memory controller 2300 may provide a read command to a memory device storing the requested data. Therefore, the memory device having received the read command may perform a first operation through an internal functional circuit. In addition, the memory controller 2300 may perform a second operation based on the result of the first operation.

[0072] The memory controller 2300 may receive status information STAT. The status information STAT may be associated with performing the first operation in each of the memory devices 2110, 2120, and 2190. For example, the status information STAT may include information associated with at least one of various conditions, such as whether the memory devices 2110, 2120, and 2190 include internal function circuits 2111, 2121, and 2191 (i.e., whether each of the memory devices 2110, 2120, and 2190 supports the first operation), whether execution of the first operation in each of the memory devices 2110, 2120, and 2190 is enabled, the type of the first operation, the capability of each of the internal function circuits 2111, 2121, and 2191, the condition of each of the memory devices 2110, 2120, and 2190 that performs the first operation, and the like.

[0073] For example, depending on the design of the memory system 2000, the memory devices 2110, 2120, and 2190 may or may not include the internal functional circuits 2111, 2121, and 2191. For example, depending on the operation policy of the memory system 2000 or the host 1100, the operation of each of the internal functional circuits 2111, 2121, and 2191 may be enabled or disabled. For example, the status of each of the memory devices 2110, 2120, and 2190 performing the first operation may be associated with various factors, such as communication bandwidth, device temperature, expected remaining life, etc. The state information STAT may be provided to the memory controller 2300 to provide information associated with performing the first operation.

[0074] A change in the state information STAT (e.g., a change in enable / disable of each of the internal functional circuits 2111, 2121, and 2191, a change in the temperature of each of the memory devices 2110, 2120, and 2190, etc.) may mean a change associated with performing the first operation. Therefore, when the state information STAT changes, the first processed data mDAT may be generated in the memory devices 2110, 2120, and 2190 to be different from the first processed data mDAT before the state information STAT changes (i.e., the first processed data mDAT generated in the memory devices 2110, 2120, and 2190 after the state information STAT changes may be different from the first processed data mDAT generated in the memory devices 2110, 2120, and 2190 before the state information STAT changes). For example, when the state information STAT changes from the first information to the second information, the context of the first processed data mDAT may be changed from the first context to the second context different from the first context. Therefore, as the state information STAT changes, the first processed data mDAT received in the memory controller 2300 may be changed.

[0075] The operation of the external variable function circuit 2310 can be changed based on the state information STAT, and the mode of the second operation can be changed based on the state information STAT. Therefore, when the state information STAT changes, the mode of the second operation can be changed. For example, the mode of the second operation can be determined according to at least one of the type of the second operation and / or the capability of the second operation.

[0076] In some exemplary embodiments, the external variable function circuit 2310 can perform the second operation in a manner selected based on the state information STAT in different ways. For example, when the state information STAT changes, the capability of the external variable function circuit 2310 can be changed from the first capability to the second capability. In some exemplary embodiments, the external variable function circuit 2310 can perform the second operation of a type selected based on the state information STAT in a plurality of different types of operations. For example, when the state information STAT changes, the type of the second operation of the external variable function circuit 2310 can be changed from the first type to the second type. Figures 7 to 15 Some examples associated with changes in the status information STAT are described.

[0077] When the state information STAT changes, the type or manner of the second operation may be changed. Therefore, when the state information STAT changes, the second processed data pDAT may be generated in the memory controller 2300 to be different from the second processed data pDAT before the state information STAT changes (i.e., before the type or manner of the second operation is changed). In other words, the second processed data pDAT generated in the memory controller 2300 after the state information STAT changes may be different from the second processed data pDAT generated in the memory controller 2300 before the state information STAT changes. For example, when the state information STAT changes from the first information to the second information, the context of the second processed data pDAT may be changed from the first context to a second context different from the first context.

[0078] The memory controller 2300 may output the second processed data pDAT. Alternatively, the memory controller 2300 may output data generated by post-processing and / or converting the second processed data pDAT. The data output from the memory controller 2300 may include requested data corresponding to the read request of the host 1100. Therefore, the memory controller 2300 may provide the requested data to the host 1100 based on the second processed data pDAT.

[0079] According to an exemplary embodiment, the memory controller 2300 (particularly, the external variable function circuit 2310) may operate differently according to the operation of the memory system 2000. Therefore, the operation may be performed to be suitable for a given situation or state, and the flexibility of the operation of the memory system 2000 may be improved.

[0080] Figure 4 It is shown Figure 3 21 is a block diagram of an exemplary configuration of a memory device 2110.

[0081] Memory device 2110 may include internal functional circuits 2111, a memory cell array 2112, an address decoder 2113, a sense amplifier 2114, an input / output circuit 2115, and a control logic circuit 2116. Each of other memory devices 2120 and 2190 may be configured the same as or similar to memory device 2110.

[0082] The memory cell array 2112 may include a plurality of memory cells (e.g., memory cells MC). Each memory cell MC may be connected to a word line WL and a bit line BL. Each memory cell MC may store a data bit. Each memory cell MC may be a single-level cell storing one bit or a multi-level cell storing at least two bits.

[0083] The address decoder 2113 may be connected to the memory cell array 2112 through the word line WL. The address decoder 2113 may receive an address ADDR' from the memory controller 2300 and may decode the received address ADDR'. The address decoder 2113 may drive the word line WL based on the decoded address ADDR'.

[0084] The sense amplifier 2114 may be connected to the memory cell array 2112 through the bit line BL. The sense amplifier 2114 may sense data read from the memory cell array 2112. The internal function circuit 2111 may perform a first operation based on the data sensed by the sense amplifier 2114.

[0085] The input / output circuit 2115 may manage data input / output of the memory device 2110 so that data DAT′ is exchanged between the memory controller 2300 and the memory cell array 2112. For example, first processed data mDAT may be generated by a first operation of the internal function circuit 2111, and the input / output circuit 2115 may output the first processed data mDAT to the memory controller 2300.

[0086] The control logic circuit 2116 may receive a command CMD′ and a control signal CTRL from the memory controller 2300. The control logic circuit 2116 may control the internal function circuit 2111, the address decoder 2113, the sense amplifier 2114, and the input / output circuit 2115 based on the received signals.

[0087] Figure 5 is shown with Figure 3 2000 is a block diagram of an exemplary configuration associated with a memory system.

[0088] For example, the memory system 2000 may include a Figure 5 Configuration of the memory system 100. Figure 5The one or more memory devices 110 may correspond to Figure 3 one or more memory devices 2100, and Figure 5 The memory controller 130 may correspond to Figure 3 For the sake of brevity, redundant descriptions associated with the memory device 110 and the memory controller 130 will be omitted below.

[0089] The memory devices 111, 112, and 119 may include ECC circuits 111a, 112a, and 119a as internal functional circuits 2111, 2121, and 2191, respectively. Each of the ECC circuits 111a, 112a, and 119a may perform error handling operations (e.g., error detection and error correction) based on data output from the respective memory devices 111, 112, and 119 according to a given ECC scheme. The memory devices 111, 112, and 119 may perform error handling operations to generate first processed data mDAT1.

[0090] For example, each of the ECC circuits 111a, 112a, and 119a may operate in a single error correction (SEC) mode. In this case, each of the ECC circuits 111a, 112a, and 119a may detect and correct a 1-bit error of data output from each memory device 111, 112, and 119, but may not be able to detect two or more bit errors.

[0091] For example, the memory controller 130 may include a rigidly configured ECC circuit 131 instead of including the external variable function circuit 2310. The ECC circuit 131 may perform error handling operations (e.g., error detection and error correction) based on the first processed data mDAT1 according to a given ECC scheme. The memory controller 130 may perform error handling operations to generate the second processed data pDAT1.

[0092] For example, the ECC circuit 131 may operate in a single error correction / double error correction (SEC / DED) mode. In this case, the ECC circuit 131 may detect and correct a 1-bit error of the first processed data mDAT1, and may detect a 1-bit or 2-bit error, but the ECC circuit 131 may not detect an error of three or more bits.

[0093] For example, the scale of semiconductor manufacturing processes may become smaller and smaller to store a large amount of data in the memory devices 111, 112, and 119 on a small circuit area, and the operation speed of the memory devices 111, 112, and 119 may become faster to process a large amount of data. Therefore, the data output from the memory devices 111, 112, and 119 may include errors.

[0094] Therefore, the ECC circuits 111a, 112a, and 119a can be used together with the ECC circuit 131 to perform stable and reliable data processing. However, in some cases, the circuit area of ​​each of the memory devices 111, 112, and 119 may be small, so the capability of each of the ECC circuits 111a, 112a, and 119a (e.g., the maximum number of detectable bits) may be lower than that of the ECC circuit 131.

[0095] Figure 6 is used to describe Figure 5 A table of error handling operations performed in the memory system 100.

[0096] For example, unlike Figure 5 , the memory devices 111, 112, and 119 may be configured without the ECC circuits 111a, 112a, and 119a of the SEC mode. When one (1) error bit occurs in the memory devices 111, 112, and 119, the memory controller 130 may receive the first processed data mDAT1 including the one error bit. In this case, the ECC circuit 131 may detect and correct the one error bit, and the memory controller 130 may generate the corrected second processed data pDAT1 without the error bit.

[0097] Meanwhile, when two (2) error bits occur in the memory devices 111, 112, and 119, the memory controller 130 may receive the first processed data mDAT1 including the two error bits. In this case, the ECC circuit 131 may detect the two error bits. The memory controller 130 may generate the second processed data pDAT1 and may notify the host 1100 that the two error bits occur.

[0098] For example, Figure 5 As shown, the memory devices 111, 112, and 119 can be configured together as ECC circuits 111a, 112a, and 119a having a SEC mode. When an error bit occurs in the memory devices 111, 112, and 119, the ECC circuits 111a, 112a, and 119a can detect and correct the error bit. Therefore, the memory controller 130 can receive the first processed data mDAT1 that has been corrected without an error bit.

[0099] Meanwhile, two error bits may occur in the memory devices 111, 112, and 119. In some cases, the ECC circuits 111a, 112a, and 119a may not be able to detect and correct the two error bits, so the memory controller 130 may receive the first processed data mDAT1 including the two error bits. In this case, the ECC circuit 131 may detect the two error bits. The memory controller 130 may generate the second processed data pDAT1, and may notify the host 1100 that the two error bits occur.

[0100] However, in some cases, the ECC circuits 111a, 112a, and 119a may perform an erroneous error handling operation on data including two error bits. Due to the erroneous error handling operation, the data including two error bits may be erroneously corrected to include three (3) error bits. Therefore, the memory controller 130 may receive the first processed data mDAT1 including three error bits. In this case, the ECC circuit 131 may not be able to correct and detect the three error bits.

[0101] Therefore, the host 1100 may not recognize the occurrence of an error and may receive erroneous data, and reliability and stability may be reduced. In this way, when the ECC circuits 111a, 112a, and 119a are used in the memory devices 111, 112, and 119, undetectable and uncorrectable errors are likely to occur.

[0102] Figure 7 is shown with Figure 3 2000 is a block diagram of an exemplary configuration associated with a memory system.

[0103] For example, the memory system 2000 may include a Figure 7 Configuration of the memory system 3000. Figure 7 The one or more memory devices 3100 may correspond to Figure 3 one or more memory devices 2100, and Figure 7 The memory controller 3300 may correspond to Figure 3 For the sake of brevity, redundant descriptions associated with the memory device 3100 and the memory controller 3300 will be omitted below.

[0104] The memory devices 3110, 3120, and 3190 may include ECC circuits 3111, 3121, and 3191 as the internal functional circuits 2111, 2121, and 2191, respectively. Each of the ECC circuits 3111, 3121, and 3191 may perform a first error handling operation (e.g., error detection and error correction) based on data stored in the respective memory devices 3110, 3120, and 3190 according to a given ECC scheme. The memory devices 3110, 3120, and 3190 may perform the first error handling operation to generate first processed data.

[0105] For example, each of the ECC circuits 3111, 3121, and 3191 may operate in the SEC mode. In this case, each of the ECC circuits 3111, 3121, and 3191 may detect and correct a 1-bit error of data stored in the respective memory devices 3110, 3120, and 3190, but may not detect errors of two or more bits.

[0106] In some exemplary embodiments, memory devices 3120 and 3190 may be provided to store data. At the same time, memory device 3110 may be provided to store parity, which is referenced to handle errors of data stored in memory devices 3120 and 3190. Figure 8 Describe the configuration.

[0107] For example, the memory controller 3300 may include a variable ECC circuit 3310 as the external variable function circuit 2310. The variable ECC circuit 3310 may perform a second error handling operation (e.g., error detection and / or error correction) based on the first processed data. The memory controller 3300 may perform the second error handling operation to generate the second processed data. The variable ECC circuit 3310 may be configured to operate in a number of different ways, and may be referred to as Figures 9 to 11 Describe the detailed operation.

[0108] The memory controller 3300 may receive status information associated with performing the first error handling operation in the memory devices 3110, 3120, and 3190. For example, the status information may include information associated with at least one of various factors, such as whether the memory devices 3110, 3120, and 3190 include the ECC circuits 3111, 3121, and 3191 (i.e., whether each of the memory devices 3110, 3120, and 3190 supports the first error handling operation), a condition of each of the memory devices 3110, 3120, and 3190 performing the first error handling operation, a parity check of the error handling, and the like.

[0109] For example, the status information may include information associated with whether to enable execution of the first error handling operation in each of the memory devices 3110, 3120, and 3190. The ECC circuits 3111, 3121, and 3191 may be enabled or disabled in association with the status information. For example, the ECC circuits 3111, 3121, and 3191 may be enabled or disabled according to an operation policy of the memory system 3000 and / or the host 1100, and the status information may indicate enablement / disablement of the ECC circuits 3111, 3121, and 3191.

[0110] The manner of the second error handling operation of the variable ECC circuit 3310 may vary based on the state information. For example, the variable ECC circuit 3310 may perform the second error handling operation of the first manner or the second error handling operation of the second manner based on the state information.

[0111] For stable and reliable data processing, the ECC circuits 3111, 3121, and 3191 may be used together with the ECC circuit 3310. In some cases, the capability of the ECC circuit 3310 may be higher than the capability of each of the ECC circuits 3111, 3121, and 3191. For example, the maximum number of errors detectable by the second error handling operation with respect to the first processed data may be greater than the maximum number of errors detectable by the first error handling operation with respect to the data stored in the memory devices 3110, 3120, and 3190.

[0112] Figure 8 is used to describe the use of Figure 7 A block diagram of an exemplary operation of a memory device 3100 to store and output data with parity check.

[0113] In some exemplary embodiments, a parity generator and checker 3107 may be provided for the memory devices 3110, 3120, and 3190. The parity generator and checker 3107 may perform a parity operation on the data D1 to Dn provided to the memory devices 3110, 3120, and 3190.

[0114] The parity generator and checker 3107 may perform a parity operation to generate a parity P corresponding to the data D1 to Dn. Errors may be processed with reference to the parity P. For example, the parity P may be an even parity or an odd parity. The memory devices 3120 and 3190 may store the data D1 to Dn, while the memory device 3110 may store the parity P.

[0115] When data D1 to Dn are output from memory devices 3120 and 3190, parity P may also be output from memory device 3110. Parity generator and checker 3107 may detect and correct errors of data D1 to Dn with reference to parity P. Parity generator and checker 3107 may correct the detected errors to output data D1 to Dn without errors.

[0116] Fig. 9 and Fig.10 is a block diagram for describing an exemplary operation of the memory controller 3300, the operation being based on Figure 7 The status information in the memory system 3000 changes.

[0117] refer to Fig. 9 In some cases, the execution of the first error handling operation may be disabled (e.g., the ECC circuits 3111, 3121, and 3191 may be disabled). The ECC circuits 3111, 3121, and 3191 may be disabled according to an operation policy of the memory system 3000 and / or the host 1100. In this case, the state information STAT2 received in the memory controller 3300 may indicate that the execution of the first error handling operation is not enabled.

[0118] In some other cases, the memory system 3000 may be designed so that the memory devices 3110, 3120, and 3190 do not include the ECC circuits 3111, 3121, and 3191. In this case, the state information STAT2 received in the memory controller 3300 may indicate that the memory devices 3110, 3120, and 3190 do not support the first error handling operation.

[0119] The memory devices 3110, 3120, and 3190 may generate first processed data mDAT2. Fig. 9 In the example of , the first processed data mDAT2 may be provided to the memory controller 3300 without being processed by the ECC circuits 3111 , 3121 , and 3191 .

[0120] The variable ECC circuit 3310 may perform the second error handling operation of the first manner selected based on the state information STAT2. The memory controller 3300 may perform the second error handling operation of the first manner based on the first processed data mDAT2 to generate the second processed data pDAT2.

[0121] In the second error handling operation of the first mode of the variable ECC circuit 3310, the memory controller 3300 may correct a first number of errors and may detect a second number of errors with respect to the first processed data mDAT2. For example, the second number may be greater than the first number. For example, the variable ECC circuit 3310 may perform the second error handling operation in a SEC / DED mode so that one (1) error bit is corrected and two (2) error bits are detected.

[0122] As reference Figure 6 As described above, when the memory devices 3110, 3120, and 3190 are configured without the ECC circuits 3111, 3121, and 3191 in the SEC mode, the variable ECC circuit 3310 operating in the SEC / DED mode can correct or detect errors in the first processed data mDAT2. Therefore, when the state information STAT2 indicates that the first error handling operation is not enabled or indicates that the first error handling operation is not supported, the variable ECC circuit 3310 can operate in the first mode (e.g., in the SEC / DED mode).

[0123] refer to Fig.10 In some cases, the first error handling operation may be enabled (e.g., the ECC circuits 3111, 3121, and 3191 may be enabled). The ECC circuits 3111, 3121, and 3191 may be enabled according to an operation policy of the memory system 3000 and / or the host 1100. In this case, the state information STAT3 received in the memory controller 3300 may indicate that the first error handling operation is enabled. The memory devices 3110, 3120, and 3190 may perform the first error handling operation to generate the first processed data mDAT3.

[0124] The variable ECC circuit 3310 may perform a second error handling operation of a second manner selected based on the state information STAT3. The memory controller 3300 may perform a second error handling operation of a second manner based on the first processed data mDAT3 to generate second processed data pDAT3.

[0125] In the second error handling operation of the second mode of the variable ECC circuit 3310, the memory controller 3300 may perform error detection without error correction on the first processed data mDAT3. For example, the variable ECC circuit 3310 may perform the second error handling operation in a cyclic redundancy check (CRC) mode so that three or more error bits are detected without error correction. For example, the variable ECC circuit 3310 operating in the CRC mode may detect a first bit position error, a second bit position error, an odd bit position error, a burst error, etc.

[0126] As reference Figure 6 As described above, when the memory devices 3110, 3120, and 3190 are configured with the ECC circuits 3111, 3121, and 3191 in the SEC mode, it is likely that errors that cannot be detected and corrected by the SEC / DED mode may occur. In this case, although the error correction capability is abandoned, it may be advantageous to detect more errors. Therefore, when the state information STAT3 indicates that the first error handling operation is enabled, the variable ECC circuit 3310 can operate in the second mode (e.g., in the CRC mode) to detect more errors.

[0127] The maximum number of errors about the first processed data mDAT3 that can be detected by the second error handling operation of the second manner may be greater than the maximum number of errors about the first processed data mDAT2 that can be detected by the second error handling operation of the first manner. According to these exemplary embodiments, the stability, reliability, and flexibility of the operation of the memory system 3000 can be improved, and the occurrence of undetectable and uncorrectable errors can be prevented.

[0128] In association with the first operation, the state information STAT2 may be changed to the state information STAT3, or vice versa. For example, when the state information STAT2 is changed from the state information STAT3, the context of the first processed data mDAT2 may be changed to the context of the first processed data mDAT3. In addition, the context of the second processed data pDAT2 may be changed to the context of the second processed data pDAT3.

[0129] Fig.11 It is shown Figure 7 33 is a block diagram of an exemplary configuration of a variable ECC circuit 3310.

[0130] In some exemplary embodiments, the variable ECC circuit 3310 may include a syndrome calculator 3311, an error detector 3313, an error locator 3315, an error corrector 3317, and a switch 3319. The variable ECC circuit 3310 may receive the first processed data mDAT2 or mDAT3 and the state information STAT2 or STAT3. The variable ECC circuit 3310 may receive an error check bit generated by an ECC encoding operation when the data has been stored in the memory devices 3110, 3120, and 3190.

[0131] The syndrome calculator 3311 may calculate a syndrome based on the first processed data mDAT2 or mDAT3 and an error check bit. The operation of calculating a syndrome and detecting and correcting an error based on the calculated syndrome can be easily understood, so a detailed description thereof will be omitted below.

[0132] The error detector 3313 may detect an error associated with the first processed data mDAT2 or mDAT3 based on the calculated syndrome. The error locator 3315 may calculate the position of a bit corresponding to the detected error in the bit string associated with the first processed data mDAT2. The error corrector 3317 may correct the value of the bit at the calculated position about the first processed data mDAT2. The error locator 3315 may be enabled or disabled based on the state information STAT2 or STAT3.

[0133] For example, the error locator 3315 may be enabled based on the state information STAT2 indicating the disabling or non-existence of the first error handling operation. In this example, the error locator 3315 may calculate the position of the error bit with respect to the first processed data mDAT2, and may output the result of the second error handling operation in the first manner (e.g., SEC / DED manner). The error corrector 3317 may correct the error bit of the calculated position with respect to the first processed data mDAT2 to output the second processed data pDAT2.

[0134] The switch 3319 may output the result of the second error handling operation of the first mode (e.g., SEC / DED mode) in response to the state information STAT2. Therefore, when the error locator 3315 is enabled, the variable ECC circuit 3310 may output the output from the error locator 3315 as the error detection result associated with the second error handling operation of the first mode. The error detection result may indicate whether an error has occurred, the number of errors, the location of an error bit, whether the error is correctable, etc.

[0135] On the other hand, the error locator 3315 may be disabled based on the state information STAT3 indicating the enablement of the first error handling operation. In this case, the error detector 3313 may detect an error associated with the first processed data mDAT3, and may output a result of the second error handling operation in a second manner (e.g., a CRC manner). The error corrector 3317 may output the second processed data pDAT3 without error correction with respect to the first processed data mDAT3.

[0136] The switch 3319 may output the result of the second error handling operation of the second mode (e.g., CRC mode) in response to the state information STAT3. In this case, the calculation of the error bit position and the correction of the error bit of the calculated position may not be performed. The variable ECC circuit 3310 may output the output from the error detector 3313 as an error detection result associated with the second error handling operation of the second mode. The error detection result may indicate whether an error has occurred, the number of errors, etc.

[0137] In this way, the memory controller 3300 can output the error detection result according to the second error handling operation. When the mode of the second error handling operation is changed, the error detection result can be changed. The error detection result can be provided to the host 1100. For example, the error detection result can be included in the second processed data pDAT2 or pDAT3 to be provided to the host 1100, or can be provided to the host 1100 in any other way.

[0138] exist Fig.11 In the example of FIG. 3 , the memory controller 3300 can selectively perform the second error handling operation of the first manner or the second error handling operation of the second manner based on the state information STAT2 or STAT3 by using only the variable ECC circuit 3310 without using an additional ECC circuit. Therefore, the variable ECC circuit 3310 may not require an additional circuit area.

[0139] exist Figures 7 to 11 In the example of, it has been described that the error handling operation modes include SEC mode, SEC / DED mode and CRC mode. However, these examples are provided for ease of understanding and are not intended to limit the present disclosure. For example, the memory devices 3110, 3120 and 3190 and the memory controller 3300 may adopt various modes of error handling operations, such as double error correction (DEC) mode, double error correction / triple error detection (DEC / TED) mode, checksum mode, hash function mode, etc.

[0140] In addition, it has been described that the operation of the variable ECC circuit 3310 varies according to the state information STAT2 or STAT3 indicating the state of the first error handling operation. However, the operation of the variable ECC circuit 3310 may vary according to other information.

[0141] For example, when the temperature of the memory devices 3110, 3120, and 3190 exceeds the reference temperature and excessively increases or the expected remaining life of the memory devices 3110, 3120, and 3190 is shorter than the reference life, it is likely that errors may occur in the data stored in the memory devices 3110, 3120, and 3190. Therefore, the operation of the variable ECC circuit 3310 may be changed according to the state information indicating the temperature or the remaining life of the memory devices 3110, 3120, and 3190. As such, the exemplary embodiments may be variously changed or modified and are not limited to the above examples.

[0142] Fig.12 is shown with Figure 3 2000 is a block diagram of an exemplary configuration associated with a memory system.

[0143] For example, the memory system 2000 may include a Fig.12Configuration of the memory system 4000. Fig.12 The one or more memory devices 4100 may correspond to Figure 3 one or more memory devices 2100, and Fig.12 The memory controller 4300 may correspond to Figure 3 For the sake of brevity, redundant descriptions associated with the memory device 4100 and the memory controller 4300 will be omitted below.

[0144] The memory devices 4110, 4120, and 4190 may include decompressor circuits 4111, 4121, and 4191 as the internal function circuits 2111, 2121, and 2191, respectively. Each of the decompressor circuits 4111, 4121, and 4191 may perform a first decompression operation based on data stored in the respective memory devices 4110, 4120, and 4190 according to a given decompression scheme.

[0145] For example, when data is stored in the memory devices 4110, 4120, and 4190, the data may be compressed to store a larger amount of data. A first decompression operation may be performed on the compressed data, and thus the decompressed data may be output from the memory devices 4110, 4120, and 4190. The memory devices 4110, 4120, and 4190 may perform the first decompression operation to generate first processed data.

[0146] For example, the memory controller 4300 may include a variable decompressor circuit 4310 as the external variable function circuit 2310. The variable decompressor circuit 4310 may perform a second decompression operation based on the first processed data according to a given decompression scheme. The memory controller 4300 may perform the second decompression operation to generate second processed data.

[0147] For example, the first decompression operation of the decompressor circuits 4111, 4121, and 4191 may provide partial decompression of the data, and the second decompression operation of the variable decompressor circuit 4310 may provide the remaining decompression of the data. For example, the first decompression operation may decompress a first portion of the compressed data, and the second decompression operation may decompress a second portion (e.g., the remaining portion) of the compressed data. When the decompressor circuits 4111, 4121, and 4191 perform partial decompression, the load of the memory controller 4300 may be reduced.

[0148] The memory controller 4300 may receive status information associated with performing the first decompression operation in the memory devices 4110, 4120, and 4190. For example, the status information may include information associated with at least one of various factors, such as whether the memory devices 4110, 4120, and 4190 include the decompressor circuits 4111, 4121, and 4191 (i.e., whether each of the memory devices 4110, 4120, and 4190 supports the first decompression operation), whether the execution of the first decompression operation in each of the memory devices 4110, 4120, and 4190 is enabled, a status of each of the memory devices 4110, 4120, and 4190 that performs the first decompression operation, a manner of the first decompression operation, and the like.

[0149] The mode (eg, scheme, performance, etc.) of the second decompression operation of the variable decompressor circuit 4310 may vary based on the state information. For example, the variable decompressor circuit 4310 may selectively perform the second decompression operation of the first mode or the second decompression operation of the second mode based on the state information.

[0150] Fig.13 and Fig.14 is a block diagram for describing an exemplary operation of the memory controller 4300, the operation being based on Fig.12 The status information in the memory system 4000 changes.

[0151] refer to Fig.13 In some cases, the execution of the first decompression operation may be disabled (e.g., the decompressor circuits 4111, 4121, and 4191 may be disabled). The decompressor circuits 4111, 4121, and 4191 may be disabled according to an operation policy of the memory system 4000 and / or the host 1100. In this case, the state information STAT4 received in the memory controller 4300 may indicate that the execution of the first decompression operation is not enabled.

[0152] The memory devices 4110, 4120, and 4190 may generate first processed data mDAT4. Fig.13 In the example of , the first processed data mDAT4 may be provided to the memory controller 4300 without being processed by the decompressor circuits 4111 , 4121 , and 4191 .

[0153] The variable decompressor circuit 4310 may perform a second decompression operation of the first mode selected based on the state information STAT4. The memory controller 4300 may perform a second decompression operation of the first mode based on the first processed data mDAT4 to generate second processed data pDAT4. For example, in the second decompression operation of the first mode of the variable decompressor circuit 4310, the memory controller 4300 may fully operate to provide maximum performance.

[0154] refer to Fig.14 , in some cases, the first decompression operation may be enabled (e.g., the decompressor circuits 4111, 4121, and 4191 may be enabled). The decompressor circuits 4111, 4121, and 4191 may be enabled according to an operation policy of the memory system 4000 and / or the host 1100. In this case, the state information STAT5 received in the memory controller 4300 may indicate that the first decompression operation is enabled. The memory devices 4110, 4120, and 4190 may perform the first decompression operation to generate the first processed data mDAT5.

[0155] The variable decompressor circuit 4310 may perform a second decompression operation of the second mode selected based on the state information STAT5. The memory controller 4300 may perform a second decompression operation of the second mode based on the first processed data mDAT5 to generate second processed data pDAT5. For example, in the second decompression operation of the second mode of the variable decompressor circuit 4310, the memory controller 4300 may partially operate to provide low performance.

[0156] Fig.15 It is shown Fig.12 A block diagram of an exemplary configuration of a variable decompressor circuit 4310.

[0157] In some exemplary embodiments, the variable decompressor circuit 4310 may include switches 4311 and 4315, decompressors 4313-1, 4313-2, 4313-3, and 4313-4, and a selector 4319. The variable decompressor circuit 4310 may receive the first processed data mDAT4 or mDAT5 and the state information STAT4 or STAT5.

[0158] The decompressors 4313-1, 4313-2, 4313-3, and 4313-4 may perform a second decompression operation in parallel. The decompressors 4313-1, 4313-2, 4313-3, and 4313-4 may perform a second decompression operation based on the first processed data mDAT4 or mDAT5. The selector 4319 may output a selection signal to cause the decompressors 4313-1, 4313-2, 4313-3, and 4313-4 to operate sequentially and / or alternately.

[0159] The switch 4311 may transmit the first processed data mDAT4 or mDAT5 to the decompressor selected in response to the selection signal. The switch 4315 may receive data from the decompressor selected in response to the selection signal, and may output the received data as the second processed data pDAT4 or pDAT5.

[0160] For example, decompressors 4313-3 and 4313-4 may be enabled or disabled based on state information STAT4 or STAT5. For example, decompressors 4313-3 and 4313-4 may be enabled based on state information STAT4, which indicates the disabling or absence of the first decompression operation. In this example, variable decompressor circuit 4310 may perform a second decompression operation (e.g., a complete operation) in a first manner, so that all decompressors 4313-1, 4313-2, 4313-3, and 4313-4 operate in parallel and may generate second processed data pDAT4 based on first processed data mDAT4.

[0161] On the other hand, decompressors 4313-3 and 4313-4 may be disabled based on state information STAT5 indicating the enablement of the first decompression operation. In this example, variable decompressor circuit 4310 may perform a second decompression operation (e.g., a partial operation) in a second manner so that only decompressors 4313-1 and 4313-2 operate in parallel, and may generate second processed data pDAT5 based on second processed data mDAT5.

[0162] In this way, the memory controller 4300 can operate to be suitable for a given situation or state, and can improve the flexibility of the operation of the memory system 4000. When the memory devices 4110, 4120, and 4190 partially process the operation to be performed in the memory controller 4300, the load of the memory controller 4300 can be reduced. Therefore, the operation performance and power consumption can be optimally managed.

[0163] Figures 7 to 15The exemplary embodiment of may be associated with an implementation in which the type of the first operation performed in the memory devices 2110, 2120, and 2190 is the same as the type of the second operation performed in the memory controller 2300. Furthermore, Figures 7 to 15 The exemplary embodiments may be associated with an implementation in which one type of second operation is performed in the memory controller 2300. However, these exemplary embodiments are provided to facilitate better understanding and are not intended to limit the present disclosure. It can be easily understood that even in an implementation in which the type of the first operation is different from the type of the second operation and in an implementation in which multiple types of second operations are performed, the exemplary embodiments may be differently employed to change the second operation based on the state information STAT.

[0164] Figures 16 to 18 is a diagram showing the use of transferring the status information STAT from Figure 3 The memory system 2000 is a block diagram providing an exemplary configuration of the memory controller 3000 .

[0165] In some exemplary embodiments, the memory system 2000 may include, for example, Fig.16 The configuration of the memory system 2000a is shown in FIG. Fig.16 , the memory system 2000 may further include a status register 2102. The status register 2102 may store status information STAT, and may manage and update status information STAT regarding the first operation performed in the one or more memory devices 2100a.

[0166] The memory controller 2300a may receive the status information STAT from the status register 2102. To this end, the memory controller 2300a may directly access the status register 2102. Alternatively, the status register 2102 may output the status information STAT in response to a request of the memory controller 2300a.

[0167] In some exemplary embodiments, the memory system 2000 may include, for example, Fig.17 The configuration of the memory system 2000b is shown in FIG. Fig.17 , the memory devices 2110 , 2120 , and 2190 may be disposed on a printed circuit board or a semiconductor package 2100 b . The printed circuit board or the semiconductor package 2100 b may include a connection terminal 2103 .

[0168] The connection terminal 2103 may be implemented in the form of a pad or a pin. The connection terminal 2103 may output a signal corresponding to the state information STAT. The signal corresponding to the state information STAT may be provided from other circuits on the memory devices 2110, 2120, and 2190 or a printed circuit board or semiconductor package 2100b. The memory controller 2300b may be connected to the connection terminal 2103 and may receive a signal corresponding to the state information STAT.

[0169] In some exemplary embodiments, the memory system 2000 may include Fig.18 The configuration of the memory system 2000c. Fig.18 , a communication sequence may be defined to transmit status information STAT between one or more memory devices 2100c and the memory controller 2300c.

[0170] For example, when the memory device 2100c and the memory controller 2300c are physically connected or when the communication between the memory device 2100c and the memory controller 2300c is reset, a connection initialization operation (S110) may be performed. Thereafter, the memory controller 2300c may transmit a status check request to the memory device 2100c (S120). The memory device 2100c may transmit status information STAT to the memory controller 2300c in response to the status check request received from the memory controller 2300c (S130).

[0171] Each of the status check request and the status information STAT can be transmitted in the form of a signal or a packet. The status check request and the status information STAT can be transmitted by being included in a reserved field of a command and response defined in an existing communication protocol. Optionally, a new command and response can be defined to transmit the status check request and the status information STAT.

[0172] Fig.19 Is a description and Figure 3 A flowchart of exemplary operations associated with the memory system 2000 is shown.

[0173] The host 1100 may transmit a read request to the memory controller 2300 (S210). The memory controller 2300 may transmit a read command to the memory device 2100 in response to the read request (S220). The read request and the read command may be generated to read data stored in the memory device 2100.

[0174] The memory controller 2300 may receive the state information STAT (S230). In addition, the memory controller 2300 may receive the first processed data mDAT (S240). The first processed data mDAT may be generated from the first operation performed in the memory device 2100, or may be generated without the first operation.

[0175] Fig.19 It is shown that the status information STAT is transmitted after the read command is transmitted. However, the present disclosure is not limited to Fig.19 The status information STAT may be transmitted in advance before a read request or a read command is transmitted. For example, the status information STAT may be transmitted during or after a connection initialization operation between the host 1100 and the memory controller 2300.

[0176] Afterwards, the memory controller 2300 may perform a second operation (S250). The second operation may be performed according to one of the variable operations selected based on the state information STAT. For example, the type of the second operation or the mode of the second operation may vary based on the state information STAT. The memory controller 2300 may output the requested data to the host 1100 based on the result of the second operation (e.g., based on the second processed data pDAT generated by the second operation) (S260).

[0177] As traditional in the art, embodiments can be described and illustrated according to the block of performing one or more functions described.These blocks (here may be referred to as unit or module, etc.) are physically implemented by analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software.For example, the circuit can be embodied in one or more semiconductor chips, or embodied on substrate supports such as printed circuit boards, etc. The circuit constituting the block can be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the block and a processor that performs other functions of the block.Without departing from the scope of the present disclosure, each block of the embodiment can be physically divided into two or more interactive and discrete blocks.Similarly, without departing from the scope of the present disclosure, the blocks of the embodiment can be physically combined into more complex blocks.

[0178] The above description is intended to provide exemplary configurations and operations for implementing the present disclosure. In addition to the above exemplary embodiments, the scope and spirit of the present disclosure may include implementations obtained by simply changing or modifying the above exemplary embodiments. In addition, the scope and spirit of the present disclosure include implementations achieved by easily changing or modifying the above exemplary embodiments later.

Claims

1. A memory system, comprising: a memory device, a plurality of internal functional circuits of the memory device performing a first error handling operation based on the stored data to generate first processed data; as well as A memory controller, the memory controller: receiving status information associated with performing the first error handling operation, and The external function circuit of the memory controller performs a second error handling operation based on the first processed data to generate second processed data, wherein: a maximum number of errors detectable by the second error handling operation with respect to the first processed data is greater than a maximum number of errors detectable by the first error handling operation with respect to the stored data, and The manner of the second error handling operation varies based on the status information, wherein the status information indicates whether the memory device supports the first error handling operation, whether the first error handling operation is enabled, a condition of the memory device performing the first error handling operation, or a parity check referenced in error handling, wherein the capability of each internal functional circuit is lower than the capability of the external functional circuit, wherein the memory controller: When the status information indicates that the memory device does not support the first error handling operation or is not enabled to perform the first error handling operation, performing the second error handling operation in a first manner so that a first number of errors are corrected and a second number of errors are detected for the first processed data, and When the state information indicates that execution of the first error handling operation is enabled, executing the second error handling operation in a second manner so that error detection is performed without error correction on the first processed data, and The second number of errors is greater than the first number of errors.

2. The memory system of claim 1 , wherein a maximum number of errors detectable by the second error handling operation of the second mode with respect to the first processed data is greater than a maximum number of errors detectable by the second error handling operation of the first mode with respect to the first processed data.

3. The memory system of claim 1, wherein: the memory controller outputting an error detection result according to the second error handling operation, and When the mode of the second error handling operation is changed, the error detection result is changed.

4. The memory system of claim 1, wherein: The plurality of internal functional circuits included in the memory device are first error correction code circuits that perform the first error handling operation, and The first error correction code circuit is enabled or disabled in association with the status information.

5. The memory system of claim 1, wherein: The memory controller includes an external functional circuit that is a second error correction code circuit that performs the second error handling operation, and The second error correction code circuit performs the second error handling operation in a first manner or the second error handling operation in a second manner based on the status information.

6. The memory system of claim 5, wherein: The second error correction code circuit comprises: a syndrome calculator, the syndrome calculator calculating a syndrome based on the first processed data and an error check bit; an error detector that detects an error with respect to the first processed data based on the calculated syndrome; an error locator that calculates a position of a bit in a bit string associated with the first processed data that corresponds to the detected error; and an error corrector that corrects a value of the bit identified by the position with respect to the first processed data, and The error locator is enabled or disabled based on the status information.

7. The memory system of claim 6, wherein the second error correction code circuit: when the error locator is enabled, outputting an output from the error locator as an error detection result associated with the second error handling operation of the first mode, and When the error locator is disabled, an output from the error detector is output as an error detection result associated with the second error handling operation of the second mode.

8. The memory system of claim 5, wherein the memory controller selectively performs the second error handling operation of the first manner or the second error handling operation of the second manner based on the status information by using the second error correction code circuit instead of another error correction code circuit.

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