Device and multi-chip module for finding and computing artificial intelligence accelerator

Abstract

According to one general aspect, a device and a multi-chip module for finding a computing artificial intelligence accelerator are provided. The device may include a storage circuit die, the storage circuit die is configured to store a lookup table, the lookup table converts first data into second data. The device may also include a logic circuit die, the logic circuit die includes a combinational logic circuit, and the combinational logic circuit is configured to receive the second data. The device may also include an optical via, the optical via is coupled between the storage circuit die and the logic circuit die and is configured to transmit the second data between the storage circuit die and the logic circuit die.

Description

Technical Field

[0001] The present disclosure relates to computing technology, and more specifically, to a high bandwidth memory (HBM) silicon photonics through silicon via (TSV) architecture for finding computing artificial intelligence (AI) accelerators. Background Art

[0002] High Bandwidth Memory (HBM) is a high-performance random access memory (RAM) interface for three-dimensional stacked dynamic random access memory (DRAM). High bandwidth memory can be used in conjunction with high-performance graphics accelerators and network devices. High bandwidth memory was adopted as an industry standard by the Joint Electron Device Engineering Council (JEDEC) in October 2013. The second generation HBM2 was accepted by JEDEC in January 2016.

[0003] Compared to traditional system memory or graphics memory, HBM achieves higher bandwidth in a substantially smaller form factor while using less power. This is achieved by stacking up to eight DRAM dies, including an optional base die with a memory controller and interconnected by through-silicon vias (TSVs) and microbumps. HBM2 is capable of 256GB / s of memory bandwidth per package.

[0004] HBM can be used with neural network or other artificial intelligence (AI) training, which is both memory intensive and computationally intensive due to the increase in training data set size and model parameters as well as the number of intermediate results processed.

[0005] [Solution to the problem]

[0006] The purpose of the present disclosure is to provide a device and a multi-chip package to implement a high bandwidth memory (HBM) silicon photonics through silicon via (TSV) architecture for searching computing artificial intelligence (AI) accelerators. Summary of the invention

[0007] According to one general aspect, a device may include a memory circuit die configured to store a lookup table that converts first data into second data. The device may also include a logic circuit die that includes a combinatorial logic circuit configured to receive the second data. The device may also include an optical via coupled between the memory circuit die and the logic circuit die and configured to transmit the second data between the memory circuit die and the logic circuit die.

[0008] According to another general aspect, a device may include a first circuit die configured to store a reconfigurable logic circuit. The device may include a second circuit die including a fixed logic circuit. The device may also include an optical link coupled between the first circuit die and the second circuit die and configured to transmit data between the first circuit die and the second circuit die. The device may be configured to first process data by the fixed logic circuit, transmit the partially processed data across the optical link to the first circuit die, and continue to process the data by the reconfigurable logic circuit.

[0009] According to another general aspect, a multi-chip module (MCM) may include a light source configured to generate an optical signal. The multi-chip module may include a logic circuit die, the logic circuit die including a fixed logic circuit and configured to transmit data to a memory circuit die in an optical manner. The multi-chip module may include an intermediate layer, the intermediate layer configured to couple the light source with the logic circuit die. The multi-chip module may include the memory circuit die, the memory circuit die configured to store a lookup table, the lookup table receiving the data. The multi-chip module may include an optical via, the optical via coupled between the memory circuit die and the logic circuit die, and configured to transmit the data between the memory circuit die and the logic circuit die.

[0010] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from a review of the description and drawings, and from a review of the claims.

[0011] Systems and / or methods for computing technology, and more specifically, for finding a high bandwidth memory (HBM) silicon photonics through silicon via (TSV) architecture for a computing artificial intelligence (AI) accelerator, are substantially shown in and / or described in connection with at least one of the figures, as more fully described in the claims.

[0012] [Beneficial effects of the present invention]

[0013] According to the present disclosure, a device and a multi-chip package are provided to implement a high bandwidth memory (HBM) silicon photonics through silicon via (TSV) architecture for searching computing artificial intelligence (AI) accelerators. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0015] Figure 2 is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0016] Figure 3 is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0017] Figure 4a is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0018] Figure 4b is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0019] Figure 4c is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0020] Figure 5 is a schematic block diagram of an information processing system that may include devices formed according to the principles of the disclosed subject matter.

[0021] Like reference symbols in the various drawings denote like elements.

[0022] [Explanation of Symbols]

[0023] 100, 300, 491, 492, 493: System

[0024] 102: Reconfigurable storage logic

[0025] 104, 510: Processor

[0026] 106: Memory

[0027] 108: Other components

[0028] 112: Component / Reconfigurable Lookup Table (RLUT) / Subarray / DRAM RLUT

[0029] 114: Component / Subarray / RAMSubarray / RAM

[0030] 116: Configuring interfaces

[0031] 118: Input / output interface

[0032] 200: System / System on Multiple Chips

[0033] 202, 302: Logic die / die

[0034] 204: Memory die / die

[0035] 212, 332, 486, 515: Combinational Logic Block (CLB)

[0036] 214, 334: Lookup table

[0037] 216: Storage array / storage unit / memory

[0038] 222: Input

[0039] 224: Output

[0040] 226: Through hole / optical through hole

[0041] 301: Middle layer

[0042] 304: Memory die / die / scheduler circuit

[0043] 322: Modulator / Optical Modulator

[0044] 324: Detector / Optical Detector

[0045] 326: Amplifier Circuits / Amplifiers

[0046] 328: Driver circuit / driver

[0047] 336: Intermediate result buffer

[0048] 340: Scheduler

[0049] 352: Via / Link / Data Via / Optical Via / Optical Link

[0050] 354: Via / Address / Command Via / Link / Optical Via

[0051] 356: Light source link / link

[0052] 390: Light source / bare chip

[0053] 402: Optical vias / waveguides

[0054] 404: Bus Network / Micro-Ring Modulator

[0055] 406: Light Source

[0056] 412: Electrical Driver

[0057] 414: Serializer Circuit

[0058] 416, 476: Buffer circuit / buffer

[0059] 420: Storage

[0060] 432: Pads / Storage Pads

[0061] 434: Pad

[0062] 464: Microring Filter

[0063] 466: Photodetector

[0064] 478: Deserializer Circuit

[0065] 480: Destination Processing Block / Processing Block

[0066] 482: Input buffer

[0067] 484: Scheduler Circuit

[0068] 488: Output buffer

[0069] 490: Storage Mat / Pad

[0070] 500: Information Processing Systems

[0071] 505: System bus

[0072] 520: Volatile memory

[0073] 530: Non-volatile memory

[0074] 540: Network interface

[0075] 550: User interface unit

[0076] 560: Hardware Components

[0077] 570: Software Components DETAILED DESCRIPTION

[0078] Hereinafter, various exemplary embodiments will be more fully described with reference to the accompanying drawings, in which some exemplary embodiments are shown. However, the subject matter disclosed herein may be implemented in many different forms and should not be considered to be limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the subject matter disclosed herein to those skilled in the art. In the accompanying drawings, the size and relative size of various layers and various regions may be exaggerated for clarity.

[0079] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Like numbers refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0080] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited to these terms. These terms are only used to distinguish various elements, components, regions, layers or sections. Therefore, the first element, component, region, layer or section discussed below may also be referred to as the second element, component, region, layer or section, which does not deviate from the teachings of the subject matter disclosed in the present invention.

[0081] For ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device shown in the figures is turned over, the elements described as being "below" or "beneath" other elements or features will now be oriented to be "above" the other elements or features. Therefore, the exemplary term "below" can encompass both the "above" and "below" orientations. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly.

[0082] Likewise, for ease of description, electrical terms such as "high", "low", "pullup", "pull down", "1", "0", etc. may be used herein to describe the relationship of the voltage level or current shown in the figures relative to other voltage levels or currents or relative to another (other) element or feature. It should be understood that the electrical relative terms are intended to encompass different reference voltages of the device in use or operation in addition to the voltages or currents shown in the figures. For example, if the device or signal shown in the figure is inverted or uses other reference voltages, currents, or charges, the elements described as "high" or "pulled up" will now be "low" or "pulled down" compared to the new reference voltage or current. Therefore, the exemplary term "high" can encompass both relatively low voltages or currents or relatively high voltages or currents. The device may be based on a different electrical reference framework and the electrical related descriptors used herein may be interpreted accordingly.

[0083] The terms used herein are only for the purpose of describing specific exemplary embodiments and are not intended to limit the subject matter disclosed in the present invention. Unless the context clearly indicates otherwise, the singular forms "a, an" and "the" used herein are intended to include plural forms as well. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0084] Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of ideal exemplary embodiments (and intermediate structures). As such, variations relative to the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be considered limited to the specific shapes of the regions shown herein, but should include shape deviations caused by, for example, manufacturing. For example, an implanted region illustrated as a rectangle should typically have circular features or curvilinear features and / or a gradient of implant concentration at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions illustrated in the drawings are schematic and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the subject matter disclosed in the present invention.

[0085] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter disclosed herein belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0086] Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0087] Figure 1 1 is a block diagram of an exemplary embodiment of a system 100 according to the disclosed subject matter. In various embodiments, the system 100 may include a processor 104, a memory 106, and a reconfigurable storage logic 102. In various embodiments, the system 100 may also include one or more other components 108 (e.g., a network interface, a memory controller, etc.).

[0088] In various embodiments, system 100 may include a system on chip (SoC). Figure 2 and Figure 3 In the embodiment shown in the figure, the system 100 may include a plurality of integrated circuit (IC) dies, which are either alone or as part of a multi-chip module (MCM). In another embodiment, the system 100 may include a series of discrete or individual components. In yet another embodiment, the system 100 may include a combination of integrated components and discrete components. In various embodiments, the system 100 may include a computing device, such as (for example) a laptop computer, a desktop computer, a workstation, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers, or a virtual machine or a virtual computing device of a virtual machine. In various embodiments, the system 100 may be used by a user (not shown in the figure).

[0089] In the illustrated embodiment, the processor 104 may be configured to execute one or more machine executable instructions or to execute software, firmware, or a combination thereof. In such an embodiment, the processor 104 may include fixed logic circuits (e.g., AND gates, flip-flops, etc.) set during the manufacture of the processor 104 (or fixed logic circuits set shortly after the manufacture of the processor 104, such as fuses, etc.), and may not substantially change after manufacture. In another embodiment, the processor 103 may include a reconfigurable device, such as (for example) a field programmable gate array (FPGA). It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0090] In various embodiments, the memory 106 may include a plurality of storage units, each of which is configured to store one or more pieces of data temporarily, permanently, semi-permanently, or in a combination of the above. The data in the memory 106 may be accessed by the processor 104. In addition, the memory 106 may include a volatile memory, a non-volatile memory, or a combination thereof.

[0091] In the illustrated embodiment, system 100 may include reconfigurable storage logic 102. Reconfigurable storage logic 102 may be similar to memory 106 in that they may include a plurality of memory cells (not explicitly shown) arranged in subarrays (shown as elements 112 and 114). Typically, a memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) includes an array of memory cells arranged in an array of rows and columns. Often, to make larger arrays more manageable, the array may be divided into subarrays of memory cells (e.g., 256 rows by 256 columns, etc.). Traditionally, dividing a memory array into subarrays may be advantageous because generally only one subarray is accessed at a time, thereby reducing power and computational complexity.

[0092] In the illustrated embodiment, the memory array (illustrated by the reconfigurable memory logic 102) may differ from the memory 106 in that the subarrays may be reconfigured to function as look-up tables (LUTs) rather than conventional memory subarrays. In such an embodiment, logic functions may be implemented in the look-up tables. For example, the look-up tables may perform arithmetic logic functions such as adders, multipliers, etc. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited to the above illustrative examples. In the illustrated embodiment, these look-up tables may be referred to as processing elements or reconfigurable look-up tables (RLUTs) 112.

[0093] In such an embodiment, once a given RLUT 112 is configured to complete a certain computing task (e.g., neural network processing), the given RLUT 112 is also and also functions as an accelerator or co-processor for the processor 104, and the memory space of the given RLUT 112 may no longer be used for data storage for the processor 104. In such an embodiment, the processor 104 may offload some cores or tasks to execute on such a stack of RLUTs 112, and once the task is completed, the processor 104 may be interrupted or otherwise notified of the task completion. On the other hand, the RLUT 112 may be configured as a pure storage stack for data storage, similar to the memory 106. In such an embodiment, the subarrays 112 and 114 may be capable of being reconfigured as memory or lookup tables.

[0094] In such an embodiment, the RLUT 112 and the logic functions implemented in the RLUT 112 may be changed simply by performing a memory write operation. This may enable the logic functions to be dynamically reconfigured or changed during operation of the system 100. Reprogramming may be accomplished using conventional write operations (or similar write operations) without requiring abnormal (i.e., non-operating or high) voltages, such as those used to program an Electrically Erasable Programmable Read Only Memory (EEPROM) or the like.

[0095] In such an embodiment, the reconfigurable storage logic 102 may include a configuration interface 116. In various embodiments, when the processor 104 (or other component) wishes to change or modify the logic function stored in the RLUT 112, the processor 104 (or other component) may perform a write operation or a specialized write operation (e.g., a write operation including an indicator indicating that the RLUT 112 is involved, etc.).

[0096] In some embodiments, all memory accesses or operations may pass through an input / output (I / O) interface 118 of the reconfigurable memory logic 102. In such embodiments, if the memory access is to a subarray storing data to be revalidated (e.g., RAM subarray 114, etc.), the input / output interface 118 may simply process the read / write request as the memory array would traditionally do. However, in some embodiments, if the memory access is to a subarray being used as a RLUT 112 (or to be used as a RLUT 112), the input / output interface 118 may pass the memory access to the configuration interface 116 for processing.

[0097] In yet another embodiment, the input / output interface 118 may be configured to read or write to the RLUT 112. In such an embodiment, the write access may involve writing to the RLUT 112 to define the logical function of the RLUT 112. In such an embodiment, the configuration interface 116 may be configured to adjust the routing of signals within or between the RLUT 112 or the entire reconfigurable storage logic 102. For example, the configuration interface 116 may be configured to adjust the routing of signals between multiple RLUTs 112 and / or RAM 114. In such an embodiment, the input / output interface 118 may be configured to manage data access to the RLUT 112 and RAM 114, and the configuration interface 116 may be configured to manage the interconnection and routing of the sub-arrays 112 and 114. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above several illustrative examples. In various embodiments, the input / output interface 118 may include the configuration interface 116.

[0098] Additionally, in the illustrated embodiment, each subarray may be used as either a RLUT 112 or a conventional RAM 114 storage subarray. As described above, the conventional RAM 114 subarray may be configured to store data and information. In such an embodiment, the number of RLUTs 112 and RAM subarrays 114 or the balance between RLUTs 112 and RAM subarrays 114 may be dynamically adjusted within the reconfigurable storage logic 102 as needed. In another embodiment, the number of RLUTs 112 and RAM subarrays 114 may be fixed during manufacturing. In yet another embodiment, the maximum number of RLUTs 112 may be fixed during manufacturing, but the RLUTs 112 may be configured to be used as RAM subarrays 114. It should be understood that the above are merely a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0099] In various embodiments, the processor 104 (or other component) may wish to configure a sub-array as a RLUT 112. In such an embodiment, the processor 104 may perform a memory access to the reconfigurable storage logic 102. The memory access may include a write operation to store a lookup table LUT in a particular RLUT 112. The memory access may include a series of memory accesses depending on the size of the lookup table. In some embodiments, a particular memory access may indicate the number of inputs to the lookup table and the number of outputs from the lookup table. Additionally, other memory accesses may indicate signal routing information for the RLUT 112. For example, as described below, multiple RLUTs 112 may be cascaded or routed together to perform a logic function (e.g., an adder, etc.).

[0100] Conversely, the processor 104 (or other component) may wish to configure the sub-array as a RAM 114. In this case, the memory access may instruct the configuration interface 116 to reconfigure the RLUT 112 as a standard RAM 114. In some embodiments, a predefined memory cell may be configured to store a bit indicating whether the sub-array is currently being used as a RLUT 112 or as a RAM 114. In various embodiments, this indication bit may be included in the sub-array or in the configuration interface 116. It should be understood that the above are merely a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0101] In various embodiments, the reconfigurable memory logic 102 may include dynamic RAM (DRAM). This is different from conventional FPGA or programmable logic device (PLD) technology in that the RLUT 112 can be reprogrammed through normal memory access operations without resorting to special voltages (e.g., to blow fuses or set transistors, etc.).

[0102] In such an embodiment, by biasing the RLUT 112 across the DRAM subarray, a higher density can be achieved compared to an SRAM-based FPGA. For example, the DRAM RLUT 112 may require only one transistor and one capacitor (1T1C) per memory cell or per information bit, compared to six transistors (6T) required for SRAM. In another embodiment, the DRAM RLUT 112 may achieve a lower cost compared to an SRAM or flash-based FPGA.

[0103] Because RLUT 112 can be modified by conventional memory accesses (or variations thereof), RLUT 112 can be self-modifying. For example, the output of a RLUT 112 computation for one clock cycle can cause a memory access to be made to reconfigure or update RLUT 112 to perform a second computational function. In another embodiment, the output of RLUT 112 can be fed back as an input to the same RLUT 112 to cause the behavior of RLUT 112 to be modified.

[0104] Additionally, in various embodiments, the intermixing of DRAM RLUT 112 and RAM 114 may provide advantages. For example, close proximity to data stored in RAM 114 may speed up computations performed by RLUT 112 and reduce power requirements because data does not need to move across a bus. In some embodiments, RLUT 112 may exist on the same die or package as processor 104 and / or memory 106 by biasing RLUT 112 with DRAM technology similar to that used to generate processor 104 and memory 106. Thus, the near-data computing provided by DRAM RLUT 112 may be faster and more efficient. Additionally, the same manufacturing process may reduce the production cost of system 100. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0105] Figure 2 is an isometric block diagram of an exemplary embodiment of a system 200 according to the disclosed subject matter. In the illustrated embodiment, multiple integrated circuit dies may be stacked (or otherwise integrated) to form a multi-chip module or system. In various embodiments, such a multi-chip system 200 may include a RLUT as described above or may include a more traditional lookup table (LUT).

[0106] In various embodiments, high bandwidth memory (HBM) may include a high-performance form of random access memory (RAM). In some embodiments, HBM may include stacked dynamic RAM (DRAM) that uses through silicon vias (TSVs) for communication. Generally speaking, high bandwidth memory combines through silicon vias (TSVs) with microbumps to connect multiple (e.g., 4, 8, etc.) memory cell array dies stacked on top of each other. In some embodiments, a memory controller (not shown) may be included on a separate die at the very bottom of the stack.

[0107] In various embodiments, system 200 may include a high bandwidth memory. In such embodiments, system 200 may include a memory controller (not shown), which may be placed at the top or bottom of the stack or in other ways, depending on the embodiment. It should be understood that the above is only an illustrative example, and the disclosed subject matter is not limited to the above illustrative examples.

[0108] In the illustrated embodiment, system 200 may include a memory (eg, DRAM, etc.) die 204 and a logic die 202. In the illustrated embodiment, memory die 204 may include a plurality of memory arrays 216. In such an embodiment, memory arrays 216 may be configured to store various data.

[0109] In the illustrated embodiment, the memory die 204 may include one or more lookup tables (LUTs) 214 or even reconfigurable lookup tables (RLUTs). In such an embodiment, the lookup table 214 may include a storage sub-array that has been configured as described above to store a lookup table LUT capable of performing a given logic function.

[0110] In various embodiments, the memory die 204 may include a plurality of memory cells 216. In such embodiments, the lookup table 214 may be configured to access data stored in the memory 216 of the memory die 204. In such embodiments, the lookup table 214 may be co-located with the accessed memory 216 or physically close to the accessed memory 216. In such embodiments, the connection between the lookup table 214 and the memory 216 may be reduced in terms of both access time and power. In addition, the required routing between the two may be reduced. It should be understood that the above is merely an illustrative example, and the disclosed subject matter is not limited to the above illustrative examples.

[0111] In various embodiments, logic die 202 may include a processor (e.g., a central processing unit, a graphics processing unit) configured to execute instructions or logic operations. In the illustrated embodiment, logic die 202 may include a plurality of logic circuits or combinatorial logical blocks (CLBs) 212. CLBs 212 generally include circuits for performing Boolean algebraic operations on input signals and on stored data, and as a practical matter typically include a mix of combinatorial logic (e.g., NAND gates and NOR gates) and sequential logic (e.g., flip-flops, latches).

[0112] In various embodiments, the lookup table 214 may communicate with the logic die 202 (e.g., CLB 212) using one or more vias 226. In such embodiments, this may enable high-speed communication between the two processing elements (e.g., the lookup table 214 and the CLB 212) without the need to communicate over a bus or external interface.

[0113] In various embodiments, via 226 may include an optical via, such as, for example, a photonic through silicon via (TSPV), an optical fiber, an optical waveguide, or an optical coupler. In such embodiments, if the lookup table 214 and the CLB 212 include circuitry, an electrical-to-optical transducer may be required at the input 222 of the via 226. Similarly, an optical-to-electrical transducer may be required at the output 224 of the via 226.

[0114] In one such embodiment, CLB 212 may process the instruction and produce a first set of data (the output of CLB 212). Logic die 202 may determine that the next stage of processing may be performed more efficiently by lookup table 214 (e.g., in terms of speed, bandwidth, power), and may instruct CLB 212 to transfer the data to lookup table 214 for processing.

[0115] In such an embodiment, CLB 212 may transmit the first data to lookup table 214 through optical via 226. In such an embodiment, optical via 226 or accompanying components may perform electrical / optical conversion as needed.

[0116] The lookup table 214 may process the first data or execute an instruction on the first data to generate a second set of data (the output of the lookup table 214). The lookup table 214 may then transmit this second data back to the logic die 202 to the same or different CLB 212 for further processing. Likewise, the data may be transmitted across the optical via 226.

[0117] In various embodiments, the lookup table 214 may generate the first data and transmit the first data to the CLB 212 for further processing (generating the second data). In such embodiments, the operation may be the reverse operation of the above operation.

[0118] In another embodiment, the lookup table 214 may use data stored in the memory 216 as input in addition to data from the CLB 212 or as the only input to the lookup table 214. In yet another embodiment, the output of the lookup table 214 may be stored in the memory 216 without being transmitted back to the CLB 212. Alternatively, the data may be copied to the memory 216 in addition to being at least partially transmitted to the CLB 212. In various embodiments, the optical via 226 may be used to read / write data from / to the memory 216. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0119] In various embodiments, the processing speed of certain operations (e.g., matrix multiplication, matrix convolution) may be limited by the internal bandwidth or the speed at which data can be moved. Thus, in the illustrated embodiment, the ability to move data between die 202 and die 204 using optical vias 226 may greatly increase processing speed.

[0120] In one embodiment, the photonic link or optical via 226 can enable much higher bandwidth density than traditional electrical links. For example, the optical via 226 can achieve a bandwidth or speed of 128 Gb / s compared to an electrical link speed of 64 Gb / s. In various embodiments, this can be accomplished through Dense Wave Division Multiplexing (DWDM), thereby enabling higher bandwidth (compared to electrical links) given substantially the same silicon footprint. It should be understood that the above is only an illustrative example, and the disclosed subject matter is not limited to the above illustrative examples.

[0121] In various embodiments, multiple memory dies 204 may be included in the system 200. In such embodiments, the memory dies 204 may be stacked on top of or on top of each other. In some embodiments, only a subset of the memory dies 204 may include the lookup table 214. In another embodiment, a plurality of optical vias 226 may be employed that directly connect the logic die 202 to a specific corresponding one of the stacked memory dies 204. In yet another embodiment, an optical via 226 may be employed that directly connects one stacked memory die 204 to another stacked memory die 204.

[0122] Figure 3300 is a block diagram of an exemplary embodiment of a system 300 according to the disclosed subject matter. In the illustrated embodiment, multiple integrated circuit dies may be stacked (or otherwise integrated) together to form a multi-chip module or system. In the illustrated embodiment, the focus is on components related to optical vias.

[0123] In the illustrated embodiment, system 300 may include memory die 304 and logic die 302, as described above. Additionally, in such an embodiment, system 300 may also include light source 390. Light source 390 may generate or otherwise provide light for use by the optical vias. In various embodiments, two or more of the dies 302, 304, or 390 may be coupled by intermediate layer 301.

[0124] In the illustrated embodiment, die 302 and die 304 may be connected via three elements. Light source link 356 may couple light source 390 to an optical element (e.g., modulator 322) of memory die 304, as described below. Address / command link or via 354 may transmit address and command data. In various embodiments, address / command via 354 may be optical or electrical. In such an embodiment, the bandwidth required for the smaller amount of information transmitted for address and command information may allow via 354 to be electrical. In another embodiment, address / command via 354 may be optical. In the illustrated embodiment, data link or via 352 may be optical, as described above. In various embodiments, links 352, 354, and 356 may include optical waveguides.

[0125] The transfer of data from the memory die 304 to the logic die 302 is discussed. In the illustrated embodiment, the memory die 304 may include a lookup table (LUT) 334 configured to perform a logic operation or function by receiving a first set of data and outputting a second set of data, as described above. The memory die 304 may include an intermediate result buffer, memory, or circuit 336 configured to store the first data or the second data.

[0126] In the illustrated embodiment, the memory die 304 may include a driver circuit 328 configured to receive the electrical version of the second data and drive or generate a version of the second data with sufficient electrical power to be converted by the modulator 322. In such an embodiment, the memory die 304 may include an optical modulator 322 configured to convert an electrical signal (e.g., the second data) into an optical signal. In such an embodiment, the modulator 322 may receive a light source 390 or a signal generated by the light source 390 (and routed to the modulator 322 by the light source link 356) and change or modulate the light source 390 based at least in part on the electrical version of the data received from the driver 328. This optical version of the data may then be transmitted to the logic die 302 across or through the data link or via 352.

[0127] In the illustrated embodiment, logic die 302 may include an optical filter and / or detector 324. The optical detector may be configured to detect optical data transmitted through a waveguide portion of an optical via (e.g., data via 352) and convert the optical data into electrical data. Logic die 302 may include amplifier circuit 326 configured to provide electrical gain or power to the received electrical data (e.g., second data). Logic die 302 may include computational or combinatorial logic 332 as described above, which may receive the data and further process the data.

[0128] In various embodiments, data transfer from logic die 302 to memory die 304 may be performed in a similar but reverse manner. In such an embodiment, logic die 302 may include its own type of driver circuit 328 and type of optical modulator 322. In such an embodiment, optical modulator 322 of logic die 302 may be coupled to light source 390 through intermediate layer 301. Memory die 304 may include its own type of optical filter and / or detector 324 and amplifier circuit 326, as described above.

[0129] In the illustrated embodiment, logic die 302 may include scheduler circuit 340, which is configured to coordinate inter-die data traffic across optical vias 352 and / or 354. In various embodiments, scheduler circuit 340 may determine when a certain operation or logic function should be performed by CLB 332 or lookup table 334. In various embodiments, scheduler circuit 304 may determine whether data should be transmitted across optical link 352 or across an electrical link (e.g., an electrical version of link 354). It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0130] In the illustrated embodiment, the lookup table 334, the intermediate result buffer 336, the amplifier 326, the driver 328, the CLB 332, and the scheduler 340 may be electrical components. In contrast, in the illustrated embodiment, the optical modulator 322, the optical detector 324, and the light source 390 may be at least primarily optical components. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0131] Figure 4a is a block diagram of an exemplary embodiment of a system 491 in accordance with the disclosed subject matter. In the illustrated embodiment, the system 491 may include a memory die, as described above. In the illustrated embodiment, bank-level granularity of access to various memory cells or elements of the memory die is discussed.

[0132] In the illustrated embodiment, system 491 may include multiple memory pads 490 (shown with memory cells and row and column decoders). These pads 490 may be arranged into memory banks 420. In various embodiments, system 491 may include multiple memory banks 420.

[0133] In this context, a memory pad 490 may be a building block of a memory bank 420. Multiple pads 490 in a memory bank 420 may be operated simultaneously to implement memory operations (e.g., read, write). Each memory pad 490 may include one or more sub-arrays or memory cells and decoder blocks (e.g., rows and columns). It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0134] In the illustrated embodiment, the memory pad 490 may be communicatively coupled to the optical via or waveguide 402 via a bus network 404. In such an embodiment, the entire memory bank 420 and the data therein may be selectively read from the optical via or waveguide 402 (as a source) or written to the optical via or waveguide 402 (as a target or destination).

[0135] In such an embodiment, when the memory bank 420 is used as a source or read from, the data of the memory bank 420 may be stored in the buffer circuit 416. The data may then be serialized at least in part by the serializer circuit 414, which converts the parallel data into a serial form. The electrical driver 412 may then provide sufficient gain or power for the electrical form of the data. The system 491 may include the buffer circuit 416, the serializer circuit 414, and the electrical driver 412.

[0136] In the illustrated embodiment, the light source 406 may then be modulated by a micro-ring modulator 404. This may be done based on the electrical form of the data so that the electrical data is transformed into optical data. In the illustrated embodiment, four micro-ring modulators 404 are shown, each of which is associated with a different wavelength (λ) or color. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited to the above illustrative examples. The new optical form of the data is transmitted across the optical via or waveguide 402.

[0137] Figure 4b is a block diagram of an exemplary embodiment of a system 492 in accordance with the disclosed subject matter. In the illustrated embodiment, the system 492 may include a memory die, as described above. In the illustrated embodiment, a memory pad-level granularity of access to various memory cells or elements of the memory die is discussed.

[0138] In the illustrated embodiment, the system 492 may include a plurality of memory pads 490 (shown with memory cells and row and column decoders), as described above. In the illustrated embodiment, the memory pads 490 may be grouped into pads 432 that are coupled to or access the optical vias or waveguides 402, and pads 434 that are disconnected from or not connected to the optical vias or waveguides 402.

[0139] In the illustrated embodiment, each of the memory pads 432 may be communicatively coupled directly to the optical vias or waveguides 402. In such an embodiment, data may be transmitted to a specific memory pad 490 rather than to a large group (e.g., bank) of memory pads 490. In various embodiments, each connected memory pad 432 may be associated with a corresponding modulation technique or format (e.g., wavelength, color, etc.).

[0140] In such an embodiment, when the connected memory pad 432 is used as a source or read from it, the data of the memory pad 490 can be stored in the buffer circuit 416. The data can then be serialized at least in part by the serializer circuit 414, which converts the parallel data into a serial form. The electrical driver 412 can then provide sufficient gain or power for the electrical form of the data. The system 491 can include the buffer circuit 416, the serializer circuit 414, and the electrical driver 412.

[0141] In the illustrated embodiment, the light source 406 may then be modulated by a micro-ring modulator 404. This may be done based on the electrical form of the data so that the electrical data is transformed into optical data. In the illustrated embodiment, four micro-ring modulators 404 are shown, each of which is associated with a different wavelength (λ) or color. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited to the above illustrative examples. The new optical form of the data is transmitted across the optical via or waveguide 402.

[0142] Figure 4c 493 is a block diagram of an exemplary embodiment of a system 493 according to the disclosed subject matter. In the illustrated embodiment, the system 493 may include a logic die, as described above. In the illustrated embodiment, the receive side of the optical via is illustrated. It should be understood that both the logic die and the memory die include their respective types of receive and transmit portions of the optical via interface.

[0143] In the illustrated embodiment, data may be transmitted across the optical via or waveguide 402. The data may be received or filtered by the microring filter 464. The system 493 may include a plurality of optical detectors or photodetectors 466. In various embodiments, each photodetector 466 may be associated with a corresponding microring filter 464. In the illustrated embodiment, four microring filters 464 and photodetectors 466 are shown, each of which is associated with a different wavelength (λ) or color. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited to the above illustrative examples. The photodetector 466 may convert the optical signal or data into an electrical signal or data, as described above.

[0144] In the illustrated embodiment, the system 493 may include a deserializer circuit 478. The deserializer circuit 478 may be configured to convert received signals or data from a serial form to a parallel form. The system 493 may include a buffer circuit 476 to store data. The data may then be sent or received by a target or destination processing block 480.

[0145] In various embodiments, each processing block 480 may include an input buffer 482 and / or an output buffer 488 (e.g., a flip-flop), one or more CLBs 486, and a scheduler circuit 484. In various embodiments, the scheduler circuit 484 may be configured to read data from / write data to a buffer circuit (e.g., buffer 476). As described above, the system 493 may include and Figure 4a and Figure 4bSuch a transmission interface (not shown) may include its own buffer circuit (similar to buffer 416) to which scheduler circuit 484 may write.

[0146] Figure 5 is a schematic block diagram of an information processing system 500 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0147] Reference Figure 5 , information processing system 500 may include one or more devices constructed according to the principles of the disclosed subject matter. In another embodiment, information processing system 500 may use or perform one or more techniques according to the principles of the disclosed subject matter.

[0148] In various embodiments, information handling system 500 may include a computing device, such as, for example, a laptop computer, a desktop computer, a workstation, a server, a blade server, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers, or a virtual machine or a virtual computing device of a virtual machine. In various embodiments, information handling system 500 may be used by a user (not shown).

[0149] The information processing system 500 according to the disclosed subject matter may also include a central processing unit (CPU), a logic or processor 510. In some embodiments, the processor 510 may include one or more functional unit blocks (FUBs) or combinatorial logic blocks (CLBs) 515. In such embodiments, the combinatorial logic blocks may include various Boolean logic operations (e.g., NAND, NOR, NOR, XOR), stabilization logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinatorial logic operations may be configured in a simple or complex manner to process input signals to achieve desired results. It should be understood that although a few illustrative examples of synchronous combinatorial logic operations are described, the disclosed subject matter is not limited thereto and may include asynchronous operations or a mixture thereof. In one embodiment, the combinatorial logic operation may include a plurality of complementary metal oxide semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged as gates for performing logic operations; although it should be understood that other technologies may also be used while being within the scope of the disclosed subject matter.

[0150] The information processing system 500 according to the disclosed subject matter may also include a volatile memory 520 (e.g., a random access memory (RAM)). The information processing system 500 according to the disclosed subject matter may also include a non-volatile memory 530 (e.g., a hard drive, an optical memory, a NAND memory, or a flash memory). In some embodiments, the volatile memory 520, the non-volatile memory 530, or a combination or some portions thereof may be referred to as a "storage medium". In various embodiments, the volatile memory 520 and / or the non-volatile memory 530 may be configured to store data in a semi-permanent form or a substantially permanent form.

[0151] In various embodiments, the information handling system 500 may include one or more network interfaces 540 configured to enable the information handling system 500 to become part of a communication network and communicate through the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE 802.11n. Examples of cellular protocols may include, but are not limited to, IEEE 802.16m (also known as Metropolitan Area Network (MAN), Long Term Evolution (LTE), Enhanced Data rates for GSM Evolution (EDGE), Evolved High-Speed ​​Packet Access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fibre Channel, Power Line Communications (e.g., HomePlug, IEEE 1901). It should be understood that the above are only a few exemplary examples, and the disclosed subject matter is not limited to the above several exemplary examples.

[0152] The information processing system 500 according to the disclosed subject matter may also include a user interface unit 550 (e.g., a display adapter, a tactile interface, a human-machine interface device). In various embodiments, such a user interface unit 550 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also enable interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and the input from the user may be received in any form, including acoustic input, voice input, or tactile input.

[0153] In various embodiments, the information processing system 500 may include one or more other devices or hardware components 560 (e.g., a display or monitor, a keyboard, a mouse, a camera, a fingerprint reader, a video processor). It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0154] The information processing system 500 according to the disclosed subject matter may also include one or more system buses 505. In such an embodiment, the system bus 505 may be configured to communicatively couple the processor 510, the volatile memory 520, the nonvolatile memory 530, the network interface 540, the user interface unit 550, and one or more hardware components 560. Data processed by the processor 510 or data input from outside the nonvolatile memory 530 may be stored in the nonvolatile memory 530 or in the volatile memory 520.

[0155] In various embodiments, the information handling system 500 may include or execute one or more software components 570. In some embodiments, the software component 570 may include an operating system (OS) and / or an application. In some embodiments, the OS may be configured to provide one or more services to the application and manage or act as an intermediary between the application and various hardware components (e.g., processor 510, network interface 540) of the information handling system 500. In such an embodiment, the information handling system 500 may include one or more local applications, which may be installed locally (e.g., installed in non-volatile memory 530) and configured to be directly executed by the processor 510 and interact directly with the OS. In such an embodiment, the local application may include pre-compiled machine executable code. In some embodiments, the local application may include a script interpreter (e.g., C shell (csh), AppleScript, AutoHotkey) or a virtual execution machine (VM) (e.g., Java virtual machine, Microsoft Common Language Runtime), which is configured to convert source code or object code into executable code, which is then executed by processor 510.

[0156] The semiconductor devices described above may be packaged using various packaging techniques. For example, a semiconductor device constructed according to the principles of the disclosed subject matter can be encapsulated using any of the following: package on package (POP) technology, ball grid array (BGA) technology, chip scale package (CSP) technology, plastic leaded chip carrier (PLCC) technology, plastic dual in-line package (PDIP) technology, die in waffle pack technology, die in wafer form technology, chip on board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic metric quad flat package (PMQFP) technology, plastic quad flat package (PQFP) technology, small outline package (SOIC) technology, shrink small outline package (SSOP) technology, thin small outline package (TSOP) technology. The present invention relates to a semiconductor device comprising a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, a semiconductor package (CMOS, TSOP) technology, or other technologies known to those skilled in the art.

[0157] The method steps may be performed by one or more programmable processors by executing a computer program to perform functions by operating on input data and generating outputs. The method steps may also be performed by a dedicated logic circuit (e.g., a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)), and the apparatus may be implemented as a dedicated logic circuit.

[0158] In various embodiments, the computer readable medium may include instructions that, when executed, cause a device to perform at least a portion of the method steps. In some embodiments, the computer readable medium may be included in magnetic media, optical media, other media, or a combination thereof (e.g., compact disc read only memory (CD-ROM), hard drive, read only memory, flash drive). In such embodiments, the computer readable medium may be an article of manufacture that is tangible and implemented in a non-transitory manner.

[0159] Although the principles of the disclosed subject matter have been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above embodiments are not restrictive, but merely illustrative. Therefore, the scope of the disclosed concepts should be determined by the broadest interpretation permitted by the above claims and their equivalents, and should not be constrained or limited by the above description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments.

Claims

1. A device for finding a computing artificial intelligence accelerator, include: a memory circuit die configured to store a lookup table that converts first data into second data; a logic circuit die, comprising a logic circuit, wherein the logic circuit is configured to receive the second data; as well as an optical via coupled between the memory circuit die and the logic circuit die and configured to transmit the second data between the memory circuit die and the logic circuit die; The device is configured to generate the first data using the logic circuit, transmit the first data to the memory circuit die through the optical via, and convert the first data into the second data based on the lookup table.

2. The device of claim 1, wherein the memory circuit die include: a driver circuit configured to receive the electrical version of the second data; as well as an optical modulator configured to change a light source based at least in part on the electrical pattern of the second data, The optical modulator is coupled to the waveguide portion of the optical via.

3. The apparatus of claim 1, wherein the memory circuit die include: an optical detector configured to detect optical data transmitted through the waveguide portion of the optical via and convert the optical data into electrical data; as well as The amplifier circuit is configured to provide electrical gain to the electrical data.

4. The apparatus of claim 1 , wherein the memory circuit die comprises one or more memory pads arranged into memory banks, and The optical via is communicatively coupled to the memory bank to select the memory bank for transmitting data through the optical via.

5. The apparatus of claim 1 , wherein the memory circuit die comprises a memory pad, and Wherein the optical via is communicatively coupled to the storage pad, wherein the storage pad is associated with a modulation format such that data transmission using the modulation format is directed to the storage pad.

6. The device of claim 1, wherein the logic circuit die include: A scheduler circuit is configured to coordinate inter-die data traffic traversing the optical via.

7. The device of claim 1, wherein the optical via comprises a photonic through silicon via, and The memory circuit die includes a reconfigurable lookup table.

8. The device of claim 1, wherein the logic circuit die include: One or more first logic circuits configured to generate the first data; an optical transmitter configured to convert the first data from an electrical form into an optical form and transmit the first data in the optical form to the memory circuit die; an optical receiver configured to receive the second data and convert the second data into an electrical form; as well as one or more second logic circuits configured to receive the second data and process the second data, and The storage circuit die comprises: the lookup table comprising a dynamically reconfigurable logic operation configured to convert the first data into the second data, and A transducer is configured to convert data between the electrical form and the optical form.

9. A device for finding a computing artificial intelligence accelerator, include: a first circuit die configured to store a reconfigurable logic circuit configured to process first data at a first efficiency; a second circuit die including one or more logic circuits configured to convert input data received by the second circuit die into the first data, the second circuit die configured to process the first data at a second efficiency; as well as An optical link is coupled between the first circuit die and the second circuit die and is configured to transmit the first data between the first circuit die and the second circuit die, wherein when the first efficiency is greater than the second efficiency, the second circuit die is configured to transmit the first data across the optical link to the first circuit die so that the first data is processed by the reconfigurable logic circuit.

10. The device of claim 9, wherein the second circuit die include: a driver circuit configured to receive an electrical version of the first data from the one or more logic circuits; an optical modulator configured to vary a light source based at least in part on the electrical pattern of the first data, Wherein the optical modulator is coupled to the optical link.

11. The apparatus of claim 9, wherein the first circuit die include: an optical detector configured to detect optical data transmitted across the optical link and convert the optical data into electrical data; as well as The amplifier circuit is configured to provide electrical gain to the electrical data and provide the electrical data to the reconfigurable logic circuit.

12. The apparatus according to claim 9, wherein the reconfigurable logic circuit comprises at least one memory pad, the at least one memory pad being arranged into a memory bank, and Wherein the optical link is communicatively coupled to the memory bank.

13. The apparatus of claim 9, wherein the reconfigurable logic circuit comprises a memory pad, and Wherein the optical link is communicatively coupled to the storage pad, wherein the storage pad is associated with a modulation format such that data transmissions using the modulation format are directed to the storage pad.

14. The apparatus of claim 9, wherein the second circuit die include: A scheduler circuit is configured to coordinate inter-die data traffic traversing the optical link.

15. The apparatus of claim 9, wherein the optical link comprises a photonic through-silicon via, and The reconfigurable logic circuit includes a lookup table.

16. A multi-chip module, include: a light source configured to generate an optical signal; a logic circuit die including logic circuits and configured to optically transfer data to a memory circuit die; an intermediate layer configured to couple the light source with the logic circuit die; The storage circuit die is configured to store a lookup table, wherein the lookup table receives the data; as well as An optical via is coupled between the memory circuit die and the logic circuit die and is configured to transmit the data between the memory circuit die and the logic circuit die.

17. The multi-chip module according to claim 16, further comprising: include: An electrical via is coupled between the memory circuit die and the logic circuit die and is configured to transmit address information between the memory circuit die and the logic circuit die.

18. The multi-chip module according to claim 16, further comprising: include: a second storage circuit die configured to store a second lookup table; as well as A second optical via is coupled between the memory circuit die and the second memory circuit die and is configured to transmit the data between the memory circuit die and the second memory circuit die.

19. The multi-chip module according to claim 16, wherein the logic circuit include: a second logic circuit configured to process the data, and A scheduler circuit is configured to transmit the data from the optical via to the second logic circuit.

20. The multi-chip module of claim 16, further comprising a scheduler circuit configured to coordinate the transmission of the data across the optical vias.

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