Hardware implementation of convolutional layers of deep neural networks

By designing multiple convolution engines in deep neural networks to process input data and weights in parallel, and reusing the same input data and weights in succession periods, the high power consumption and high bandwidth requirements of the convolutional layer are solved, and the problem of high power consumption and high bandwidth is realized Flexible DNN hardware implementation.

CN110046700BActive Publication Date: 2024-12-24IMAGINATION TECH LTD
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Patent Information

Application Number
CN201811299906.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2017-11-03
Filing Date
2018-11-02
Publication Date
2024-12-24
Estimated Expiration
2040-01-04

AI Technical Summary

Technical Problem

In existing deep neural network (DNN) hardware implementations, the power consumption and memory bandwidth requirements of the convolutional layer are high, limiting its performance in resource-constrained applications and difficult to support the flexibility of multiple DNN configurations.

Method used

A hardware implementation solution is designed to process input data and weights in parallel through multiple convolution engines, and reuse the same input data and weights in succession periods, reducing the number of memory reads, reducing power consumption and bandwidth requirements, and supporting multiple DNN configuration.

Benefits of technology

It effectively reduces the power consumption and memory bandwidth requirements of the convolutional layer, improves resource utilization, supports a variety of DNN configurations, and improves the flexibility and efficiency of hardware implementation.

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Abstract

The present disclosure relates to a hardware implementation of a convolutional layer of a deep neural network. A hardware implementation of a convolutional layer of a deep neural network DNN and a method for processing a convolutional layer of the DNN are provided, the hardware implementation comprising a plurality of convolutional engines, wherein input data and weights are provided to the convolutional engines in an order that allows the input data and weights to be read from a memory for at least two filter-window calculations performed by the same convolutional engine in consecutive cycles or by different convolutional engines in the same cycle. For example, in some hardware implementations of the convolutional layer, the convolutional engines are configured to process the same weights and different input data in each cycle, however the input data of each convolutional engine remains the same for at least two cycles, so that the convolutional engines use the same input data in at least two consecutive cycles.
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