Thin film resistors with through-hole vias

Abstract

The present application relates to a thin film resistor with a through via, wherein a device including a thin film resistor (TFR) structure is disclosed. The TFR structure is accessible through one or more conductive vias, which extend vertically from an upper metal layer to completely penetrate the TFR layer located therebelow. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the penetration site. The TFR structure can be manufactured by a method comprising the steps of etching a through-hole trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the through-hole trench with a conductor coupled to the sidewalls of the TFR layer.

Description

Background Art

[0001] Thin film transistors (TFRs) offer low temperature coefficient of resistivity (TCR) and low mismatch and have many applications. For example, due to the low TCR, high precision analog circuits (e.g., voltage references, digital-to-analog converters) may include one or more TFRs. Due to process variations, the actual resistance of a TFR may deviate from its target resistance. As the thickness of the TFR decreases, this deviation becomes more susceptible to process variations. In the case of ultra-thin (e.g., less than )TFR high-precision analog applications, even a small amount of resistor deviation can cause mismatch problems. Summary of the invention

[0002] The present disclosure discovers one or more process variations during the formation of a conductive via coupled to a thin film resistor (TFR) layer. The discovered process variations may cause deviations in the actual resistance of the TFR layer from its target resistance. To address these deviations, the present disclosure introduces methods and apparatus for minimizing process variations during the formation of a conductive via coupled to one or more TFR layers.

[0003] For example, in one embodiment, the present disclosure introduces a method comprising: forming a thin film resistor (TFR) layer above a substrate, forming a dielectric layer above the TFR layer, etching a through hole completely through the dielectric layer and the TFR layer, and filling the through hole with a conductor coupled to the sidewall of the TFR layer.

[0004] For example, in another embodiment, the present disclosure introduces a method, comprising: forming a first thin film resistor (TFR) layer above a substrate, forming a first dielectric layer above the first TFR layer, forming a second TFR layer above the first dielectric layer, forming a second dielectric layer above the second TFR layer, forming a first conductive via completely passing through the first and second dielectric layers and completely passing through a first terminal region of the first TFR layer, and forming a second conductive via completely passing through the second dielectric layer and completely passing through a second terminal region of the second TFR layer.

[0005] For example, in yet another embodiment, the present disclosure introduces a device that includes a substrate, a thin film resistor (TFR) layer, a dielectric layer, and a conductive via. The TFR layer is located above the substrate, and the dielectric layer is located above the TFR layer. The conductive via completely penetrates the dielectric layer and completely passes through the TFR layer. In addition, the conductive via is coupled to the sidewall of the TFR layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of a device having multiple thin film resistor (TFR) structures is shown.

[0007] Figure 2A-2BA cross-sectional view of a TFR structure with through-vias according to one aspect of the present disclosure is shown.

[0008] Figure 3 A cross-sectional view of a device having multiple TFR structures with through vias reaching an etch stop layer according to one aspect of the present disclosure is shown.

[0009] Figure 4 A cross-sectional view of a device having a single TFR structure with multiple TFR layers, each TFR layer including through-vias, according to one aspect of the present disclosure is shown.

[0010] Figure 5 According to one aspect of the present disclosure, Figure 4 A top view of the device is shown.

[0011] Figure 6 A flow chart describing a process of fabricating one or more TFR structures having through-vias according to one aspect of the present disclosure is shown.

[0012] Figure 7A-7E Shows the manufacturing Figure 4 and Figure 5 A cross-sectional view of the device process shown in FIG. Figure 6 The flow chart shown is slightly different.

[0013] The same reference numerals in the various drawings indicate the same elements. The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. The drawings are not drawn to scale, and they are provided only to illustrate the present disclosure. Specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. Other features and advantages may be apparent from the specification and drawings, and from the claims. DETAILED DESCRIPTION

[0014] Figure 1 A cross-sectional view of a device 100 having a plurality of thin film resistor (TFR) structures is shown. The device 100 may be a semiconductor device, such as an integrated circuit having one or more analog circuits. The device 100 includes a semiconductor substrate 102 and a dielectric layer stack 110 on the semiconductor substrate 102. The dielectric layer stack 110 may be formed by sequentially depositing a first dielectric layer 112, depositing a second dielectric layer 114 on the first dielectric layer 112, depositing a third dielectric layer 115 on the second dielectric layer 114, depositing a fourth dielectric layer 116 on the third dielectric layer 115, and depositing a fifth dielectric layer 118 on the fourth dielectric layer 116.

[0015] The device 100 includes one or more metal layers for accessing transistor regions in the substrate 102 and / or electronic components located above the substrate 102. For example, in one embodiment, the device 100 may include a first metal layer 121 and second metal layers 122, 123, 124, 125, and 126. The first metal layer 121 is located between the first dielectric layer 112 and the second dielectric layer 114, and the second metal layers 122, 123, 124, 125, and 126 are located between the fourth dielectric layer 116 and the fifth dielectric layer 118.

[0016] The device 100 also includes one or more TFR structures, such as a first TFR structure 130 and a second TFR structure 140. The first TFR structure 130 includes a first TFR layer 132 located between the second dielectric layer 114 and the third dielectric layer 115. The second TFR structure 140 includes a second TFR layer 142 located between the third dielectric layer 115 and the fourth dielectric layer 116. Typically, the TFR layer may have a thickness of less than 0.5 μm. For example, the first TFR layer 132 may have a thickness of less than The second TFR layer 142 may have a thickness of and Due to its relatively small thickness, the TFR layer typically has a high sheet resistance (eg, 100-1000 Ω / □) and a near-zero temperature coefficient of resistance (TCR) with very low mismatch (eg, less than 5000 ppm-μm mismatch).

[0017] Each of the first TFR layer 132 and the second TFR layer 142 can be approached / accessed through the upper metal layer using one or more conductive vias. For example, the first TFR layer 132 is coupled to the second metal layers 123 and 124 through the first conductive via V2A and the second conductive via V2B, respectively. Similarly, the second TFR layer 142 is coupled to the second metal layers 125 and 126 through the first conductive via V3A and the second conductive via V3B. Because the second TFR layer 142 is relatively thick, the first via V3A and the second via V3B can be etched into the top surface of the TFR layer 142 to form an ohmic contact. In contrast, the first TFR layer 132 is relatively thin, so that a first landing pad (e.g., titanium nitride (TiN) or silicon chromium (SiCr) material) and a second landing pad (e.g., TiN or SiCr material) can be used to receive the first conductive via V2A and the second conductive via V2B and to establish an ohmic contact.

[0018] The first TFR layer 132 and the second TFR layer 142 are both located between the first metal layer 121 and the second metal layer 122. In this way, conductive vias V2A, V2B, V3A, and V3B are formed together with the conductive via V1 that couples the first metal layer 121 to the second metal layer 122. These conductive vias have at least three different depths, where the conductive via V1 is the deepest, the first conductive via V2A and the second conductive via V2B are the second deepest, and the first conductive via V3A and the second conductive via V3B are the least deep. The process of forming conductive vias with three or more depths can be challenging because the etching of the via trenches can cause a certain amount of inaccuracy. This inaccuracy can, in turn, cause the actual resistance of the first TFR structure 130 and the second TFR structure 140 to deviate from their respective target resistances.

[0019] For example, referring to the first TFR structure 130, the first conductive via V2A extends deeper and further into the first landing pad 134 than the second conductive via V2B extends into the second landing pad 136. Any such penetration difference may produce a mismatch in the head resistance (or terminal resistance) across the first TFR layer 132. If the head resistance mismatch is significant (e.g., greater than 10% of the total mismatch), the actual resistance of the first TFR structure 130 may become inaccurate for its intended application.

[0020] Furthermore, for example, referring to the second TFR structure 140, the first conductive via V3A extends deeper and further into the second TFR layer 142 than the second conductive via V3B. Likewise, any such penetration difference may produce a mismatch in the head resistance (or terminal resistance) across the second TFR layer 142. If the head resistance mismatch is significant (e.g., greater than 10% of the total mismatch), the actual resistance of the second TFR structure 140 may become inaccurate for its intended application.

[0021] The present disclosure introduces a solution to minimize the variability of head resistance due to process variations during the manufacture of one or more TFR structures. The disclosed solution also provides additional process efficiencies compared to conventional processes for manufacturing TFR structures (e.g., the first TFR structure 130 and the second TFR structure 140). For example, in one embodiment, the disclosed solution includes a conductive via that completely penetrates the TFR layer and forms an ohmic contact with the sidewall of the TFR layer at or near the penetration site. The sidewall coupling between the conductive via and the TFR layer is more uniform and less susceptible to process variations (e.g., a depth difference between a pair of conductive vias used to access the TFR layer) than the top surface coupling employed by the first TFR structure 130 and the second TFR structure 140.

[0022] refer to Figure 2A, which shows a TFR structure 200 with through vias VA and VB according to one aspect of the present disclosure. For a more realistic and detailed description, Figure 2B A high-resolution scanning electron microscope (SEM) image is shown of a partial cross-sectional view of the TFR structure 200 . The TFR structure 200 may be a portion or discrete component of an electronic device, such as the device 100 , which includes a semiconductor substrate 202 and a dielectric layer stack 210 .

[0023] The TFR structure 200 includes a TFR layer 230 located above the substrate 202 and between the first dielectric layer 212 and the second dielectric layer 214. The TFR layer 230 may be a thin resistive layer (e.g., less than 0.5 μm) with a relatively large sheet resistance (e.g., 100-1000 Ω / □). For example, in one embodiment, the TFR layer 230 may include a silicon-chromium (SiCr)-based intermetallic compound having Si x Cr y C z O w Example compositions (relative atomic %) of , where x and y may be in the range of 5% to 50%, and z and w may be in the range of 0% to 50%. For example, in another embodiment, the TFR layer 230 may include a nickel-chromium (NiCr) based intermetallic mixture having Ni x Cr y C z O w Example compositions (relative atomic %) of , where x and y may be in the range of 5% to 50%, and z and w may be in the range of 0% to 50%. For example, in yet another embodiment, the TFR layer 230 may include a polysilicon material.

[0024] The TFR layer 230 has a first terminal region 232 located near the first end and a second terminal region 234 located near the second end opposite to the first end. The distance between the first terminal region 232 and the second terminal region 234 defines the bulk resistance of the TFR layer 230. The TFR structure 200 includes a first upper metal layer 222 and a second upper metal layer 224 vertically aligned with the first terminal region 232 and the second terminal region 234, respectively. The first upper metal layer 222 and the second upper metal layer 224 are located between the second dielectric layer 214 and the third dielectric layer 216.

[0025] The TFR structure 200 also includes a first through via VA and a second through via VB for providing a conductive path between the first upper metal layer 222 and the second upper metal layer 224 and through the TFR layer 230. The first through via VA and the second through via VB are conductive in nature, and they may include conductive materials such as tungsten, aluminum and / or copper. The first through via VA and the second through via VB each completely penetrate the dielectric layer (e.g., the second dielectric layer 214) between the TFR layer 230 and the upper metal layers 222 and 224. In addition, the first through via VA and the second through via VB each completely penetrate the TFR layer 230, so that the through vias VA and VB are coupled to the first sidewall 236 and the second sidewall 238 of the TFR layer 230 at or near the penetration site.

[0026] The first through via VA is a first conductive via that completely penetrates the first terminal region 232. The first barrier layer 262 may be deposited between the conductive material of the first through via VA and the first sidewall 236 of the TFR layer 230 to be penetrated to enhance ohmic contact and adhesion therebetween. For example, in one embodiment, the first barrier layer 262 may include a titanium (Ti) layer followed by a titanium nitride (TiN) material. For example, in another embodiment, the first barrier layer 262 may be omitted. The first through via VA may extend below the first terminal region 232 of the TFR layer 230 and include a first tip 242 and a second tip 244 protruding from the bottom surface of the TFR layer 230. Alternatively, the first through via VA may stop extending and be flush with the bottom surface of the TFR layer 230.

[0027] In a similar manner, the second through via VB is a second conductive via that completely penetrates the second terminal region 234. A second barrier layer 266 may be deposited between the conductive material of the second through via VB and the second sidewall 238 of the TFR layer 230 that is penetrated to enhance ohmic contact and adhesion therebetween. For example, in one embodiment, the second barrier layer 266 may include a titanium (Ti) layer followed by a titanium nitride (TiN) material. For example, in another embodiment, the second barrier layer 266 may be omitted. The second through via VB may extend below the second terminal region 234 of the TFR layer 230 and include a first tip 246 and a second tip 248 that protrude from the bottom surface of the TFR layer 230. Alternatively, the second through via VB may stop extending and be flush with the bottom surface of the TFR layer 230.

[0028] refer to Figure 2B , the landing pad 250 can be used to locate and align the etching site to form the first through via VA. In this particular process configuration, the first through via VA also completely penetrates the landing pad 250 before penetrating the TFR layer 230. In other embodiments, the landing pad 250 can be omitted altogether.

[0029] The TFR structure 200 having through vias VA and VB provides several advantages over conventional TFR structures. From a structural perspective, the contacts between the through vias VA and VB and the TFR layer 230 are along the sidewalls 236 and 238 at or near the penetration sites. The resistivity of these sidewall contacts is fairly uniform and is independent of the respective depths of the through vias VA and VB. In this way, the through vias VA and VB can promote uniform current flow (e.g., I1, I2, I3, and I4) across the perimeter of the sidewall contacts. The uniform current flow can be attributed to relatively precise resistances in the terminal regions (e.g., 232 and 234). Advantageously, the TFR structure 200 provides precise resistances for high precision analog applications, and it is less sensitive to process variations than, for example, Figure 1 The TFR structures 130 and 140 are shown and described.

[0030] From a process perspective, the manufacturing of the TFR structure 200 is more flexible and requires fewer process steps. This flexible and simplified manufacturing process (see below) Figure 6 -Description of FIG. 7) allows multiple TFR layers to be positioned at different depths from the device top surface and connected during a back-end-of-line (BEL) process without requiring a via trench etch process that is selective to one or more resistive materials. Advantageously, multiple via trenches of different depths can be etched: (1) without the assistance of any landing pad, (2) during a single etch process, and (3) within a single etch time period.

[0031] Although the technique of forming through vias is described herein as being applied to connecting one or more TFR layers, the technique may also be applied to connecting other types of conductive layers within a semiconductor device. For example, in one embodiment, through vias may be used to interconnect multiple metal layers and / or polysilicon layers.

[0032] The TFR structure 200 can be configured, arranged, and modified in many ways. The following description provides some example embodiments of the TFR structure 200 and processes for manufacturing the TFR structure 200. For example, Figure 3As shown, according to one aspect of the present disclosure, the device 300 includes a first TFR structure 330 and a second TFR structure 350, each TFR structure having through vias (e.g., VAX, VBX, VBX, and VBY) reaching an etch stop layer (e.g., 334, 336, 352, 354). The device 300 includes a semiconductor substrate 302 and a dielectric layer stack 310 on the semiconductor substrate 302. The dielectric layer stack 310 is formed by sequentially depositing a first dielectric layer 312, depositing a second dielectric layer 314 on the first dielectric layer 312, depositing a third dielectric layer 316 on the second dielectric layer 314, and depositing a fourth dielectric layer 318 on the third dielectric layer 316.

[0033] The first TFR structure 330 and the second TFR structure 350 are each located above the semiconductor substrate 302 and within the dielectric layer stack 310. Each of the first TFR structure 330 and the second TFR structure 350 includes the structural features of the TFR structure 200. For simplicity, Figure 3 Some of these features are not shown or described again in FIG. 3 , but it should be understood that the first TFR structure 330 and the second TFR structure 350 may still include these features.

[0034] The first TFR structure 330 includes a first TFR layer 332 located between the second dielectric layer 314 and the third dielectric layer 316. The first TFR layer 332 has a dielectric structure similar to that shown in FIG. Figure 2A The first TFR layer 332 has similar characteristics to the TFR layer 230 shown and described in FIG. The first TFR layer 332 has a first terminal region 334 and a second terminal region 336. The distance between the first terminal region 334 and the second terminal region 336 defines a bulk resistance accessible from the TFR layer 332. The first TFR structure 330 includes upper metal layers 322 and 324 for accessing the first TFR layer 332. The first TFR structure 330 includes a first through (conductive) via VAX and a second through (conductive) via VBX, both of which extend from the upper metal layers 322 and 324 to completely penetrate the first TFR layer 332.

[0035] Specifically, the first through via VAX penetrates the first terminal region 334 of the first TFR layer 332 and protrudes from the bottom surface of the first TFR layer 332. Similarly, the second through via VAX penetrates the second terminal region 336 of the first TFR layer 332 and protrudes from the bottom surface of the first TFR layer 332. The first through via VAX and the second through via VBX are coupled to the sidewall of the first TFR layer 332 at or near the penetration site. Depending on the process flow, a barrier layer may be deposited between each of the first through via VAX and the second through via VBX and the corresponding sidewall of the first TFR layer 332 (see, e.g., Figure 2A 262 in the ).

[0036] As a modification from the TFR structure 200, the first TFR structure 330 includes an etch stop layer below the first TFR layer 332. In one embodiment, the etch stop layer may include a first lower metal layer 321 and a second lower metal layer 323, both of which are located between the second dielectric layer 312 and the third dielectric layer 314. Vertically aligned with the first terminal region 334 and the second terminal region 336, the lower metal layers 321 and 323 may serve as landing layers for receiving the first through via VAX and the second through via VBX, respectively. Depending on the etching time used to etch the through via trenches, the first through via VAX and the second through via VBX may reach the first lower metal layer 321 and the second lower metal layer 323 without completely penetrating them.

[0037] The second TFR structure 350 includes a second TFR layer 352 located between the second dielectric layer 314 and the third dielectric layer 316. The second TFR layer 352 has a dielectric structure similar to that shown in FIG. Figure 2A The second TFR layer 352 has similar characteristics to the TFR layer 230 shown and described in FIG. The second TFR layer 352 has a first terminal region 354 and a second terminal region 356. The distance between the first terminal region 354 and the second terminal region 356 defines a bulk resistance accessible from the TFR layer 352. The second TFR structure 350 includes upper metal layers 326 and 328 for accessing the second TFR layer 352. The second TFR structure 350 includes a first through (conductive) via VAY and a second through (conductive) via VBY, both of which extend from the upper metal layers 326 and 328 to completely penetrate the second TFR layer 352.

[0038] Specifically, the first through via VAY penetrates the first terminal region 354 of the second TFR layer 354 and protrudes from the bottom surface of the second TFR layer 352. Similarly, the second through via VBY penetrates the second terminal region 356 of the second TFR layer 354 and protrudes from the bottom surface of the second TFR layer 352. The first through via VAY and the second through via VBY are coupled to the sidewall of the first TFR layer 352 at or near the penetration site. Depending on the process flow, a barrier layer may be deposited between each of the first through via VAY and the second through via VBY and the corresponding sidewall of the second TFR layer 352 (see, e.g., Figure 2A 266).

[0039] As a modification from the TFR structure 200, the second TFR structure 350 includes an etch stop layer below the second TFR layer 352. In one embodiment, the etch stop layer may include a first silicon nitride (SiN) layer 325 and a second silicon nitride (SiN) layer 327, both of which are located between the third dielectric layer 314 and the fourth dielectric layer 316. The first SiN layer 325 and the second SiN layer 327 may be located directly below the second TFR layer 352. Moreover, the first SiN layer 325 and the second SiN layer 327 may be located above the lower metal layers 321 and 323. Vertically aligned with the first terminal region 354 and the second terminal region 356, the SiN layers 325 and 327 may serve as landing layers for receiving the first through via VAY and the second through via VBY, respectively. Depending on the etching time for etching the through via trenches, the first through via VAY and the second through via VBY may reach the first SiN layer 325 and the second SiN layer 327 without completely penetrating them.

[0040] refer to Figure 4 , the TFR structure 200 can be configured and arranged to form a single TFR structure 400 having multiple TFR layers (e.g., 430 and 450). The TFR structure 400 is formed in a device having a substrate 402 and a dielectric layer stack 410. The dielectric layer stack 410 is formed by sequentially depositing a first dielectric layer 412, a second dielectric layer 414 on the first dielectric layer 412, a third dielectric layer 416 on the second dielectric layer 414, a fourth dielectric layer 418 on the third dielectric layer 416, and a fifth dielectric layer 419 on the fourth dielectric layer 419.

[0041] TFR structure 400 includes the structural features of TFR structure 200. Figure 4 4. Some of these features are not shown or described again in the drawings, but it should be understood that the TFR structure 400 may still include these features. The TFR structure 400 includes a first TFR layer 430 located above the substrate 402. The first TFR layer 430 positioned between the first dielectric layer 414 and the second dielectric layer 416 may be formed after the first dielectric layer 414 and before the second dielectric layer 416. The second TFR layer 450 positioned between the second dielectric layer 416 and the third dielectric layer 418 may be formed after the second dielectric layer 416 and before the third dielectric layer 418.

[0042] The first TFR layer 430 and the second TFR layer 450 each have Figure 2A The first TFR layer 430 and the second TFR layer 450 are coupled in series to form a resistor chain. To reduce die size, the second TFR layer 450 is arranged to at least partially overlap and coextensive with the first TFR layer 430. For example, Figure 5 As shown, the first TFR layer 430 and the second TFR layer 450 coextensively overlap each other between the upper metal layer 424 and the upper metal layer 426. Three through (conductive) vias VAZ, VBZ and VCZ are used to access different resistor segments of the resistor chain formed by the first TFR layer 430 and the second TFR layer 450.

[0043] The first through via VAZ extends from the first upper metal layer 422 to completely penetrate the first terminal region 432 of the first TFR layer 430. The first through via VAZ protrudes from the bottom surface of the first TFR layer 430 to reach the first etch stop layer (or landing pad layer), such as the first lower metal layer 421. The first through via VAZ is coupled to the sidewall of the first TFR layer 430 at or near the penetration site.

[0044] The second through via VBZ extends from the second upper metal layer 424 to completely penetrate the first terminal region 452 of the second TFR layer 450. The second through via VAZ protrudes from the bottom surface of the second TFR layer 450 to reach the second etch stop layer (or landing pad layer), such as the second lower metal layer 423. The second through via VBZ is coupled to the sidewall of the second TFR layer 450 at or near the penetration site. Figure 5 As shown, the second through via VBZ is located out of the plane of the first TFR layer 430, so that the second through via VBZ does not cross the path or penetrate the first TFR layer 430. Unlike the first through via VAZ, the second through via VBZ does not establish any direct ohmic contact with the first TFR layer 430.

[0045] The third through via VCZ extends from the third upper metal layer 426 to completely penetrate the second terminal region 454 of the second TFR layer 450 and the second terminal region 434 of the first TFR layer 430. The third through via VCZ protrudes from the bottom surfaces of the second TFR layer 450 and the first TFR layer 430 to reach a third etch stop layer (or landing pad layer), such as the third lower metal layer 425. When the third through via VCZ establishes ohmic contact with both the first TFR layer 430 and the second TFR layer 450, it serves as a connector for connecting between the first TFR layer 430 and the second TFR layer 450.

[0046] The first through via VAZ and the third through via VCZ together establish a conductive path through the first TFR layer 430. As such, the first upper metal layer 422 and the third upper metal layer 426 can be used to access the bulk resistance of the first TFR layer 430 between the first terminal region 432 and the second terminal region 434. Similarly, the second through via VBZ and the third through via VCZ establish a conductive path through the second TFR layer 450. As such, the second upper metal layer 424 and the third upper metal layer 426 can be used to access the bulk resistance of the second TFR layer 450 between the first terminal region 452 and the second terminal region 454. In addition, the first through via VAZ and the second through via VBZ establish a conductive path through the first TFR layer 430, the third through via VCZ, and the second TFR layer 450. The first upper metal layer 422 and the second upper metal layer 424 can be used to access the aggregate bulk resistance of the first TFR layer 430 and the second TFR layer 450. In this configuration, the TFR structure 400 can be used as a voltage divider, where the first upper metal layer 422 is coupled to a high potential terminal (eg, V H ), the second upper metal layer 424 is coupled to a low potential terminal (eg, V L ), and the third upper metal layer 426 is configured to transmit an intermediate potential between the high potential and the low potential (eg, V Div =(V H -V L )*R TFR2 / (R TFR1 +R TFR2 )).

[0047] Although the TFR structure 400 includes only two TFR layers, the present disclosure can be applied to construct TFR structures having more than two TFR layers. For example, the TFR structure 400 can include a third TFR layer above the second TFR layer, which can be accessed by a second through-via VBZ and additional through-vias. Advantageously, through-vias help improve the space efficiency of traditional resistor chains by allowing multiple resistor segments to be stacked vertically on top of each other.

[0048] In addition, despite Figure 4 The multilayer TFR structure 400 is shown configured as a series resistor chain, but the same multilayer TFR architecture can be configured to form a capacitor. For example, the TFR structure 400 can remove the third through-via VCZ so that the first TFR layer 430 and the second TFR layer 450 are not electrically coupled to each other. But instead, the first TFR layer 430 and the second TFR layer 450 are capacitively coupled by overlapping each other with the second dielectric layer 416 located therebetween.

[0049] Figure 6A flow chart is shown describing a method 600 for manufacturing one or more TFR structures (e.g., TFR structures 200, 330, 350, and / or 400) having through vias (e.g., VA, VB, VAX, VBX, VAY, VBY, VAZ, VBZ, VCZ) according to one aspect of the present disclosure. The method 600 includes a first process 610 and a second process 630. The first process 610 is used to manufacture a TFR structure (e.g., TFR structure 200, 330, and / or 350) having a single TFR layer, while the second process 630 is combined with the first process 610 to manufacture a TFR structure (e.g., TFR structure 400) having multiple TFR layers. The first process 610 includes a first sequence 620 for forming one or more through vias penetrating a single TFR layer. The second process 630 includes a second sequence 640 for forming one or more through vias penetrating multiple TFR layers. Although Figure 6 The first sequence 620 is shown to be performed before and separately from the second sequence 640 , but the first sequence 620 may be integrated into the second process 630 such that the two processes are performed during the same process sequence.

[0050] The method 600 begins at step 612, which involves forming a first dielectric layer over a semiconductor substrate. The first dielectric layer may be the first dielectric layer 212, 312, or 412. Step 612 may be performed by depositing a silicon oxide material or any other suitable dielectric material.

[0051] The method 600 proceeds to step 614, which involves forming an etch stop layer (or landing pad layer) over the first dielectric layer. Figure 3 As shown, the etch stop layer may be a lower metal layer M1 or a SiN layer. Step 614 may be performed by patterning a mask and depositing the etch stop layer into the opening defined by the mask, or alternatively by first depositing the etch stop layer and then patterning and etching it using a photoresist process.

[0052] The method 600 proceeds to step 616, which involves forming a first thin film resistor (TFR) layer above the etch stop layer and the first dielectric layer. A chemical mechanical polishing step may also be performed before the TFR layer is laid down to obtain additional processing uniformity. The first TFR layer may be TFR layers 230, 332, 352, and 430. For example, in one embodiment, step 616 may be performed by physical vapor deposition of a power-pressed sputtering target material, wherein the power-pressed sputtering target material includes a silicon (Si) material, a chromium (Cr) material, a carbon (C) material, and an oxygen material. Thus, the first TFR layer may include a Si (Si) material having an example composition (relative atomic %) of Si. x Cr y C z Ow wherein x and y may be in the range of 5% to 50%, and z and w may be in the range of 0% to 50%. For example, in another embodiment, step 616 may be performed by physical vapor deposition of a power-pressed sputtering target material, the power-pressed sputtering target material comprising a nickel (Ni) material, a chromium (Cr) material, a carbon (C) material, and an oxygen material. Thus, the first TFR layer may include a Ni (Ni) material having an example composition (relative atomic %) of x Cr y C z O w wherein x and y may be in a range of 5% to 50%, and z and w may be in a range of 0% to 50%. For example, in yet another embodiment, step 616 may be performed by depositing a polysilicon material. Thus, the first TFR layer may include a polysilicon layer.

[0053] The method 600 proceeds to step 618, which involves forming a second dielectric layer over the first TFR layer. The second dielectric layer may be dielectric layers 214, 316, and 416. Step 618 may be performed by depositing a silicon oxide material or any other suitable dielectric material. Step 618 may include a chemical mechanical polishing process that makes the top surface of the second dielectric layer uniform, because the underlying first TFR layer may have plateaus during the deposition of the silicon oxide material.

[0054] The method 600 proceeds to a first sequence 620 for forming one or more conductive vias penetrating a single TFR layer formed during steps 612 to 618. The first sequence 620 begins at step 622, which involves etching a first via trench completely through the second dielectric layer and the first TFR layer. Step 622 may be performed by patterning a mask to define an opening aligned with a terminal region (e.g., 232 and / or 234) of the first TFR layer (e.g., 230) and by etching the underlying material through the opening. For example, in one embodiment, step 622 may be performed by reactive ion etching. The etching duration is predetermined so that the via trench is sufficient to completely penetrate the first TFR layer. If and when step 614 is performed prior to step 622, the etching may be delayed and / or slowed by an etch stop layer. In this way, the via trench may reach the etch stop layer without completely penetrating the etch stop layer.

[0055] Then, the first sequence 620 proceeds to step 624, which includes depositing a first barrier layer on the via sidewalls of the first via trench through the first TFR layer. The barrier layer (e.g., 262 and / or 266) may include a titanium layer covered by a titanium nitride layer. For example, Figure 2AAs shown, the barrier layer may also cover the sidewalls of the dielectric layer above and below the TFR layer near the penetration site.

[0056] The first sequence 620 then proceeds to step 626, which involves filling the first via trench with a first conductor coupled to the sidewall of the first TFR layer. The first conductor may include a tungsten material, an aluminum material, and / or other materials having a sufficiently high conductivity to function as a conductive via. If and when step 624 is performed, the first conductor is coupled to the sidewall of the first TFR layer through the barrier layer. Otherwise, the first conductor may establish direct ohmic contact with the sidewall of the TFR layer at or near the penetration site. The first conductor and the via trench together form a conductive via that penetrates the terminal region of the first TFR layer.

[0057] The first sequence 620 can be performed simultaneously at multiple terminal regions of one or more TFR layers of one or more TFR structures. Because the first sequence 620 is insensitive to different via trench depths, it can be used to form multiple conductive vias, each conductive via penetrating a TFR layer having a different depth from other TFR layers.

[0058] The method 600 may be implemented to form conductive vias, each of which may be formed in a single TFR structure (e.g., Figure 4 In this embodiment, the method 600 may skip the first sequence 620 after performing step 618. Then, the method 600 proceeds to step 632, which involves forming a second TFR layer above the second dielectric layer. Figure 4 As shown and described in , the second TFR layer can be TFR layer 450. Step 632 can be performed under substantially the same process parameters as in step 616. For example, in one embodiment, step 632 can be performed by physical vapor deposition of a power-pressed sputtering target material, the power-pressed sputtering target material comprising a silicon (Si) material, a chromium (Cr) material, a carbon (C) material, and an oxygen material. Thus, the second TFR layer can include a Si (Si) material having an example composition (relative atomic %) of Si. x Cr y C z O w wherein x and y may be in the range of 5% to 50%, and z and w may be in the range of 0% to 50%. For example, in another embodiment, step 632 may be performed by physical vapor deposition of a power-pressed sputtering target material, the power-pressed sputtering target material comprising a nickel (Ni) material, a chromium (Cr) material, a carbon (C) material, and an oxygen material having a Ni x Cr y C z O wExample compositions (relative atomic %) of Cr, where x and y may be in the range of 5% to 50%, and z and w may be in the range of 0% to 50%. x O y +Si x O y +Cr x Si y +Si x C y Wherein x is in the range of 0 to 3, and y is in the range of 0 to 3. For example, in yet another embodiment, step 632 may be performed by depositing a polysilicon material. Thus, the second TFR layer may include a polysilicon layer.

[0059] Then, the method 600 proceeds to step 634, which involves forming a third dielectric layer over the second TFR layer. The third dielectric layer may be Figure 4 The dielectric layer 418 shown and described in . Step 634 may be performed by depositing a silicon oxide material or any other suitable dielectric material.

[0060] The method 600 then proceeds to a second sequence 640 for forming one or more conductive vias penetrating the one or more TFR layers, which are formed during steps 612 to 618 and steps 632 to 634. The second sequence 640 begins at step 642, which involves etching a second via completely through the third dielectric layer and the second TFR layer. Figure 4 The via trench of the second through via VBZ shown may be etched through the dielectric layer 418 and the second TFR layer 450. In addition, step 622 from the first sequence 620 may be performed together with step 642 using the same mask. Figure 4 The via trench of the illustrated first through via VAZ may be etched through the dielectric layers 418 and 416 and the first TFR layer 430. A single mask may define openings aligned with the first terminal region 432 of the first TFR layer 230 and with the first terminal region 452 of the second TFR layer 450. The single mask allows a single etch to remove underlying material from the first terminal regions 432 and 452 via these openings. For example, in one embodiment, step 642 may be performed by a reactive ion etching process. The etching duration is predetermined so that the via trench is sufficient to completely penetrate the second TFR layer and the optional first TFR layer. If and when step 614 is performed prior to step 642, the etching may be delayed and / or slowed by an etch stop layer. In this way, the via trench may reach the etch stop layer without completely penetrating the etch stop layer.

[0061] In addition, step 644 may also be performed simultaneously with step 642 and use the same mask as step 642. Step 644 involves etching a third via completely through the third dielectric layer, the second TFR layer, the second dielectric layer, and the first TFR layer. Figure 4 The via trench of the illustrated third through via VCZ may be etched through the dielectric layer 418, the second TFR layer 450, the dielectric layer 416, and the first TFR layer 430. A single mask may define openings aligned with the first terminal region 432 of the first TFR layer 230, the first terminal region 452 of the second TFR layer 450, and the second terminal region 454 of the second TFR layer 450 and the second terminal region 434 of the first TFR layer 430, respectively.

[0062] Advantageously, the single mask method allows a single etch to form multiple via trenches through multiple TFR layers at different depths. The via trenches accommodate different thicknesses of the TFR layers and different thicknesses of the dielectric layers above and below the TFR layers. For example, in one embodiment, step 644 can be performed by a reactive ion etching process. The etching duration is predetermined so that the via trench is sufficient to completely penetrate the second TFR layer and the first TFR layer. If and when step 614 is performed prior to step 644, the etching can be delayed and / or slowed by an etch stop layer. In this way, the via trench can reach the etch stop layer without completely penetrating the etch stop layer.

[0063] Next, the second sequence 640 proceeds to step 646, which involves depositing a second barrier layer on the second and third via sidewalls of the second and third vias through the second TFR layer and the first TFR layer. Step 646 is similar to step 624, so step 646 can be performed after step 644 and together with step 624.

[0064] Finally, the second sequence 640 proceeds to step 648, which involves filling the second and third vias with second and third conductors coupled to the second and third via sidewalls of the second and first TFR layers. Figure 4As shown, a third through-hole via VCZ can be formed by filling a conductive material in a corresponding through-hole trench. The through-hole trench conductor is coupled to the sidewalls of the second TFR layer 450 and the first TFR layer 430 at or near the penetration site. Step 648 is similar to step 626, so if step 646 is omitted, step 648 can be performed after step 644 together with step 626, or if step 646 is performed, step 648 is performed after step 646. The through-hole trench conductor may include tungsten material, aluminum material, and / or other materials with sufficiently high conductivity to be used as conductive vias. If and when step 646 is performed, the conductor is coupled to the sidewall of the corresponding TFR layer through the barrier layer. Otherwise, the conductor may establish direct ohmic contact with the sidewalls of the corresponding (multiple) TFR layer at or near the penetration site. The conductor and the through-hole trench together form a conductive via that penetrates the corresponding terminal region of the corresponding TFR layer.

[0065] Figure 7A-7E It shows that Figure 4 and Figure 5 The cross-sectional view of the device during its manufacturing process is shown. Figure 6 The method 600 shown is slightly different. Specifically, Figure 7A-7E The process shown has integrated the first sequence 620 into the second sequence 640. By this integration, Figure 7A-7E The process shown simplifies the etching process so that a single mask is used to etch all through via trenches.

[0066] Fig. 7A The beginning of the manufacturing process is shown, where steps 612 and 614 of method 600 have been performed. A first dielectric layer 412 is deposited on semiconductor substrate 402. A lower metal layer including M1 metal layers 421, 423 and 425 is formed on the first dielectric layer 412. The lower metal layer can be used as an interconnect layer coupled to the upper metal layer. The lower metal layer can also be used as an etch stop layer or landing pad layer for receiving through vias coupled to one or more TFR layers. A second dielectric layer 414 is deposited on the lower metal layer and then polished by a chemical mechanical polishing process. However, in some embodiments, the polishing process can be omitted.

[0067] The process then proceeds to Figure 7B , wherein step 616 from method 600 is performed. Specifically, the first TFR layer 430 is formed on the second dielectric layer 614. Next, the process proceeds to Figure 7C , wherein steps 618 and 632 are performed in sequence. Specifically, the third dielectric layer 416 is deposited on the first TFR layer 630. After the third dielectric layer 416 is polished by a chemical mechanical polishing process, the second TFR layer 450 is formed on the third dielectric layer 416.

[0068] The process then proceeds to Fig.7D , wherein step 634 of method 600 is first performed. More specifically, fourth dielectric layer 418 is deposited on second TFR layer 450. After fourth dielectric layer 418 is polished by a chemical mechanical polishing process, a single mask 702 is deposited on fourth dielectric layer 418.

[0069] like Fig.7D As shown, steps 622, 642, and 644 of process 600 are performed simultaneously because mask 702 is patterned to have openings aligned with the corresponding terminal regions of the respective TFR layers. Specifically, mask 702 is patterned to have at least: (1) a first opening 712 aligned with the first terminal region 432 of the first TFR layer 430, (2) a second opening 714 aligned with the first terminal region 452 of the second TFR layer 450, and (3) a third opening 716 aligned with the second terminal region 454 of the second TFR layer 450 and the second terminal region 434 of the first TFR layer 430, respectively. During a single etching process, via trenches for through-hole vias VAZ, VBZ, and VCZ can be etched simultaneously through dielectric layers 418, 416, and 414 and through the second TFR layer 450 and the first TFR layer 430. The single etching process can be delayed, slowed, or terminated by the lower metal layers 421, 423, and 425.

[0070] After the single etching process, steps 624 and 646 of method 600 may be performed to deposit a barrier layer onto the sidewalls of the via trenches. Next, steps 626 and 648 of method 600 may be performed to fill the via trenches with a conductive material. At this point, a first through (conductive) via VAZ, a second through (conductive) via VBZ, and a third through (conductive) via VCZ are formed.

[0071] Finally, the process proceeds to Fig. 7E , wherein an upper metal layer including M2 metal layers 422, 424, and 426 is formed on the fourth dielectric layer 418. The M2 metal layers 422, 424, and 426 are each coupled to a corresponding through-via, so that they each serve as an access point for accessing the terminal region of one or more TFR layers. After the upper metal layer is formed, a fifth dielectric layer 419 is deposited on the fourth dielectric layer 418, and then a chemical mechanical polishing process is performed.

[0072] like Figure 7A-7E The manufacturing process shown provides a superior manufacturing Figure 1Several advantages of the device 100 shown. First, the disclosed process employs a single mask approach to form a conductive via for accessing a TFR layer without any resistor heads and the overhead resistance associated therewith. Second, by eliminating the variability of the head resistance, the disclosed process also eliminates the need to match the head resistance between several TFR structures having different depth levels within a semiconductor device. Third, the disclosed process eliminates the additional process step of forming an additional protective hard mask and / or etch stop layer after forming one or more TFR layers. Fourth, by employing a non-selective via etching process, the disclosed process eliminates the need to adjust the via etching so as to form a good ohmic contact between the conductive via and the TFR layer.

[0073] Consistent with the present disclosure, the term "configured to" is intended to describe the structural and functional characteristics of one or more tangible, non-transitory components. For example, the term "configured to" may be understood as having a specific configuration that is designed or dedicated to perform a specific function. In this understanding, if a device includes tangible, non-transitory components that can be enabled, activated, or powered to perform a specific function, then such a device is "configured to" perform that specific function. Although the term "configured to" may include the concept of configurable, the term should not be limited to such a narrow definition. Therefore, when used to describe a device, the term "configured to" does not require that the device being described is configurable at any given point in time.

[0074] In addition, the term "exemplary" is used herein to indicate use as an example, instance, illustration, etc., and is not necessarily advantageous. Moreover, although the present disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will be apparent when reading and understanding this specification and the drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. Specifically, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe these components are intended to correspond to any component that performs the specified function of the component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure. In addition, although specific features of the present disclosure may be disclosed only with respect to one embodiment in several embodiments, such features may be combined with one or more other features of other embodiments, as this may be desirable and advantageous for any given or specific application.

[0075] Furthermore, relative terms such as "about," "approximately," "substantially," "close to," "near," "enough to," "maximum," and "minimum" applied to features of integrated circuits and / or semiconductor devices may be understood as manufacturing tolerances for a particular process used to manufacture the integrated circuits and / or semiconductor devices. Additionally, these relative terms may be understood within the framework of one or more functions performed by the integrated circuits and / or semiconductor devices.

[0076] For example, more specifically, the terms "substantially the same", "substantially equal to", and "approximately the same" are intended to describe a quantitative relationship between two objects. Such a quantitative relationship may preferably refer to two objects being identical in design, but it is expected that a certain amount of variation may be introduced by the manufacturing process. In one aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of a second resistor, wherein the first resistor and the second resistor are claimed to have the same resistance, but the manufacturing process introduces a slight variation between the first resistor and the first resistor. Thus, the first resistor may be substantially equal to the second resistor even if the first resistor and the second resistor are manufactured to exhibit a slight difference in resistance. Such a slight difference may be within 5% of the design target. In another aspect, the first resistor may have a first resistance that is substantially equal to the second resistance of the second resistor, wherein the process variation is known a priori, so that the first resistor and the second resistor may be preset to slightly different values ​​to account for the known process variation. Thus, the first resistor may be substantially equal to the second resistor even when the design values ​​of the first resistor and the second resistor are preset to include a slight difference to account for the known process variation. Such a slight difference may be within 5% of the design target.

[0077] Although this specification contains many details, these details should not be interpreted as limitations on the scope of protection that can be claimed, but as descriptions of features that may be specifically used for specific embodiments. Certain features described in this specification in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although the above features may be described as working in certain combinations and even initially claimed as such, one or more features of the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a sub-combination or a variation of the sub-combination.

[0078] Similarly, although some operations are depicted in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed to achieve the desired results, unless the order is recited in one or more claims. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a thin film resistor layer, i.e., a TFR layer, over the substrate; forming a dielectric layer over the TFR layer; etching a via completely through the dielectric layer and the TFR layer; and The via is filled with a conductor coupled to the sidewalls of the TFR layer.

2. The method according to claim 1, further comprising: forming a metal layer below the TFR layer before forming the TFR layer, The through hole reaches the metal layer without completely penetrating the metal layer.

3. The method according to claim 1, further comprising: forming an etch stop layer under the TFR layer before forming the TFR layer, The through hole reaches the etch stop layer without completely penetrating the etch stop layer.

4. The method according to claim 1, wherein forming the TFR layer comprises: Physical vapor deposition of a target material including a silicon material, a chromium material, and a carbon material is performed.

5. The method according to claim 1, wherein forming the TFR layer comprises: Physical vapor deposition of a target material including a nickel material, a chromium material, a carbon material, and an oxygen material is performed.

6. The method according to claim 1, wherein: The TFR layer includes a first terminal region and a second terminal region spaced apart from the first terminal region; and The through holes include a first through hole that completely passes through the first terminal region and a second through hole that completely passes through the second terminal region.

7. The method according to claim 1, wherein: Forming the TFR layer includes: forming a first TFR layer over the substrate and under the dielectric layer; and forming a second TFR layer over the dielectric layer, the second TFR layer at least partially overlapping and coextensive with the first TFR layer; and Etching the via includes etching the via completely through the second TFR layer, the dielectric layer, and the first TFR layer.

8. A method for manufacturing a semiconductor device, comprising: forming a first thin film resistor layer, i.e., a first TFR layer, over the substrate; forming a first dielectric layer over the first TFR layer; forming a second TFR layer over the first dielectric layer; forming a second dielectric layer over the second TFR layer; forming a first conductive via completely through the first dielectric layer and the second dielectric layer and completely through a first terminal region of the first TFR layer; as well as A second conductive via is formed completely through the second dielectric layer and completely through the second terminal region of the second TFR layer. 9 . The method of claim 8 , wherein the first TFR layer at least partially overlaps and is coextensive with the second TFR layer.

10. The method according to claim 8, further comprising: A third conductive via is formed completely through: the second dielectric layer; a third terminal region of the second TFR layer; the first dielectric layer; and The fourth terminal region of the first TFR layer is aligned with the third terminal region along a vertical direction.

11. The method according to claim 8, further comprising: Before forming the first TFR layer, forming a first metal pad below the first terminal region of the first TFR layer; Before forming the second TFR layer, forming a second metal pad below the second terminal region of the second TFR layer; The first conductive via stops at and contacts the first metal pad, and the second conductive via stops at and contacts the second metal pad.

12. The method according to claim 11, wherein: Forming the first metal pad includes: forming a metal layer before forming the first TFR layer, and patterning the first metal pad from the metal layer; and Forming the second metal pad includes patterning the second metal pad from the metal layer.

13. The method according to claim 8, further comprising: Before forming the first TFR layer, forming a first etch stop layer below the first terminal region of the first TFR layer; and Before forming the second TFR layer, forming a second etch stop layer below the second terminal region of the second TFR layer; in: the first conductive via reaches the first etch stop layer without completely penetrating the first etch stop layer; and The second conductive via reaches the second etch stop layer without completely penetrating the second etch stop layer.

14. A semiconductor device comprising: substrate; a thin film resistor layer, i.e., a TFR layer, over the substrate; a dielectric layer over the TFR layer; as well as A conductive via is passed completely through the dielectric layer and completely through the TFR layer, the conductive via being coupled to a sidewall of the TFR layer.

15. The semiconductor device according to claim 14, wherein: The TFR layer includes: a first terminal area; and a second terminal region spaced apart from the first terminal region; and The conductive via comprises: a first conductive via extending completely through the first terminal region; and A second conductive via completely passes through the second terminal region.

16. The semiconductor device according to claim 14, further comprising: The metal pads below the TFR layer, The conductive via reaches the metal pad without completely penetrating the metal pad.

17. The semiconductor device according to claim 14, further comprising: an etch stop layer below the TFR layer, The conductive via reaches the etch stop layer without completely penetrating the etch stop layer. 18 . The semiconductor device of claim 14 , wherein the TFR layer comprises a silicon-chromium (SiCr) intermetallic mixture.

19. The semiconductor device of claim 14, wherein the TFR layer comprises a nickel-chromium (NiCr) intermetallic mixture.

20. The semiconductor device according to claim 14, wherein: The TFR layer includes: a first TFR layer over the substrate; and a second TFR layer overlying and at least partially overlapping and coextensive with the first TFR layer; The dielectric layer comprises: a first dielectric layer between the first TFR layer and the second TFR layer; and a second dielectric layer over the second TFR layer; The conductive via comprises: a first conductive via that passes completely through the second dielectric layer, the first dielectric layer, and the first TFR layer; a second conductive via that passes completely through the second dielectric layer, the second TFR layer, and the first dielectric layer, the second conductive via being positioned in a different plane relative to the first TFR layer; and A third conductive via completely passes through the second dielectric layer, the second TFR layer, the first dielectric layer, and the first TFR layer.

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