High Signal Voltage Tolerance in a Single-Ended Memory Interface

Abstract

The present disclosure relates to high signal voltage tolerance in a single-ended memory interface. The apparatus includes a line termination circuit and a continuous-time linear equalizer circuit. The line termination circuit can be configured to generate a data signal in response to an input signal. The input signal typically exists in a first voltage domain. The input signal can be single-ended. The data signal can be generated in the first voltage domain. The continuous-time linear equalizer circuit can be configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous-time linear equalizer circuit typically operates in a second voltage domain. The first voltage domain can be higher than the second voltage domain.

Description

Technical Field

[0001] The present invention generally relates to signal receivers, and more particularly to methods and / or apparatuses for achieving high signal voltage tolerance in a single-ended memory interface. Background Art

[0002] Conventional Double Data Rate Fourth Generation (DDR4) interfaces are specified to operate at data rates up to 3.2 gigabits per second. At such high data rates, signal integrity becomes an issue. Continuous Time Linear Equalizer (CTLE) circuits are widely used to compensate for channel insertion loss and return loss. A slicer circuit differentiates the compensated signal. Under various power supply conditions, the CTLE output common mode voltage may become too high for the slicer circuit to properly differentiate. Tests show that the receiver fails at high power supply voltages. Under large input voltage swing conditions, the receiver setup time results in poor timing margin and poor data eye diagram symmetry.

[0003] It would be desirable to achieve high signal voltage tolerance in a single-ended memory interface. Summary of the Invention

[0004] The present invention relates to an apparatus including a line termination circuit and a continuous time linear equalizer circuit. The line termination circuit is configured to generate a data signal in response to an input signal. The input signal exists in a first voltage domain. The input signal is single-ended. The data signal is generated in the first voltage domain. The continuous time linear equalizer circuit is configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous time linear equalizer circuit operates in a second voltage domain. The first voltage domain is higher than the second voltage domain.

[0005] In some embodiments of the apparatus described above, the apparatus includes a double data rate memory module.

[0006] In some embodiments of the apparatus described above, the double data rate memory module includes a Double Data Rate Fourth Generation Dual In-line Memory Module.

[0007] In some embodiments, the apparatus aspect described above further includes a slicer circuit configured to generate an output signal by slicing the intermediate signal. The output signal is generated in a third voltage domain. The second voltage domain is higher than the third voltage domain.

[0008] In some embodiments, the apparatus aspect described above further includes a reference voltage circuit configured to generate a reference voltage in the first voltage domain.

[0009] In some embodiments of the apparatus described above, (i) the line termination circuit includes a plurality of first transistors of a first type, (ii) the continuous-time linear equalizer circuit includes a plurality of second transistors of a second type, and (iii) the first transistors of the first type are slower than the second transistors of the second type.

[0010] In some embodiments of the apparatus described above, the continuous-time linear equalizer circuit is configured to maintain an intermediate signal within a second voltage domain while a common-mode voltage between the data signal and a reference voltage exceeds the second voltage domain.

[0011] In some embodiments of the apparatus described above, (i) the continuous-time linear equalizer circuit includes a first transistor having a first gate receiving a data signal and a second transistor having a second gate receiving a reference voltage, and (ii) each of the first transistor and the second transistor has a bulk node directly connected to a respective source node.

[0012] In some embodiments of the apparatus described above, (i) the continuous-time linear equalizer circuit includes a differential amplifier, and (ii) each side of the differential amplifier includes a transistor configured to conduct and cut off that side.

[0013] In some embodiments of the apparatus described above, the apparatus implements a staging clock driver circuit.

[0014] The present invention also encompasses aspects related to a method for high signal voltage tolerance in a single-ended memory interface, including the steps of: (i) generating a data signal in response to an input signal using a line termination circuit, and (ii) generating an intermediate signal by equalizing the data signal relative to a reference voltage in a continuous-time linear equalizer circuit. The input signal exists in a first voltage domain. The input signal is single-ended. The data signal is generated in the first voltage domain. The continuous-time linear equalizer circuit operates in a second voltage domain. The first voltage domain is higher than the second voltage domain.

[0015] In some embodiments of the above method, the steps are performed in a double data rate memory module.

[0016] In some embodiments of the above method, the double data rate memory module includes a double data rate fourth generation dual in-line memory module.

[0017] In some embodiments, the above method aspect further includes the step of generating an output signal by clipping the intermediate signal. The output signal is generated in a third voltage domain. The second voltage domain is higher than the third voltage domain.

[0018] In some embodiments, the above method aspect further includes the step of generating a reference voltage in the first voltage domain.

[0019] In some embodiments of the above method, (i) the line termination circuit includes a plurality of first transistors of a first type, (ii) the continuous-time linear equalizer circuit includes a plurality of second transistors of a second type, and (iii) the first transistors of the first type are slower than the second transistors of the second type.

[0020] In some embodiments of the above method, the continuous-time linear equalizer circuit is configured to maintain an intermediate signal within a second voltage domain while a common-mode voltage between the data signal and a reference voltage exceeds the second voltage domain.

[0021] In some embodiments, the above method further includes the steps of: (i) receiving a data signal at a first gate of a first transistor of the continuous-time linear equalizer circuit, and (ii) receiving a reference voltage at a second gate of a second transistor of the continuous-time linear equalizer circuit. Each of the first transistor and the second transistor has a bulk node directly connected to a corresponding source node.

[0022] In some embodiments of the above method, (i) the continuous-time linear equalizer circuit includes a differential amplifier, and (ii) each side of the differential amplifier includes a transistor configured to conduct and cut off that side.

[0023] In some embodiments of the above method, the steps are performed in a staging clock driver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present invention will become apparent from the following detailed description, appended claims, and drawings, in which:

[0025] Figure 1 are diagrams of several circuits;

[0026] Figure 2 is a block diagram illustrating a memory module;

[0027] Figure 3 is a block diagram of a receiver portion of a staging clock driver circuit according to an embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of a continuous-time linear equalizer circuit;

[0029] Figure 5 is a schematic diagram of a limiting circuit; and

[0030] Figure 6 is a schematic diagram of a line termination circuit. DETAILED DESCRIPTION

[0031] Embodiments of the present invention include providing high signal voltage tolerance in a single-ended memory interface, which can (i) operate at a high supply voltage, (ii) tolerate a high signal voltage swing, (iii) sequentially reduce the input voltage swing through multiple voltage domains, (iv) provide low latency, (v) provide balanced rise time delay and fall time delay, and / or (vi) be implemented as one or more integrated circuits.

[0032] In various embodiments of the present invention, a continuous-time linear equalizer (CTLE) circuit operating in an intermediate voltage domain can compensate for channel loss and reflection in a multi-drop application, such as a memory interface circuit system. Output signals and input signals generated and received by the memory interface circuit system typically exist in a high voltage domain. A data sampling slicer circuit operating in a low voltage domain can distinguish the compensated input signals created by the CTLE circuit. Compared with existing designs, the CTLE circuit and the slicer circuit can tolerate a higher-than-normal supply voltage application and / or tolerate a higher-than-normal input signal voltage swing. Moreover, the CTLE circuit and the slicer circuit can be implemented using fast core transistors (or devices). As a result, the CTLE circuit generally has a lower latency than common designs, as well as more balanced rise / fall delays. The lower latency and balanced delays can improve the timing margin and the symmetry of the data eye diagram.

[0033] Reference Figure 1 , shows a diagram illustrating several example circuits 50a - 50n. In the example, the circuits 50a - 50n can be implemented as memory modules (or boards). For example, the memory modules 50a - 50n can be implemented as double data rate fourth generation (DDR4) synchronous dynamic random access memory (SDRAM) modules. The memory modules 50a - 50n can include a number of blocks (or circuits) 90a - 90n, a block (or circuit) 100, and / or various other blocks, circuits, pins, connectors, and / or traces. The circuits 90a - 90n can be configured as data buffers. The circuit 100 can be implemented as a registered clock driver (RCD). In the example, the RCD circuit 100 can be implemented as a DDR4 RCD circuit. The type, arrangement, and / or number of components of the memory modules 50a - 50n can be varied to meet the design criteria of a particular implementation.

[0034] Memory modules 50a - 50n are shown connected to block (or circuit) 20. Circuit 20 can be a memory controller. Circuit 20 can be located in another device, such as a computing engine. Various connectors / pins / traces 60 can be implemented to connect memory modules 50a - 50n to memory controller 20. In some embodiments, the connectors / pins / traces 60 can be in a 288 - pin configuration. In an example, memory controller 20 can be a component of a computer motherboard. In another example, memory controller 20 can be a component of a microprocessor. In yet another example, memory controller 20 can be a component of a central processing unit (CPU).

[0035] In an example, some of the connectors / pins / traces 60 can be part of the memory modules 50a - 50n and some of the connectors / pins / traces 60 can be part of the motherboard and / or memory controller 20. Memory modules 50a - 50n can be connected (e.g., by pins, traces, and / or connectors 60) to a computer motherboard to transfer data between components of a computing device and the memory modules 50a - 50n. In an example, memory controller 20 can be implemented on the north bridge of the motherboard and / or as a component of a microprocessor (e.g., Intel CPU, AMD CPU, ARM CPU, etc.). The implementation of memory controller 20 can vary according to the design criteria of a particular implementation.

[0036] In various embodiments, memory modules 50a - 50n can be DDR4 SDRAM memory modules. The DDR4 SDRAM memory modules 50a - 50n can have a memory module density of 512 gigabytes (GB), terabytes, or higher per module (e.g., compared to 128GB per dual - in - line memory module (DIMM) in DDR3). The DDR4 SDRAM memory modules 50a - 50n can operate at a voltage of 1.2 - 1.35 volts (V) with frequencies between 800 - 2133 megahertz (MHz) (e.g., compared to 1.5 - 1.65V with frequencies between 400 - 1067MHz in DDR3). In some embodiments, memory modules 50a - 50n can be implemented as low - voltage DDR4 and operate at 1.05V. For example, compared to DDR3 memory, the DDR4 SDRAM memory modules 50a - 50n can achieve 35% power savings. DDR4 SDRAM can transfer data at speeds of 2.13 - 4.26 gigatransfers per second (GT / s) and higher (e.g., compared to 0.8 - 2.13GT / s in DDR3). The operating parameters of memory modules 50a - 50n can vary according to the design criteria of a particular implementation.

[0037] In the example, the memory modules 50a - 50n may comply with the DDR4 specification JESD79 - 4A, titled "DDR4 SDRAM", released by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association, Arlington, Virginia, November 2013. The entire content of the appropriate sections of the DDR4 specification is incorporated herein by reference.

[0038] The memory modules 50a - 50n may be implemented as DDR4 Load Reduced DIMMs (LRDIMMs) or DDR4 Registered DIMMs (RDIMMs). The data buffers 90a - 90n may allow the memory modules 50a - 50n configured as DDR4 LRDIMMs to operate at a higher bandwidth and / or higher capacity, as compared to DDR4 RDIMMs (e.g., at a 384GB capacity, 1333MT / s for DDR4 LRDIMMs, as compared to 1067MT / s for DDR4 RDIMMs). For example, as compared to a DDR4 RDIMM configuration, the DDR4 LRDIMM configuration of the memory modules 50a - 50n may allow for improved signal integrity with respect to data signals, lower component latency through the data buffers 90a - 90n, and / or better intelligence and / or post - buffering awareness by the memory controller 20.

[0039] Reference Figure 2 , shows a block diagram of an exemplary memory module 50a. The memory module 50a may be representative of the memory modules 50b - 50n. The memory module 50a shown communicates with the memory controller 20. The memory controller 20 is shown as part of a block (or circuit) 10. The circuit 10 may be a motherboard, or other electronic component or computing engine that communicates with the memory module 50a.

[0040] Memory module 50a may include one or more blocks (or circuits) 80a - 80n and / or RCD circuit 100. Circuits 80a - 80n may implement the data path of memory module 50a. For example, data path 80a may include block 82a and / or data buffer 90a. Data paths 80b - 80n may have a similar implementation. Circuits 82a - 82n may each be implemented as a memory channel. Each of memory channels 82a - 82n may include a number of blocks (or circuits) 84a - 84n. Circuits 84a - 84n may be implemented as random access memory (RAM) chips. For example, RAM chips 84a - 84n may implement volatile memory, such as dynamic RAM (DRAM). In some embodiments, RAM chips 84a - 84n may be physically located on both sides (e.g., front and back) of the circuit board of memory modules 50a - 50n. The capacity of the memory on memory module 50a may vary according to the design criteria of a particular implementation.

[0041] Memory controller 20 may generate signals (e.g., CLK) and a number of control signals (e.g., ADDR / CMD). Signal CLK and / or signal ADDR / CMD may be presented to RCD circuit 100. Data bus 30 may be connected between memory controller 20 and data paths 80a - 80n. Memory controller 20 may generate and / or receive data signals (e.g., DQa - DQn) that may be presented to / received from data bus 30. Signals DQa - DQn may be presented to each of data paths 80a - 80n.

[0042] RCD circuit 100 may be configured to communicate with memory controller 20, memory channels 82a - 82n, and / or data buffers 90a - 90n. RCD circuit 100 may decode instructions received from memory controller 20. For example, RCD circuit 100 may receive a register command word (RCW). In another example, RCD circuit 100 may receive a buffer control word (BCW). RCD circuit 100 may be configured to train DRAM chips 84a - 84n, data buffers 90a - 90n, and / or command and address lines among memory controllers 20. For example, RCW may flow from memory controller 20 to RCD circuit 100. RCW may be used to configure RCD circuit 100.

[0043] The RCD circuit 100 can be used in LRDIMM and RDIMM configurations. The RCD circuit 100 can implement a 32-bit 1:2 command / address register. The RCD circuit 100 can support a full-speed bus (e.g., the BCOM bus between the RCD circuit 100 and the data buffers 90a-90n). The RCD circuit 100 can implement automatic impedance calibration. The RCD circuit 100 can implement command / address parity checking. The RCD circuit 100 can control the RCW readback of the register. The RCD circuit 100 can implement a 1 MHz internal integrated circuit (I2C) bus (e.g., a serial bus). The input to the RCD circuit 100 can be pseudo-differential using external and / or internal voltages. The clock output, command / address output, control output, and / or data buffer control output of the RCD circuit 100 can be grouped and enabled and independently driven with different strengths.

[0044] The RCD circuit 100 can receive the signal CLK and / or the signal ADDR / CMD from the memory controller 20. Various digital logic components of the RCD circuit 100 can be used to generate signals based on the signal CLK and / or the signal ADDR / CMD and / or other signals (e.g., RCW). The RCD circuit 100 can also be configured to generate a signal (e.g., CLK’) and a signal (e.g., ADDR’ / CMD’). For example, the signal CLK’ can be the signal Y_CLK in the DDR4 specification. The signal CLK’ and / or the signal ADDR’ / CMD’ can be presented to each of the memory channels 82a-82n. For example, the signal CLK’ and / or ADDR’ / CMD’ can be transmitted on the common bus 54. The RCD circuit 100 can generate one or more signals (e.g., DBC). The signal DBC can be presented to the data buffers 90a-90n. The signal DBC can be transmitted on the common bus 56 (e.g., the data buffer control bus).

[0045] The data buffers 90a-90n can be configured to receive data from the bus 56. The data buffers 90a-90n can be configured to generate data to the bus 30 / receive data from the bus 30. The bus 30 can include traces, pins, and / or connections between the memory controller 20 and the data buffers 90a-90n. The bus 58 can carry data between the data buffers 90a-90n and the memory channels 82a-82n. The data buffers 90a-90n can be configured to buffer the data on the buses 30 and 58 for write operations (e.g., data transfer from the memory controller 20 to the corresponding memory channels 82a-82n). The data buffers 90a-90n can be configured to buffer the data on the buses 30 and 58 for read operations (e.g., data transfer from the corresponding memory channels 82a-82n to the memory controller 20).

[0046] The data buffers 90a - 90n can exchange data with the DRAM chips 84a - 84n in small units (e.g., 4 - bit nibbles). In various embodiments, the DRAM chips 84a - 84n can be arranged in multiple (e.g., two) sets. For a two - set / two - DRAM - chip 84a - 84b implementation, each set can contain a single DRAM chip 84a - 84n. Each DRAM chip 84A - 84b can be connected to its respective data buffer 90a - 90n via a high - order nibble and a low - order nibble. For a two - set / four - DRAM - chip 84a - 84d implementation, each set can contain two DRAM chips 84a - 84d. One set can be connected to its respective data buffer 90a - 90n via a high - order nibble. The other set can be connected to its respective data buffer 90a - 90n via a low - order nibble. For a two - set / eight - DRAM - chip 84a - 84h implementation, each set can contain four of the DRAM chips 84a - 84h. Four DRAM chips 84a - 84d of one set can be connected to its respective data buffer 90a - 90n via a high - order nibble. Four DRAM chips 84e - 84h of the other set can be connected to its respective data buffer 90a - 90n via a low - order nibble. Other numbers of sets, other numbers of DRAM chips, and other data unit sizes can be implemented to meet the design criteria of a particular implementation.

[0047] The DDR4 LR - DIMM configuration can reduce many data loads to reduce the signal integrity on the data bus of the memory module (e.g., bus 30) from a maximum of several (e.g., four) data loads to a single data load. Compared with the DDR3 LR - DIMM design that uses a centralized memory buffer, the distributed data buffers 90a - 90n can allow the DDR4 LR - DIMM design to achieve a shorter I / O trace length. For example, shorter stubs connected to the memory channels 82a - 82n can result in fewer significant signal reflections (e.g., improved signal integrity). In another example, the shorter trace can result in a reduction in latency (e.g., approximately 1.2 nanoseconds (ns), 50% less latency than DDR3 buffer memory). In yet another example, the shorter trace can reduce the I / O bus turnaround time. For example, without using the distributed data buffers 90a - 90n (e.g., in DDR3 memory applications), the trace would be routed to a centralized memory buffer, increasing the trace length by up to six inches compared to the Figure 2 DDR4 LR - DIMM implementation shown.

[0048] In some embodiments, a DDR4 LR-DIMM configuration can implement nine of the data buffers 90a - 90n. The memory modules 50a - 50n can implement 2 millimeter (mm) front side bus traces and back side traces (e.g., connectors / pins / traces 60). The propagation delay through the data buffers 90a - 90n can be 33% faster than through a DDR3 memory buffer (e.g., resulting in reduced latency). In some embodiments, the data buffers 90a - 90n can be smaller than the data buffers used for DDR3 applications (e.g., reduced area parameter).

[0049] Reference Figure 3 , a block diagram showing an example implementation of a receiver portion of an RCD circuit 100 in accordance with an embodiment of the present invention. The receiver portion generally includes a limiter block (or circuit) 102, a CTLE block (or circuit) 104, a reference voltage generator block (or circuit) 106, and a line termination block (or circuit) 108. The circuits 102 through 108 can be implemented as one or more integrated circuits.

[0050] The circuits 104, 106, and 108 can receive a supply voltage (e.g., VDDA) that defines an input / output (or high) voltage domain (e.g., Vdda). The CTLE circuit 104 can receive another supply voltage (e.g., VDDB) that defines an intermediate (or medium) voltage domain (e.g., Vddb). The limiter circuit 102 can receive yet another supply voltage (e.g., VDDC) that defines a core (or low) voltage domain (e.g., Vddc). The core supply voltage VDDC can have a relatively fixed voltage. In various embodiments, all of the voltage domains Vdda, Vddb, and Vddc can share a common ground. The input / output voltage domain Vdda can have an upper voltage that is higher relative to the common ground than the intermediate voltage domain Vddb (e.g., Vdda > Vddb). The intermediate voltage domain Vddb generally has an upper voltage that is higher relative to the common ground than the core voltage domain Vddc (e.g., Vddb > Vddc).

[0051] A signal (e.g., IN) can be received by the line termination circuit 108. In various embodiments, the signal IN can represent any of a command in the signal CMD, an address in the signal ADDR, and / or other information transmitted from the memory controller 20 to the RCD circuit 100. The signal IN can be a single-ended signal present in the input / output voltage domain Vdda. A signal (e.g., DATA) can be generated by the line termination circuit 108 and transmitted to the CTLE circuit 104. The signal DATA can be a variation of the signal IN. The signal DATA can be generated in the input / output voltage domain Vdda. A signal (e.g., VREF) can be generated by the reference voltage generator circuit 106 and received by the CTLE circuit 104. The signal VREF can implement a reference voltage generated in the input / output voltage domain Vdda. Differential signals (e.g., EQOP and EQON) can be generated by the CTLE circuit 104 and received by the limiting circuit 102. The differential signals EQOP / EQON can implement an equalized version of the signal DATA. The differential signals EQOP / EQON can be present in the intermediate voltage domain Vddb. Differential signals (e.g., QP and QN) can be generated and presented by the limiting circuit 102. The differential signals QP / QN can implement the received data signal. The differential signals QP / QN can be present in the core voltage domain Vddc. The combination of the signal QP and the signal QN can be referred to as an output signal (e.g., OUT). The clock signal CLK can be received by the limiting circuit 102.

[0052] The limiting circuit 102 can operate to convert the differential signals EQOP / EQON into the signal OUT. The limiting circuit 102 can sample the differential signals EQOP / EQON at each positive edge (or each negative edge) of the signal CLK. The signal OUT can carry a shaped version of the information received in the differential signals EQOP / EQON. Shaping generally preserves the level portion of the information that represents the nominal value of the information in the intervals between successive transitions. The limiting circuit 102 can be implemented with core transistors (e.g., NMOS transistors) as input devices to achieve a small clock-to-data output (ck-q) delay. The voltage levels in the differential signals EQOP / EQON generated by the CTLE circuit 104 generally do not exceed the maximum operating voltage of the core transistors in the limiting circuit 102.

[0053] The CTLE circuit 104 can be configured to increase the data eye height and improve the shmoo results regarding the width of the information in the signal DATA. Although the information in the signal DATA and the reference voltage signal VREF comes from the input / output input / output voltage domain Vdda, the CTLE circuit 104 is typically placed below the intermediate voltage domain Vddb. The input circuitry of the CTLE circuit 104 is typically designed to tolerate the possible high voltage swings of the signal DATA. The CTLE circuit 104 can be implemented using relatively small and relatively fast core transistors used in the core voltage domain Vddc. From a system perspective, the receiver data sample preparation time can mainly correspond to the latency through the CTLE circuit 104. By using relatively fast core transistors with higher current in the CTLE circuit 104, the data preparation time (e.g., tSU) can be reduced and more balance can be achieved between the data high-to-low preparation time (e.g., tSU_HL) and the data low-to-high preparation time (e.g., tSU_LH). Due to the timing criteria, the relatively fast core transistors powered by the lower core voltage domain Vddc can be used in the limiting circuit 102. The CTLE circuit 104 is typically configured to create an appropriate voltage swing in the differential signals EQOP / EQON for the limiting circuit 102.

[0054] The reference voltage generator circuit 106 can operate to provide a fixed reference voltage in the signal VREF to multiple (e.g., up to 33) replicas of the CTLE circuit 104. In some embodiments, the signal VREF can be generated as a fraction (e.g., half) of the input / output input / output voltage domain Vdda. The fraction can be implemented using a resistor divider network. Other reference voltages can be generated to meet the design criteria of a particular implementation. In various embodiments, multiple instantiations of the reference voltage generator circuit 106 can be implemented based on the number of CTLE circuits 104 consuming the signal VREF.

[0055] The line termination circuit 108 can implement an input bus termination buffer for each input signal IN. The line termination circuit 108 can be implemented as a resistor divider, having an effective impedance of several hundred (e.g., 200) ohms to the input / output power supply voltage VDDA and several hundred (e.g., 200 ohms) to ground (e.g., VSS) for termination of the signal IN. Compared with the core transistors used in the intermediate voltage domain Vddb and the core voltage domain Vddc, the line termination circuit 108 can use relatively slow input / output transistors for the input / output voltage domain Vdda.

[0056] Core devices (e.g., transistors) can be used in the limiting circuit 102 to achieve timing benefits without overvoltage reliability risks. In the illustrated structure, the CTLE output common-mode voltage of the differential signal EQOP / EQON typically follows the intermediate supply voltage VDDB that powers the CTLE circuit 104. Thus, the CTLE output common-mode voltage can be insensitive to variations in the input / output supply voltage VDDA, regardless of how wide the operating range of the input / output supply voltage VDDA may be.

[0057] Reference Figure 4 , a schematic diagram showing an example implementation of the CTLE circuit 104. The CTLE circuit 104 typically includes a plurality of transistors M0 to M6, a plurality of resistors R1, R2, and RS, a capacitor CS, and a current source IA.

[0058] The signal DATA can be received at the gate node of the transistor M1. The signal VREF can be received at the gate node of the transistor M2. A power-down (or power control) signal (e.g., PD_B) can be received at the gate nodes of the transistors M5 and M6 from the logic within the RCD circuit 100. The load resistors R1 and R2 can receive the intermediate supply voltage VDDB. The current source IA can receive the input / output supply voltage VDDA.

[0059] The transistors M1 and M2 are typically arranged as an amplifier having parallel paths (or sides). The load resistors R1 and R2 can be connected to the intermediate supply voltage VDDB, to the transistors M1 and M2 respectively. The capacitor CS and the resistor RS can be connected in parallel between the source nodes of the transistors M1 and M2 to set the filter frequency characteristics of the CTLE circuit 104. In various embodiments, the filter characteristics can cause the CTLE circuit 104 to function as a negative impedance converter.

[0060] The transistors M5 and M6 can be in series with the transistors M1 and M2 on the rejection side of the amplifier. The power-down signal PD_B can be used to turn the amplifier on and off. When the power-down signal PD_B is active (e.g., high voltage or logic one state), the transistors M5 and M6 can conduct, the amplifier can be turned on, and the differential signal EQOP / EQON can respond to the signal DATA with respect to the reference voltage signal VREF. When the power-down signal PD_B is inactive (e.g., low voltage or logic zero state), the transistors M5 and M6 can be non-conducting, the amplifier can be turned off, and the individual signals EQOP and EQON can be pulled to the intermediate supply voltage VDDB by the load resistors R1 and R2.

[0061] Transistors M3 and M4 can be connected in series with transistors M5 and M6 on respective sides of the amplifier. Transistors M3 and M4 can operate as current sources. The biasing of the gate nodes of transistors M3 and M4 can be controlled by current source IA and transistor M0. The current generated by current source IA can be insensitive to power supply fluctuations and thus the input / output supply voltage VDDA is used.

[0062] In an example, the equalization performed by CTLE circuit 104 can boost high-frequency components of differential signal EQOP / EQON relative to lower-frequency components. A certain amount of crosstalk (e.g., noise) between signal EQOP and signal EQON can place a certain limit on the amount of boosting that can be applied. CTLE circuit 104 can increase the amount of the amplitude of differential signal EQOP / EQON. The amplitude can be increased without an increase in the amount of crosstalk and / or reflections (e.g., noise).

[0063] From a system perspective, the latency of CTLE circuit 104 can be regarded as the data setup time tSU before the flip of signal CLK. Common CTLE designs typically show that the setup time tSU_HL for a data high-to-low transition can be much larger than the setup time tSU_LH for a data low-to-high transition, especially for large input voltage swings.

[0064] When signal DATA transitions from a high voltage to a low voltage, the corresponding input transistor M1 should be turned off (e.g., non-conducting), and the opposite input transistor M2 should be turned on (e.g., conducting) for a short amount of time. However, the reference voltage signal VREF can be default-fixed at 0.5×VDDA volts. Thus, the source node voltage of transistor M2 can take time to stabilize below (0.5×VDDA)-Vth volts, and transistor M2 is fully conducting, where Vth is the threshold voltage of the transistor. Since the stabilization time is typically limited by the input transistor threshold voltage, input transistor pair M1 and M2 can be implemented using relatively fast core transistors, and the tail current flowing through transistor pair M3 and M4 can be a relatively large current. Thus, the input transistor gate-to-source voltage can be increased and thus the tSU_HL / tSU_LH balance can be improved. Also, the size of the core transistors can be smaller than the size of the input / output transistors, resulting in smaller parasitic capacitances and shorter setup time tSU.

[0065] Since signal DATA can exist in the input / output voltage domain Vdda, the core should be protected from overvoltage risks. Each core transistor in input transistor pair M1 and M2 can have a device bulk node connected to the respective source node. Power-down transistors M5 and M6 can be inserted between input transistors M1 and M2 and tail current transistors M3 and M4. Thus, all core transistors can be protected from overvoltage risks regardless of whether CTLE circuit 104 is on or off.

[0066] Reference Figure 5 , a schematic diagram showing an example implementation of the limiting circuit 102. The limiting circuit 102 generally includes a plurality of transistors M7 to M17 and a plurality of inverter gates (or circuits) INVA to INVD.

[0067] The limiting circuit 102 generally receives the differential signals EQOP / EQON from the CTLE circuit 104. The signal OUT can be generated by the limiting circuit 102 as the differential signals QP / QN.

[0068] In various embodiments, the transistors M9, M10, M11, M13, M15, and M17 can be implemented as NMOS transistors. The transistors M7, M8, M14, and M16 can be implemented as PMOS transistors. Other transistor types can be implemented to meet the design criteria of specific applications. Two of the inverter circuits (INVA and INVB) can invert the signals generated at the drain nodes of the transistors M9 and M10 to present the signals to the gate nodes of the transistors M5 and M17, respectively. The other two inverter circuits (INVC and INVD) can be arranged as a latch.

[0069] The transistors M7 to M12 can be arranged as a differential amplifier. The signal EQOP can be received at the gate node of the transistor M11. The signal EQON can be received at the gate node of the transistor M12.

[0070] The source nodes of the transistors M11 and M12 can be connected to the drain node of the transistor M13. The gate node of the transistor M13 can receive the signal CLK. The source node of the transistor M13 can be connected to the signal ground.

[0071] The gate nodes of the transistors M9 and M10 can be cross-coupled to the opposite source nodes. The gate nodes of the transistors M7 and M8 can be cross-coupled to the opposite source nodes. The drains of the transistors M9 and M1 can be connected to the respective source nodes of the transistors M7 and M8. The drains of the transistors M7 and M8 can be connected to the core power supply node VDDC.

[0072] The gate node of transistor M14 can be connected to the drain node of transistor M10. The gate node of transistor M15 can be connected to the output node of inverter circuit INVA. The input node of inverter circuit INVA can be connected to the drain node of transistor M9. Transistors M14 and M15 can be configured to pull up or pull down the ends of the latch respectively, which generates signal QN. The gate node of transistor M16 can be connected to the drain node of transistor M9. The gate node of transistor M17 can be connected to the output node of inverter circuit INVB. The input node of inverter circuit INVB can be connected to the drain node of transistor M10. Transistors M16 and M17 can be configured to pull up and pull down the other end of the latch respectively, which generates signal QP.

[0073] Reference Figure 6 , a schematic diagram showing an example implementation of the line termination circuit 108. The line termination circuit 108 generally includes a plurality of resistors RA to RC, a plurality of diodes DA and DB, and a plurality of transistors M18 and M19.

[0074] Resistor RA and transistor M18 can be connected in series between the input / output supply voltage VDDA and the center node. Resistor RB and transistor M19 can be connected in series between ground and the center node. Resistor RA and transistor M18 can provide an effective impedance of several hundred (e.g., 200) ohms to the input / output supply voltage VDDA. Resistor RB and transistor M19 can provide several hundred (e.g., 200 ohms) to ground for terminating signal IN.

[0075] Resistor RC and diodes DA and DB can be configured as a clamping circuit for signal DATA. Diode DA can prevent the voltage of signal DATA from exceeding the high rail diode threshold voltage of the input / output supply voltage VDDA. Diode DB can prevent the voltage of signal DATA from dropping more than the diode threshold voltage below signal ground.

[0076] When implemented in a prototype silicon device, embodiments of the present invention have shown improved performance. Tests using automatic test equipment generally show no failures until the input / output supply voltage VDDA is large (e.g., >2 volts), as compared to failures occurring at 1.6 volts for common devices. Compared to common designs, the difference between high to low setup time and low to high setup time in the present invention is generally smaller and more balanced.

[0077] Although Figure 3The CTLE circuit 104 is shown in the context of the RCD circuit 100 when receiving information, but a copy of the CTLE circuit 104 can be implemented at other locations, other data paths, and / or other control paths. In some embodiments, a copy of the CTLE circuit 104 can be located in the data buffer circuits 90a - 90n to improve the signals received from the memory controller 20 during a write cycle. In various embodiments, a copy of the CTLE circuit 104 can be located at the other end of the data bus 30 to improve the various signals generated by the memory modules 50a - 50n and received by the memory controller 20. For example, the memory controller 20 can include a copy of the CTLE circuit 104 to equalize the read data transmitted from the memory modules 50a - 50n in the signals DQa - DQn during a read cycle. Instances of the CTLE circuit 104 can also be implemented in other circuitry within the memory modules 50a - 50n.

[0078] Although embodiments of the present invention have been described in the context of DDR4 applications, the present invention is not limited to DDR4 applications, but can equally be applied in other high data rate digital communication applications, where there can be different transmission line effects, cross - coupling effects, traveling wave distortion, phase changes, impedance mismatches, and / or line imbalances. The present invention addresses problems related to high - speed communication, flexible clock structures, specified command sets, and lossy transmission lines. Future generations of DDR are expected to provide increased speed, more flexibility, additional commands, and different propagation characteristics. The present invention can also be applied to memory systems implemented in accordance with existing (legacy) memory specifications or future memory specifications.

[0079] As will be apparent to those of ordinary skill in the relevant art, one or more designs, simulations, emulations, and / or emulations of conventional general - purpose processors, digital computers, microprocessors, microcontrollers, distributed computer resources, and / or similar computing machines programmed according to the teachings of this specification can be used to Figures 1 to 6 illustrate the functions and structures illustrated in the figures of. As will also be apparent to those of ordinary skill in the relevant art, appropriate software, firmware, coding, routines, instructions, opcodes, microcode, and / or program modules can be readily prepared by an ordinary programmer in the art based on the teachings of this disclosure. Software is typically implemented on one medium or several media, such as non - transitory storage media, and can be executed by one or more of the processors sequentially or in parallel.

[0080] Embodiments of the present invention may also be implemented in one or more of an ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), CPLD (Complex Programmable Logic Device), sea-of-gates, ASSP (Application Specific Standard Product), and integrated circuits. The circuit system may be implemented based on one or more hardware description languages. Embodiments of the present invention may be used in conjunction with flash memory, non-volatile memory, random access memory, read-only memory, magnetic disks, floppy disks, optical disks such as DVDs and DVD RAMs, magneto-optical disks, and / or distributed storage systems.

[0081] When used herein in conjunction with the word "is" and a verb, the terms "may" and "generally" are meant to convey the intention that the description is exemplary and that it is believed that the description is broad enough to cover both the specific examples shown in the present disclosure and alternative examples that may be derived based on the disclosure. As used herein, the terms "may" and "generally" should not be construed as necessarily implying an expectation or likelihood of omitting the corresponding element.

[0082] Although the present invention has been particularly shown and described with reference to its embodiments, those of ordinary skill in the art should understand that various changes in form and detail may be made without departing from the scope of the present invention.

Claims

1. An apparatus for achieving high signal voltage tolerance, comprising: A line termination circuit configured to generate a data signal in response to an input signal, wherein (i) the input signal exists in a first voltage domain, (ii) the input signal is single-ended, and (iii) the data signal is generated in the first voltage domain; and A continuous-time linear equalizer circuit configured to generate an intermediate signal by equalizing the data signal with respect to a reference voltage, wherein (i) the continuous-time linear equalizer circuit operates in a second voltage domain, and (ii) the first voltage domain is higher than the second voltage domain.

2. The apparatus according to claim 1, wherein the apparatus includes a double data rate memory module.

3. The apparatus according to claim 2, wherein the double data rate memory module includes a double data rate fourth generation dual in-line memory module.

4. The apparatus according to claim 1, further comprising a limiting circuit configured to generate an output signal by limiting the intermediate signal, wherein (i) the output signal is generated in a third voltage domain, and (ii) the second voltage domain is higher than the third voltage domain.

5. The apparatus according to claim 1, further comprising a reference voltage circuit configured to generate the reference voltage in the first voltage domain.

6. The apparatus according to claim 1, wherein (i) the line termination circuit includes a plurality of first transistors of a first type, (ii) the continuous-time linear equalizer circuit includes a plurality of second transistors of a second type, and (iii) the first transistors of the first type are slower than the second transistors of the second type.

7. The apparatus according to claim 1, wherein the continuous-time linear equalizer circuit is configured to maintain the intermediate signal within the second voltage domain while a common-mode voltage between the data signal and the reference voltage exceeds the second voltage domain.

8. The apparatus according to claim 1, wherein (i) the continuous-time linear equalizer circuit includes a first transistor having a first gate receiving the data signal and a second transistor having a second gate receiving the reference voltage, and (ii) each of the first transistor and the second transistor has a bulk node directly connected to a corresponding source node.

9. The apparatus according to claim 1, wherein (i) the continuous-time linear equalizer circuit includes a differential amplifier, and (ii) each of an input side and an output side of the differential amplifier includes a transistor configured to conduct and cut off that side.

10. The apparatus according to claim 1, wherein the apparatus implements a staging clock driver circuit.

11. A method for high signal voltage tolerance in a single-ended memory interface, comprising the steps of: Using a line termination circuit to generate a data signal in response to an input signal, wherein (i) the input signal exists in a first voltage domain, (ii) the input signal is single-ended, and (iii) the data signal is generated in the first voltage domain; and An intermediate signal is generated by equalizing the data signal relative to a reference voltage in a continuous-time linear equalizer circuit, where (i) the continuous-time linear equalizer circuit operates in a second voltage domain, and (ii) the first voltage domain is higher than the second voltage domain.

12. The method according to claim 11, wherein the steps are performed in a double data rate memory module.

13. The method according to claim 12, wherein the double data rate memory module includes a double data rate fourth generation dual in-line memory module.

14. The method according to claim 11, further comprising the step of: generating an output signal by clipping the intermediate signal, where (i) the output signal is generated in a third voltage domain, and (ii) the second voltage domain is higher than the third voltage domain.

15. The method according to claim 11, further comprising the step of: generating the reference voltage in the first voltage domain.

16. The method according to claim 11, wherein (i) the line termination circuit includes a plurality of first transistors of a first type, and (ii) the continuous-time linear equalizer circuit includes a plurality of second transistors of a second type, and (iii) the first transistors of the first type are slower than the second transistors of the second type.

17. The method according to claim 11, wherein the continuous-time linear equalizer circuit is configured to maintain the intermediate signal within the second voltage domain while a common-mode voltage between the data signal and the reference voltage exceeds the second voltage domain.

18. The method according to claim 11, further comprising the step of: receiving the data signal at a first gate of a first transistor of the continuous-time linear equalizer circuit; and receiving the reference voltage at a second gate of a second transistor of the continuous-time linear equalizer circuit, where each of the first transistor and the second transistor has a bulk node directly connected to a respective source node.

19. The method according to claim 11, wherein (i) the continuous-time linear equalizer circuit includes a differential amplifier, and (ii) each of an input side and an output side of the differential amplifier includes a transistor configured to conduct and cut off that side.

20. The method according to claim 11, wherein the steps are performed in a staging clock driver circuit.

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