Integrated circuit including load standard unit and design method thereof

Abstract

In order to design an integrated circuit, input data defining the integrated circuit is received, and a plurality of load standard cells with different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library, and output data defining the integrated circuit is generated based on the results of the placement and routing. By designing an integrated circuit with delay matching and duty cycle adjustment using load standard cells, the design efficiency and performance of the integrated circuit are improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2017-0179484 filed on December 26, 2017 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate generally to semiconductor integrated circuits, and more particularly to an integrated circuit including a signal loading unit and a method of designing the integrated circuit. Background Art

[0004] Standard cells with fixed functions can be used in the design of integrated circuits. Standard cells have a predetermined architecture and are stored in a cell library. When designing an integrated circuit, standard cells are obtained from the cell library and placed at the desired location on the integrated circuit layout. Then wiring is performed to connect standard cells to each other and to other cells. Standard cells have a predetermined (or set) architecture, which may include cell width, cell height, conductive track width, location and number of pin points, etc. The design efficiency of the integrated circuit can be determined based on the configuration of the standard cells. Summary of the invention

[0005] Some example embodiments may provide an integrated circuit having an effective signal delay and a method of designing the integrated circuit.

[0006] According to some example embodiments, a method of designing an integrated circuit includes: receiving input data defining the integrated circuit; providing a plurality of load standard cells having different delay characteristics in a standard cell library; performing placement and routing based on the input data and the standard cell library; and generating output data defining the integrated circuit based on a result of the placement and routing.

[0007] According to some example embodiments, an integrated circuit includes: a logic standard cell including a delay node requiring a delay; and a load standard cell including a load node connected to the delay node to provide the required delay.

[0008] According to some example embodiments, an integrated circuit includes: a first logic standard cell including a first delay node; a second logic standard cell including a second delay node; a first load standard cell including a first load node providing a first delay, the first load node being connected to the first delay node; and a second load standard cell including a second load node providing a second delay different from the first delay, the second load node being connected to the second delay node.

[0009] An integrated circuit and a method of designing an integrated circuit according to some example embodiments may improve design efficiency and performance of an integrated circuit by designing an integrated circuit with delay matching and duty cycle adjustment using a load standard cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a diagram illustrating a method of designing and manufacturing an integrated circuit according to some example embodiments.

[0012] Figure 2 is a block diagram illustrating a design system for an integrated circuit according to some example embodiments.

[0013] Figure 3 It shows Figure 2 A flowchart of an example operation of the design system.

[0014] Figure 4 is a diagram illustrating a layout of an integrated circuit according to some example embodiments.

[0015] Figure 5 is a diagram showing the layout of an example standard cell.

[0016] Fig. 6A , Figure 6B and Figure 6C It is possible to Figure 5 A cross-sectional view of a standard cell having the same layout.

[0017] Figure 7 is a block diagram illustrating an example integrated circuit.

[0018] Figure 8 It shows Figure 7 A timing diagram of the operation of the integrated circuit.

[0019] Fig. 9 is a diagram illustrating an integrated circuit according to some example embodiments.

[0020] Fig.10 It shows Fig. 9 A timing diagram of the operation of the integrated circuit.

[0021] Fig.11 is a diagram for describing delay matching and duty cycle adjustment in an integrated circuit according to some example embodiments.

[0022] FIG. 12A to FIG. 16B is a diagram illustrating a load standard unit according to some example embodiments.

[0023] Fig.17is a block diagram illustrating an integrated circuit according to some example embodiments.

[0024] Fig.18A and Fig.18B It shows Fig.17 A timing diagram of the operation of the integrated circuit.

[0025] Fig.19 is a block diagram illustrating an integrated circuit according to some example embodiments.

[0026] Fig. 20 is a block diagram illustrating a mobile device according to some example embodiments. DETAILED DESCRIPTION

[0027] Various example embodiments will be described more fully below with reference to the accompanying drawings, in which some example embodiments are shown. In the accompanying drawings, the same reference numerals always represent the same elements. Repeated descriptions may be omitted.

[0028] Figure 1 is a diagram illustrating a method of designing and manufacturing an integrated circuit according to some example embodiments.

[0029] Figure 1 The method may include a method of designing a layout of an integrated circuit, the method being performed by a design tool. In some example embodiments, the design tool may include programming software including a plurality of instructions executable by a processor, i.e., software implemented in some form of hardware (e.g., a processor, an ASIC, etc.).

[0030] refer to Figure 1 , input data defining an integrated circuit may be received (S100). For example, the integrated circuit may be defined by a plurality of cells, and a cell library including information of the plurality of cells may be used to design the integrated circuit. Hereinafter, the cell may be a standard cell, and the cell library may be a standard cell library.

[0031] In some example embodiments, the input data may be data generated according to an abstract form of behavior of the integrated circuit. For example, the input data may be defined in a register transfer level (RTL) by synthesis using a standard cell library. For example, the input data may be a bitstream and / or a netlist generated by synthesizing an integrated circuit defined by a hardware description language (HDL) (e.g., VHSIC hardware description language (VHDL) or Verilog).

[0032] In some example embodiments, the input data may be data for defining a layout of an integrated circuit. For example, the input data may include geometric information for defining structures implemented as semiconductor materials, metals, and insulators. For example, the layout of the integrated circuit indicated by the input data may have a layout of cells and wires for connecting the cells to other cells.

[0033] A plurality of load standard cells having different delay characteristics are provided in a standard cell library (S200). The plurality of load standard cells may be a part of the standard cells included in the standard cell library.

[0034] The term "standard cell" may refer to an integrated circuit unit whose layout size meets a preset or specified rule. The standard cell may include an input pin and an output pin, and may process a signal received through the input pin to output the signal through the output pin. For example, a standard cell may be a basic cell (such as an AND logic gate, an OR logic gate, an NOR logic gate, or an inverter), a composite cell (such as an OR / AND / Inverter (OAI) or an AND / OR / Inverter (AOI)), and a storage element (such as a master-slave flip flop or a latch). The term "load standard cell" may refer to a unit of an integrated circuit, which includes one or more capacitors or is composed of one or more capacitors, the first node of each capacitor being connected to (e.g., directly connected to) the standard cell, and the second node being connected to (e.g., directly connected to) a power supply.

[0035] The load standard cell may include only one input-output pin corresponding to the load node. According to some example embodiments, a plurality of capacitors with different capacitance values ​​may be provided as a plurality of load standard cells with different delay characteristics. FIG. 12A to FIG. 16B Some example embodiments of load standard cells are described.

[0036] The standard cell library may include information about a plurality of standard cells. For example, the standard cell library may include the name and function of the standard cell, as well as timing information, power information, and layout information of the standard cell. The standard cell library may be stored in a storage device, and the standard cell library may be provided by accessing the storage device.

[0037] Placement and routing are performed based on input data and a standard cell library (S300), and output data defining an integrated circuit is provided based on the results of the placement and routing (S400). The integrated circuit may be produced (eg, fabricated) using one or more photomasks generated based on the output data (S500).

[0038] In some example embodiments, when the received input data is data such as a bitstream or a netlist generated by synthesizing an integrated circuit, the output data may be a bitstream or a netlist. In other example embodiments, when the received input data is data defining a layout of an integrated circuit (e.g., data in a Graphic Data System II (GDSII) format), the format of the output data may also be data defining a layout of an integrated circuit.

[0039] Therefore, by designing an integrated circuit with delay matching and duty cycle adjustment using load standard cells, a method of designing an integrated circuit according to some example embodiments and an integrated circuit involved by the method may improve design efficiency and performance of the integrated circuit.

[0040] Figure 2 is a block diagram illustrating a design system for an integrated circuit according to some example embodiments.

[0041] refer to Figure 2 , the design system 1000 may include a storage medium 1100 , a design module 1400 , and a processor 1500 .

[0042] The storage medium 1100 (e.g., a storage device) may store a standard cell library SCLB 1110. The standard cell library 1110 may be provided to the design module 1400 from the storage medium 1100. The standard cell library 1110 may include a plurality of standard cells. These standard cells may include a plurality of load standard cells having different delay characteristics. The standard cell may be a small (e.g., minimum) unit for designing a block, a device, and / or a chip.

[0043] The storage medium 1100 may include any computer-readable storage medium for providing commands and / or data to a computer. For example, the computer-readable storage medium 1100 may include volatile memory (such as random access memory (RAM), read-only memory (ROM), etc.) and non-volatile memory (such as flash memory, magnetoresistive RAM (MRAM), phase change RAM (PRAM), resistive RAM (RRAM), etc.). The computer-readable storage medium 1100 may be inserted into a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and / or a wireless link.

[0044] The design module 1400 may include a placement module PLMD 1200 and a routing module RTMD 1300 .

[0045] As used herein, the term "module" may refer to, but is not limited to, software and / or hardware components that perform specific tasks, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). A module may be configured to be located on a tangible, addressable storage medium and configured to execute on one or more processors. For example, a module may include a software component, a class component, a task component, a process, a function, a property, a program, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, a parameter, etc. A module may be divided into multiple modules that perform detailed functions.

[0046] The layout module 1200 may use the processor 1500 to arrange the standard cells based on the input data DI defining the integrated circuit and the standard cell library 1110. The routing module 1300 may perform signal routing with respect to the cell routing provided by the layout module 1200. If the routing is unsuccessful, the layout module 1200 may modify the previous cell routing, and the routing module 1300 may perform signal routing using the modified cell routing. When the routing is successfully completed, the routing module 1300 may provide output data DO defining the integrated circuit.

[0047] The placement module 1200 and the routing module 1300 may be implemented by a single integrated design module 1400, or may be implemented by separate and different modules. The integrated design module 1400 including the placement module 1200 and the routing module 1300 may perform placement and routing so that delay matching and / or duty cycle adjustment may be implemented in an integrated circuit using a plurality of load standard cells.

[0048] The layout module 1200 and / or the routing module 1300 may be implemented in software, but the inventive concept is not limited thereto. If the layout module 1200 and the routing module 1300 are implemented in software, they may be stored as program codes in the storage medium 1100 or in other storage media.

[0049] When the design module 1400 performs calculations, the processor 1500 may be used. Figure 2 In the embodiment, only one processor 1500 is shown, but the inventive concept is not limited thereto. For example, the design system 1000 may include a plurality of processors. In addition, the processor 1500 may include a cache memory to increase computing capacity.

[0050] The design module 1400 may determine a delay difference between a first signal path and a second signal path of an integrated circuit, wherein delay matching is required or specified between the first signal path and the second signal path. The layout module 1200 may layout a selected load standard cell from a plurality of load standard cells, wherein the selected load standard cell will provide a delay corresponding to the delay difference through a load node. The routing module 1300 may route the selected load standard cell so that a load node of the selected load standard cell is connected to a signal path having a smaller delay in the first signal path and the second signal path.

[0051] Therefore, the integrated circuit and the method of designing the integrated circuit according to some example embodiments may improve the design efficiency and performance of the integrated circuit by designing the integrated circuit with delay matching and duty cycle adjustment using load standard cells.

[0052] Figure 3 It shows Figure 2 A flowchart of an example operation of the design system.

[0053] refer to Figure 2 and Figure 3 , the design module 1400 may receive input data DI defining the integrated circuit (S11). The layout module 1200 may refer to the standard cell library 1110 to extract the standard cell corresponding to the input data DI, and may perform cell layout using the extracted standard cell (S12). The routing module 1300 may perform signal routing with respect to the laid-out cell (S13). When the signal routing is unsuccessful (S14: No), the layout module 1200 may replace at least one standard cell (for example, at least one standard cell may be replaced with another standard cell) to modify the layout of the cell. The routing module 1300 may perform signal routing again with respect to the modified layout (S13).

[0054] In this way, replacement and routing can be repeated until signal routing is successfully completed. The success of placement and routing can include the success of delay matching and / or duty cycle adjustment. When signal routing is successfully completed (S14: Yes), the design module 1400 can generate output data DO that defines the integrated circuit (S16).

[0055] Hereinafter, a cell and a structure of an integrated circuit including a plurality of cells are described using a first direction X, a second direction Y, and a third direction Z in a three-dimensional space. The first direction X may be a row direction, the second direction Y may be a column direction, and the third direction Z may be a vertical direction.

[0056] Figure 4 is a diagram illustrating a layout of an integrated circuit according to some example embodiments.

[0057] Figure 4 The integrated circuit 300 may be an application specific integrated circuit (ASIC). The layout of the integrated circuit 300 may be determined by performing the above-mentioned placement and routing of the standard cells SC1 to SC12. Power may be provided to the standard cells SC1 to SC12 through conductive rails 311 to 316. The conductive rails 311 to 316 may include high conductive rails 311, 313, and 315, which are configured to provide a first power supply voltage VDD, and may also include low conductive rails 312, 314, and 316, which are configured to provide a second power supply voltage VSS lower than the first power supply voltage VDD. For example, the first power supply voltage VDD may have a positive voltage level, and the second power supply voltage VSS may have a ground level (e.g., 0V) or a negative voltage level.

[0058] The high conductive tracks 311, 313 and 315 and the low conductive tracks 312, 314 and 316 extend in the row direction X and are alternately arranged one by one in the column direction Y to form boundaries of a plurality of circuit rows CR1-CR5 arranged in the column direction Y. The number of conductive tracks and circuit rows is a non-limiting example and may be variously determined.

[0059] According to some example embodiments, power may be distributed to the conductive rails 311 to 316 through the grid lines 321 to 324 extending along the column direction Y. Some grid lines 322 and 324 may provide a first power supply voltage VDD, while other grid lines 321 and 323 may provide a second power supply voltage VSS. The grid lines 321 to 324 may be connected to the conductive rails 311 to 316 through vertical contacts VC (e.g., through-hole contacts).

[0060] Generally, each of the circuit rows CR1-CR5 can be connected to two adjacent conductive rails located at its border to be powered. For example, the standard cells SC1, SC2, SC3 and SC4 in the first circuit row CR1 can be connected to adjacent and corresponding conductive rail pairs including high conductive rail 311 and low conductive rail 312.

[0061] For example, Figure 4 As shown in , the output node of the eighth standard cell SC8 and the input node of the ninth standard cell SC9 can be connected by wiring 331 and 332. The eighth standard cell SC8 and the ninth standard cell SC9 can be logic standard cells that perform each logic operation, and the output node of the eighth standard cell SC8 or the input node of the ninth standard cell SC9 can be a delay node that requires a specific delay. In this case, the fourth standard cell SC4 corresponding to the above-mentioned load standard cell can be connected to the delay node by wiring 333.

[0062] Figure 5 is a diagram showing a layout of an example standard cell, and Fig. 6A , Figure 6B and Figure 6C It is possible to Figure 5 A cross-sectional view of a standard cell having the same layout.

[0063] Fig. 6A , Figure 6B and Figure 6C A portion of a standard cell SCL including a fin field effect transistor (FinFET) is shown. Fig. 6A yes Figure 5 FIG. 5 is a cross-sectional view of a standard cell SCL cut along line AA′. Figure 6B yes Figure 5 FIG. 5 is a cross-sectional view of a standard cell SCL taken along line BB′. Figure 6C yes Figure 5 FIG. 5 is a cross-sectional view of a standard cell SCL cut along line CC′.

[0064] refer to Figure 5 , Fig. 6A , Figure 6B and Figure 6C , the standard cell SCL may be formed on a substrate 110 having an upper surface 110A extending in a horizontal direction (eg, a first direction X and a second direction Y).

[0065] In some example embodiments, the substrate 110 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In some example embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. The substrate 110 may include a conductive region, for example, a doped well or a doped structure.

[0066] The standard cell SCL includes a first device region RX1, a second device region RX2, and an active cutting region ACR separating the first and second device regions RX1 and RX2. In each of the first and second device regions RX1 and RX2, a plurality of fin type active regions AC protruding from the substrate 110 may be formed.

[0067] The plurality of active regions AC may extend parallel to each other in the first direction X. A device isolation layer 112 may be formed between the plurality of active regions AC on the substrate 110. The plurality of active regions AC protrude from the device isolation layer 112 in the form of fins.

[0068] A plurality of gate insulating layers 118 and a plurality of gate lines PC11, 12, 13, 14, 15, and 16 may be formed on the substrate 110. The gate lines PC 11, 12, 13, 14, 15, and 16 may extend in the second direction Y across the plurality of active regions AC. The plurality of gate insulating layers 118 and the plurality of gate lines PC 11, 12, 13, 14, 15, and 16 may cover the upper surface and both sidewalls of each active region AC and the upper surface of the device isolation layer 112 while extending. A plurality of metal oxide semiconductor (MOS) transistors may be formed along the plurality of gate lines PC 11, 12, 13, 14, 15, and 16. The MOS transistor may have a three-dimensional structure in which a channel is formed in the upper surface and both sidewalls of the active region AC.

[0069] The gate insulating layer 118 may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof. A plurality of gate lines PC11, 12, 13, 14, 15, and 16 may extend on the gate insulating layer 118 across a plurality of active regions AC while covering an upper surface and both sidewalls of each active region AC.

[0070] A mask 122 may be formed on each of the gate lines PC 11, 12, 13, 14, 15, and 16. The sidewalls of the insulating layer 118, the gate lines PC, and the mask 122 may be covered by a spacer 124. The structure of the gate lines PC 11, 12, 13, 14, 15, and 16 may include a metal nitride layer, a metal layer, a conductive capping layer, and a gap filling metal layer stacked in sequence. The metal nitride layer and the metal layer may include Ti, Ta, W, Ru, Nb, Mo, and / or Hf. For example, the metal layer and the metal nitride layer may be formed by using an atomic layer deposition (ALD) method, a metal organic ALD method, and / or a metal organic chemical vapor deposition (MOCVD) method. The conductive capping layer may be used as a protective layer to prevent oxidation of the metal layer surface. In addition, the conductive capping layer may be used as an adhesion layer (e.g., a wetting layer) to promote deposition of another conductive layer on the metal layer. The conductive capping layer may be formed of a metal nitride such as TiN or TaN or a combination thereof, but the inventive concept is not limited thereto. The gap-fill metal layer may fill the space between the active regions AC and extend on the conductive capping layer. The gap-fill metal layer may be formed of a W (eg, tungsten) layer. The gap-fill metal layer may be formed, for example, by using an ALD method, a CVD method, or a physical vapor deposition (PVD) method.

[0071] A plurality of conductive contacts CA and CB are formed at the first layer LY1 on the active region AC. The plurality of conductive contacts CA and CB include a plurality of first contacts CA 21, 22, 23, 24, 25, 31, 32, 33, 34, and 35 connected to the source / drain regions 116 of the active region AC and a plurality of second contacts CB 41, 42, and 43 connected to the gate lines 11, 12, 13, 14, 15, and 16.

[0072] The plurality of conductive contacts CA and CB may be insulated from each other by the first interlayer insulating layer 132 covering the active region AC and the gate line PC. The plurality of conductive contacts CA and CB may have upper surfaces substantially at the same level as an upper surface of the first interlayer insulating layer 132. The first interlayer insulating layer 132 may be formed of a silicon oxide layer, but the inventive concept is not limited thereto.

[0073] A second interlayer insulating layer 134 and a plurality of lower via contacts V0 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, and 62 passing through the second interlayer insulating layer 134 are formed on the first interlayer insulating layer 132. The second interlayer insulating layer 134 may be formed of a silicon oxide layer, but the inventive concept is not limited thereto.

[0074] A plurality of wirings M1 71 , 72 , 73 , 74 , 75 , 76 , 77 , and 78 extending in a horizontal direction at a second layer LY2 higher than the first layer LY1 are formed on the second interlayer insulating layer 134 .

[0075] Each of the wirings M1 may be connected to one of the plurality of conductive contacts CA and CB through one of the plurality of lower via contacts V0 formed between the first layer LY1 and the second layer LY2. Each of the plurality of lower via contacts V0 may be connected to one of the plurality of conductive contacts CA and CB, for example, by passing through the second interlayer insulating layer 134. The plurality of lower via contacts V0 may be insulated from each other by the second interlayer insulating layer 134.

[0076] The wirings 71 to 78 may include internal connection wirings that electrically connect multiple regions in the standard cell SCL. For example, the internal connection wiring 78 may electrically connect the active region AC in the first device region RX1 and the active region AC in the second device region RX2 through the lower via contacts 55 and 58 and the first contacts 24 and 33.

[0077] The wirings 71 and 72 may correspond to the first conductive rail and the second conductive rail, respectively. The first conductive rail 71 may be connected to the active region AC located in the first device region RX1, and the second conductive rail 72 may be connected to the active region AC located in the second device region RX2. One of the first conductive rail 71 and the second conductive rail 72 may be a wiring for providing a power supply voltage (e.g., the first power supply voltage VDD), and the other of the first conductive rail 71 and the second conductive rail 72 may be a wiring for providing a ground voltage (e.g., the second power supply voltage VSS).

[0078] The first conductive track 71 and the second conductive track 72 may extend parallel to each other on the second layer LY2 along the first direction X. In some example embodiments, the conductive tracks 71 and 72 may be formed substantially simultaneously with other wirings 73 to 78. The wiring M1 may be formed to pass through the third interlayer insulating layer 136. The third interlayer insulating layer 136 may insulate the wirings M1 from each other.

[0079] A height CH of the standard cell SCL may be defined by a distance between the first conductive rail 71 and the second conductive rail 72 along the second direction Y. In addition, a width CW of the standard cell SCL may be defined along the first direction X parallel to the conductive rails 71 and 72 .

[0080] The wiring M1 must satisfy the constraints due to the minimum spacing rule. For example, the wiring M1 must satisfy the constraints according to the "tip to side" constraint and the "corner rounding" constraint. The size and arrangement of the wiring M1 may be limited by such constraints.

[0081] The lower via contact V0 and the wiring M1 may have a stacked structure of a barrier layer and a wiring conductive layer. The barrier layer may be formed, for example, of TiN, TaN, or a combination thereof. The wiring conductive layer may be formed, for example, of W, Cu, an alloy thereof, or a combination thereof. The wiring M1 and the lower via contact V0 may be formed using a CVD method, an ALD method, and / or an electroplating method.

[0082] An integrated circuit according to some example embodiments may correspond to a single standard cell or a combination of various standard cells formed as described above.

[0083] Figure 7 is a diagram showing an example integrated circuit, and Figure 8 It shows Figure 7 A timing diagram of the operation of the integrated circuit.

[0084] refer to Figure 7 , the integrated circuit 401 may include a first NAND gate (NAND) ND0, a second NAND gate ND1, and a third NAND gate ND2. Figure 7 The integrated circuit corresponds to a configuration for generating a double data rate (DDR) signal.

[0085] The first NAND gate ND0 performs a NAND operation on the first data signal D0 and the inverted signal Sb of the selection signal SEL to generate a first internal signal d0i. The selection signal SEL may be as follows: Figure 8 The second NAND gate ND1 performs a NAND operation on the second data signal D1 and the selection signal SEL to generate a second internal signal d1i. The third NAND gate ND2 performs a NAND operation on the first internal signal d0i and the second internal signal d1i to generate an output signal OUT.

[0086] refer to Figure 7 and Figure 8 , the integrated circuit 401 samples the second data signal D1 in synchronization with the rising edge of the selection signal SEL, and samples the first data signal D0 in synchronization with the falling edge of the selection signal SEL. The delay of the sampling data of the second data signal D1 included in the output signal OUT is tND1+tND2, and the delay of the sampling data of the first data signal D0 included in the output signal OUT is tINV+tND0+tND2. Here, tINV represents the delay of the inverter INV, tND0 represents the delay of the first NAND gate ND0, tND1 represents the delay of the second NAND gate ND1, and tND2 represents the delay of the third NAND gate ND2.

[0087] Due to the delay of the inverting signal Sb relative to the selection signal SEL, a delay difference may be caused between the first internal signal d0i and the second internal signal d1i. The delay difference is reflected in the output signal OUT, so the output signal OUT has a propagation delay deviation. For example, due to the delay of the inverter INV, a propagation delay deviation is caused between the case where the selection signal SEL is a logic low "0" and the case where the selection signal SEL is a logic high "1". In this case, as shown below with reference to Fig.11 As described above, degradation occurs in the eye diagram of the output signal OUT, and the effective window margin may be reduced.

[0088] Fig. 9 is a diagram illustrating an integrated circuit according to some example embodiments, and Fig.10 It shows Fig. 9 A timing diagram of the operation of the integrated circuit.

[0089] refer to Fig. 9 , the integrated circuit 402 may include a first NAND gate ND0 , a second NAND gate ND1 , a third NAND gate ND2 , and a load standard cell LSC. Fig. 9 Integrated circuits and Figure 7 The configuration corresponds to that of the DDR signal.

[0090] The first NAND gate ND0 performs a NAND operation on the first data signal D0 and the inverted signal Sb of the selection signal SEL to generate a first internal signal d0i. The selection signal SEL may be as follows: Fig.10 The clock signal shown. The second NAND gate ND1 performs a NAND operation on the second data signal D1 and the selection signal SEL to generate a second internal signal d1id. The load standard cell LSC is connected to the output node of the second NAND gate ND1 to provide an additional delay. The load standard cell LSC may include a first electrode connected to the output node of the second NAND gate ND1 and a second electrode connected to the bias voltage VB. The third NAND gate ND2 performs a NAND operation on the first internal signal d0i and the second internal signal d1id to generate an output signal OUT.

[0091] refer to Fig. 9 and Fig.10 , the integrated circuit 402 can sample the second data signal D1 synchronously with the rising edge of the selection signal SEL, and can sample the first data signal D0 synchronously with the falling edge of the selection signal SEL. The delay of the sampling data of the second data signal D1 included in the output signal OUT is (tND1+tL)+tND2, and the delay of the sampling data of the first data signal D0 included in the output signal OUT is tINV+tND0+tND2. Here, tL represents the delay of the load standard cell LSC, tINV represents the delay of the inverter INV, tND0 represents the delay of the first NAND gate ND0, tND1 represents the delay of the second NAND gate ND1, and tND2 represents the delay of the third NAND gate ND2. tND0, tND1 and tND3 can be substantially the same.

[0092] Even if a delay difference between the first internal signal d0i and the second internal signal d1id may be caused due to the delay of the inverting signal Sb relative to the selection signal SEL, the delay difference can be compensated by the delay tL of the load standard cell LSC. According to some example embodiments, the propagation delay can be controlled by connecting the load standard cell LSC to the output node of the second NAND gate ND1. Delay matching can be performed by selecting the best load standard cell among a plurality of load standard cells having different delay characteristics, so that the delay difference between tND1+tL and tINV+tND0 can be as small as possible. Through such delay matching, the effective window margin of the output signal OUT can be ensured.

[0093] Fig.11 is a diagram for describing delay matching and duty cycle adjustment in an integrated circuit according to some example embodiments.

[0094] exist Fig.11 The left part shows Figure 7 The eye diagram corresponding to the integrated circuit 401, and in Fig.11 The right part shows Fig. 9 The eye diagram corresponding to the integrated circuit 402 is shown.

[0095] like Fig.11 As shown in , if the eye diagram of the output signal OUT is measured without delay matching, the effective window margin of the eye diagram is reduced due to the propagation delay deviation. If delay matching is performed to compensate for the propagation delay deviation using a load standard cell LSC, the effective window margin can be increased.

[0096] Therefore, the performance of the integrated circuit can be improved by performing delay matching using a plurality of load standard cells having different delay characteristics in a layout design based on automatic replacement and routing.

[0097] FIG. 12A to FIG. 16B is a diagram illustrating a load standard unit according to some example embodiments.

[0098] FIG. 12A to FIG. 16B Example embodiments of load standard cells having different delay characteristics are shown. Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B Shown with reference Figures 5 to 6C The load standard cell compatible with the FinFET process described above is not limited to this. Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B In FIG. 1 , PC represents a gate line, CA represents a first contact, CB represents a second contact, V0 represents a through-hole contact, M1 represents a wiring, CW1 and CW2 represent a cell width of a load standard cell, CH represents a cell height of a load standard cell, RX1 represents a first device region, RX2 represents a second device region, and ACR represents an active cut region. Figures 5 to 6C understand Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B Therefore, repeated description can be omitted.

[0099] Fig. 12A FIG. 1 is a schematic diagram of a load standard cell LSC1 including a P-channel metal oxide semiconductor (PMOS) transistor TP and an N-channel metal oxide semiconductor (NMOS) transistor TN. Fig. 12A, the source electrode and drain electrode of the PMOS transistor TP can be connected to the power supply voltage VDD, the source electrode and drain electrode of the NMOS transistor TN can be connected to the ground voltage VSS, and the gate electrode of the PMOS transistor TP and the gate electrode of the NMOS transistor TN can be commonly connected to the load node NL to provide a delay. The PMOS transistor TP and the NMOS transistor TN connected in this way can be provided as a single load standard cell LSC1 and included in the standard cell library.

[0100] Fig. 12B Shown with Fig. 12A The schematic diagram of the load standard cell LSC1 corresponds to the example layout. Reference 12A and Fig. 12B , the PMOS transistor TP is formed in the first device region RX1 , and the NMOS transistor TN is formed in the second device region RX2 . In this case, the power supply voltage VDD may be provided through the first conductive rail 71 , and the ground voltage VSS may be provided through the second conductive rail 72 .

[0101] The source electrode and the drain electrode of the PMOS transistor TP may be connected to the power supply voltage VDD through the first contacts 21 and 22 and the via contacts 51 and 52. The source electrode and the drain electrode of the NMOS transistor TN may be connected to the ground voltage VSS through the first contacts 31 and 32 and the via contacts 53 and 54. The common gate line 11 of the PMOS transistor TP and the NMOS transistor TN may be connected to the wiring 75 through the via contact 61, and the wiring 75 corresponding to the load node NL may be connected to the delay node of another standard cell.

[0102] Therefore, a load standard cell can be implemented using a metal oxide semiconductor (MOS) capacitor formed by connecting a source electrode and a drain electrode of a MOS transistor. A plurality of MOS capacitors can be implemented to have different capacitance values ​​so that a plurality of load standard cells including MOS capacitors can have different delay characteristics.

[0103] In some example embodiments, the MOS capacitor may be designed such that: during the manufacture of the integrated circuit, by adjusting the gate electrode (ie, Fig. 12B The capacitance of the MOS capacitor is controlled by adjusting the density of impurities in the gate line 11).

[0104] In some example embodiments, the capacitance of the MOS capacitor can be controlled by adjusting the size of the MOS capacitor or the MOS transistor. The size of the MOS capacitor can include the size or relative position of two opposing conductors of the MOS capacitor, etc. For example, the capacitance value of the MOS capacitor can be controlled by adjusting the length of the gate line 11.

[0105] In some example embodiments, this can be accomplished by using Fig.13A and Fig. 13B Parallel structure and / or Fig.14A and Fig. 14B The series structure controls the capacitance of the MOS capacitor to achieve different delay characteristics.

[0106] Fig.13A FIG. 1 is a schematic diagram of a load standard cell LSC2 including a plurality of PMOS transistors TP1 and TP2 and a plurality of NMOS transistors TN1 and TN2. Fig.13A A non-limiting example of two PMOS transistors and two NMOS transistors is shown, and the number of transistors may be varied in various ways.

[0107] refer to Fig.13A , the source electrode and drain electrode of the first PMOS transistor TP1 can be connected to the power supply voltage VDD, and the source electrode and drain electrode of the first NMOS transistor TN1 are connected to the ground voltage VSS. In the same way, the source electrode and drain electrode of the second PMOS transistor TP2 can be connected to the power supply voltage VDD, and the source electrode and drain electrode of the second NMOS transistor TN2 can be connected to the ground voltage VSS. The gate electrode of the first PMOS transistor TP1, the gate electrode of the second PMOS transistor TP2, the gate electrode of the first NMOS transistor TN1, and the gate electrode of the second NMOS transistor TN2 can be connected to the load node NL in common to provide a delay. The PMOS transistors TP1 and TP2 and the NMOS transistors TN1 and TN2 connected in parallel in this way can be provided as a single load standard cell LSC2 and included in the standard cell library.

[0108] Fig. 13B Shown with Fig.13A The schematic diagram of the load standard cell LSC2 corresponds to the example layout. Fig.13A and Fig. 13B , PMOS transistors TP1 and TP2 are formed in the first device region RX1, and NMOS transistors TN1 and TN2 are formed in the second device region RX2. In this case, the power supply voltage VDD may be provided through the first conductive rail 71, and the ground voltage VSS may be provided through the second conductive rail 72.

[0109] Source and drain electrodes of the PMOS transistors TP1 and TP2 may be connected to a power supply voltage VDD through first contacts 21, 22, 23, and 24 and via contacts 51, 52, 53, and 54. Source and drain electrodes of the NMOS transistors TN1 and TN2 may be connected to a ground voltage VSS through first contacts 31, 32, 33, and 34 and via contacts 55, 56, 57, and 58.

[0110] The common gate line 11 of the first PMOS transistor TP1 and the first NMOS transistor TN1 and the common gate line 13 of the second PMOS transistor TP2 and the second NMOS transistor TN2 can be connected to the wiring 75 through the through-hole contacts 61 and 62, and the wiring 75 corresponding to the load node NL can be connected to the delay node of another standard cell. The gate line 12 is a dummy gate line in a floating state.

[0111] Fig.14A FIG. 1 is a schematic diagram of a load standard cell LSC3 including a plurality of PMOS transistors TP1 and TP2 and a plurality of NMOS transistors TN1 and TN2. Fig.14A A non-limiting example of two PMOS transistors and two NMOS transistors is shown, and the number of transistors may be varied in various ways.

[0112] refer to Fig.14A , the source electrode and drain electrode of the first PMOS transistor TP1 can be connected to the gate electrode of the second PMOS transistor TP2, and the source electrode and drain electrode of the second PMOS transistor TP2 can be connected to the power supply voltage VDD. The source electrode and drain electrode of the first NMOS transistor TN1 can be connected to the gate electrode of the second NMOS transistor TN2, and the source electrode and drain electrode of the second NMOS transistor TN2 are connected to the ground voltage VSS. The gate electrode of the first PMOS transistor TP1 and the gate electrode of the first NMOS transistor TN1 can be commonly connected to the load node NL to provide a delay. The PMOS transistors TP1 and TP2 and the NMOS transistors TN1 and TN2 connected in series in this way can be provided as a single load standard cell LSC3 and included in the standard cell library.

[0113] Fig. 14B Shown with Fig.14A The schematic diagram of the load standard cell LSC3 corresponds to the example layout. Fig.14A and Fig. 14B , PMOS transistors TP1 and TP2 are formed in the first device region RX1, and NMOS transistors TN1 and TN2 are formed in the second device region RX2. In this case, the power supply voltage VDD may be provided through the first conductive rail 71, and the ground voltage VSS may be provided through the second conductive rail 72.

[0114] The source electrode and the drain electrode of the first PMOS transistor TP1 may be connected to the gate electrode (i.e., the gate line segment 13) of the second PMOS transistor TP2 through the first contacts 21 and 22, the via contacts 62, 63, and 64, and the wiring 76. The source electrode and the drain electrode of the second PMOS transistor TP2 may be connected to the power supply voltage VDD through the first contacts 23 and 24 and the via contacts 51 and 52.

[0115] The source electrode and the drain electrode of the first NMOS transistor TN1 may be connected to the gate electrode (e.g., the gate line segment 14) of the second NMOS transistor TN2 through the first contacts 31 and 32, the via contacts 65, 66, and 67, and the wiring 77. The source electrode and the drain electrode of the second NMOS transistor TN2 may be connected to the ground voltage VSS through the first contacts 33 and 34 and the via contacts 53 and 54.

[0116] The common gate line 11 of the first PMOS transistor TP1 and the first NMOS transistor TN1 may be connected to the wiring 75 through the via contact 61, and the wiring 75 corresponding to the load node NL may be connected to a delay node of another standard cell. The gate line 12 is a dummy gate line in a floating state.

[0117] Fig.15A FIG. 4 shows a schematic diagram of a load standard cell LSC4 including a PMOS transistor TP. Fig.15A , the source electrode and the drain electrode of the PMOS transistor TP may be connected to the power supply voltage VDD, and the gate electrode of the PMOS transistor TP may be connected to the load node NL to provide a delay. The corresponding NMOS transistor according to the complementary MOS (CMOS) manufacturing process may be maintained in a dummy state, and in Fig.15A The PMOS transistor TP connected in this way can be provided as a single load standard cell LSC4 and included in the standard cell library.

[0118] Fig. 15B Shown with Fig.15A The schematic diagram of the load standard cell LSC4 corresponds to the example layout. Fig.15A and Fig. 15B , the PMOS transistor TP is formed in the first device region RX1, and the corresponding NMOS transistor in the second device region RX2 can be omitted. In this case, the power supply voltage VDD can be provided through the first conductive rail 71, and the ground voltage VSS can be provided through the second conductive rail 72.

[0119] The source electrode and the drain electrode of the PMOS transistor TP may be connected to the power supply voltage VDD through the first contacts 21 and 22 and the via contacts 51 and 52. The gate line segment 12 corresponding to the gate electrode of the PMOS transistor TP may be connected to the wiring 75 through the via contact 61, and the wiring 75 corresponding to the load node NL may be connected to the delay node of another standard cell. Another gate line segment 11 may be a floating dummy segment.

[0120] Fig.16A FIG. 5 shows a schematic diagram of a load standard cell LSC5 including an NMOS transistor TN. Fig.16A , the source electrode and the drain electrode of the NMOS transistor TN may be connected to the ground voltage VSS, and the gate electrode of the NMOS transistor TN may be connected to the load node NL to provide a delay. The corresponding PMOS transistor according to the CMOS manufacturing process may be maintained in a dummy state, and Fig.16A The NMOS transistor TN connected in this way can be provided as a single load standard cell LSC5 and included in the standard cell library.

[0121] Fig. 16B Shown with Fig.16A The schematic diagram of the load standard cell LSC5 corresponds to the example layout. Fig.16A and Fig. 16B , the NMOS transistor TN is formed in the second device region RX2, and the corresponding PMOS transistor in the first device region RX1 can be omitted. In this case, the power supply voltage VDD can be provided through the first conductive rail 71, and the ground voltage VSS can be provided through the second conductive rail 72.

[0122] The source electrode and the drain electrode of the NMOS transistor TN may be connected to the ground voltage VSS through the first contacts 31 and 32 and the via contacts 51 and 52. The gate line segment 11 corresponding to the gate electrode of the NMOS transistor TN may be connected to the wiring 75 through the via contact 61, and the wiring 75 corresponding to the load node NL may be connected to the delay node of another standard cell. Another gate line segment 12 may be a floating dummy segment.

[0123] Because the power supply voltage VDD is applied to the opposite electrode of the load node NL, Fig.15A The load standard cell LSC4 may cause the delay of the falling edge of the signal to be greater than the delay of the rising edge of the signal. On the contrary, because the ground voltage VSS is applied to the opposite electrode of the load node NL, Fig.16AThe load standard cell LSC5 may cause the delay of the rising edge of the signal to be greater than the delay of the falling edge of the signal. At least one of the load standard cells LSC4 and LSC5 having different delay characteristics may be used to adjust the duty cycle of the signal of the integrated circuit.

[0124] Fig.17 is a block diagram illustrating an integrated circuit according to some example embodiments.

[0125] refer to Fig.17 , the integrated circuit 403 may include a first logic standard cell SC1 (which includes a first delay node ND1), a second logic standard cell SC2 (which includes a second delay node ND2), a third logic standard cell SC3, a fourth logic standard cell SC4, a first load standard cell LSCa and a second load standard cell LSCb.

[0126] The first load standard cell LSCa may include a first load node providing a first delay, and the first load node is connected to the first delay node ND1. The second load standard cell LSCb includes a second load node providing a second delay different from the first delay, and the second load node is connected to the second delay node ND2. A first bias voltage VB1 may be applied to an opposite electrode of the first load node of the first load standard cell LSCa, and a second bias voltage VB2 may be applied to an opposite electrode of the second load node of the second load standard cell LSCb.

[0127] The first logic standard cell SC1 may perform a logic operation on the first signal S1 to generate a second signal S2, and the third logic standard cell SC3 may perform a logic operation on the second signal S2 to generate a third signal S3. The second logic standard cell SC2 may perform a logic operation on the fourth signal S4 to generate a fifth signal S5, and the fourth logic standard cell SC4 may perform a logic operation on the fifth signal S5 to generate a sixth signal S6.

[0128] One of the first bias voltage VB1 and the second bias voltage VB2 may correspond to the power supply voltage VDD, and the other of the first bias voltage VB1 and the second bias voltage VB2 may correspond to the ground voltage VSS. Fig.15A and Fig. 15B As described, one of the first load standard cell LSCa and the second load standard cell LSCb may provide a larger delay to the rising edge of the signal, and the other of the first load standard cell LSCa and the second load standard cell LSCb may provide a larger delay to the falling edge of the signal.

[0129] Fig.18A and Fig.18B It shows Fig.17 A timing diagram of the operation of the integrated circuit.

[0130] refer to Fig.17 and Fig.18A , the first load standard cell LSCa may cause the delay of the falling edge of the signal to be greater than the delay of the rising edge of the signal. According to the delay characteristics of the first load standard cell LSCa, the falling time tF1 of the second signal S2 may be longer than the rising time tR1 of the second signal S2, and thus the delay tDF1 of the falling edge of the third signal S3 relative to the falling edge of the first signal S1 may be greater than the delay tDR1 of the rising edge of the third signal S3 relative to the rising edge of the first signal S1. If the first signal S1 has a duty cycle less than 0.5, the duty cycle of the third signal S3 may be increased to a value close to 0.5 using the first load standard cell LSCa.

[0131] refer to Fig.17 and Fig.18B , the second load standard cell LSCb may cause the delay of the rising edge of the signal to be greater than the delay of the falling edge of the signal. According to the delay characteristics of the second load standard cell LSCb, the rising time tR2 of the fifth signal S5 may be longer than the falling time tF2 of the fifth signal S5, and thus the delay tDR2 of the rising edge of the sixth signal S6 relative to the rising edge of the fourth signal S4 may be greater than the delay tDF2 of the falling edge of the sixth signal S6 relative to the falling edge of the fourth signal S4. If the fourth signal S4 has a duty cycle greater than a value of 0.5, the duty cycle of the sixth signal S6 may be reduced to a value close to 0.5 using the second load standard cell LSCb.

[0132] Therefore, the duty ratio of the signal of the integrated circuit may be adjusted using at least one of the first load standard cell LSCa and the second load standard cell LSCb having different delay characteristics.

[0133] Fig.19 is a block diagram illustrating an integrated circuit according to some example embodiments.

[0134] Fig.19 An example embodiment of a digitally controlled delay line is shown as an example integrated circuit. Fig.19 4 shows a digitally controlled delay line with five stages controlled by 5-bit selection signals SEL1 to SEL5, but the number of stages in the delay line can be determined in various ways.

[0135] refer to Fig.19 The integrated circuit 404 may include a plurality of input NAND gates GA1-GA5, a plurality of intermediate NAND gates GB0-GB4, a plurality of output NAND gates GC0-GC4, a plurality of intermediate load standard cells LSC12-LSC15, and a plurality of output load standard cells LSC21-LSC25.

[0136] Each of the plurality of input NAND gates GA1 to GA5 may perform a NAND operation on each of the inverted signals of the selection signals SEL1 to SEL5, and may receive the output of the previous input NAND gate. The first input NAND gate GA1 receives the input signal IN. Each of the plurality of intermediate NAND gates GB0 to GB4 may perform a NAND operation on each of the selection signals SEL1 to SEL5, and may receive the output of the corresponding input NAND gate. The first intermediate NAND gate GB0 receives the input signal IN. Each of the plurality of output NAND gates GC0 to GC4 performs a NAND operation on the output of the corresponding intermediate NAND gate and the output of the previous output NAND gate. The first output NAND gate GC0 provides a final delayed output signal OUT.

[0137] The selection signals SEL1-SEL5 can form a thermometric code. Fig.19 As shown in , the first selection signal SEL1, the second selection signal SEL2, and the third selection signal SEL3 may have a value of "0", and the fourth selection signal SEL4 and the fifth selection signal SEL5 may have a value of "1". In this case, the input signal IN passes through three input NAND gates GA1, GA2, and GA3, one middle NAND gate GB3, and four output NAND gates GC3, GC2, GC1, and GC0 to provide a final delayed output signal OUT.

[0138] Each output of the input NAND gates GA1-GA5 is provided as an input to two NAND gates, i.e., the input to the next input NAND gate and the corresponding intermediate NAND gate. In contrast, each output of the intermediate NAND gates GB0-GB4 is provided as an input to one NAND gate, i.e., the input to the corresponding output NAND gate. Due to this mismatch of the output load, the delay mismatch may cause the operating characteristics of the integrated circuit 404 to degrade. According to some example embodiments, a plurality of intermediate load standard cells LSC11-LSC15 may be connected to the output nodes of the plurality of intermediate NAND gates GB0-GB4 to achieve delay matching. In the same manner, a plurality of output load standard cells LSC21-LSC25 may be connected to the output nodes of the plurality of output NAND gates GC0-GC4.

[0139] Fig. 20 is a block diagram illustrating a mobile device according to some example embodiments.

[0140] refer to Fig. 20 , the mobile device 4000 may include at least one application processor 4100 , a communication module 4200 , a display / touch module 4300 , a storage device 4400 , and a buffer RAM 4500 .

[0141] The application processor 4100 controls the operation of the mobile device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be or may include an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. As described above, the storage device 4400 may perform caching of mapping data and user data.

[0142] The buffer RAM 4500 may temporarily store data for processing operations of the mobile device 4000. For example, the buffer RAM 4500 may be or may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0143] According to some example embodiments, at least one component in the mobile device 4000 may include at least one load standard cell. As described above, the design of the load standard cell may be included in a standard cell library, and an integrated circuit included in the mobile device 4000 may be designed through automatic placement and routing of a design tool.

[0144] As described above, the integrated circuit and the method of designing the integrated circuit according to some example embodiments may improve the design efficiency and performance of the integrated circuit by designing the integrated circuit with delay matching and duty cycle adjustment using load standard cells.

[0145] The inventive concept can be applied to any electronic device and system. For example, the inventive concept can be applied to the following systems: such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable cameras, personal computers (PCs), server computers, workstations, notebook computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0146] By designing and / or manufacturing an integrated circuit to include load standard cells with different delay characteristics, the design efficiency and performance of the integrated circuit can be improved.

[0147] Example embodiments are described with reference to actions and symbolic representations (e.g., in the form of flow charts, schematic diagrams, data flow diagrams, structure diagrams, block diagrams, etc.) of operations that may be implemented in conjunction with units and / or devices discussed in greater detail below. Although discussed in a particular manner, the functions or operations specified in a particular block may be performed in a manner different from the processes specified in the flow chart, flow diagram, etc. For example, functions or operations illustrated as being performed serially in two consecutive blocks may actually be performed in parallel, simultaneously, or in some cases in a reverse order.

[0148] The units and / or devices according to one or more example embodiments may be implemented using hardware, a combination of hardware and software, or a storage medium storing software. The hardware may be implemented using processing circuitry, such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more systems on chips (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more application specific integrated circuits (ASICs), or any other device or devices capable of responding to and executing instructions in a defined manner.

[0149] Software may include computer programs, program codes, instructions, or a combination thereof to independently or collectively instruct or configure hardware devices to operate as desired. Computer programs and / or program codes may include programs or computer-readable instructions, software components, software modules, data files, data structures, etc. that can be implemented by one or more hardware devices (e.g., one or more of the hardware devices mentioned above). Examples of program code include machine code generated by a compiler and higher-level program code executed using an interpreter.

[0150] For example, when the hardware device is a computer processing device (for example, one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device can be configured to execute program code by performing arithmetic, logic, and input / output operations according to the program code. Once the program code is loaded into the computer processing device, the computer processing device can be programmed to execute the program code, thereby transforming the computer processing device into a special-purpose computer processing device. In a more specific example, when the program code is loaded into the processor, the processor is programmed to execute the program code and the operation corresponding thereto, thereby transforming the processor into a special-purpose processor. In another example, the hardware device can be an integrated circuit customized in a special-purpose processing circuit (for example, ASIC).

[0151] A hardware device such as a computer processing device can run an operating system (OS) and one or more software applications running on the OS. In addition, the computer processing device can also access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, one or more example embodiments may be illustrated as a computer processing device; however, those skilled in the art will recognize that the hardware device may include multiple processing elements and multiple types of processing elements. For example, the hardware device may include multiple processors or a processor and a controller. In addition, other processing configurations are also possible, such as parallel processors.

[0152] Software and / or data may be implemented permanently or temporarily in any type of storage medium (including but not limited to any machine, component, physical or virtual device, or computer storage medium or device) that can provide instructions or data to a hardware device or can be interpreted by a hardware device. Software may also be distributed on a network-coupled computer system so that the software is stored and executed in a distributed manner. Specifically, for example, software and data may be stored by one or more computer-readable recording media, including tangible or non-transitory computer-readable storage media as discussed herein.

[0153] According to one or more example embodiments, the storage medium may also include one or more storage devices at the unit and / or device. One or more storage devices may be tangible or non-temporary computer-readable storage media, such as random access memory (RAM), read-only memory (ROM), permanent mass storage device (such as disk drive) and / or any other similar data storage mechanism capable of storing and recording data. One or more storage devices may be configured to store computer programs, program codes, instructions or some combinations thereof for one or more operating systems and / or for implementing the example embodiments described herein. A drive mechanism may also be used to load a computer program, program code, instruction or some combination thereof from a separate computer-readable storage medium into one or more storage devices and / or one or more computer processing devices. This separate computer-readable storage medium may include a universal serial bus (USB) flash drive, a memory stick, a Blu-ray / DVD / CD-ROM drive, a memory card and / or other similar computer-readable storage media. A computer program, program code, instruction or some combination thereof may be loaded into one or more storage devices and / or one or more computer processing devices from a remote data storage device via a network interface rather than via a computer-readable storage medium. In addition, a computer program, program code, instruction, or some combination thereof may be loaded into one or more storage devices and / or one or more processors from a remote computing system configured to transmit and / or distribute the computer program, program code, instruction, or some combination thereof via a network. The remote computing system may transmit and / or distribute the computer program, program code, instruction, or some combination thereof via a wired interface, an air interface, and / or any other similar medium.

[0154] One or more hardware devices, storage media, computer programs, program codes, instructions, or some combination thereof may be specially designed and constructed for the purposes of the example embodiments, or they may be known devices that have been altered and / or modified for the purposes of the example embodiments.

[0155] The foregoing is illustrative of some exemplary embodiments and is not to be construed as limiting thereof.

Claims

1. A method for designing an integrated circuit, comprising: receiving input data defining the integrated circuit; Providing a plurality of load standard cells having different delay characteristics in a standard cell library, the load standard cell comprising a transistor having a source and a drain, the source and the drain being directly connected to each other; performing placement and routing based on the input data and the standard cell library; as well as generating output data defining the integrated circuit based on a result of the placing and the routing, The providing of the plurality of load standard cells comprises: providing at least one load standard cell capable of controlling the capacitance value of the transistor by adjusting the density of impurities injected into the gate electrode of the transistor.

2. The method according to claim 1, wherein: Providing the plurality of load standard units comprises: A plurality of capacitor standard cells having different capacitance values ​​are provided as the plurality of load standard cells.

3. The method according to claim 1, wherein: Providing the plurality of load standard units also includes: The capacitance value of the transistor is controlled by adjusting the size of the transistor.

4. The method according to claim 1, wherein: Providing the plurality of load standard units comprises: connecting a plurality of MOS capacitors in series; and The plurality of MOS capacitors connected in series are provided as a single load standard unit.

5. The method according to claim 1, wherein: Providing the plurality of load standard units comprises: connecting a plurality of MOS capacitors in parallel; and The plurality of MOS capacitors connected in parallel are provided as a single load standard unit.

6. The method according to claim 1, wherein: Providing the plurality of load standard units comprises: connecting a source electrode and a drain electrode of a P-channel metal oxide semiconductor (PMOS) transistor to a power supply voltage; Connecting the source electrode and the drain electrode of the N-channel metal oxide semiconductor (NMOS) transistor to a ground voltage; connecting a gate electrode of the PMOS transistor and a gate electrode of the NMOS transistor to a load node for providing a delay; and The PMOS transistor and the NMOS transistor are provided as a single load standard cell.

7. The method according to claim 1, wherein: Providing the plurality of load standard units comprises: providing a first load standard unit, wherein the first load standard unit is configured to make the delay of a falling edge of a signal greater than the delay of a rising edge of the signal; and A second load standard unit is provided, wherein the second load standard unit is configured to make the delay of the rising edge of the signal greater than the delay of the falling edge of the signal.

8. The method according to claim 7, wherein: Performing the placement and routing includes: A duty cycle of a signal of the integrated circuit is adjusted using at least one of the first load standard cell and the second load standard cell.

9. The method according to claim 1, wherein: Providing the plurality of load standard units comprises: connecting a source electrode and a drain electrode of a P-channel metal oxide semiconductor (PMOS) transistor to a power supply voltage; connecting a gate electrode of the PMOS transistor to a first load node for providing a delay; and The PMOS transistor is provided as a first load standard unit.

10. The method according to claim 9, wherein: Providing the plurality of load standard units also includes: Connecting the source electrode and the drain electrode of the N-channel metal oxide semiconductor (NMOS) transistor to a ground voltage; connecting a gate electrode of the NMOS transistor to a second load node for providing a delay; and The NMOS transistor is provided as a second load standard unit.

11. The method according to claim 10, wherein: Performing the placement and routing includes: A duty cycle of a signal of the integrated circuit is adjusted using at least one of the first load standard cell and the second load standard cell.

12. The method according to claim 1, wherein: Performing the placement and routing includes: determining a delay difference between a first signal path of the integrated circuit and a second signal path of the integrated circuit; Arranging a selected load standard cell among the plurality of load standard cells, the selected load standard cell having a load node, the selected load standard cell providing a delay corresponding to the delay difference; and The selected load standard cell is wired so that the load node of the selected load standard cell is connected to a signal path having a smaller delay between the first signal path and the second signal path.

13. The method according to claim 1, further comprising: The integrated circuit is fabricated using at least one photomask, the at least one photomask being based on the output data.

14. An integrated circuit comprising: Logic standard cells, including delay nodes that need to be delayed; as well as a load standard cell, comprising a load node connected to the delay node, the load standard cell being configured to provide a required delay, the load standard cell comprising a transistor having a source and a drain, the source and the drain being shorted together, Wherein, the associated delay of the load standard cell is based on the density of impurities implanted into the gate electrode of the transistor.

15. The integrated circuit of claim 14, wherein: The load standard unit comprises: a P-channel metal oxide semiconductor (PMOS) transistor having a gate electrode connected to the load node and source and drain electrodes connected to a power supply voltage; and An N-channel metal oxide semiconductor (NMOS) transistor has a gate electrode connected to the load node and a source electrode and a drain electrode connected to a ground voltage.

16. The integrated circuit of claim 14, wherein: The load standard unit includes at least one of the following: a P-channel metal oxide semiconductor (PMOS) transistor having a gate electrode connected to the load node and source and drain electrodes connected to a power supply voltage; and An N-channel metal oxide semiconductor (NMOS) transistor has a gate electrode connected to the load node and a source electrode and a drain electrode connected to a ground voltage.

17. The integrated circuit of claim 14, wherein: The load standard unit includes at least one of the following: A first load standard unit configured to make the delay of a falling edge of a signal greater than the delay of a rising edge of the signal; and The second load standard unit is configured to make the delay of the rising edge of the signal greater than the delay of the falling edge of the signal, At least one of the first load standard unit and the second load standard unit is configured to adjust a duty cycle of a signal of the integrated circuit.

18. An integrated circuit comprising: A first logic standard cell including a first delay node; A second logic standard cell including a second delay node; A first load standard unit, comprising a first load node providing a first delay, wherein the first load node is connected to the first delay node; as well as a second load standard unit, comprising a second load node providing a second delay different from the first delay, the second load node being connected to the second delay node, The first load standard unit includes a first transistor, wherein the first transistor has a first source node and a first drain node shared with the first source node. The second load standard unit includes a second transistor, the second transistor has a second source node and a second drain node shared with the second source node, and A first amount of impurities injected into a first gate electrode of the first transistor is different from a second amount of impurities injected into a second gate electrode of the second transistor.

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