Display device having dummy patterns in non-display areas

Abstract

The present invention relates to a display device having a dummy pattern in a non-display area. The display device includes a substrate, and the substrate includes a display area and a non-display area. A first insulating layer, a second insulating layer, and a third insulating layer are sequentially arranged on the substrate. A plurality of pixels are arranged in the display area. Each of the plurality of pixels includes a transistor and a light-emitting element connected to the transistor. A data line is arranged in the display area. The data line is configured to supply a data signal to each of the plurality of pixels. A wiring portion is arranged in the non-display area. The wiring portion includes a connecting line connected to the data line and a fan-out line connected to the connecting line. The dummy pattern is arranged in the non-display area. The dummy pattern overlaps at least partially with the wiring portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0008989 filed on January 24, 2018, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device having a dummy pattern in a non-display area of ​​the display device. Background Art

[0004] The display device includes a plurality of pixels for displaying an image, and each of the pixels includes a plurality of transistors, a capacitor, and a wiring portion of a display element connected to the transistor to drive the pixel. The configuration in each pixel can be formed by a photolithography process that exposes a pattern in a photoresist through a mask.

[0005] Because the pattern in the display area of ​​the display device is significantly denser than the pattern in the non-display area, the difference in the photoresist pattern thus obtained can cause a significant density difference between the display area where a plurality of pixels are arranged and the non-display area where pixels are not arranged. In particular, in the non-display area where the photoresist pattern is arranged at a low density, the amount of photoresist dissolved in the development process can be greater than the amount of photoresist in the display area where the photoresist pattern is arranged at a higher density. Therefore, the concentration of the developer applied to the non-display area can be significantly lower than the concentration of the developer applied to the display area, and there can be a steep concentration difference between the developer on the display area and the developer on the non-display area.

[0006] This difference in concentration can cause a non-uniform thickness of the photoresist within each area. Summary of the invention

[0007] A display device includes a substrate, the substrate including a display area and a non-display area. A first insulating layer is arranged on the substrate. A second insulating layer is arranged on the first insulating layer. A third insulating layer is arranged on the second insulating layer. A plurality of pixels are arranged in the display area. Each of the plurality of pixels includes at least one transistor and a light-emitting element connected to the at least one transistor. A data line is arranged in the display area. The data line is configured to supply a data signal to each of the plurality of pixels. A wiring portion is arranged in the non-display area. The wiring portion includes a connection line connected to the data line and a fan-out line connected to the connection line. A dummy pattern is arranged in the non-display area. The dummy pattern overlaps at least partially with the wiring portion.

[0008] A display device includes a substrate, the substrate including a display area and a non-display area. A first insulating layer is arranged on the substrate. A second insulating layer is arranged on the first insulating layer. A third insulating layer is arranged on the second insulating layer. A plurality of pixels are arranged in the display area. Each of the plurality of pixels includes at least one transistor and a light-emitting element connected to the at least one transistor. A plurality of data lines are arranged in the display area. The plurality of data lines are configured to supply data signals to each of the plurality of pixels. A wiring portion is arranged in the non-display area. The wiring portion includes a plurality of connection lines connected to corresponding data lines in the plurality of data lines. A first fan-out line is connected to a corresponding connection line in the plurality of connection lines. A second fan-out line is connected to a corresponding connection line in the plurality of connection lines. The first fan-out line and the second fan-out line are arranged on different layers. A dummy pattern is arranged in the non-display area. The dummy pattern at least partially overlaps with the wiring portion. The dummy pattern includes a dummy active pattern at least partially overlapping with the plurality of connection lines, a first dummy line at least partially overlapping with the first fan-out line, and a second dummy line at least partially overlapping with the second fan-out line.

[0009] A display device includes a substrate having a display area and a non-display area. A plurality of pixels are arranged on the display area. A data line is arranged in the display area. The data line is configured to supply a data signal to each of the plurality of pixels. A wiring portion is arranged in the non-display area. The wiring portion includes a connection line connected to the data line and a fan-out line connected to the connection line. A dummy pattern is arranged in the non-display area. The dummy pattern overlaps the wiring portion at least partially. The display area has a first pattern density. The non-display area has a second pattern density. The first pattern density is substantially equal to the second pattern density. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete appreciation of the present disclosure and its many attendant aspects will be readily obtained as the present disclosure becomes better understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0012] Figure 2 It is a graphic Figure 1 A perspective view of an example of a display device;

[0013] Figure 3 The diagram is included in Figure 1 A block diagram of an example of a plurality of pixels and a driver in a display device;

[0014] Figure 4 It is a graphic Figure 3 An equivalent circuit diagram of an example of a pixel among pixels of;

[0015] Figure 5 It is a graphic Figure 4 A plan view of an example of pixels;

[0016] Figure 6 It is along Figure 5 A cross-sectional view taken along the section line AA';

[0017] Figure 7 It is along Figure 5 A cross-sectional view taken along the section line BB';

[0018] Figure 8 It is a graphic Figure 1 An enlarged view of an example of area EA1;

[0019] Fig. 9 It is along Figure 8 A sectional view taken along the section line CC';

[0020] Fig.10 It is along Figure 8 A sectional view taken along the section line D-D';

[0021] Fig.11 It is along Figure 8 A sectional view taken along the section line E-E';

[0022] Fig.12 It is a graphic with Figure 1 An example plan view of a fan-out area corresponding to area EA1;

[0023] Fig.13 It is along Fig.12 A sectional view taken along the section line F-F';

[0024] Fig.14 It is along Fig.12 A sectional view taken along the section line G-G';

[0025] Fig.15 It is along Fig.12 A sectional view taken along the section line H-H';

[0026] Fig.16 It is a graphic with Figure 1 An example plan view of a fan-out area corresponding to area EA1;

[0027] Fig.17 It is along Fig.16 A sectional view taken along section line II';

[0028] Fig.18 It is along Fig.16 A sectional view taken along the section line J-J'; and

[0029] Fig.19 It is along Fig.16 A cross-sectional view taken along section line K-K'. DETAILED DESCRIPTION

[0030] Because the present disclosure becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, a more complete understanding of the present disclosure and its many incidental aspects will be readily obtained. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. It should be understood that the present invention is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0031] The same reference numerals may represent similar elements in the specification and the drawings. In the drawings, for clarity, the size and relative size of the layer and region may be exaggerated. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, patterns and / or parts, these elements, components, regions, layers, patterns and / or parts should not be limited to these terms. These terms are only used to distinguish an element, component, region, layer, pattern or part from another element, component, region, layer, pattern or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part, without departing from the teaching of the exemplary embodiment. As used herein, the singular forms "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0032] Figure 1 is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 2 It is a graphic Figure 1 A perspective view of an example of a display device.

[0033] Reference Figure 1 and Figure 2 , the display device may include a substrate SUB, a plurality of pixels PXL arranged on the substrate SUB, a wiring portion LP connected to the pixels PXL, and a driving circuit board connected to the wiring portion LP.

[0034] The substrate SUB may include a display area DA and a non-display area NDA disposed at at least one side of the display area DA.

[0035] The substrate SUB may substantially have a rectangular shape. In some exemplary embodiments of the present disclosure, the substrate SUB may include a pair of shorter sides parallel to each other and extending in the first direction DR1, and a pair of longer sides parallel to each other and extending in the second direction DR2.

[0036] However, the shape of the substrate SUB may be different from that described herein, and the substrate SUB may have various other shapes. For example, the substrate SUB may have a closed polygonal shape including straight edges, a circle, a semicircle, a semi-ellipse, etc. In some exemplary embodiments of the present disclosure, when the substrate SUB has straight edges, at least some of the corners may be curved. For example, when the substrate SUB has a rectangular shape, the portion where adjacent straight edges meet may be replaced by a curve with a predetermined curvature. This shape may be referred to as a rounded rectangle. For example, the vertex portion of the rectangular shape may be formed by curved sides connected to two straight edges adjacent to each other and having a predetermined curvature. The predetermined curvature may be set differently depending on the position. For example, the curvature may vary depending on the position at which the curve starts and the length of the curve.

[0037] The display area DA may be an area in which the pixels PXL are arranged. The display area DA may be capable of displaying an image. The display area DA may be arranged in a shape corresponding to the shape of the substrate SUB. For example, the display area DA may include a closed polygon including straight sides, a circle, an ellipse, a semicircle, a semi-ellipse, etc. In some exemplary embodiments of the present disclosure, when the display area DA has straight sides, at least some of the corners may be bent to form a rounded rectangle.

[0038] The pixels PXL may be arranged in a display area DA of a substrate SUB. Each of the pixels PXL may be a minimum unit for displaying an image. Each of the pixels PXL may emit white light and / or colored light. Each pixel PXL may emit one of red, green, blue, and white light. However, the pixels may emit light of different colors such as cyan, magenta, and yellow.

[0039] Each of the pixels PXL may be a light emitting element including an organic light emitting layer. However, the pixel PXL is not limited thereto. For example, the pixel PXL may be embodied in various forms such as a liquid crystal element, an electrophoretic element, an electrowetting element, and the like.

[0040] In some exemplary embodiments of the present disclosure, the pixels PXL may be arranged in a matrix form including rows extending in a first direction DR1 and columns extending in a second direction DR2. However, the arrangement of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in various other forms. For example, the pixels PXL may be arranged so that the row direction is inclined with respect to the column direction.

[0041] The pixel PXL may include a first pixel G for displaying green, a second pixel R for displaying red, and a third pixel B for displaying blue.

[0042] The first pixel G may be arranged in the second direction DR2 to form a first pixel column. The second pixel R and the third pixel B may be alternately arranged in the second direction DR2 to form a second pixel column. The first pixel column and the second pixel column may be provided in plurality and alternately arranged along the first direction DR1. Each pixel column may be connected to a data line DL.

[0043] The arrangement structure of the first pixel G, the second pixel R, and the third pixel B may correspond to a pan-tiled matrix pixel PXL structure that applies a rendering operation of sharing adjacent pixels PXL and expressing colors so that a desired resolution can be achieved with a smaller number of pixels PXL.

[0044] In some exemplary embodiments of the present disclosure, the first pixel G, the second pixel R, and the third pixel B have the same area, but according to other methods, different types of pixels may have different areas.

[0045] The wiring portion LP may be arranged in the non-display area NDA and may be connected to the pixel PXL. The wiring portion LP may supply a signal to each pixel PXL and may include a fan-out line connected to the data line DL and a power line configured to apply power to each pixel PXL of the display area DA. The wiring portion LP may further include other lines as needed.

[0046] In some exemplary embodiments of the present disclosure, the non-display area NDA may further include an additional area ADA protruding from a portion of the non-display area NDA. The additional area ADA may protrude from a side of the non-display area NDA. The additional area ADA may be a fan-out area FTA. A wiring portion LP electrically connected to a data line DL arranged in each pixel PXL may be provided in the fan-out area FTA.

[0047] The driver may be mounted on a driving circuit board. The driver may supply a signal to each pixel PXL through a wiring portion LP. The driver may include a gate driver for supplying a scan signal to each pixel PXL, a data driver DDV for supplying a data signal to each pixel PXL along a data line DL, a timing controller for controlling the gate driver and the data driver DDV, and the like.

[0048] The driving circuit board may include a chip on film COF connected to the substrate SUB and a printed circuit board connected to the COF.

[0049] The COF may process various signals input from the printed circuit board and output the processed signals to the substrate SUB. One end of the COF may be attached to the substrate SUB, and the other end of the COF may be attached to the printed circuit board.

[0050] The data driver DDV may be directly mounted on the substrate SUB, but the data driver DDV may alternatively be mounted at other locations. For example, the data driver DDV may be formed on a separate chip and connected to the substrate SUB. In some exemplary embodiments of the present disclosure, the data driver DDV may be formed on a separate chip and then mounted on a COF. The data signal of the data driver DDV may be applied to the data line DL of the display area DA through the wiring portion LP.

[0051] In some exemplary embodiments of the present disclosure, at least a portion of the display device may be flexible and / or foldable. For example, the display device may include a curved area BA, and flat areas FA1 and FA2 that are arranged on at least one side of the curved area BA and are flat and not folded. The flat areas FA1 and FA2 may be flexible or rigid.

[0052] In some exemplary embodiments of the present disclosure, the bending area BA is shown to be arranged in the additional area ADA. The flat areas FA1 and FA2 may include a first flat area FA1 and a second flat area FA2 spaced apart from each other, and the bending area BA is between the first flat area FA1 and the second flat area FA2. The first flat area FA1 may include the display area DA. Therefore, the bending area BA may be spaced apart from the display area DA.

[0053] When a line folded by the display device is referred to as a folding line, the folding line may be arranged in the bending area BA. The term "foldable" or "foldable" as used herein is intended to mean that the shape is not fixed but can be modified from its original shape to another shape and can be folded, bent or curled along one or more specific lines (e.g., folding lines). Figure 2 As shown in , the display device can be folded so that the two flat areas FA1 and FA2 are parallel to each other and face each other. However, the folded state of the flat areas FA1 and FA2 can be set separately. For example, the display device can be folded so that the faces of the two flat areas FA1 and FA2 can be at a predetermined angle (e.g., an acute angle, a right angle, or an obtuse angle), and the curved area BA is inserted between the two flat areas FA1 and FA2.

[0054] In some exemplary embodiments of the present disclosure, the additional area ADA may be bent along the folding line, whereby the width of the bezel of the display device may be reduced as viewed in a plan view.

[0055] Figure 3 The diagram is included in Figure 1 A block diagram of an example of multiple pixels and drivers in a display device.

[0056] Reference Figure 1 and Figure 3, the display device may include a pixel PXL, a driver, and a wiring portion.

[0057] The driver may include a scan driver SDV, an emission driver EDV, a data driver DDV, and a timing controller TC. Figure 3 , the positions of the scan driver SDV, the emission driver EDV, the data driver DDV, and the timing controller TC are shown in one possible configuration. In an embodiment of the display device, each driver may be arranged at other positions within the display device.

[0058] The wiring portion may be arranged in the display area DA and may include a plurality of scan lines S1 to Sn, a plurality of data lines D1 to Dm, emission control lines E1 to En, a power line PL, and an initialization power line for supplying a signal from a driver to the pixel PXL.

[0059] The pixels PXL may be arranged in the display area DA. When a scan signal is applied to a corresponding scan line, each pixel PXL may receive a data signal from a corresponding data line. The pixel PXL receiving the data signal may control a current flowing from a first power source ELVDD provided through a power source line PL to a second power source ELVSS via a light emitting element.

[0060] The scan driver SDV may apply the scan signal to the scan lines S1 to Sn in response to the first gate control signal GCS1 from the timing controller TC. For example, the scan driver SDV may sequentially apply the scan signal to the scan lines S1 to Sn. When the scan signal is sequentially supplied to the scan lines S1 to Sn, the pixels PXL may be sequentially selected in units of horizontal lines.

[0061] The emission driver EDV may apply the emission control signal to the emission control lines E1 to En in response to the second gate control signal GCS2 from the timing controller TC. For example, the emission driver EDV may sequentially supply the emission control signal to the emission control lines E1 to En.

[0062] The emission control signal may be set to be wider than the scan signal. For example, at least a portion of the emission control signal supplied to the i-th (where "i" is a natural number) emission control line Ei may overlap with the scan signal supplied to the (i-1)th scan line Si-1 and the i-th scan line Si. In addition, the emission control signal may be set to a gate-off voltage (e.g., a high voltage) so that the transistor included in the pixel PXL may be turned off, and the scan signal may be set to a gate-on voltage (e.g., a low voltage) so that the included transistor may be turned on.

[0063] The data driver DDV may apply data signals to the data lines D1 to Dm in response to the data control signal DCS. The data signals supplied to the data lines D1 to Dm may be supplied to the pixels PXL selected by the scan signal.

[0064] The timing controller TC may apply the generated gate control signals GCS1 and GCS2 to the scan driver SDV and the emission driver EDV based on an externally supplied timing signal, and may apply the data control signal DCS to the data driver DDV.

[0065] Each of the gate control signals GCS1 and GCS2 may include a start pulse and a clock signal. The start pulse controls the timing of the first scan signal or the timing of the first emission control signal. The clock signal is used to shift the start pulse.

[0066] The data control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the sampling start time of the data, and the clock signal may be used to control the sampling operation.

[0067] Figure 4 It is a graphic Figure 3 For ease of description, the equivalent circuit diagram of an example of a pixel among the pixels of Figure 4 The figure shows a pixel PXL connected to the j-th data line Dj, the (i-1)-th scan line Si-1, the i-th scan line Si, and the (i+1)-th scan line Si+1.

[0068] Reference Figure 3 and Figure 4 , the pixel PXL may include a light emitting element OLED, first to seventh transistors T1 to T7 , and a storage capacitor Cst.

[0069] The anode electrode of the light emitting element OLED may be connected to the first transistor T1 via the sixth transistor T6, and the cathode electrode of the light emitting element OLED may be connected to the second power source ELVSS. The light emitting element OLED may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor T1. The first power source ELVDD applied to the power line PL may be set to a voltage higher than the second power source ELVSS so that current may flow through the light emitting element OLED.

[0070] The source electrode of the first transistor T1 (e.g., the driving transistor) may be connected to the first power source ELVDD via the fifth transistor T5. The drain electrode of the first transistor T1 may be connected to the anode electrode of the light emitting element OLED. The first transistor T1 may control a current flowing from the first power source ELVDD to the second power source ELVSS via the light emitting element OLED in response to a voltage of the first node N1 (e.g., the gate electrode of the first transistor T1).

[0071] The second transistor T2 (e.g., a switching transistor) may be connected between the jth data line Dj and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line Si. When a scan signal is applied to the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1.

[0072] The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the i-th scan line Si. When the scan signal is supplied to the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may have a diode-connected state.

[0073] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be connected to the (i-1)th scan line Si-1. When the scan signal is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 may be turned on to transmit the voltage of the initialization power supply Vint to the first node N1. The initialization power supply Vint may be set to a voltage lower than the data signal.

[0074] The fifth transistor T5 may be connected between the first power source ELVDD and the source electrode of the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the i-th emission control line Ei. The fifth transistor T5 may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0075] The sixth transistor T6 may be connected between the drain electrode of the first transistor T1 and the anode electrode of the light emitting element OLED. The gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0076] The seventh transistor T7 may be connected between the initialization power supply Vint and the anode electrode of the light emitting element OLED. The gate electrode of the seventh transistor T7 may be connected to the (i+1)th scan line Si+1. When the scan signal is provided to the (i+1)th scan line Si+1, the seventh transistor T7 may be turned on to transmit the voltage of the initialization power supply Vint to the anode electrode of the light emitting element OLED.

[0077] The storage capacitor Cst may be connected between the first power source ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal and a threshold voltage of the first transistor T1.

[0078] Figure 5 It is a graphic Figure 4 A plan view of an example of a pixel. Figure 6 It is along Figure 5 A cross-sectional view taken along section line AA'. Figure 7 It is along Figure 5 A cross-sectional view taken along section line BB'.

[0079] exist Figures 5 to 7 In FIG. 5 , three scan lines Si−1, Si, and Si+1, an emission control line Ei, a power line PL, and a data line Dj are connected to a single pixel PXL disposed at an i-th row and a j-th column.

[0080] In order to facilitate Figures 5 to 7 For explanation, the scan line in the (i-1)th row is called the (i-1)th scan line Si-1, the scan line in the i-th row is called the i-th scan line Si, the scan line in the (i+1)th row is called the (i+1)th scan line Si+1, the emission control line in the i-th row is called the emission control line Ei, the data line in the j-th column is called the data line Dj, and the power line in the j-th column is called the power line PL.

[0081] Reference Figures 4 to 7 , the display device may include a substrate SUB, a wiring portion, and a pixel PXL.

[0082] The substrate SUB may include a transparent insulating material configured to transmit light. The substrate SUB may be a rigid substrate or a flexible substrate. The rigid substrate may include glass, quartz, glass-ceramic and / or crystallized glass. The flexible substrate may be a film substrate including a polymer organic material and / or plastic. For example, the flexible substrate may be formed of polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and / or cellulose acetate propionate (CAP). In addition, the flexible substrate may include fiberglass reinforced plastic (FRP).

[0083] The material applied to the substrate SUB may preferably have sufficient heat resistance to support high processing temperatures in the manufacturing process of the display device. In some exemplary embodiments of the present disclosure, the substrate SUB may be completely or at least partially flexible.

[0084] The wiring portion may provide a signal to the pixel PXL, and may include scan lines Si-1, Si, and Si+1, a data line Dj, an emission control line Ei, a power line PL, and an initialization power line IPL.

[0085] The scan lines Si-1, Si, and Si+1 may extend in a first direction DR1. The scan lines Si-1, Si, and Si+1 may be sequentially arranged along a second direction DR2 intersecting the first direction DR1. Scan signals may be applied to the scan lines Si-1, Si, and Si+1. For example, the (i-1)th scan signal may be applied to the (i-1)th scan line Si-1, the i-th scan signal may be applied to the i-th scan line Si, and the (i+1)th scan signal may be applied to the (i+1)th scan line Si+1.

[0086] In some exemplary embodiments of the present disclosure, three scan lines Si-1, Si and Si+1 are shown for applying scan signals to the pixel PXL, but other numbers of scan lines may be used. For example, the scan signal may be applied to the pixel PXL via two scan lines Si-1 and Si. In this example, the i-th scan line Si among the two scan lines Si-1 and Si may be branched into two lines, and the branched i-th scan line Si may be connected to different transistors. For example, the i-th scan line Si may include an upper i-th scan line adjacent to the (i-1)-th scan line Si-1, and a lower i-th scan line that is farther from the (i-1)-th scan line Si-1 than the upper i-th scan line.

[0087] The emission control line Ei may extend in the first direction DR1 and be disposed between the i-th scan line Si and the (i+1)-th scan line Si+1. The emission control line Ei may be spaced apart from the (i+1)-th scan line Si+1 and the i-th scan line Si. An emission control signal may be applied to the emission control line Ei.

[0088] The data lines Dj may extend in the second direction DR2 and may be sequentially disposed along the first direction DR1. A data signal may be applied to the data lines Dj.

[0089] The power line PL may extend in the second direction DR2. The power line PL may be spaced apart from the data line Dj. The first power source ELVDD may be applied to the power line PL.

[0090] The initialization power line IPL may extend along the first direction DR1. The initialization power line IPL may be disposed between the (i+1)th scan line Si+1 and the (i-1)th scan line Si-1 of the next row of pixels. The initialization power Vint may be applied to the initialization power line IPL.

[0091] The pixel PXL may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting element OLED.

[0092] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , a first drain electrode DE1 , and a first connection line CNL1 .

[0093] The first gate electrode GE1 may be connected to the third drain electrode DE3 of the third transistor T3 and the fourth drain electrode DE4 of the fourth transistor T4. The first connection line CNL1 may connect the first gate electrode GE1, the third drain electrode DE3, and the fourth drain electrode DE4. One end of the first connection line CNL1 may be connected to the first gate electrode GE1 through the first contact hole CH1, and the other end of the first connection line CNL1 may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through the second contact hole CH2.

[0094] In some exemplary embodiments of the present disclosure, each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor layer in which impurities are not doped or doped. For example, the first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor layer doped with impurities, and the first active pattern ACT1 may include a semiconductor layer in which impurities are not doped.

[0095] The first active pattern ACT1 may have a strip shape extending mainly in a predetermined direction, and may be bent one or more times along the extended longitudinal direction. When viewed in a plan view, the first active pattern ACT1 may overlap with the first gate electrode GE1. The channel region of the first transistor T1 may be relatively long by forming the first active pattern ACT1 to be long. Therefore, the driving range of the gate voltage applied to the first transistor T1 may be widened. Thus, the grayscale of the light emitted from the organic light emitting element OLED may be finely controlled.

[0096] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may be connected to the third source electrode SE3 of the third transistor T3 and the sixth source electrode SE6 of the sixth transistor T6.

[0097] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0098] The second gate electrode GE2 may be connected to the i-th scan line Si. The second gate electrode GE2 may be a portion of the i-th scan line Si or may protrude from the i-th scan line Si.

[0099] In some exemplary embodiments of the present disclosure, each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of a semiconductor layer that has been doped or has not been doped. For example, the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor layer doped with impurities, and the second active pattern ACT2 may include a semiconductor layer in which impurities are not doped.

[0100] The second active pattern ACT2 may correspond to a portion overlapping the second gate electrode GE2. The second source electrode SE2 may have one end connected to the second active pattern ACT2 and the other end connected to the data line Dj through the sixth contact hole CH6. The second drain electrode DE2 may have one end connected to the second active pattern ACT2 and the other end connected to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0101] The third transistor T3 may have a dual-gate structure configured to prevent leakage current. For example, the third transistor T3 may include a 3a transistor T3a and a 3b transistor T3b. The 3a transistor T3a may include a 3a gate electrode GE3a, a 3a active pattern ACT3a, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor T3b may include a 3b gate electrode GE3b, a 3b active pattern ACT3b, a 3b source electrode SE3b, and a 3b drain electrode DE3b. For ease of explanation, the 3a gate electrode GE3a and the 3b gate electrode GE3b are referred to as the third gate electrode GE3, the 3a active pattern ACT3a and the 3b active pattern ACT3b are referred to as the third active pattern ACT3, the 3a source electrode SE3a and the 3b source electrode SE3b are referred to as the third source electrode SE3, and the 3a drain electrode DE3a and the 3b drain electrode DE3b are referred to as the third drain electrode DE3.

[0102] The third gate electrode GE3 may be connected to the i-th scan line Si. The third gate electrode GE3 may be a portion of the i-th scan line Si or may protrude from the i-th scan line Si.

[0103] Each of the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be formed of a semiconductor layer that has been doped or has not been doped. For example, the third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor layer doped with impurities, and the third active pattern ACT3 may include a semiconductor layer in which impurities are not doped. The third active pattern ACT3 may correspond to a portion overlapping the third gate electrode GE3.

[0104] One end of the third source electrode SE3 may be connected to the third active pattern ACT3. The other end of the third source electrode SE3 may be connected to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 may be connected to the third active pattern ACT3. The other end of the third drain electrode DE3 may be connected to the fourth drain electrode DE4 of the fourth transistor T4. The third drain electrode DE3 may be electrically connected to the first gate electrode GE1 of the first transistor T1 through the first connection line CNL1, the second contact hole CH2, and the first contact hole CH1.

[0105] The fourth transistor T4 may have a dual-gate structure configured to prevent leakage current. For example, the fourth transistor T4 may include a 4a-th transistor T4a and a 4b-th transistor T4b. The 4a-th transistor T4a may include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a. The 4b-th transistor T4b may include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. In some exemplary embodiments of the present disclosure, for ease of explanation, the 4a gate electrode GE4a and the 4b gate electrode GE4b are referred to as the fourth gate electrode GE4, the 4a active pattern ACT4a and the 4b active pattern ACT4b are referred to as the fourth active pattern ACT4, the 4a source electrode SE4a and the 4b source electrode SE4b are referred to as the fourth source electrode SE4, and the 4a drain electrode DE4a and the 4b drain electrode DE4b are referred to as the fourth drain electrode DE4.

[0106] The fourth gate electrode GE4 may be connected to the (i-1)th scan line Si-1. The fourth gate electrode GE4 may be a portion of the (i-1)th scan line Si-1 or may protrude from the (i-1)th scan line Si-1.

[0107] Each of the fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 may be formed of a semiconductor layer that has been doped or has not been doped. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 may be formed of a semiconductor layer doped with impurities, and the fourth active pattern ACT4 may be formed of a semiconductor layer in which impurities are not doped. The fourth active pattern ACT4 may correspond to a portion overlapping the fourth gate electrode GE4.

[0108] One end of the fourth source electrode SE4 may be connected to the fourth active pattern ACT4. The other end of the fourth source electrode SE4 may be connected to the initialization power line IPL of the pixel PXL in the (i-1)th row and the seventh drain electrode DE7 of the seventh transistor T7 of the pixel PXL. The auxiliary connection line AUX may be arranged between the fourth source electrode SE4 and the initialization power line IPL. One end of the auxiliary connection line AUX may be connected to the fourth source electrode SE4 through the ninth contact hole CH9. The other end of the auxiliary connection line AUX may be connected to the initialization power line of the pixel PXL in the (i-1)th row through the eighth contact hole CH8 of the pixel PXL in the (i-1)th row. One end of the fourth drain electrode DE4 may be connected to the fourth active pattern ACT4. The other end of the fourth drain electrode DE4 may be connected to the third drain electrode DE3 of the third transistor T3. The fourth drain electrode DE4 may also be connected to the first gate electrode GE1 of the first transistor T1 through the first connection line CNL1, the second contact hole CH2, and the first contact hole CH1.

[0109] The fifth transistor T5 may include a fifth gate electrode GE5 , a fifth active pattern ACT5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0110] The fifth gate electrode GE5 may be connected to the emission control line Ei. The fifth gate electrode GE5 may be a part of the emission control line Ei or may protrude from the emission control line Ei. Each of the fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 may be formed of a doped or undoped semiconductor layer. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 may be formed of a semiconductor layer in which impurities are not doped. The fifth active pattern ACT5 may correspond to a portion overlapping with the fifth gate electrode GE5.

[0111] One end of the fifth source electrode SE5 may be connected to the fifth active pattern ACT5. The other end of the fifth source electrode SE5 may be connected to the power line PL through the fifth contact hole CH5. One end of the fifth drain electrode DE5 may be connected to the fifth active pattern ACT5. The other end of the fifth drain electrode DE5 may be connected to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0112] The sixth transistor T6 may include a sixth gate electrode GE6 , a sixth active pattern ACT6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0113] The sixth gate electrode GE6 may be connected to the emission control line Ei. The sixth gate electrode GE6 may be a part of the emission control line Ei or may protrude from the emission control line Ei. Each of the sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 is formed of a doped or undoped semiconductor layer. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 may be formed of a semiconductor layer doped with impurities, and the sixth active pattern ACT6 may be formed of a semiconductor layer in which impurities are not doped. The sixth active pattern ACT6 may correspond to a portion overlapping with the sixth gate electrode GE6.

[0114] One end of the sixth source electrode SE6 may be connected to the sixth active pattern ACT6. The other end of the sixth source electrode SE6 may be connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 may be connected to the sixth active pattern ACT6. The other end of the sixth drain electrode DE6 may be connected to the seventh source electrode SE7 of the seventh transistor T7.

[0115] The seventh transistor T7 may include a seventh gate electrode GE7 , a seventh active pattern ACT7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 .

[0116] The seventh gate electrode GE7 may be connected to the (i+1)th scan line Si+1. The seventh gate electrode GE7 may be a portion of the (i+1)th scan line Si+1 or may protrude from the (i+1)th scan line Si+1. Each of the seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of a doped or undoped semiconductor layer. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor layer doped with impurities, and the seventh active pattern ACT7 may be formed of a semiconductor layer in which impurities are not doped. The seventh active pattern ACT7 may correspond to a portion overlapping with the seventh gate electrode GE7.

[0117] One end of the seventh source electrode SE7 may be connected to the seventh active pattern ACT7. The other end of the seventh source electrode SE7 may be connected to the sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 may be connected to the seventh active pattern ACT7. The other end of the seventh drain electrode DE7 may be connected to the initialization power line IPL. The seventh drain electrode DE7 may be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL disposed in the (i+1)th row. The seventh drain electrode DE7 may be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL disposed in the (i+1)th row through the auxiliary connection line AUX, the eighth contact hole CH8, and the ninth contact hole CH9.

[0118] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be the first gate electrode GE1 of the first transistor T1.

[0119] When viewed in a plan view, the upper electrode UE may overlap with and cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area of ​​the upper electrode UE and the lower electrode LE. The upper electrode UE may extend in the first direction DR1. In some exemplary embodiments of the present disclosure, a voltage of the same level as that of the first power supply ELVDD may be applied to the upper electrode UE. The upper electrode UE may have an opening OPN in a region where the first contact hole CH1 is formed, and the first gate electrode GE1 and the first connection line CNL1 are connected to the first contact hole CH1.

[0120] The organic light emitting element OLED may include a first electrode AD, a second electrode CD, and a light emitting layer EML disposed between the first electrode AD and the second electrode CD.

[0121] The first electrode AD may be arranged in the light emitting region corresponding to the pixel PXL. The first electrode AD may be connected to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7 and the tenth contact hole CH10. The second connection line CNL2 and the bridge pattern BRP may be arranged between the seventh contact hole CH7 and the tenth contact hole CH10 so that the sixth drain electrode DE6 and the seventh source electrode SE7 may be connected to the first electrode AD.

[0122] In the following, reference will be made to Figures 5 to 7 A structure of a display device according to an exemplary embodiment of the present disclosure is described.

[0123] The buffer layer BFL may be disposed on the substrate SUB.

[0124] The buffer layer BFL may prevent impurities from diffusing into the first to seventh transistors T1 to T7. The buffer layer BFL may be a single layer, but may alternatively include two or more layers. When the buffer layer BFL includes multiple layers, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material and / or process conditions of the substrate SUB.

[0125] Active patterns ACT1 to ACT7 (hereinafter referred to as ACT) may be disposed on the buffer layer BFL. The active patterns ACT may include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 may be formed of a semiconductor material.

[0126] The gate insulating layer GI may be disposed on the buffer layer BFL and the active pattern ACT. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include silicon nitride, silicon oxide, and / or silicon oxynitride.

[0127] The (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei, and the first gate electrode GE1 to the seventh gate electrode GE7 may be arranged on the gate insulating layer GI. The first gate electrode GE1 may be the lower electrode LE of the storage capacitor Cst. The second gate electrode GE2 and the third gate electrode GE3 may be formed integrally with the i-th scan line Si. The fourth gate electrode GE4 may be formed integrally with the (i-1)th scan line Si-1, and the seventh gate electrode GE7 may be formed integrally with the (i+1)th scan line Si+1. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be formed integrally with the emission control line Ei.

[0128] The first insulating layer IL1 may be disposed on the substrate SUB on which the scan lines Si-1, Si, Si+1, etc. are disposed.

[0129] An upper electrode of the storage capacitor Cst and the initialization power line IPL may be disposed on the first insulating layer IL1. The upper electrode UE may cover the lower electrode LE. The upper electrode UE may form a storage capacitor Cst together with the lower electrode LE with the first insulating layer IL1 interposed therebetween.

[0130] The second insulating layer IL2 may be disposed on the substrate SUB on which the upper electrode UE and the initialization power line IPL are disposed.

[0131] The first and second connection lines CNL1 and CNL2 and the auxiliary connection line AUX may be disposed on the second insulating layer IL2 .

[0132] The first connection line CNL1 may be connected to the first gate electrode GE1 through a first contact hole CH1 sequentially passing through the first and second insulating layers IL1 and IL2. The first connection line CNL1 is electrically connected to the third and fourth drain electrodes DE3 and DE4 through second contact holes CH2 sequentially passing through the gate insulating layer GI and the first and second insulating layers IL1 and IL2.

[0133] The second connection line CNL2 is a medium between the sixth drain electrode DE6 and the first electrode AD, connecting the sixth drain electrode DE6 and the first electrode AD. The second connection line CNL2 can be electrically connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7 sequentially passing through the gate insulating layer GI and the first insulating layer IL1 and the second insulating layer IL2.

[0134] The auxiliary connection line AUX may be connected to the initialization power line IPL through an eighth contact hole CH8 passing through the second insulating layer IL2. The auxiliary connection line AUX may be electrically connected to the fourth source electrode SE4 and the seventh drain electrode DE7 of the pixel PXL in the (i-1)th row through a ninth contact hole CH9 passing through the gate insulating layer GI and the first insulating layer IL1 and the second insulating layer IL2.

[0135] In some exemplary embodiments of the present disclosure, as shown in the figure, the first connection line CNL1 and the second connection line CNL2 may be arranged on the second insulating layer IL2. However, the arrangement of the first connection line CNL1 and the second connection line CNL2 is not limited thereto. For example, the first connection line CNL1 and the second connection line CNL2 may be arranged on the third insulating layer IL3 described below.

[0136] The third insulating layer IL3 may be arranged on the first connection line CNL1 and the second connection line CNL2 and the auxiliary connection line AUX. The third insulating layer IL3 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In some exemplary embodiments of the present disclosure, the third insulating layer IL3 may be an organic insulating layer. The third insulating layer IL3 may be a single layer as shown in the figure, but other arrangements may be used. For example, the third insulating layer IL3 may be formed of multiple layers. When the third insulating layer IL3 is formed of multiple layers, the third insulating layer IL3 may have a structure in which a plurality of inorganic insulating layers and a plurality of organic insulating layers are alternately stacked. For example, the third insulating layer IL3 may have a structure in which a first organic insulating layer, an inorganic insulating layer, and a second organic insulating layer are sequentially stacked.

[0137] The bridge pattern BRP, the data line Dj, and the power line PL may each be disposed on the third insulating layer IL3.

[0138] The bridge pattern BRP may be connected to the second connection line CNL2 through a tenth contact hole CH10 passing through the third insulating layer IL3 .

[0139] The data line Dj may be electrically connected to the second source electrode SE2 through a sixth contact hole CH6 penetrating the gate insulating layer GI and the first to third insulating layers IL1 to IL3. Figure 7 As illustrated in FIG. 1 , the data line Dj may be arranged on the third insulating layer IL3 , but other arrangements may be used. For example, the data line Dj may be arranged on the second insulating layer IL2 and on the same layer as the first and second connection lines CNL1 and CNL2 .

[0140] The power line PL may be connected to the upper electrode UE through the third contact hole CH3 and the fourth contact hole CH4 passing through the second insulating layer IL2 and the third insulating layer IL3. The power line PL may be electrically connected to the fifth source electrode SE5 through the fifth contact hole CH5 passing through the gate insulating layer GI and the first insulating layer IL1 to the third insulating layer IL3. Figure 6 As illustrated in FIG. 1 , the power line PL may be arranged on the third insulating layer IL3 , but other arrangements may be used. For example, the power line PL may be arranged on the second insulating layer IL2 and on the same layer as the first and second connection lines CNL1 and CNL2 .

[0141] The first electrode AD may be disposed on the bridge pattern BRP. The first electrode AD may be connected to the bridge pattern BRP through the eleventh contact hole CH11 passing through the passivation layer PSV. Since the bridge pattern BRP is connected to the second connection line CNL2 through the tenth contact hole CH10, the first electrode AD may be finally connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the bridge pattern BRP and the second connection line CNL2.

[0142] The pixel defining layer PDL may be disposed on the substrate SUB on which the first electrode AD is formed to define a light emitting region corresponding to each pixel PXL. The pixel defining layer PDL may expose an upper surface of the first electrode AD and may protrude from the substrate SUB along a periphery of the pixel PXL.

[0143] The light emitting layer EML may be disposed on the exposed upper surface of the first electrode AD. The second electrode CD may be disposed on the light emitting layer EML.

[0144] The pixel defining layer PDL may include an organic insulating material. For example, the pixel defining layer PDL may be formed of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide, polyarylether, heterocyclic polymer, polyparaxylene, epoxy resin, benzocyclobutene (BCB), siloxane-based resin and / or silane-based resin, etc.

[0145] The light-emitting layer EML may be arranged on the exposed upper surface of the first electrode AD. The light-emitting layer EML may have a multilayer thin film structure including at least a light-generating layer. For example, the light-emitting layer EML may include a hole injection layer for injecting holes, a hole transport layer for increasing the recombination opportunity of holes and electrons, a light-generating layer for emitting light by recombination of injected electrons and holes, a hole blocking layer for suppressing the movement of holes that are not coupled in the light-generating layer, an electron transport layer for smoothly transporting electrons to the light-generating layer, and an electron injection layer for injecting electrons.

[0146] The color of light generated in the light generating layer may be one of red, green, blue and white, but other colors may also be generated. For example, the color of light generated in the light generating layer of the light emitting layer EML may be one of magenta, cyan and yellow.

[0147] The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be common layers connected to each other in adjacent light emitting regions.

[0148] A thin film encapsulation TFE covering the second electrode CD may be disposed on the second electrode CD.

[0149] The thin film encapsulation TFE may be composed of a single layer, but may alternatively include multiple layers. The thin film encapsulation TFE may include multiple insulating layers covering the light emitting element OLED. For example, the thin film encapsulation TFE may include multiple inorganic layers and multiple organic layers. For example, the thin film encapsulation TFE may have a structure in which inorganic layers and organic layers are alternately stacked. In some exemplary embodiments of the present disclosure, the thin film encapsulation TFE may be an encapsulation substrate arranged on the light emitting element OLED and bonded to the substrate SUB through a sealant.

[0150] The display device may further include a touch sensor arranged on the thin film encapsulation TFE. The touch sensor may be arranged on the surface of the substrate SUB in the direction of emitting the image to receive a user's touch input. A touch event input to the display device may be recognized by a user's hand or another input tool.

[0151] The touch sensor may be driven by a mutual capacitance method. The mutual capacitance method senses the capacitance change due to the interaction between two touch sensing electrodes. In addition, the touch sensor may be driven by a self-capacitance method. The self-capacitance method uses touch sensing electrodes arranged in a matrix form and a sensing line connected to each of the touch sensing electrodes to sense the capacitance change of the sensing electrodes in the touched area.

[0152] The touch sensor may include a touch sensing electrode, a sensing line connected to the touch sensing electrode, and a pad portion connected to an end of the sensing line.

[0153] A window for protecting the exposed surface of the touch sensor may be arranged on the touch sensor. The window transmits an image from the substrate SUB and protects the display device from external impact. Therefore, the display device can be prevented from being damaged or malfunctioning due to external impact.

[0154] Figure 8 It is a graphic Figure 1 An enlarged view of an example of area EA1. Fig. 9 It is along Figure 8 A cross-sectional view taken along section line CC'. Fig.10 It is along Figure 8 A sectional view taken along section line D-D'. Fig.11 It is along Figure 8 A cross-sectional view taken along section line EE'.

[0155] Figures 8 to 11 The connection relationship between the lines in the fan-out region of the substrate is shown. For the convenience of explanation, the connection lines connected to the data lines of the display region and the fan-out lines connecting the connection lines and the driver are shown.

[0156] Reference Figures 1 to 11 , the substrate SUB may include a display area DA and a non-display area NDA.

[0157] A plurality of pixels PXL may be arranged in the display area DA.

[0158] Each of the pixels PXL may include first to seventh transistors T1 to T7 , and a light emitting element OLED connected to the first to seventh transistors T1 to T7 to emit light.

[0159] The pixels PXL may be arranged in a matrix form. For example, the pixels PXL may be composed of a plurality of pixel rows and a plurality of pixel columns in the display area DA. The pixel row may include a plurality of pixels PXL arranged in a first direction DR1 and may extend in the first direction DR1. The pixel column may include a plurality of pixels PXL arranged in a second direction DR2 and may extend in the second direction DR2. The pixel columns may be arranged in the first direction DR1.

[0160] In some exemplary embodiments of the present disclosure, the pixel PXL may include a first pixel G for displaying green, a second pixel R for displaying red, and a third pixel B for displaying blue.

[0161] The first pixel G may be arranged in the second direction DR2 to form a first pixel column. The second pixel R and the third pixel B may be alternately arranged in the second direction DR2 to form a second pixel column. The first pixel column and the second pixel column may be provided in plurality and alternately arranged along the first direction DR1. Each pixel column may be connected to a data line DL.

[0162] The first transistor T1 may include a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second transistor T2 may include a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The third transistor T3 may include a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3. The fourth transistor T4 may include a fourth active pattern ACT4, a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4. The fifth transistor T5 may include a fifth active pattern ACT5, a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5. The sixth transistor T6 may include a sixth active pattern ACT6, a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6. The seventh transistor T7 may include a seventh active pattern ACT7, a seventh gate electrode GE7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0163] The non-display area NDA may include a wiring portion LP configured to apply a signal from the data driver DDV to the pixel PXL. The wiring portion LP may be arranged in the fan-out area FTA of the non-display area NDA. The wiring portion LP may include a plurality of connection lines CL and a plurality of fan-out lines FL.

[0164] In some exemplary embodiments of the present disclosure, the fan-out area FTA may include a first area I in which the fan-out line FL is disposed and a second area II in which the connection line CL is disposed. The first area I may be an area adjacent to the data driver DDV in the fan-out area FTA, and the second area II may be an area farther from the data driver DDV than the first area I in the fan-out area FTA.

[0165] Each connection line CL may be a medium for electrically connecting one data line DL arranged in the display area DA and the corresponding fan-out line FL. For example, one end of each connection line CL may be connected to the corresponding one data line DL, and the other end of each connection line CL may be connected to the corresponding one fan-out line FL. One end of each connection line CL may be electrically connected to the corresponding data line DL through a separate contact electrode, but other arrangements may be used. For example, one end of each connection line CL may be integrally formed with the corresponding data line DL and may be directly electrically connected to the corresponding data line DL.

[0166] In the second region II of the fan-out area FTA, the connection lines CL may extend in the second direction DR2. The connection lines CL may extend approximately in the second direction DR2, and a space between adjacent connection lines CL may become narrower in the second direction DR2.

[0167] Each of the fan-out lines FL may be electrically connected to a corresponding one of the connection lines CL and the data driver DDV. For example, one end of each of the fan-out lines FL may be connected to the corresponding connection line CL, and the other end of each of the fan-out lines FL may be connected to the data driver DDV. The data signal from the data driver DDV may be ultimately supplied to a corresponding one of the data lines DL of the display area DA through each of the fan-out lines FL and the connection line CL.

[0168] In some exemplary embodiments of the present disclosure, the fan-out line FL may include a first fan-out line FL1 and a second fan-out line FL2. The first fan-out line FL1 and the second fan-out line FL2 may be arranged on different layers. For example, the first fan-out line FL1 may be arranged on a first insulating layer IL1 on a substrate SUB, and the second fan-out line FL2 may be arranged under the first insulating layer IL1. When viewed in a plan view, the first fan-out line FL1 and the second fan-out line FL2 may be alternately arranged.

[0169] The first fan-out line FL1 may be connected to the data line DL in the first pixel column. The second fan-out line FL2 may be connected to the data line DL in the second pixel column.

[0170] The wiring portion LP of the non-display area NDA and the pixels PXL of the display area DA may be formed through a mask process using a photoresist pattern.

[0171] The signal lines connected to the first to seventh transistors T1 to T7 and the first to seventh transistors T1 to T7 in each pixel PXL provided in the display area DA may be formed by a mask process using a photoresist pattern. The signal lines may include scan lines (see Figure 5 Si-1, Si and Si+1 in), emission control line (see Figure 5 Ei in), data line DL and power line (see Figure 5 PL in), etc.

[0172] In the non-display area NDA, the wiring portion LP arranged in the fan-out area FTA may be formed through a mask process using a photoresist pattern.

[0173] As described above, in the display area DA where an image is displayed, the number of structures formed using the photoresist pattern may be greater than the number of structures formed using the photoresist pattern in the non-display area NDA. The density of the photoresist pattern may vary depending on the area of ​​the substrate SUB. For example, the photoresist pattern used in the mask process may be disposed in the display area DA to a greater extent than in the non-display area NDA.

[0174] In the non-display area NDA in which the photoresist pattern is arranged at a low density, the amount of photoresist dissolved in the development process may be greater than the amount of photoresist in the display area DA in which the photoresist pattern is arranged at a high density. Therefore, the developer applied to the non-display area NDA may have a reduced concentration, and a concentration difference of the developer between the non-display area NDA and the display area DA may occur. When such a concentration difference occurs, the high-concentration developer may move toward the low-concentration developer by the diffusion principle. Therefore, the photoresist pattern of the non-display area NDA is over-developed (for example, developed in excess of an appropriate amount), and the thickness of the display device becomes uneven. This uneven thickness may cause defects such as short circuits in the wiring portion LP of the non-display area NDA.

[0175] In some exemplary embodiments of the present disclosure, a dummy pattern may be arranged in the non-display area NDA to compensate for the density difference of the photoresist pattern between the display area DA and the non-display area NDA. Therefore, the density of the photoresist pattern may be uniform in the display area DA and the non-display area NDA.

[0176] In some exemplary embodiments of the present disclosure, the dummy pattern may be a dummy active pattern DACT.

[0177] The dummy active pattern DACT may be arranged in the second region II of the fan-out region FTA. The dummy active pattern DACT may be floated. The shape of the dummy active pattern DACT may be as follows: Figure 8 , the dummy active pattern DACT may have various other shapes. For example, the dummy active pattern DACT may be shaped as a polygon, a circle, a semicircle, a semi-ellipse, etc.

[0178] In a plan view, the dummy active pattern DACT may overlap with a plurality of connection lines CL. The dummy active pattern DACT is shown as overlapping with a portion of the plurality of connection lines CL, but other arrangements may be used. In some exemplary embodiments of the present disclosure, the dummy active pattern DACT may be arranged in the second region II so as to overlap with each of the plurality of connection lines CL. The dummy active pattern DACT may be partially or completely connected to the connection line CL within a range that uniformizes the density of the photoresist pattern of the display area DA and the non-display area NDA.

[0179] The dummy active pattern DACT may be disposed on a buffer layer BFL on the substrate SUB. The buffer layer BFL may be a buffer layer provided in the display area DA (see Figure 6 in BFL).

[0180] The dummy active pattern DACT may be a semiconductor pattern including polysilicon, amorphous silicon, an oxide semiconductor, etc. In some exemplary embodiments of the present disclosure, the dummy active pattern DACT may include the same material as the first to seventh active patterns ACT1 to ACT7 and may be arranged on the same layer as the first to seventh active patterns ACT1 to ACT7.

[0181] The gate insulating layer GI may be disposed on the dummy active pattern DACT. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. The inorganic insulating layer may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0182] The second fan-out line FL2 may be arranged on the gate insulating layer GI. In some exemplary embodiments of the present disclosure, the second fan-out line FL2 may include the same material as the scan lines Si-1, Si and Si+1, and the emission control line Ei in each pixel PXL, and may be arranged on the same layer as the scan lines Si-1, Si and Si+1, and the emission control line Ei. The second fan-out line FL2 may be arranged on the same layer as the first gate electrode GE1 to the seventh gate electrode GE7.

[0183] The first insulating layer IL1 may be disposed on the second fan-out line FL2. The first insulating layer IL1 may include the same material as the gate insulating layer GI, but other materials may be used.

[0184] The first fan-out line FL1 may be disposed on the first insulating layer IL1. In some exemplary embodiments of the present disclosure, the first fan-out line FL1 may include the same material as the upper electrode UE of the storage capacitor Cst disposed in each pixel PXL, and may be disposed on the same layer as the upper electrode UE. In addition, the first fan-out line FL1 may include the same material as the initialization power line IPL disposed in each pixel PXL, and may be disposed on the same layer as the initialization power line IPL.

[0185] The second insulating layer IL2 may be disposed on the first fan-out line FL1. The second insulating layer IL2 may include the same material as the first insulating layer IL1 and the gate insulating layer GI, but other materials may be used.

[0186] The connection line CL may be disposed on the second insulating layer IL2. In some exemplary embodiments of the present disclosure, the connection line CL may include the same material and be disposed on the same layer as the first and second connection lines CNL1 and CNL2 disposed in each pixel PXL.

[0187] In some exemplary embodiments of the present disclosure, Fig.10 As shown in FIG. 1 , the first fan-out line FL1 may be connected to the corresponding connection line CL through the first through hole TH1 passing through the second insulating layer IL2. Therefore, the data signal applied to the first fan-out line FL1 from the data driver DDV may be transmitted to the connection line CL electrically connected to the first fan-out line FL1. As a result, the data signal transmitted to the connection line CL may be finally applied to the data line DL corresponding to the connection line CL.

[0188] like Fig.11 As shown in FIG. 1 , the second fan-out line FL2 may be electrically connected to the corresponding connection line CL through the second through hole TH2 sequentially passing through the first insulating layer IL1 and the second insulating layer IL2. Therefore, the data signal applied to the second fan-out line FL2 from the data driver DDV may be transmitted to the connection line CL electrically connected to the second fan-out line FL2. As a result, the data signal transmitted to the connection line CL may be finally applied to the data line DL corresponding to the connection line CL.

[0189] The third insulating layer IL3 may be disposed on the connection line CL. The third insulating layer IL3 may be disposed in the display area DA.

[0190] In some exemplary embodiments of the present disclosure, the dummy active pattern DACT may be formed by the same process as the first to seventh active patterns ACT1 to ACT7 included in each pixel PXL. For example, the dummy active pattern DACT may be added to the fan-out area FTA by a mask process using a photoresist pattern in the same manner as the first to seventh active patterns ACT1 to ACT7.

[0191] Since a separate photoresist pattern is added to the non-display area NDA to form a dummy active pattern DACT in the fan-out area FTA, the density of the photoresist pattern in the non-display area NDA can be increased. Therefore, the density of the photoresist pattern in the non-display area NDA can be made similar to the density of the photoresist pattern in the display area DA. The dummy active pattern DACT can be formed in various shapes within a range in which the density of the photoresist pattern in the non-display area NDA can be increased by widening the area overlapping the connection line CL.

[0192] As described above, the display device according to the exemplary embodiment of the present disclosure may include the dummy active pattern DACT in the non-display area NDA so that defects due to the density difference between the display area DA and the non-display area NDA can be prevented. As a result, the reliability of the display device can be improved.

[0193] Fig.12 It is a graphic with Figure 1 A plan view of an example of a fan-out region corresponding to region EA1. Fig.13 It is along Fig.12 A cross-sectional view taken along section line F-F'. Fig.14 It is along Fig.12 A cross-sectional view taken along section line G-G'. Fig.15 It is along Fig.12 The same reference numerals may refer to the same reference numerals as those in the above description. Figures 1 to 11 Elements described are identical or similar elements, and it can be assumed that any omitted details may be at least similar to the elements described above with respect to the corresponding elements.

[0194] Figures 12 to 15 The connection relationship between the lines in the fan-out region of the substrate is shown. For the convenience of explanation, the connection lines connected to the data lines of the display region and the fan-out lines connecting the connection lines and the driver are shown.

[0195] Reference Figures 1 to 7 as well as Figures 12 to 15 , the substrate SUB may include a display area DA and a non-display area NDA.

[0196] A plurality of pixels PXL may be arranged in the display area DA. Each pixel PXL may include a first transistor T1 to a seventh transistor T7, a light emitting element OLED connected to the first transistor T1 to the seventh transistor T7 for emitting light, and a signal line for transmitting a signal to the first transistor T1 to the seventh transistor T7. The signal line may include a scan line (see Figure 5 Si-1, Si, Si+1), emission control line (see Figure 5 Ei in), data line DL and power line (see Figure 5 PL in), etc.

[0197] The non-display area NDA may include a fan-out area FTA in which a plurality of connection lines CL and a plurality of fan-out lines FL are disposed. In some exemplary embodiments of the present disclosure, the fan-out area FTA may include a second area II in which the connection lines CL are disposed and a first area I in which the fan-out lines FL are disposed.

[0198] Each of the connection lines CL may be a medium for electrically connecting one data line DL arranged in the display area DA and the corresponding fan-out line FL. The connection lines CL may extend in the second direction DR2 in the second area II, and intervals between adjacent connection lines CL may become narrower in the second direction DR2.

[0199] Each of the fan-out lines FL may be a medium for electrically connecting the corresponding connection line CL and the data driver DDV. For example, one end of each fan-out line FL may be connected to the corresponding connection line CL, and the other end of each fan-out line FL may be connected to the data driver DDV. Therefore, the data signal from the data driver DDV may be finally provided to the corresponding one of the data lines DL through the fan-out line FL and the corresponding connection line CL.

[0200] In some exemplary embodiments of the present disclosure, the fan-out line FL may include a first fan-out line FL1 and a second fan-out line FL2. The first fan-out line FL1 and the second fan-out line FL2 may be arranged on different layers. For example, the first fan-out line FL1 may be arranged on a first insulating layer IL1 on a substrate SUB, and the second fan-out line FL2 may be arranged under the first insulating layer IL1. When viewed in a plan view, the first fan-out line FL1 and the second fan-out line FL2 may be alternately arranged.

[0201] The first fan-out line FL1 may be connected to the data line DL in the first pixel column in which the first pixel G emitting green light among the pixels PXL is arranged in the second direction DR2. The second fan-out line FL2 may be connected to the data line DL in the second pixel column. The second pixel column may have a column having a second pixel R arranged in the second direction DR2 and a column having a third pixel B arranged in the second direction DR2. The column having the second pixel R and the column having the third pixel B may be alternately arranged in the first direction DR1.

[0202] The fan-out area FTA may further include a dummy pattern overlapping the fan-out line FL so that the density of the photoresist pattern of the non-display area NDA is similar to that of the display area DA.

[0203] In some exemplary embodiments of the present disclosure, the dummy pattern may be a dummy line DFL including a first dummy line DFL1 and a second dummy line DFL2. In some exemplary embodiments of the present disclosure, the first dummy line DFL1 and the second dummy line DFL2 may be arranged in different layers.

[0204] The first dummy line DFL1 may be arranged in the first region I of the fan-out area FTA and may extend along the second direction DR2. When viewed in a plan view, the first dummy line DFL1 may overlap the first fan-out line FL1. The first dummy line DFL1 may partially overlap the first fan-out line FL1, but other arrangements may be used. For example, the first dummy line DFL1 may completely overlap the first fan-out line FL1.

[0205] In some exemplary embodiments of the present disclosure, the first dummy line DFL1 and the first fan-out line FL1 may be arranged on different layers. The first dummy line DFL1 and the first fan-out line FL1 may overlap each other, and the first insulating layer IL1 and the gate insulating layer GI under the first insulating layer IL1 are interposed between the first dummy line DFL1 and the first fan-out line FL1. The first dummy line DFL1 may be arranged under the first fan-out line FL1.

[0206] The second dummy line DFL2 may be arranged in the first region I of the fan-out area FTA and may extend in the second direction DR2. When viewed in a plan view, the second dummy line DFL2 may overlap the second fan-out line FL2. The second dummy line DFL2 may partially overlap the second fan-out line FL2, but other arrangements may be used. For example, the second dummy line DFL2 may completely overlap the second fan-out line FL2.

[0207] In some exemplary embodiments of the present disclosure, the second dummy line DFL2 and the second fan-out line FL2 may be arranged on different layers. The second dummy line DFL2 and the second fan-out line FL2 may overlap each other, with the first insulating layer IL1 and the second insulating layer IL2 on the first insulating layer IL1 interposed between the second dummy line DFL2 and the second fan-out line FL2. The second dummy line DFL2 may be arranged on the second fan-out line FL2. The second dummy line DFL2 may be designed to have a width greater than that of the second fan-out line FL2 along the first direction DR1 to completely cover the second fan-out line FL2, but other arrangements may be used. For example, the second dummy line DFL2 may be designed to have the same width as the second fan-out line FL2.

[0208] In the following, we will refer to Figures 13 to 15 The stacking order of φ describes the first and second dummy lines DFL1 and DFL2 , the first and second fan-out lines FL1 and FL2 , and the connection line CL.

[0209] First, the buffer layer BFL may be disposed on the substrate SUB.

[0210] The first dummy line DFL1 may be disposed on the buffer layer BFL. The first dummy line DFL1 may be a semiconductor pattern including polysilicon, amorphous silicon, an oxide semiconductor, etc. In some exemplary embodiments of the present disclosure, the first dummy line DFL1 may be formed of the same material as the first to seventh active patterns ACT1 to ACT7 respectively included in the first to seventh transistors T1 to T7, and may be disposed on the same layer as the first to seventh active patterns ACT1 to ACT7.

[0211] A gate insulating layer GI may be disposed on the first dummy line DFL1 .

[0212] The second fan-out line FL2 may be arranged on the gate insulating layer GI. In some exemplary embodiments of the present disclosure, the second fan-out line FL2 may include the same material as the scan lines Si-1, Si and Si+1, and the emission control line Ei arranged in each pixel PXL, and may be arranged on the same layer as the scan lines Si-1, Si and Si+1, and the emission control line Ei. The second fan-out line FL2 may be arranged in the same layer as the first gate electrode GE1 to the seventh gate electrode GE7 included in the first transistor T1 to the seventh transistor T7.

[0213] The first insulating layer IL1 may be disposed on the second fan-out line FL2. The first insulating layer IL1 may include the same material as the gate insulating layer GI, but other materials may be used.

[0214] The first fan-out line FL1 may be disposed on the first insulating layer IL1. In some exemplary embodiments of the present disclosure, the first fan-out line FL1 may include the same material as the upper electrode UE of the storage capacitor Cst in each pixel PXL and may be disposed on the same layer as the upper electrode UE. In addition, the first fan-out line FL1 may include the same material as the initialization power line IPL disposed in each pixel PXL and may be disposed on the same layer as the initialization power line IPL.

[0215] In some exemplary embodiments of the present disclosure, the first fan-out line FL1 may be electrically connected to the first dummy line DFL1 through a first through hole TH1 sequentially passing through the first insulating layer IL1 and the gate insulating layer GI. For example, the first fan-out line FL1 and the first dummy line DFL1 may be electrically connected. Therefore, a data signal applied to the first fan-out line FL1 from the data driver DDV may be transmitted to the first dummy line DFL1 through the first through hole TH1. As a result, the same signal may be applied to the first dummy line DFL1 and the first fan-out line FL1.

[0216] The second insulating layer IL2 may be disposed on the first fan-out line FL1 .

[0217] The connection line CL and the second dummy line DFL2 may be disposed on the second insulating layer IL2. The connection line CL and the second dummy line DFL2 may be disposed on the same layer and may include the same material as the first and second connection lines CNL1 and CNL2 of each pixel PXL.

[0218] In some exemplary embodiments of the present disclosure, the connection line CL disposed in the second region II of the fan-out area FTA may extend along the second direction DR2 and may be connected to the second dummy line DFL2 disposed in the first region I of the fan-out area FTA. The connection line CL and the second dummy line DFL2 may be integrally formed.

[0219] like Fig.14 As illustrated in FIG. 1 , in some exemplary embodiments of the present disclosure, the connection line CL corresponding to the first fan-out line FL1 may be electrically connected to the first fan-out line FL1 through the second through hole TH2 passing through the second insulating layer IL2. Therefore, the data signal applied from the data driver DDV to the first fan-out line FL1 may be applied to the connection line CL corresponding to the first fan-out line FL1 through the second through hole TH2. The data signal transmitted to the connection line CL may be finally transmitted to one data line DL of the display area DA through the connection line CL. As a result, the same data signal may be applied to the first dummy line DFL1, the first fan-out line FL1, the connection line CL, and one data line DL.

[0220] like Fig.15As illustrated in FIG. 1 , in some exemplary embodiments of the present disclosure, the connection line CL corresponding to the second fan-out line FL2 may be electrically connected to the second fan-out line FL2 through a third through hole TH3 sequentially passing through the first insulating layer IL1 and the second insulating layer IL2. Therefore, the data signal applied from the data driver DDV to the second fan-out line FL2 may be applied to the connection line CL corresponding to the second fan-out line FL2 through the third through hole TH3. The data signal transmitted to the connection line CL may be ultimately transmitted to one data line DL of the display area DA through the connection line CL. Since the connection line CL is integrally formed with the second dummy line DFL2, the data signal applied to the connection line CL may be transmitted to the second dummy line DFL2. As a result, the same data signal may be applied to the second dummy line DFL2, the second fan-out line FL2, the connection line CL, and one corresponding data line DL.

[0221] The third insulating layer IL3 may be disposed on the connection line CL and the second dummy line DFL2 .

[0222] Since a separate photoresist pattern is added to the non-display area NDA to form the first and second dummy lines DFL1 and DFL2 in the fan-out area FTA, the density of the photoresist pattern in the non-display area NDA can be increased. Therefore, the density of the photoresist pattern in the non-display area NDA can be made similar to that in the display area DA.

[0223] After the first and second dummy lines DFL1 and DFL2 are arranged in the fan-out area FTA, the density of the photoresist pattern in the display area DA and the density of the photoresist pattern in the non-display area NDA are shown in Table 1 below.

[0224] [Form 1]

[0225]

[0226]

[0227] In the comparative example, the first dummy line DFL1 and the second dummy line DFL2 are omitted. In the inventive example, the first dummy line DFL1 and the second dummy line DFL2 exist.

[0228] As can be seen from Table 1, when the first dummy line DFL1 is arranged in the non-display area NDA, the density of the photoresist pattern in the inventive example is higher than that of the comparative example.

[0229] Similarly, when the second dummy line DFL2 is disposed in the non-display area NDA, the density of the photoresist pattern in the inventive example is higher than that of the comparative example.

[0230] The display device according to an exemplary embodiment of the present disclosure may include the first dummy line DFL1 and the second dummy line DFL2 in the non-display area NDA so that defects caused by the density difference of the photoresist pattern between the display area DA and the non-display area NDA can be prevented. As a result, the reliability of the display device can be improved.

[0231] Fig.16 It is a graphic with Figure 1 A plan view of an example of a fan-out region corresponding to region EA1. Fig.17 It is along Fig.16 A cross-sectional view taken along section line II'. Fig.18 It is along Fig.16 A sectional view taken along section line J-J'. Fig.19 It is along Fig.16 The same reference numerals may be used to refer to the same reference numerals as those used above. Figures 1 to 15 Identical or similar components are described, and to the extent that detailed disclosure of certain elements is omitted, it can be assumed that the details are at least similar to corresponding elements already described.

[0232] Figures 16 to 19 The connection relationship between the lines in the fan-out region of the substrate is shown. For the convenience of explanation, the connection lines connected to the data lines of the display region and the fan-out lines connecting the connection lines and the driver are shown.

[0233] Reference Figures 1 to 7 as well as Figures 16 to 19 , the substrate SUB may include a display area DA and a non-display area NDA.

[0234] A plurality of pixels PXL may be arranged in the display area DA. Each pixel PXL may include a first transistor T1 to a seventh transistor T7, a light emitting element OLED connected to the first transistor T1 to the seventh transistor T7 for emitting light, and a signal line for transmitting a signal to the first transistor T1 to the seventh transistor T7. The signal line may include a scan line (see Figure 5 Si-1, Si, Si+1), emission control line (see Figure 5 Ei in), data line DL and power line (see Figure 5 PL in), etc.

[0235] The non-display area NDA may include a fan-out area FTA in which a plurality of connection lines CL and a plurality of fan-out lines FL are disposed. In some exemplary embodiments of the present disclosure, the fan-out area FTA may include a second area II in which the connection lines CL are disposed and a first area I in which the fan-out lines FL are disposed.

[0236] Each of the connection lines CL may be a medium for electrically connecting one data line DL and a corresponding fan-out line FL arranged in the display area DA.

[0237] Each of the fan-out lines FL may be a medium for electrically connecting the corresponding connection line CL and the data driver DDV.

[0238] In some exemplary embodiments of the present disclosure, the fan-out line FL may include a first fan-out line FL1 and a second fan-out line FL2. The first fan-out line FL1 and the second fan-out line FL2 may be arranged on different layers. When viewed in a plan view, the first fan-out line FL1 and the second fan-out line FL2 may be alternately arranged.

[0239] The first fan-out line FL1 may be connected to the data line DL in the first pixel column in which the first pixel G emitting green light among the pixels PXL is arranged in the second direction DR2. The second fan-out line FL2 may be connected to the data line DL in the second pixel column. The second pixel column may have a column having a second pixel R arranged in the second direction DR2 and a column having a third pixel B arranged in the second direction DR2. The column having the second pixel R and the column having the third pixel B may be alternately arranged in the first direction DR1.

[0240] The fan-out area FTA may further include a dummy pattern overlapping the fan-out line FL so that the density of the photoresist pattern of the non-display area NDA is similar to that of the display area DA.

[0241] In some exemplary embodiments of the present disclosure, the dummy pattern may include a dummy active pattern DACT, a first dummy line DFL1, and a second dummy line DFL2. In some exemplary embodiments of the present disclosure, the dummy active pattern DACT, the first dummy line DFL1, and the second dummy line DFL2 may be arranged in different layers.

[0242] The dummy active pattern DACT may be disposed in the second region II of the fan-out region FTA. The dummy active pattern DACT may float. When viewed in a plan view, the dummy active pattern DACT may overlap with the plurality of connection lines CL.

[0243] The first dummy line DFL1 may be arranged in the first region I of the fan-out area FTA and may extend along the second direction DR2. When viewed in a plan view, the first dummy line DFL1 may overlap with the first fan-out line FL1. In some exemplary embodiments of the present disclosure, the first dummy line DFL1 and the first fan-out line FL1 may be arranged on different layers. The first dummy line DFL1 and the first fan-out line FL1 may overlap with each other, with the first insulating layer IL1 and the gate insulating layer GI arranged under the first insulating layer IL1 interposed between the first dummy line DFL1 and the first fan-out line FL1. The first dummy line DFL1 may be arranged under the first fan-out line FL1.

[0244] The second dummy line DFL2 may be arranged in the first region I of the fan-out area FTA and may extend in the second direction DR2. When viewed in a plan view, the second dummy line DFL2 may overlap the second fan-out line FL2. In some exemplary embodiments of the present disclosure, the second dummy line DFL2 and the second fan-out line FL2 may be arranged on different layers, and the second dummy line DFL2 and the second fan-out line FL2 may overlap each other, with the first insulating layer IL1 and the second insulating layer IL2 on the first insulating layer IL1 interposed between the second dummy line DFL2 and the second fan-out line FL2. The second dummy line DFL2 may be arranged on the second fan-out line FL2.

[0245] In the following, reference will be made to Figures 17 to 19 The dummy active pattern DACT, the first and second dummy lines DFL1 and DFL2, the first and second fan-out lines FL1 and FL2, and the connection lines CL are described.

[0246] First, the buffer layer BFL may be disposed on the substrate SUB.

[0247] The first dummy line DFL1 and the dummy active pattern DACT may be disposed on the buffer layer BFL. Each of the dummy active pattern DACT and the first dummy line DFL1 may be a semiconductor pattern including polysilicon, amorphous silicon, an oxide semiconductor, etc. The dummy active pattern DACT and the first dummy line DFL1 may be formed of the same material as the first active pattern ACT1 to the seventh active pattern ACT7 respectively included in the first transistor T1 to the seventh transistor T7, and may be disposed on the same layer as the first active pattern ACT1 to the seventh active pattern ACT7.

[0248] A gate insulating layer GI may be disposed on the first dummy line DFL1 and the dummy active pattern DACT.

[0249] The second fan-out line FL2 may be disposed on the gate insulating layer GI. The second fan-out line FL2 may include the same material as the scan lines Si-1, Si and Si+1, and the emission control line Ei, and may be disposed on the same layer as the scan lines Si-1, Si and Si+1, and the emission control line Ei. The second fan-out line FL2 may be disposed in the same layer as the first gate electrode GE1 to the seventh gate electrode GE7 respectively included in the first transistor T1 to the seventh transistor T7.

[0250] The first insulating layer IL1 may be disposed on the second fan-out line FL2 .

[0251] The first fan-out line FL1 may be disposed on the first insulating layer IL1. In some exemplary embodiments of the present disclosure, the first fan-out line FL1 may include the same material as the upper electrode UE of the storage capacitor Cst in each pixel PXL and may be disposed on the same layer as the upper electrode UE. In addition, the first fan-out line FL1 may include the same material as the initialization power line IPL in each pixel PXL and may be disposed on the same layer as the initialization power line IPL.

[0252] In some exemplary embodiments of the present disclosure, the first fan-out line FL1 may be electrically connected to the first dummy line DFL1 through a first through hole TH1 sequentially passing through the first insulating layer IL1 and the gate insulating layer GI. For example, the first fan-out line FL1 and the first dummy line DFL1 may be electrically connected. Therefore, a data signal applied to the first fan-out line FL1 from the data driver DDV may be transmitted to the first dummy line DFL1 through the first through hole TH1. As a result, the same signal may be applied to the first dummy line DFL1 and the first fan-out line FL1.

[0253] The second insulating layer IL2 may be disposed on the first fan-out line FL1 .

[0254] The connection line CL and the second dummy line DFL2 may be disposed on the second insulating layer IL2. The connection line CL and the second dummy line DFL2 may be disposed on the same layer and may include the same material as the first and second connection lines CNL1 and CNL2 of each pixel PXL.

[0255] In some exemplary embodiments of the present disclosure, the connection line CL disposed in the second region II of the fan-out area FTA may extend along the second direction DR2 and may be connected to the second dummy line DFL2 disposed in the first region I of the fan-out area FTA. The connection line CL and the second dummy line DFL2 may be integrally formed.

[0256] In some exemplary embodiments of the present disclosure, the connection line CL corresponding to the first fan-out line FL1 may be electrically connected to the first fan-out line FL1 through the second through hole TH2 passing through the second insulating layer IL2 .

[0257] In some exemplary embodiments of the present disclosure, the connection line CL corresponding to the second fan-out line FL2 may be electrically connected to the second fan-out line FL2 through the third through hole TH3 sequentially passing through the first insulating layer IL1 and the second insulating layer IL2 .

[0258] The third insulating layer IL3 may be disposed on the connection line CL and the second dummy line DFL2 .

[0259] Since a separate photoresist pattern is added to the non-display area NDA to form the first and second dummy lines DFL1 and DFL2 and the dummy active pattern DACT in the fan-out area FTA, the density of the photoresist pattern in the non-display area NDA can be increased. Therefore, the density of the photoresist pattern in the non-display area NDA can be made similar to that of the photoresist pattern in the display area DA.

[0260] The display device according to an exemplary embodiment of the present disclosure may include first and second dummy lines DFL1 and DFL2 and a dummy active pattern DACT in the non-display area NDA, so that defects caused by a density difference of a photoresist pattern between the display area DA and the non-display area NDA may be prevented. As a result, the reliability of the display device may be improved.

[0261] The present embodiment can be applied to any display device and any system including a display device. For example, the present embodiment can be applied to televisions, computer monitors, laptop systems, digital cameras, cellular phones, smart phones, smart tablets or tablet computers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, navigation systems, game consoles, video phones, wearable devices such as smart watches, etc.

[0262] Therefore, the display device according to the exemplary embodiment of the present disclosure may have improved reliability.

[0263] The exemplary embodiments described herein are illustrative, and many variations may be introduced without departing from the spirit of the present disclosure or the scope of the appended claims. For example, elements and / or features of different exemplary embodiments may be combined and / or replaced with each other within the scope of the disclosure and the appended claims.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a plurality of pixels arranged in the display area, each of the plurality of pixels including at least one transistor and a light emitting element connected to the at least one transistor; a data line disposed in the display area, the data line configured to supply a data signal to each of the plurality of pixels; a wiring portion arranged in the non-display area, the wiring portion including a connection line connected to the data line and a fan-out line connected to the connection line; as well as a dummy pattern arranged in the non-display area, the dummy pattern at least partially overlapping the wiring portion, Wherein, the dummy pattern is arranged between the substrate and the first insulating layer, Wherein, the connecting wire is arranged on the third insulating layer, and Wherein, the fan-out line is arranged between the dummy pattern and the connection line.

2. The display device according to claim 1, further comprising: A dummy active pattern is disposed between the substrate and the first insulating layer, the dummy active pattern at least partially overlapping the connection line.

3. The display device according to claim 2, wherein: The at least one transistor comprises: an active pattern disposed on the substrate; a gate electrode disposed on the active pattern, the first insulating layer being interposed between the active pattern and the gate electrode; a source electrode connected to the active pattern; and connected to a drain electrode of the active pattern, The dummy active pattern is arranged on the same layer as the active pattern.

4. The display device according to claim 3, wherein: The connection line electrically connects the fan-out line and the data line to each other.

5. The display device according to claim 4, wherein: The fan-out lines include a first fan-out line and a second fan-out line arranged on different layers from each other, and The first fan-out line is arranged on the second insulating layer, and the second fan-out line is arranged on the first insulating layer.

6. The display device according to claim 5, wherein: The first fan-out line is electrically connected to the connection line through a first through hole passing through the third insulating layer, and The second fan-out line is electrically connected to the connection line through a second through hole passing through each of the second insulating layer and the third insulating layer.

7. The display device according to claim 5, wherein: The dummy pattern includes a first dummy line at least partially overlapping the first fan-out line and a second dummy line at least partially overlapping the second fan-out line.

8. The display device according to claim 7, wherein: The first dummy line is arranged between the substrate and the first insulating layer, and the second dummy line is arranged on the third insulating layer.

9. The display device according to claim 8, wherein: The first dummy line is arranged on the same layer as the dummy active pattern, and The second dummy line is arranged on the same layer as the connecting line and is formed integrally with the connecting line.

10. The display device according to claim 9, wherein: The first dummy line is connected to the first fan-out line through at least one contact hole passing through the first insulating layer and the second insulating layer.

11. The display device according to claim 10, wherein: The same signal is supplied to the first fan-out line and the first dummy line.

12. The display device according to claim 9, wherein: The second dummy line is connected to the second fan-out line through at least one contact hole passing through the second insulating layer and the third insulating layer.

13. The display device according to claim 12, wherein: The same signal is supplied to the second fan-out line and the second dummy line.

14. The display device according to claim 8, further comprising: a scan line and a lower electrode disposed on the first insulating layer and disposed in each of the plurality of pixels; as well as An upper electrode is disposed on the second insulating layer, the upper electrode at least partially overlapping the lower electrode to form a storage capacitor.

15. The display device according to claim 14, wherein: The second fan-out line is arranged on the same layer as the scan line and the lower electrode, and The first fan-out line is arranged on the same layer as the upper electrode.

16. The display device according to claim 15, wherein: The first fan-out lines and the second fan-out lines are alternately arranged along a direction of the substrate.

17. The display device according to claim 16, wherein: The plurality of pixels include a first pixel displaying a first color, a second pixel displaying a second color, and a third pixel displaying a third color, and Wherein the first color is green, the second color is red and the third color is blue.

18. The display device according to claim 17, wherein: The first fan-out line is connected to a data line connected to the first pixel, and the second fan-out line is connected to data lines connected to the second pixel and the third pixel.

19. The display device according to claim 1, wherein: The dummy pattern comprises: a dummy active pattern disposed between the substrate and the first insulating layer, the dummy active pattern at least partially overlapping the connecting line; a first dummy line, the first dummy line at least partially overlapping with a first fan-out line of the fan-out line disposed on the second insulating layer; and A second dummy line at least partially overlaps a second fan-out line of the fan-out line disposed on the first insulating layer.

20. The display device according to claim 19, wherein The non-display area includes a fan-out area, the fan-out line is arranged in the fan-out area, and The fan-out region includes a first region and a second region, the fan-out line is arranged in the first region, and the connection line is arranged in the second region.

21. The display device according to claim 19, further comprising: a fourth insulating layer arranged on the connecting line and at least partially covering the connecting line, The data line is arranged on the fourth insulating layer.

22. A display device comprising: A substrate, the substrate comprising a display area and a non-display area; a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a plurality of pixels arranged in the display area, each of the plurality of pixels including at least one transistor and a light emitting element connected to the at least one transistor; a plurality of data lines arranged in the display area, the plurality of data lines being configured to supply a data signal to each of the plurality of pixels; a wiring portion arranged in the non-display area, the wiring portion comprising a plurality of connection lines connected to corresponding data lines among the plurality of data lines, a first fan-out line connected to corresponding connection lines among the plurality of connection lines, and a second fan-out line connected to corresponding connection lines among the plurality of connection lines, the first fan-out line and the second fan-out line being arranged on different layers; as well as a dummy pattern arranged in the non-display area, the dummy pattern at least partially overlapping the wiring portion, The dummy pattern comprises: a dummy active pattern at least partially overlapping the plurality of connection lines and arranged between the substrate and the first insulating layer; a first dummy line at least partially overlapping the first fan-out line and disposed between the substrate and the first insulating layer; and A second dummy line at least partially overlaps the second fan-out line and is disposed on the third insulating layer.

23. The display device according to claim 22, wherein: The first dummy line is arranged on the same layer as the dummy active pattern, and The second dummy line is arranged on the same layer as the plurality of connection lines and is integrally formed with each of the plurality of connection lines.

24. The display device according to claim 23, wherein: The first fan-out line is arranged on the second insulating layer, and the second fan-out line is arranged on the first insulating layer.

25. The display device according to claim 24, wherein: The first dummy line is connected to the first fan-out line through at least one contact hole passing through the first insulating layer and the second insulating layer.

26. The display device according to claim 24, wherein: The second dummy line is connected to the second fan-out line through at least one contact hole passing through the second insulating layer and the third insulating layer.

27. The display device according to claim 24, wherein: The first fan-out lines and the second fan-out lines are alternately arranged along a direction of the substrate.

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