Driver circuit, corresponding system and method

Abstract

The present application relates to a driver circuit, a corresponding system and method. The driver circuit includes a power supply node, a control node configured to receive a control signal, and an output node. An output transistor is coupled to the output node to provide a CAN bus drive signal via a current path through the output transistor. A current mirror is in a current line from the power supply node to the output node through the output transistor. The current line includes an intermediate portion between the current mirror and the output transistor. The current mirror is configured to switch between a first dominant mode and a second recessive mode according to a control signal, in which the CAN bus drive signal is applied to the output node via the output transistor in the first dominant mode, and in which the output transistor provides a high output impedance at the output node in the second recessive mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102018000001660, filed on January 23, 2018, which is hereby incorporated herein by reference. Technical Field

[0003] This specification relates to driver circuits. Background Art

[0004] International standards such as ISO 11898-2 dealing with CAN applications (e.g. CAN-HS and CAN-FD transceivers, i.e. the physical layer) continue to evolve following the ISO 16845-2 conformance test plan.

[0005] The development involves various improvements and new features, such as flexible data rate (CAN-FD) and increased robustness constraints for the physical layer.

[0006] For example, standards such as ISO 11898-2 establish certain requirements for the Rin resistor by establishing specifications for Rin values ​​and their matching, such as the high side (CANH) and the low side (CANL).

[0007] However, no measurement method is provided for the input resistance, and no valid range for the CANH / CANL voltages required to determine Rin is specified.

[0008] The standard ISO 16845-2 (2015 edition) provides certain test specifications for the resistor Rin. For example, the Rin measurement is specified with respect to a 5V (external) test voltage generator and a series 10k ohm test resistor.

[0009] By setting up such a measurement, in active mode (when the Rin value is within the specified range), the CANH voltage is not expected to exceed 4.6 V. In addition, the CANH pin voltage is not expected to exceed the VDD_CAN supply voltage.

[0010] The standard ISO16845-2 (2017 edition) again provides certain test specifications for the resistor Rin, but does not fully describe the corresponding measurement setup. In addition, the Rin resistor is specified in the -2V to +7V pin voltage range. According to these new specifications, the CANH pin voltage may exceed the VDD_CAN supply voltage.

[0011] In general (ie, regardless of technology limitations), the CANH / L driver topology can be driven following the Absolute Maximum Ratings (AMR) requirements, ie, within a voltage range between -27V and +40V.

[0012] To this end, the CANL driver may include a cascaded current generator capable of withstanding +40V and limiting the output current and dominant voltage in case of a short circuit, with a series connected high voltage (HV) diode capable of withstanding a short circuit condition of -27V.

[0013] A corresponding (ideal) CANH driver may then comprise a cascaded current generator capable of withstanding -27V and limiting the output current and dominant voltage in case of a short circuit, with a series connected HV diode capable of withstanding a short circuit condition of +40V.

[0014] The CAN transceiver can be integrated into an automotive system basis chip (SBC) by representing commercial functionality in, for example, less than 5% of the total device area in silicon area.

[0015] Under certain possible limitations, for example related to the unavailability of HV diodes with cathode terminals capable of floating down to -27V, automotive SBCs can be integrated using low-cost 40V technology, such as Bipolar-CMOS-DMOS technology.

[0016] It is observed that this technological limitation can be overcome by adopting more expensive technology options such as silicon-on-insulator (SOI) or dual epitaxial / dual buried layer technology.

[0017] It was also observed that this approach would have a negative impact on SBC cost, an impact that would be difficult to justify with such a relatively small function.

[0018] These factors may lead to certain design trade-offs that ultimately result in a CANH driver topology that is asymmetric with respect to the associated CANL driver topology: for example, the input characteristics (both static and dynamic) of a CANH driver, e.g. in recessive mode (or state), may vary significantly depending on whether the driver is disabled or enabled, while this is not the case for the homologous CANL driver. Summary of the invention

[0019] One or more embodiments may be applied in a CAN (Controlled Area Network) bus arrangement for use, for example, in the automotive field.

[0020] One or more embodiments may help to overcome the limitations discussed above.

[0021] One or more embodiments may relate to corresponding devices (e.g., CAN bus drivers for use in the automotive field). One or more embodiments may relate to corresponding methods. The claims are an integral part of the technical disclosure of the embodiments provided herein.

[0022] One or more embodiments make it possible to implement a CAN driver that is able to avoid current flow through its output lines when in recessive mode or state (CANTX=1).

[0023] One or more embodiments may be implemented using low-cost BCD technology.

[0024] One or more embodiments facilitate a simplified and robust implementation that meets input resistance specifications set forth, for example, in the ISO 11898-2 standard, with a pin voltage range up to +7V or wider, such as -12V to +12V (which may be a future requirement in the ISO 16845-2 test specification). In this document, references to standards mean references to all versions of the standards that are valid on the effective filing date of this patent.

[0025] One or more embodiments enable significant advantages to be achieved in terms of cost savings.

[0026] One or more embodiments facilitate providing driver topologies using base components that are available as low-cost technology options while providing benefits (eg, in terms of electrical parameters) that are currently only available by resorting to relatively expensive components.

[0027] One or more embodiments make it possible to achieve the advantages outlined above without resorting to complex technical solutions for integrating a fully floating HV diode.

[0028] One or more embodiments may provide a novel CANH driver topology that provides (arbitrarily) low input current in recessive mode.

[0029] One or more embodiments may facilitate meeting absolute maximum rating requirements for 12V systems (-27V to +40V) without resorting to high voltage diodes that can float down to -27V (40V average).

[0030] One or more embodiments facilitate providing satisfactory EMC (electromagnetic compatibility) performance in terms of emissions and in terms of RF interference immunity.

[0031] Possible uses of one or more embodiments may be detected, for example by measurements at the device pins, for example by measuring the IV characteristics of the CANH pin in recessive mode (REC) and dominant mode (DOM) and analyzing whether different behaviors can be tracked for the frequency of the applied stimulus. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0033] Figure 1 is an example of a CAN bus driver arrangement,

[0034] Figure 2 is the circuit diagram of CANH driver topology,

[0035] Figure 3 is a circuit diagram of an embodiment.

[0036] Figure 4 is a detailed circuit diagram of the embodiment, and

[0037] Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A and Figure 7B is an illustration of various operating modes applicable in a CANH driver topology. DETAILED DESCRIPTION

[0038] In the following description, one or more specific details are illustrated to provide a deeper understanding of examples of embodiments of the present specification. Embodiments may be obtained without one or more specific details or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments will not be covered.

[0039] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0040] The reference numerals used herein are provided for convenience only and do not thereby limit the scope of protection or the scope of the embodiments.

[0041] like Figure 1 The CAN transceiver TSC illustrated in the example can provide three main functions:

[0042] The bias of the associated bus B (involving the input resistor R in and the associated bias generator V bias ), the associated bus B is coupled to the CANH node and the CANL node for the "high" side and the "low" side of the bus, respectively,

[0043] The receiver operates, for example, by means of a comparator on the bus differential voltage (CANH-CANL) coupled to the receiver node CANRX,

[0044] The transmitter operates by driving CANH and CANL via a high-side driver 10 and a low-side driver LS, respectively, according to a signal applied to the transmitter node CANTX.

[0045] Such a transceiver TSC may be intended to be supplied with a supply (rail) voltage VDD_CAN of, for example, 5 V (nominal value) and to operate under the control of a microcontroller MC coupled to the nodes CANTX and CANRX.

[0046] Operation of the transmitter in such a transceiver TSC may involve driving a differential voltage of, for example, 2V (nominal) on bus B when transmitter operation is enabled, for example by applying a voltage CANTX=0 to input node CANTX in a dominant mode or state ("DOM").

[0047] Such a transmitter should ideally provide a high impedance value to the CAN bus when a voltage CANTX=1 is applied to the input node CANTX CAN, for example in the so-called recessive mode or state ("REC"). In the recessive mode, the bus is coupled to the bias structure (R in , V bias ) and "sees" R set to, for example, 35k ohms (nominal value) in impedance.

[0048] like Figure 1 The overall structure and mode of operation of the CAN transceiver TSC illustrated in FIG. 4 are particularly conventional in the art, so that it is not necessary to provide a more detailed description in this document.

[0049] Figure 2 is a CANH driver topology suitable for use with bipolar-CMOS-DMOS (BCD) designs (e.g. Figure 1 10) in the figure.

[0050] exist Figure 2 In the arrangement illustrated in FIG. 1 , a CANH driver 10 (hereinafter referred to as “driver”) is powered via a supply node having a supply voltage VDD_CAN (eg, 5V nominal) and is configured to operate according to, for example, a power supply node such as a power supply node. Figure 1 A microcontroller such as the MC in the control node TXD (which may correspond to Figure 1 A control signal is applied at the node CANTX in the CAN bus, and a drive signal for the high side of the CAN bus is provided at the output node CANH (see, for example, Figure 1 B).

[0051] exist Figure 2In the figure, reference numeral 12 denotes a diode (obtained, for example, by means of a transistor such as a MOS transistor in a diode arrangement, the gate of which is short-circuited to the source), which provides a voltage VDD_CAN-V at the supply node A. diode (Where V diode denoting the voltage drop across the diode 12). Node A provides a bias current I to the driver stage 14. bias , driver stage 14 receives a signal at node TXD to control switch 16 (e.g., an electronic switch such as a transistor), which is configured to selectively couple node A with node B, which is located between a current mirror 18 (e.g., a 1:100 3.3VP channel current mirror) and a current generator 20 (e.g., 720 μA) effective between node B and ground.

[0052] It should be understood that the representation provided herein, including the driver stage 14 and the switch 16, is a simplified representation of how activation of the current mirror 18 may be controlled and is presented herein merely for simplicity and ease of explanation.

[0053] Practical arrangements for controlling the switching on / off of the output current depending on the TXD (digital) input signal may in fact be more complex: these arrangements are particularly well known to a person skilled in the art, so that no more detailed description is necessary in this context.

[0054] Reference numeral 22 denotes a transistor (eg, a 45V P-dex MOSFET with a buried layer) which is arranged to have its current path (source-drain) cascaded (connected in series) between the current path of the output transistor through the current mirror 18 and the output node CANH.

[0055] In this way, the cascade arrangement of transistor 22 and the output transistor in current mirror 18, with the midpoint therebetween being at voltage Vs, is arranged between the floating supply rails defined by node A (intended to be placed at voltage V high ) and the output node CANH.

[0056] As an explanation, Figure 2 The circuit diagram also includes a representation of a voltage generator 24 (eg 3.3V) arranged between the floating supply rail and the gate of transistor 22 (intended to bring the voltage to V low =V high -3.3V). This representation is for explanation purposes only: in actual implementations, the low =V high The current of -3.3V can be directly included (considered) in the bias current I to the driver 14 bias middle.

[0057] Switch 16 is Figure 2 The circuit illustrated in is an illustration of the possibility (discussed previously) of switching between a dominant mode (DOM) when the input node TXD is set to a first value, such as CANTX=0, and a recessive mode (REC) when the input node TXD is set to a second value, such as CANTX=1.

[0058] It is observed that in Figure 2 In the arrangement illustrated in , during the transition between DOM mode and REC mode (DOM←→REC), the gate voltage generator for transistor 22 should be expected to be able to sink / source a current of up to, for example, 1.6 mA (with limited voltage variation) so that the electromagnetic emission (EME) performance is not affected even in the presence of falling / rising edges as short as 20 ns (which may be the case for a class AB output stage used to drive the gate of transistor 22 with a quiescent current of 450 μA).

[0059] As pointed out earlier, in Figure 2 In the arrangement illustrated in FIG. 1 , the voltage V low is set equal to V high -3.3V fixed (gate) voltage.

[0060] It is observed that in Figure 2 In the arrangement illustrated in , in recessive mode (REC) where the pin voltage is driven above VDD_CAN (e.g. 5V), the driver may draw input current, which may impair the CANH input resistance measurement. The ISO16845-2 standard published on January 31, 2017 specifies input resistance test conditions where the CANX pin is from -2V to 7V.

[0061] It is observed that Figure 2 The topology illustrated in may not meet these requirements.

[0062] As noted, this problem can be solved by taking a technical approach that allows integration of a fully floating HV diode (eg, minimum 40V breakdown, able to float down to at least -27V): standalone CAN transceivers using SOI (Silicon On Insulator) technology are actually available.

[0063] Standard junction isolation BCD technology (which has a lower cost and is therefore widely accepted for integrated automotive system basis chips) can also be considered; however, this would involve additional technical steps / features such as double epitaxial layers and double buried layer diffusions, resulting in an overall cost increase of about 10%-20%. As pointed out, such a cost increase would be unacceptable - given the small "weight" of the CAN transceiver in terms of silicon area in the corresponding automotive system basis chip SBC (e.g., 5% or less).

[0064] One or more embodiments may be implemented by taking Figure 3 The arrangement illustrated in the circuit diagram (in general terms) solves these problems.

[0065] exist Figure 3 In the drawings, parts or elements such as those already discussed in connection with previous figures are indicated by the same reference numerals / numbers: for the sake of brevity, the corresponding description is not repeated here.

[0066] It can be considered Figure 3 The arrangement illustrated in is based on the concept of moving the HV diode between a (low voltage) current mirror 18 (e.g., P-channel) and a high voltage cascode element illustrated by a (e.g., P-channel MOSFET) transistor 22, which is an example of a HV P-channel cascode element cascaded to the LV P-channel current mirror 18.

[0067] This concept is Figure 3 This is illustrated in FIG. 1 by such a HV diode designated 12 ′, which may be implemented as a MOSFET transistor, such as a 40V N-drift MOSFET with a buried layer (gate shorted to source) in a diode configuration.

[0068] and Figure 2 Similar to the topology illustrated in FIG, the gate voltage of transistor 22 may depend on V high , except in Figure 3 In this case, (theoretically) the voltage across the voltage generator 24 will now be equal to, for example, 3.3V+V diode , where V diode represents the voltage drop across the diode 12'.

[0069] It should be noted that driving (the gate of) transistor 22 with such a voltage generator 24 will - under normal operating conditions - provide Figure 2 However, in the case where CANH is shorted to +40V, the gate oxide voltage of transistor 22 will not be limited to the maximum allowed value (as established, e.g., 3.6V, for technical reasons), and transistor 22 will be at risk of being damaged. Therefore, an improved solution for driving the gate voltage of transistor 22 is desired.

[0070] Also note that if Figure 3 The arrangement generally illustrated in , where the driver circuit controls the timing of the bus which is now supplied on a fixed rail (node ​​A), can ideally solve the problems discussed above.

[0071] A problem may arise related to the gate voltage of the generating transistor 22: when the driver 10 is driven above VDD_CAN, the voltage Vgs (across the gate oxide) should ideally be limited (clamped) to the highest allowed value (technology dependent) by drawing a small current in recessive mode, while in dominant mode and during DOM←→REC transitions, higher input currents can be tolerated.

[0072] When the CANH output node is driven above VDD_CAN, one or more embodiments may take into account that when the transceiver is in recessive mode (REC), there may be a (very) low input current (e.g., approximately 4 μA on the CANH output node or pin); while in dominant mode (DOM) and during mode transitions, the current may be (much) higher, e.g., up to 1.6 mA.

[0073] The gate of the HV P-channel cascode element (i.e., transistor 22) is driven to facilitate the following considerations: Figure 3 Operation of the circuit illustrated in FIG. 1: By taking into account that a typical upper limit for the operating Vgs voltage may be about 3.6V (which may be the case using 70 Angstroms gate oxide thickness) - similar constraints exist for other technologies, and the associated driver circuit should ideally protect the HV P-channel cascode gate oxide (in practice a 45V P-channel MOSFET transistor can barely withstand a voltage of, for example, 45V between gate and source).

[0074] Furthermore, when the CANH output voltage is driven above VDD_CAN, e.g. up to 40V (which might be the case for a short circuit condition on the external wire), the protection should ideally function with reduced current drawn by the circuit to avoid compromising the resistance (provided by the bias circuit) measured at the CANH output pin or node.

[0075] Furthermore, under normal operating conditions (eg, no short circuit on the output), the gate of transistor 22 should ideally be at a low impedance (eg, at a voltage equal to VDD_CAN-3.3VV). diode The gate is driven by a voltage level of , as mentioned above, providing a current of up to, for example, 1.6 mA to the gate during the DOM←→REC transition, thereby avoiding distortion of the output waveform.

[0076] One or more embodiments may be implemented by taking the following approach: Figure 4 The circuit arrangement illustrated in FIG. 1 solves these problems.

[0077] Figure 4 The circuit diagram is provided which is configured for use in Figure 3A detailed example of a circuit for gate control of transistor 22 (HV P-channel cascode element) is provided within the framework of the circuit arrangement illustrated in , generally referenced 100 , while a different approach is adopted for the generator referenced 24 .

[0078] It is also observed that the topologies considered herein may face certain risks in terms of direct power injection (DPI) robustness, for example when the entire gate bias structure is disconnected.

[0079] For this reason, in Figure 4 In the drawings, parts or elements such as those already discussed in connection with previous figures are indicated by the same reference numerals / numbers: for the sake of brevity, the corresponding description is not repeated here.

[0080] exist Figure 4 In the circuit diagram of FIG. 1 , reference numeral 101 denotes a diode arrangement, which comprises a MOSFET transistor (gate and source are short-circuited) in a diode arrangement, which is substantially similar to Figure 2 (and Figure 3 ) is one of the diodes 12 (and 12'). For example, Figure 4 The diode 101 in the embodiment may comprise a 40V N-drift MOSFET which varies with the current drawn. Figure 2 (and Figure 3 ) has a scaled-down buried layer compared to the corresponding components marked 12 (and 12') in FIG.

[0081] A voltage equal to VDD_CAN-V is provided on the cathode of diode 101 at node 100A. diode The voltage, V diode The voltage drop across the diode 101 is indicated.

[0082] Reference numeral 102 indicates a pull-down network coupled to node 100A and employing a conventional AB output stage solution, which includes a resistor R and a pull-down current generator using a pull-down current (e.g., 160 μA static) to provide, for example, a 3.3V drop from the cathode of HV diode 101 and a voltage equal to VDD_CAN-V at node 100B. diode -3.3V output voltage.

[0083] In one or more embodiments, the network in question may include two transistor pairs (e.g., MOSFET transistors) 102A, 102B, where:

[0084] The transistors in each pair have their control terminals (gates in the case of field effect transistors such as MOSFETs) coupled to each other;

[0085] Also shown is the first transistor in each pair in the diode arrangement ( Figure 4 102B);

[0086] The second transistor in each pair is also shown ( Figure 4 ), which is arranged with a current path cascaded in a current line from node 100A to the second pull-down generator 104, the second pull-down generator 104 in a current line that draws a pull-down current (e.g., 320 μA) to be discussed later; an intrinsic diode, through these latter two transistors.

[0087] Still another transistor (e.g., a MOSFET transistor) 102C is shown having its current path extending between the common gate of the transistors in pair 102A and the current line between pull-down generator 103 and node 100A at a point between the diode-coupled transistors in pair 102A, 102A for safe operating area (SOA) protection.

[0088] As noted, reference numeral 103 denotes the entire pull-down current generator (to which a supply voltage of, for example, 3.3V is applied), which draws a current equal to, for example, 160 μA, which is given by, for example, (3.3V-VgsN) / R', where R' denotes the resistance value of a resistor coupled to the 3.3V supply, and VgsN denotes the gate-source voltage drop across a transistor in, for example, a diode configuration in an N-channel current mirror between resistor R' and ground (gate shorted to drain). As discussed below, the current generated by signal I may be provided. GATEbias _DISABLE controls the switch 103A to short-circuit the source and drain of the subsequent transistor.

[0089] As illustrated herein, the further pull-down current generator 104 generates a current having a value of, for example, 1.6 mA to provide a current limit to the output voltage of the circuit portion indicated as 102 , wherein the current limit corresponds to the highest current intensity that the generator 104 can draw.

[0090] As discussed below, a switch 104A controlled by a signal Gatesink_DIS may be provided to short-circuit the source and drain (gate to drain) of a transistor in a diode configuration, e.g., an N-channel current mirror, in the generator 104 to render the current mirror 104 inactive: when the switch 104A is activated, the circuit portion 102 will effectively draw no current, and only the circuit portion 105 (as discussed below) may draw current from the output node 100B.

[0091] Reference numeral 105 denotes a further pull-down current generator. Generator 105 may like pull-down current generators 103 and 104 be implemented as an N-channel current mirror which provides a current drawn from node 100B, wherein in the case of generator 105 this current is a (very) small value, for example 4 μA.

[0092] When the CANH output voltage is driven above VDD_CAN (e.g., up to about 8.3 V), current from generator 105 may flow from the source-drain terminal of transistor 22 (HV P-channel cascode) to output terminal CANH through clamp circuit 106 (discussed later).

[0093] With respect to the input resistance (Rin, such as the combination of Figure 1 As discussed in the introduction to the specification), the current value of the current generator 105 may be selected to be small enough to be negligible.

[0094] Figure 4 Reference numeral 106 in FIG. 1 denotes a clamp circuit active between the gate and source of the output cascode transistor 22 (Vgs clamp circuit).

[0095] The clamp circuit 106 may be configured to drive a (very) small current when the value of Vgs is below a certain threshold (eg 3.3 V, which may correspond to a normal condition without a short circuit on the output voltage at the CANH node).

[0096] In one or more embodiments, the clamp circuit 106 may include any conventional clamp circuit arrangement, such as shown in the figure. The clamp circuit is a two-terminal component that clamps when the applied voltage is below V clamp Ideally, no current is driven at this value, and once the voltage reaches V clamp value drives any current.

[0097] In short, a Zener diode that clamps the Vgs voltage at a value of, for example, 3.3 V to protect the gate oxide interface in the HV P-channel transistor 22 may be considered as an example of a clamping circuit 106 suitable for use in one or more embodiments.

[0098] Any circuit providing such behavior may therefore represent a suitable clamp for use in one or more embodiments, having the capability to be configured so as to be able to drive sufficiently high current (eg, up to 1.6 mA) to limit the voltage drop Vgs to below a value of, for example, 3.6V.

[0099] Finally, reference numeral 107 denotes an (optional) circuit portion which is configured to, for example, provide a voltage level of 0 when the gate of transistor 22 rises above VDD_CAN via signal I GATEbias_DISABLE The switch 103A is acted upon to disconnect the pull-down current generator 103 .

[0100] For example, circuit 107 may include a signal on the gate of transistor 22 (node ​​100B) and a desired reference threshold V that may be set to, for example, VDD_CAN. threshold Sensitive input comparator 107A.

[0101] In one or more embodiments, comparator 107A may provide hysteresis behavior corresponding to the following conditions:

[0102] V threshold >VDD_CAN-V diode -V th-Nch

[0103] V threshold <VDD_CAN-V diode +V NwPw-Nch .

[0104] in:

[0105] V diode is the voltage drop across the diode 101 coupled to VDD_CAN;

[0106] V th-Nch is the threshold voltage of the N-channel pair 102A;

[0107] V NwPw-Nch is the voltage drop across the intrinsic diode shown at 102A.

[0108] Comparator 107 may be followed by an asymmetric filter (T filter) 107B, which together with comparator 107A may help avoid undesired validation during direct power injection (DPI).

[0109] The circuit 107 illustrated herein further includes an AND gate 107C so that the signal I Gatesbias_DISABLE The issuance is selected by the signal Gatesink_DIS.

[0110] This digital signal can be generated to be high only in the recessive state after the DOM→REC transition is fully completed (e.g., internally, under the control of the MC). Therefore, this signal can be considered equal to TXD with a rising edge, corresponding to the DOM→REC transition, sufficiently delayed to provide an effective gate bias function in DOM mode and during the REC→DOM transition.

[0111] After the DOM→REC transition, the same signal Gatesink_DIS may be applied to the disable switch 104A to disable the current generator 104 in the REC mode.

[0112] If the (optional) circuit 107 is not present, the current drawn from the CANH node in the case of a short circuit up to, for example, 8.3 V corresponds essentially to the current of the generator 105, and is increased by the addition of the current from the generator 103 when the voltage is above 8.3 V, because under this condition (CANH above 8.3 V) the node 100A is pulled up to V(CANH)-Vclamp (Vs=~V(CANH)) by the intrinsic diode at 102A.

[0113] In contrast, if circuit 107 is present, then for any CANH voltage value above VDD_CAN, the current drawn from the CANH node remains equal to the current from generator 105 under the same conditions.

[0114] It should be understood that the pull-down current generator 104 can remain active only in DOM mode and during DOM←→REC transitions. In recessive mode (REC), the generator 102 can provide a voltage to bias the gate of the cascode transistor 22 by (only) drawing a small current provided by the generator 105. This facilitates drawing a small current from the CANH node in those cases where the actual voltage V(CANH) at the node CANH is only higher than VDD_CAN in recessive mode (e.g., when measuring the CANH input resistance is of interest).

[0115] like Figure 4 The arrangement illustrated in the example facilitates solving the problem based on Figure 3 Various problems with the topology illustrated in .

[0116] The first problem concerns the possibility that the CANH voltage rises to, for example, 40 V. In that case, node Vs (i.e., the source of transistor 22) may rise to a corresponding voltage, for example, 40 V-V diode And the voltage between the source and gate of transistor 22 may reach high values, with the risk of causing component failure.

[0117] This problem is addressed and resolved by clamp circuit 106, which is configured to maintain the gate-source voltage across transistor 22 to a safe value, thereby avoiding failure of the component.

[0118] Another issue may involve facilitating operation of the circuit during dominant (DOM) mode, where the gate of transistor 22 should ideally be driven in such a manner as to source and sink high current values ​​(e.g., in the range of 1.6 mA) while maintaining high voltage coupling effects while limiting voltage spikes during transitions of the CANH output node.

[0119] This problem can be solved by means of a class AB arrangement (generator 102 essentially cooperating with generators 103, 104).

[0120] Another issue may involve providing a high impedance structure during recessive mode (REC) when the CANH node may rise as high as 7 V. In that case, the right side of the structure 102, 103, 104 (essentially the generator 104) may be disconnected via the switch 104A actuated by the Gatesink_DIS signal, thereby setting a high impedance mode, while the generator 105 may remain active to adequately bias the clamp circuit 106. In this case, the current may be limited to, for example, 4 μA to meet the impedance specification, and only this low value bias current may be provided to the CANH node.

[0121] Another issue may involve facilitating efficient operation until the CANH voltage is below, for example, 8 V. With the CANH voltage above this value, the intrinsic diode in the right transistor of pair 102A in circuit portion 102 conducts, and the current flowing in the left side of current portion 102 (determined by pull-down current generator 103, e.g., 160 μA) flows through the intrinsic diode, the Vgs clamp, transistor 22 to the CANH output node.

[0122] In the arrangement illustrated herein, there is a disable signal I generated by circuit 107. GATEbias_DISABLE The possibility of disconnecting the current path through the intrinsic diode renders the pull-down current generator 103 inoperative. Such a signal can be generated by detecting when the gate of transistor 22 (as input to comparator 107A) is above VDD_CAN. In that case, the diode arrangement 101 is in reverse mode, while the intrinsic diode discussed above is in forward state.

[0123] FIG. 5A to FIG. 5B Provides that all bias branches (i.e. Figure 4 The various current generators shown in FIG. 1 are always effective, that is, the signal Gatesink_DIS is not used and is fixed to, for example, "0" and the switch 104A is kept open. Figure 4 The current of the CANH driver shown in the example ( Figure 5A )-vertical axis (A) and voltage ( Figure 5B )-vertical axis (V) comparison diagram of the characteristics.

[0124] While possibly suitable for certain types of operation, this solution can still be considered as compromising the CANH input resistance.

[0125] FIG. 6A to FIG. 6B Two graphs are shown indicating the IV characteristics of the CAN driver exemplified herein, where the gate current sinking structure (eg, 104 ) is disconnected in recessive mode and circuit 107 is not included in the circuit (if included, it is disabled).

[0126] FIG. 6A to FIG. 6B The behavior illustrated in may be considered an acceptable compromise to meet the input resistance specifications (absolute value and matching) over a CANH voltage range of, for example, -2V to +7V.

[0127] Fig. 7A and Figure 7B ' is an illustration of possible IV characteristics of the CANH driver illustrated herein in a complete configuration including and enabling circuit 107 .

[0128] This arrangement is able to meet the input resistance specifications (absolute value and matching) over the entire -12V to +12V CANH voltage range.

[0129] A circuit (eg, 10) according to one or more embodiments may include:

[0130] a power supply node (e.g., VDD_CAN) configured to receive power,

[0131] a control node (eg, TXD) configured to receive a control signal having a first value and a second value (eg, CANTX=0, CANTX=1),

[0132] an output node (e.g., CANH) configured to provide a driving signal to a CAN bus (e.g., B) according to a control signal,

[0133] an output transistor (e.g., 22) coupled to the output node to provide the CAN bus drive signal via a current path through the output transistor (e.g., source-drain in the case of a field effect transistor such as a MOSFET),

[0134] A current mirror (18) in a current line from a supply node to an output node through an output transistor, the current line including an intermediate portion between the current mirror and the output transistor, wherein the current mirror is coupled to a control node (e.g., via 14, 16), the current mirror being configured to switch between the following modes according to the control signal:

[0135] a first (dominant) mode (or state) in which the CAN bus drive signal is applied to the output node via the output transistor (eg, switch 16 is non-conductive), and

[0136] a second (recessive) mode (or state), in which the output transistor provides a high output impedance at the output node (e.g., switch 16 is on),

[0137] Therein, the circuit includes a high voltage diode (eg, 12 ′) arranged in the middle portion of the current line between the current mirror and the output transistor.

[0138] In one or more embodiments, the high voltage diode may include a transistor in a diode-like arrangement, where a control terminal (eg, a gate in the case of a field effect transistor such as a MOSFET) is coupled to a current path through the transistor.

[0139] In one or more embodiments, the high voltage diode is arranged with its anode facing the current mirror.

[0140] One or more embodiments may include a clamp circuit block (eg, 106 ) active between a control terminal of an output transistor (eg, a gate in the case of a field effect transistor such as a MOSFET) and a current path therethrough opposite an output node.

[0141] One or more embodiments may include a bias current generator (eg, 105 ) coupled to the clamp circuit block to provide a bias current thereto.

[0142] One or more embodiments may include a class AB stage (eg, 102 , 103 , 104 ) active between a supply node and a control terminal of an output transistor (eg, via node 100B) configured to facilitate current flow through the output transistor in a first (dominant) mode.

[0143] In one or more embodiments, the class AB stage may include a first pair (e.g., 102A) and a second pair (e.g., 102B) of pn junction devices (e.g., transistors, possibly in a diode-like configuration, Figure 4 In the left side of the figure, the corresponding transistors in the first pair and the second pair ( Figure 4 ) have an intermediate node (e.g., 100B) between them that is coupled to the control terminal of the output transistor.

[0144] In one or more embodiments, the class AB stage may be coupled to a first current line and a second current line from a supply node to ground, wherein:

[0145] The first current line may include a resistor (eg, R) and a first pull-down current generator (eg, 103) that draws a first current from a supply node, the strength of the first current being a function of the resistance value of the resistor, and

[0146] The second current line may include a second pull-down current generator (eg, 104) that draws a second current from the output node (CANH, eg, via node 100B), the second current having an upper limit value, thereby limiting the output current drawn by the class AB stage.

[0147] In one or more embodiments, the respective transistors in the first pair and the second pair may be arranged in cascade connection with each other in the second current line.

[0148] In one or more embodiments, after transitioning from the dominant mode to the recessive mode, the second pull-down current generator in the second current line may be selectively deactivated in the second recessive mode (eg, 104A; Gatesink_DIS).

[0149] One or more embodiments may include a sensor circuit block (eg, 107) that is sensitive to a voltage at a control terminal of an output transistor, the sensor circuit block being active on a first pull-down current generator (eg, I GATEbias_DISABLE ) to selectively deactivate the first pull-down current generator when the voltage at the control terminal of the output transistor reaches an upper threshold.

[0150] In one or more embodiments, the sensor circuit block may include:

[0151] at least one comparator stage (e.g., 107A), optionally with hysteresis, to compare the voltage at the control terminal of the output transistor with at least one reference threshold, and

[0152] A gating component (eg, 107C) couples the sensor circuit block with the first pull-down current generator to facilitate disabling of the first pull-down current generator in the second recessive mode after the transition from the first dominant mode to the second recessive mode is (fully) completed.

[0153] A system according to one or more embodiments may include:

[0154] CAN bus (e.g. B); and

[0155] According to one or more embodiments, the driver circuit (eg, 10 ) has its output node optionally coupled to a CAN bus at its high side to provide a CAN bus driving signal to the CAN bus.

[0156] A method of operating a circuit or system according to one or more embodiments may include applying a control signal having a first value and a second value to a control node, thereby causing operation of the circuit or system in the following mode:

[0157] a first dominant mode, in which the CAN bus drive signal is applied to the output node via the output transistor (22), and

[0158] The second is a recessive mode where the output transistor provides a high output impedance at the output node.

[0159] Without affecting the basic principle, various details and embodiments may vary, even significantly, with respect to what is described merely by way of example, without departing from the scope of protection.

[0160] The scope of protection is defined by the appended claims.

Claims

1. A circuit comprising: a power supply node, the power supply node being configured to receive power; a control node, the control node being configured to receive a control signal, the control signal switching between a first value and a second value; an output node, the output node being configured to provide a driving signal for a CAN bus according to the control signal; an output transistor having a current path coupled to the output node to provide the CAN bus drive signal via the current path of the output transistor; a switch having a current path coupled to the supply node and a control terminal coupled to the control node; a current mirror comprising a first current mirror transistor and a second current mirror transistor, the first current mirror transistor having a current path coupled between the supply node and the switch, the second current mirror transistor having a control terminal coupled to a control terminal of the first current mirror transistor and a current path coupled to the current path of the output transistor, wherein the current mirror is configured to switch between a first mode in which the CAN bus drive signal is applied to the output node via the output transistor and a second mode in which the output transistor provides a high output impedance at the output node according to the control signal; as well as a high voltage diode having an anode coupled to the current path of the second current mirror transistor and a cathode coupled to the current path of the output transistor.

2. The circuit according to claim 1, wherein The high voltage diode comprises a transistor in a diode-like arrangement having a control terminal.

3. The circuit of claim 1 further comprising a clamp circuit block effective between the control terminal of the output transistor and an intermediate node coupled between the current path of the output transistor and the cathode of the high voltage diode. 4 . The circuit of claim 3 , further comprising a bias current generator coupled to the clamp circuit block to provide a bias current to the clamp circuit block.

5. A circuit comprising: a power supply node, the power supply node being configured to receive power; a control node configured to receive a control signal switched between a first value and a second value; an output node, the output node being configured to provide a driving signal for a CAN bus according to the control signal; an output transistor having a current path coupled to the output node to provide the CAN bus drive signal via the current path of the output transistor; a switch having a current path coupled to the supply node and a control terminal coupled to the control node; a current mirror comprising a first current mirror transistor and a second current mirror transistor, the first current mirror transistor having a current path coupled between the supply node and the switch, the second current mirror transistor having a control terminal coupled to a control terminal of the first current mirror transistor and a current path coupled to the current path of the output transistor, wherein the current mirror is configured to switch between a first mode in which the CAN bus drive signal is applied to the output node via the output transistor and a second mode in which the output transistor provides a high output impedance at the output node according to the control signal; a class AB stage active between the supply node and a control terminal of the output transistor, the class AB stage being configured to facilitate current flow through the output transistor in the first mode; as well as a high voltage diode having an anode coupled to the current path of the second current mirror transistor and a cathode coupled to the current path of the output transistor.

6. The circuit according to claim 5, wherein: The high voltage diode comprises a transistor in a diode-like arrangement having a control terminal.

7. The circuit of claim 5, further comprising a clamp circuit block effective between the control terminal of the output transistor and an intermediate node coupled between the current path of the output transistor and the cathode of the high voltage diode. 8 . The circuit of claim 7 , further comprising a bias current generator coupled to the clamp circuit block to provide a bias current to the clamp circuit block.

9. The circuit according to claim 5, wherein: The class AB stage includes a first pair of pn junction devices and a second pair of pn junction devices, wherein respective transistors in the first pair and the second pair have an intermediate node therebetween, the intermediate node being coupled to the control terminal of the output transistor.

10. A circuit comprising: a power supply node, the power supply node being configured to receive power; a control node configured to receive a control signal switched between a first value and a second value; an output node, the output node being configured to provide a driving signal for a CAN bus according to the control signal; an output transistor coupled to the output node to provide the CAN bus drive signal via a current path of the output transistor; a current mirror in a current line from the supply node to the output node through the output transistor, the current line including an intermediate portion between the current mirror and the output transistor, wherein the current mirror is coupled to the control node, wherein the current mirror is configured to switch between a first mode in which the CAN bus drive signal is applied to the output node via the output transistor and a second mode in which the output transistor provides a high output impedance at the output node according to the control signal; a class AB stage active between the supply node and a control terminal of the output transistor, the class AB stage being configured to facilitate current flow through the output transistor in the first mode; as well as a high voltage diode arranged in the middle portion of the current line between the current mirror and the output transistor, wherein the class AB stage is coupled to a first current line and a second current line from the supply node to ground; wherein the first current line comprises a resistor and a first pull-down current generator, the first pull-down current generator being configured to draw a first current from the supply node, the first current having a strength that is a function of a resistance value of the resistor; as well as The second current line includes a second pull-down current generator configured to draw a second current from the output node, the second current having an upper limit value, thereby limiting the current drawn by the class AB stage.

11. The circuit according to claim 10, wherein: The class AB stage includes a first pair of pn junction devices and a second pair of pn junction devices, wherein respective transistors in the first pair and the second pair have an intermediate node therebetween, the intermediate node being coupled to the control terminal of the output transistor.

12. The circuit according to claim 11, wherein The corresponding transistors in the first pair and the second pair are arranged in cascade connection with each other in the second current line.

13. The circuit according to claim 10, wherein: After switching from the first mode to the second mode, the second pull-down current generator in the second current line may be selectively deactivated in the second mode.

14. The circuit of claim 10 further comprising a sensor circuit block sensitive to a voltage at the control terminal of the output transistor, the sensor circuit block being active on the first pull-down current generator so as to selectively deactivate the first pull-down current generator when the voltage at the control terminal of the output transistor reaches an upper threshold.

15. The circuit of claim 14, wherein: The sensor circuit block comprises: a comparator stage configured to compare the voltage at the control terminal of the output transistor with a reference threshold; and A gating component couples the sensor circuit block with the first pull-down current generator to facilitate disabling of the first pull-down current generator in the second mode after transition from the first mode to the second mode is completed.

16. The circuit of claim 15, wherein: The comparator stage includes a comparator stage with hysteresis.

17. A system comprising: CAN bus; a power supply node, the power supply node being configured to receive power; a control node, the control node being configured to receive a control signal, the control signal switching between a first value and a second value; an output node coupled to the CAN bus to provide a CAN bus drive signal, wherein the CAN bus drive signal is a function of the control signal; an output transistor having a current path coupled to the output node to provide the CAN bus drive signal via the current path of the output transistor; a switch having a current path coupled to the supply node and a control terminal coupled to the control node; a current mirror comprising a first current mirror transistor and a second current mirror transistor, the first current mirror transistor having a current path coupled between the supply node and the switch, the second current mirror transistor having a control terminal coupled to a control terminal of the first current mirror transistor and a current path coupled to the current path of the output transistor, wherein the current mirror is configured to switch between a first mode in which the CAN bus drive signal is applied to the output node via the output transistor and a second mode in which the output transistor provides a high output impedance at the output node according to the control signal; as well as a high voltage diode having an anode coupled to the current path of the second current mirror transistor and a cathode coupled to the current path of the output transistor.

18. The system of claim 17, wherein: The output node is coupled to a high side of the CAN bus to provide the CAN bus driving signal to the CAN bus.

19. A method of operating the system according to claim 17, comprising: The control signal is applied to the control node, resulting in operation of the system in the first mode, in which the CAN bus drive signal is applied to the output node via the output transistor, and then in the second mode, in which the output transistor provides a high output impedance at the output node.

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