Heterogeneous computing system and operation method thereof

Abstract

A heterogeneous computing system includes a first processor and a second processor of heterogeneity. The second processor is configured to execute multiple kernels unloaded from the first processor in order. A consistency controller is configured to classify each of the multiple kernels into one of a first group and a second group based on the attributes of the instructions included in each of the multiple kernels before the multiple kernels are executed, and is also configured to reclassify the one of the multiple kernels from the second group to the first group based on the interaction generated between the first processor and the second processor during the execution of the one of the multiple kernels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0009400 filed on January 25, 2018 with the Korean Intellectual Property Office is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concepts described herein relate to heterogeneous computing systems including different types of processors, and more particularly, to controlling cache coherence in the heterogeneous computing systems. Background Art

[0004] With the advancement of semiconductor technology, computing systems including multiple processors are being actively studied. Specifically, based on various factors (including the ability to process complex and various operations, the increase in user demand, etc.), the application scope of heterogeneous computing systems that do not include homogeneous processors but include heterogeneous processors is expanding. Typically, a heterogeneous computing system may include a central processing unit (CPU) and a graphics processing unit (GPU).

[0005] Task allocation is important for improving the computing power of heterogeneous computing systems. Relatively complex operations such as graphics processing are usually performed by the GPU. The processing of programs and / or kernels by the GPU may not be completed at the GPU stage, and the results of the processing of programs and / or kernels by the GPU may be shared with the CPU. In this process, cache consistency issues may occur because data is shared between the CPU and the GPU.

[0006] When considering cache coherence of heterogeneous computing systems, the workload of programs and / or kernels to be processed by the GPU is generally not considered. Typically, cache coherence is controlled in terms of cache hits or cache misses. Therefore, when data sharing between the CPU and GPU is frequent, programs and / or kernels can be processed in a non-cache coherent manner. When data sharing between the CPU and GPU is rare or infrequent, programs and / or kernels can be processed in a cache coherent manner. The above data processing and cache management may not be ideal in terms of resource management, power management, and system performance. Summary of the invention

[0007] Embodiments of the inventive concept provide a heterogeneous computing system in which cache coherence is adaptively controlled based on data shared by a CPU and a GPU.

[0008] According to some embodiments of the present inventive concept, a heterogeneous computing system may include: a first processor; a second processor configured to execute multiple kernels unloaded from the first processor in order, the first processor and the second processor being heterogeneous; and a consistency controller configured to classify each of the multiple kernels into one of a first group and a second group based on attributes of instructions included in each of the multiple kernels before the multiple kernels are executed. The consistency controller is also configured to reclassify one of the multiple kernels from the second group to the first group based on an interaction between the first processor and the second processor during execution of one of the multiple kernels.

[0009] According to other embodiments conceived by the present invention, a method for operating a heterogeneous computing system including a heterogeneous first processor and a second processor, the method including the following steps: unloading multiple cores from the first processor to the second processor; classifying each of the multiple cores into one of a first group and a second group based on attributes of instructions included in each of the multiple cores; executing the multiple cores in sequence using the second processor, wherein a first core of the multiple cores belonging to the first group can be executed in a cache-consistent manner, and a second core of the multiple cores belonging to the second group can be executed in a non-cache-consistent manner; and reclassifying the one of the second cores of the multiple cores from the second group to the first group based on interaction between the first processor and the second processor during execution of the one of the second cores of the multiple cores.

[0010] According to some other embodiments conceived by the present invention, a heterogeneous computing system may include: a CPU; a GPU, which executes multiple kernels unloaded from the CPU in sequence; and a consistency controller, which is configured to classify each of the multiple kernels into one of a first group and a second group based on attributes of instructions included in each of the multiple kernels before the multiple kernels are executed, and is also configured to reclassify one of the multiple kernels from the second group to the first group based on interaction between the CPU and the GPU during the execution of the one of the multiple kernels. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating an example configuration of a heterogeneous computing system according to an embodiment of the inventive concept;

[0013] Figure 2 is a block diagram illustrating an example configuration of a heterogeneous computing system according to some embodiments of the inventive concept;

[0014] Figure 3A is a diagram showing some embodiments of the present invention. Figure 2 A block diagram of another example configuration of a heterogeneous computing system is shown;

[0015] Figure 3B is a diagram showing some embodiments of the present invention. Figure 2 A block diagram of another example configuration of a heterogeneous computing system is shown;

[0016] Figure 3C is a diagram showing some embodiments of the present invention. Figure 2 A block diagram of another example configuration of a heterogeneous computing system is shown;

[0017] Figure 3D is a diagram showing some embodiments of the present invention. Figure 2 A block diagram of another example configuration of a heterogeneous computing system is shown;

[0018] Figure 4 is a block diagram illustrating the configuration and operation of a heterogeneous computing system according to some embodiments of the inventive concept;

[0019] Figure 5 The present invention is conceptually illustrated in some embodiments of the present invention. Figure 4 A diagram of the operation of a first consistency conflict analyzer is shown;

[0020] Figure 6 The present invention is conceptually illustrated in some embodiments of the present invention. Figure 4 A diagram of the operation of a second analyzer or consistency conflict tracker as shown;

[0021] Fig. 7A and Figure 7B is a diagram conceptually illustrating how a kernel offloaded from a central processing unit (CPU) is executed by a graphics processing unit (GPU) according to some embodiments of the inventive concept;

[0022] Figure 8 is a diagram illustrating an example of frequent data sharing (ie, dynamic sharing) between a CPU and a GPU according to some embodiments of the inventive concept;

[0023] Fig. 9 is a block diagram conceptually illustrating example operations for determining dynamic sharing of data between a CPU and a GPU according to some embodiments of the inventive concept;

[0024] Fig.10is a block diagram conceptually illustrating other example operations for determining dynamic sharing of data between a CPU and a GPU according to some embodiments of the inventive concept;

[0025] Fig.11 is a block diagram conceptually illustrating other example operations for determining dynamic sharing of data between a CPU and a GPU according to some embodiments of the inventive concept;

[0026] Fig.12 is a flow chart illustrating a method of controlling cache coherence of a heterogeneous computing system according to some embodiments of the inventive concept;

[0027] Fig.13 is a flow chart illustrating a method of controlling cache coherence of a heterogeneous computing system according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. Throughout the description of the accompanying drawings, the same reference numerals refer to the same elements. It should be noted that aspects of the invention described with reference to one embodiment may be combined with different embodiments, although this is not explicitly described. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0029] As used herein, the term "real time" means that operations are performed without the insertion of any scheduled or artificial delays.

[0030] Some embodiments of the inventive concept arise from the fact that in a heterogeneous computing system including, for example, a central processing unit (CPU) and a graphics processing unit (GPU), cache coherence can be managed primarily based on cache hits and misses by different processors. This can result in a situation where a kernel is executed in a non-cache coherent manner even when data is frequently shared between processors, and can also result in a situation where a kernel is executed in a cache coherent manner even when data is rarely shared between processors. Embodiments of the present invention may provide a cache coherence controller configured to classify kernels into a non-cache coherent group or a cache coherent group based on an analysis of the kernels' respective instructions prior to execution. However, the cache coherence controller may be further configured to reclassify the kernels between the two groups, such as reclassifying the kernels from a non-cache coherent group to a cache coherent group based on an analysis of data sharing between processors when executing the kernels. As a result, the reclassification can improve system performance by adaptively using cache memory for those kernels where data is more likely and / or more frequently shared between processors.

[0031] Figure 11 is a block diagram showing an example configuration of a heterogeneous computing system 100 according to some embodiments of the inventive concept. The heterogeneous computing system 100 may include two or more heterogeneous processors 110 and 120 and a coherence controller 130. Components constituting the heterogeneous computing system 100 may be communicatively connected through a bus 180.

[0032] In addition, in another embodiment, the system on chip SoC may be implemented to include a memory controller 140, a storage device controller 150, a communication module 160, and a display adapter 170. A system memory 145 may be connected to the memory controller 140. A storage device (storage) 155 may be connected to the storage device controller 150. A display 175 may be connected to the display adapter 170.

[0033] The heterogeneous computing system 100 may include one or more electronic devices, such as desktop computers, notebook computers, tablets, smart phones, wearable devices, video game consoles, workstations, and servers. In some embodiments, two or more heterogeneous processors 110 and 120 and the coherence controller 130 may be system-on-chip SoCs implemented in these devices.

[0034] Two or more heterogeneous processors 110 and 120 may be provided in one chip to provide a heterogeneous computing environment. For example, the two or more heterogeneous processors 110 and 120 may include a central processing unit (CPU) 110 and a graphics processing unit (GPU) 120.

[0035] The CPU 110 may control the overall operation of the heterogeneous computing system 100. The CPU 110 may process various arithmetic operations and / or logical operations. In some embodiments, the CPU 110 may be a multi-core processor including one or more processor cores. The CPU 110 may include a cache memory used by the one or more processor cores to perform various operations. The cache memory may temporarily store commands and / or parameter values ​​used by the CPU 110 to execute applications.

[0036] The GPU 120 may perform 2D and / or 3D processing. The GPU 120 may be used to perform rendering to output images through the display 175. In addition, the GPU 120 may be used to perform complex operations, such as calculations of geometric structures and calculations of scalar floating points and vector floating points. The GPU 120 may execute various commands encoded using an application programming interface (API) such as OpenCL, OpenGL, or WebGL. The GPU 120 may include a dedicated memory. In this case, the dedicated memory embedded in or connected to the GPU 120 may be used as a frame buffer, texture mapping, and / or array storage space.

[0037] The coherence controller 130 may be configured to maintain cache coherence between the CPU 110 and the GPU 120. For example, the coherence controller 130 may control information about data and / or variables that are frequently exchanged between the CPU 110 and the GPU 120. For example, the coherence controller 130 may allow the CPU 110 to share processing results of a kernel that is offloaded from the CPU 110 and processed by the GPU 120.

[0038] As described in more detail below, the coherence controller 130 may pre-analyze kernels that are offloaded from the CPU 110 and to be executed by the GPU 120, and may classify the kernels into two groups. For example, the first group of the classified groups may include kernels with memory-bound characteristics in which data sharing frequently occurs between the CPU 110 and the GPU 120. The second group of the classified groups may include kernels with compute-bound characteristics in which data sharing rarely or infrequently occurs between the CPU 110 and the GPU 120.

[0039] In addition, the coherence controller 130 may reclassify the kernels belonging to the second group while the kernels are executed by the GPU 120. For example, the coherence controller 130 may reclassify the kernels that are determined to belong to the second group but are subject to frequent data sharing between the CPU 110 and the GPU 120 as the first group. The CPU 110 and the GPU 120 may share the processing results of the kernels belonging to the first group through the cache memory included in the CPU 110 and the GPU 120. On the contrary, the CPU 110 and the GPU 120 may share the processing results of the kernels belonging to the second group through the system memory 145.

[0040] The memory controller 140 may control the system memory 145. For example, the memory controller 140 may control data input / output between the heterogeneous computing system 100 and the system memory 145.

[0041] The system memory 145 may temporarily store data processed by the CPU 110 and / or the GPU 120 or data to be processed by the CPU 110 and / or the GPU 120. In a boot operation, an operating system (OS), basic applications, and / or firmware are loaded into the system memory 145. For example, when the heterogeneous computing system 100 is booted, an OS image stored in the storage device 155 may be loaded into the system memory 145 based on a boot order. The overall input / output operation of the heterogeneous computing system 100 may be supported by the operating system OS. In addition, an application and / or firmware selected by a user or used to provide basic services (e.g., associated with graphics processing) may be loaded into the system memory 145.

[0042] For example, the system memory 145 may include a volatile memory such as a dynamic random access memory (DRAM) or a synchronous DRAM (SDRAM) and / or a non-volatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM). However, for the purpose of description, it is assumed below that the system memory is implemented by a DRAM based on a double data rate (DDR) interface.

[0043] The storage device controller 150 may control the storage device 155. For example, the storage device controller 150 may control data input / output between the heterogeneous computing system 100 and the storage device 155.

[0044] The storage device 155 may include one or more memory devices and a controller. The memory devices of the storage device 155 may retain data regardless of power. For example, the storage device 155 may include a non-volatile memory such as a flash memory, a PRAM, an MRAM, a ReRAM, or a FRAM. For example, the storage device 155 may include a storage medium such as a solid state drive (SSD), a removable storage, an embedded storage, etc.

[0045] The communication module 160 can communicate with external devices / systems of the heterogeneous computing system 100. Figure 1 As shown, at least a portion of the functionality of communication module 160 may be incorporated into a SoC including CPU 110, GPU 120, and coherence controller 130. However, in other embodiments, communication module 160 may be a functional block, circuit, or semiconductor chip manufactured independently of the SoC.

[0046] For example, the communication module 160 may support one or more wireless communication protocols such as (but not limited to) Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID); and / or one or more wired communication protocols such as (but not limited to) Transmission Control Protocol / Internet Protocol (TCP / IP), Universal Serial Bus (USB), and FireWire.

[0047] The bus 180 may provide a communication path between components of the heterogeneous computing system 100. For example, the bus 180 may include an off-chip interconnect. The components of the heterogeneous computing system 100 may exchange data with each other based on the bus format of the bus 180. For example, the bus format may include one or more of various interface protocols, such as USB, small computer system interface (SCSI), peripheral component interconnect express (PCIe), mobile PCIe (M-PCIe), advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS), integrated drive electronics (IDE), enhanced IDE (EIDE), non-volatile memory express (NVMe), and universal flash storage (UFS).

[0048] Figure 2 is a block diagram illustrating an example configuration of a heterogeneous computing system according to some embodiments of the inventive concept. Figure 1 Unlike the described embodiments, the heterogeneous computing system 200 may be implemented via a network on a chip (NoC) based on an on-chip interconnect.

[0049] The heterogeneous computing system 200 may have one or more modules including hardware intellectual property (IP). The hardware IP may include two or more heterogeneous processors 210 and 220, a consistency controller 230, a memory controller 240, a storage device controller 250, a communication module 260, and a display adapter 270. The configuration of the heterogeneous computing system 200 is not limited thereto. For example, the heterogeneous computing system 200 may further include a hardware IP 280. For example, the hardware IP 280 may be a user interface for providing convenience to the user, such as a camera module, an audio module, or a touch pad.

[0050] System memory 245 may be connected to memory controller 240, and storage device 255 may be connected to storage device controller 250. Display 275 may be connected to display adapter 270. Hardware IP and Reference Figure 1 The components described are substantially the same, and therefore, a detailed description thereof will not be repeated here.

[0051] However, each of the hardware IPs may include a network interface unit NIU. The network interface unit NIU provides an interface for communication between the hardware IPs. The hardware IPs may be connected to each other through the network interface unit NIU and a router "R". For example, the router "R" may include a buffer and an on-chip network switch. The hardware IPs may be connected in a communication manner through the switching operation of the on-chip network switch.

[0052] The routers “R”, the physical links connecting the routers “R” to each other, and the physical links connecting the routers “R” to the network interface unit NIU are called “on-chip interconnects.” Parallel communications between hardware IPs can be performed via the on-chip interconnects.

[0053] According to the example configurations of the heterogeneous computing systems 100 and 200 briefly described above, the kernels unloaded from the CPU are analyzed in advance and in real time. Since data sharing between the CPU and the GPU is performed through the cache memory based on the analysis results, the speed of accessing the shared data can be improved. In addition, since data is not unnecessarily shared through the system memory, system performance reduction or degradation can be prevented or reduced.

[0054] Figure 3A is a diagram showing some embodiments of the present invention. Figure 2 300a. The heterogeneous computing system 300a may include a CPU 310a, a GPU 320a, a coherence controller 330a, a memory controller 340a, a system memory 345a, a storage device controller 350a, and a storage device 355a. The components of the heterogeneous computing system 300a correspond to Figure 2 Therefore, the description provided above will not be repeated below, and the specific operation of the heterogeneous computing system 300a will be described based on the differences between the previously described embodiments.

[0055] Each of the CPU 310a and the GPU 320a includes a last level cache LLC. Figure 3A 310a and GPU 320a may also include a higher level cache. The CPU 310a and GPU 320a may communicate with the coherence controller 330a via an on-chip interconnect 390a. The on-chip interconnect 390a may support data sharing between the CPU 310a and GPU 320a performed by utilizing at least one of the last level caches LLC.

[0056] The coherence controller 330a may communicate with components of the heterogeneous computing system 300a via an on-chip interconnect 390a. The on-chip interconnect 390a may support both a cache coherent interconnect CCI and a non-cache coherent interconnect NCCI. The on-chip interconnect 390a may include a processor (e.g., a processor that performs an exchange operation between the CCI and the NCCI) and a processor that performs an exchange operation between the CCI and the NCCI. Figure 2 The on-chip network switch in the router “R” allows data processed by the CPU 310a and / or GPU 320a to be processed by any other hardware / software components.

[0057] The GPU driver 346a provides an interface that enables applications loaded into the system memory 345a to communicate with the GPU 320a. For example, the GPU driver 346a may call a program from an application to be executed on the heterogeneous computing system 300a or framework. The program called by the GPU driver 346a may be executed by the GPU 320a. That is, the program called by the GPU driver 346a may include multiple kernels (hereinafter referred to as "GPU kernels") that are unloaded by the CPU 310a to be executed on the GPU 320a. The GPU driver 346a may be loaded into the system memory 345a.

[0058] The kernel scheduler 348a can schedule the kernels to be executed on the CPU 310a and / or the GPU 320a and the threads of each kernel. The kernel scheduler 348a can analyze and identify the kernels to be executed on the CPU 310a and / or the GPU 320a. In addition, the kernel scheduler 348a can be a program generated by using an API such as OpenGL. The kernel scheduler 348a can be a program stored in the storage device 355a and loaded into the system memory 345a and executed on the system memory 345a.

[0059] Figure 3B is a diagram showing some embodiments of the present invention. Figure 2 2 is a block diagram of another example configuration of the heterogeneous computing system 200. The configuration and operation of the heterogeneous computing system 300b are similar to Figure 3A The illustrated heterogeneous computing system 300a is similar and will be described based on the differences from previously described embodiments.

[0060] The CPU 310b and the GPU 320b may communicate with the hardware and software components constituting the heterogeneous computing system 300b through the on-chip interconnect 390b. In particular, a consistency controller 330b that controls data sharing between the CPU 310b and the GPU 320b may be provided in the memory controller 340b. Figure 3B In the embodiment of the present invention, the on-chip interconnect 390b may support both CCI and NCCI.

[0061] The consistency controller 330b may be implemented in the memory controller 340b. For example, data associated with a GPU core in which data sharing between the CPU 310b and the GPU 320b is frequently performed may be referenced through the cache consistency directory of the consistency controller 330b. That is, because data is shared using the last level cache LLC of the CPU 310b and the GPU 320b instead of using the system memory 345b, the processing speed of the GPU core may be increased, and unnecessary waste of system memory 345b resources may be prevented or reduced.

[0062] Figure 3C is a diagram showing some embodiments of the present invention. Figure 2 The configuration and operation of the heterogeneous computing system 300c are similar to those of Figure 3A or Figure 3B The illustrated heterogeneous computing systems 300a or 300b are similar and will be described based on the differences from previously described embodiments.

[0063] The consistency controller 330c may be implemented in both the CPU 310c and the GPU 320c. For example, the first consistency controller CH CTRL1 may be implemented in the CPU 310c, and the second consistency controller CH CTRL2 may be implemented in the GPU 320c. The first consistency controller CH CTRL1 and the second consistency controller CH CTRL2 may not be configured to store the same data. That is, the second consistency controller CH CTRL2 may not be a replica of the first consistency controller CH CTRL1. However, the first consistency controller CH CTRL1 and the second consistency controller CH CTRL2 may be connected to each other through the on-chip interconnect 390c to share data.

[0064] For example, data associated with a GPU core in which data sharing between the CPU 310 c and the GPU 320 c is frequently performed may be referenced through the cache coherence directory of the first coherence controller CH CTRL1 or the cache coherence directory of the second coherence controller CH CTRL2. That is, data is shared by using the last level cache LLC of the CPU 310 c and the GPU 320 c instead of the system memory 345 c.

[0065] Figure 3D is a diagram showing some embodiments of the present invention. Figure 2 The configuration and operation of the heterogeneous computing system 300d are similar to those of Figure 3A The heterogeneous computing system 300a shown is similar and will be described based on the differences from the previously described embodiments. However, the heterogeneous computing system 300d may include a shared last level cache. For example, the shared last level cache may be implemented external to the CPU 310d and the GPU 320d.

[0066] Reference FIG. 3A to FIG. 3D describe Figure 2 However, the present invention is not limited to on-chip networks based on on-chip interconnects. That is, the present invention can be applied to Figure 1However, in the embodiments described below, the description will be provided based on the assumption that the inventive concept is applied to an on-chip network based on an on-chip interconnect.

[0067] Figure 4 4 is a block diagram illustrating a configuration and operation of a heterogeneous computing system according to some embodiments of the inventive concept. The heterogeneous computing system 400 may include a CPU 410, a GPU 420, a coherence controller 430, and a system memory 445. As described above, the CPU 410, the GPU 420, and the coherence controller 430 may constitute an on-chip network manufactured using one chip.

[0068] First, for purposes of illustration, it is assumed that the program unloaded from the CPU 410 includes multiple kernels and the multiple kernels are executed in order. The GPU kernels may be analyzed before the GPU 420 executes the GPU kernels. For example, a compiler 446 loaded into the system memory 445 and executed thereon may analyze the instructions of each kernel. The instructions of the multiple kernels may include arithmetic commands, load and store commands, texture commands, and / or any other commands. The analysis results of the compiler 446 (i.e., kernel instruction distribution) are transferred to a first analyzer (i.e., consistency conflict analyzer; CIA) 434.

[0069] The coherence controller 430 may include a cache coherence directory 432, a first analyzer 434, and a second analyzer (i.e., a coherence conflict tracker; CIT) 436. The cache coherence directory 432 may include data types, cache addresses, sharing information, and validity information to be referenced by the CPU 410 and / or the GPU 420. Here, the sharing information includes information on whether the data to be referenced by the cache address is shared by the CPU 410 and the GPU 420.

[0070] Before the GPU kernel is executed, the first analyzer 434 can statically analyze each kernel. For example, based on the kernel instruction distribution received from the compiler 446, the first consistency conflict analyzer 434 can determine whether each kernel has a memory-bound characteristic or a computation-bound characteristic.

[0071] If the ratio of the instructions with specific attributes to all instructions of the kernel is greater than or equal to the threshold, the first analyzer 434 may classify the corresponding kernel as a kernel with memory constraint characteristics. Here, the instructions with specific attributes may be instructions related to loading from and / or storing to the CPU 410. In other words, loading from the CPU 410 may mean unloading the GPU kernel and / or loading the intermediate processing results of the CPU 410. The storage to the CPU 410 may return the intermediate processing results or the final processing results of the GPU 420.

[0072] The analysis result of the first coherency conflict analyzer 434 may be stored in a memory (eg, a last level cache LLC and / or a higher level cache) of the CPU 410 , but embodiments of the inventive concept are not limited thereto.

[0073] exist Figure 4 In the embodiment of FIG. 4 , first coherency conflict analyzer 434 is shown as a hardware block included in coherency controller 430. However, in other embodiments, coherency controller 430 may alternatively or additionally be a software module loaded into system memory 445 and executed thereon, or may be included in a dedicated memory (not shown) in or connected to GPU 420.

[0074] The CPU 410 or the GPU 420 may execute the kernel classified by the first analyzer 434. That is, the kernel having the memory constraint characteristic may be processed in a cache-consistent manner, and the processing result of the kernel may be shared through the last level cache LLC. On the contrary, the kernel having the computation constraint characteristic may be processed in a non-cache-consistent manner, and the processing result of the kernel may be shared through the system memory 445.

[0075] The efficiency of data sharing between the CPU 410 and the GPU 420 may be improved by uniformly analyzing the kernel based on the analysis result of the compiler 446. However, while executing the kernel to be processed in a non-cache coherent manner, data may be exchanged (i.e., interacted) between the CPU 410 and the GPU 420. In this case, data sharing through the last level cache LLC may be more efficient than data sharing through the system memory 445.

[0076] In some embodiments of the present inventive concept, the second analyzer 436 may reclassify the kernel having the computational constraint characteristic while the kernel is being executed. For example, the second analyzer 436 may monitor the data exchange between the CPU 410 and the GPU 420 in real time. In addition, the second consistency conflict tracker 436 may additionally monitor various factors associated with the data exchange between the CPU 410 and the GPU 420. The process in which the second consistency conflict tracker 436 reclassifies the kernel being executed will be described more fully below.

[0077] When it is determined that data is exchanged between the CPU 410 and the GPU 420 based on a certain frequency while the kernel to be processed in a non-cache coherent manner is being executed, the second analyzer 436 may update the cache coherence directory 432 so that the kernel being executed is processed in a cache coherent manner. As a result, data sharing between the CPU 410 and the GPU 420 during the execution of the kernel may be performed through the last level cache LLC. That is, the shared data stored in the system memory 445 may be copied to the shared cache area.

[0078] Above Figure 4 The embodiment is based on Figure 3A However, with appropriate modifications / changes Figure 4 The embodiments are applied to FIG. 3B to FIG. 3D Embodiment of the invention.

[0079] Figure 5 The present invention is conceptually illustrated in some embodiments of the present invention. Figure 4 4 is a diagram of the operation of the first consistency conflict analyzer 434 shown in FIG. As described above, the program unloaded from the CPU includes a plurality of GPU kernels Kernel#1 to Kernel#N that are sequentially executed by the CPU 410 or the GPU 420. For better understanding, reference will be made to FIG. Figure 4 and Figure 5 Describe them together.

[0080] The GPU kernels Kernel#1 to Kernel#N are analyzed by the compiler 446 before execution. The first analyzer 434 may treat the executed kernel classification in order based on the analysis results (i.e., the distribution of kernel instructions). For example, the first consistency conflict analyzer 434 may classify the kernels that are expected to have frequent data exchange between the CPU 410 and the GPU 420 into a first group. The kernels belonging to the first group indicated by the CCI may be processed in a cache consistent manner. On the contrary, the first analyzer 434 may classify the kernels that are expected to have little or infrequent data exchange between the CPU 410 and the GPU 420 into a second group. The second group of kernels indicated by the NCCI may be processed in a non-cache consistent manner.

[0081] Then, the GPU 420 may execute the kernels in order from kernel Kernel#1 to kernel Kernel#N.

[0082] Figure 6 It is conceptually shown Figure 4 436. Figure 4 and Figure 6 Provide a description along with it.

[0083] The second consistency conflict tracker 436 may monitor the data exchange between the CPU 410 and the GPU 420 while each kernel is being executed, and may reclassify the kernel being executed based on the monitoring result. The kernels targeted for monitoring and reclassification are the kernels of the second group indicated by the NCCI. The kernels in the second group that are determined to have frequent data exchanges between the CPU 410 and the GPU 420 may be reclassified as belonging to the first group. For example, the number of exchanges and / or the frequency of exchanges may be considered. In an embodiment, Figure 6 The example in FIG. 1 shows that kernels Kernel#N-1 and Kernel#N are reclassified as belonging to the first group.

[0084] The second consistency conflict tracker 436 may update the cache consistency directory 432 with respect to the reclassified kernels Kernel #N-1 and Kernel #N. As the cache consistency directory 432 is updated, the data type, cache address, sharing information, and validity information of the reclassified kernels Kernel #N-1 and Kernel #N may be updated. That is, the CPU 410 and the GPU 420 may share data through the last level cache LLC instead of the system memory 445 with reference to the cache consistency directory 432 information.

[0085] Fig. 7A and Figure 7B is a diagram conceptually illustrating how a kernel offloaded from a CPU is executed by a GPU according to some embodiments of the present invention. Figure 4 and Figure 6 Provide a description along with it.

[0086] Fig. 7A An example is shown in which data is not shared between the CPU 410 and the GPU 420. The kernel offloaded from the CPU 410 is transferred as input to the GPU 420. The GPU 420 processes the thread of the offloaded kernel. For example, Fig. 7A The embodiment may correspond to a case where a dedicated memory included in or connected to the GPU 420 is initialized. Since the thread is processed only by the GPU 420, data is not shared between the CPU 410 and the GPU 420. In this case, since the kernel does not need to be processed in a cache-coherent manner, the kernel may be processed in a non-cache-coherent manner.

[0087] Figure 7B 4 shows an example in which data sharing is performed between the CPU 410 and the GPU 420. The GPU 420 can process the threads of the kernel unloaded from the CPU 410, and the processing results are transferred to the CPU 410. For example, Figure 7BThe embodiment of may correspond to an example in which GPU 420 performs all operations and CPU 410 receives and processes the operation results. Even if data is once shared between CPU 410 and GPU 420, the kernel being executed may be continuously processed in a non-cache consistent manner.

[0088] Figure 8 4 is a diagram showing an example of frequently sharing (ie, dynamically sharing) data between the CPU 410 and the GPU 420. For better understanding, reference will be made to Figure 4 and Figure 6 Provide a description along with it.

[0089] For example, the kernel unloaded from the CPU 410 is input to the GPU 420 as the first input Input#1. The GPU 420 processes the first thread Threads#1 according to the first input Input#1, and outputs the first output Output#1 as a processing result. The CPU 410 processes the first output Output#1 as an intermediate result, and inputs the intermediate result to the GPU 420 as the second input Input#2. The k-th output Output#k processed by the GPU 420 may be input to the CPU 410 through a series of the above-mentioned processes.

[0090] from Figure 8 It is understood that the data exchange between the CPU 410 and the GPU 420 is frequent. For example, when the image frame is divided into a plurality of tiles and processed in units of tiles, the data exchange between the CPU 410 and the GPU 420 may be frequent. The reason is that the adjacency information of the adjacent tiles can be used when processing any one of the plurality of tiles constituting the image frame. For another example, when performing complex computing operations, the data exchange between the CPU 410 and the GPU 420 may be frequent.

[0091] The second analyzer or consistency input tracker 436 may monitor the data exchange between the CPU 410 and the GPU 420 in real time. The second consistency conflict tracker 436 may determine that data is dynamically shared between the CPU 410 and the GPU 420, for example, based on the amount of data exchanged between the CPU 410 and the GPU 420, the number of data exchanges, etc. The second analyzer or second consistency conflict tracker 436 may reclassify the kernels determined to dynamically share data into the first group. In addition, the second analyzer or second consistency conflict tracker 436 may update the cache consistency directory 432 with respect to the kernel being executed.

[0092] As the cache coherence directory 432 is updated, data sharing between the CPU 410 and the GPU 420 may be performed through the last level cache LLC instead of the system memory 445. That is, even if the kernel is being executed, the kernel reclassified as belonging to the first group may be processed in a cache coherent manner instead of the existing non-cache coherent manner (i.e., the reclassified kernel is processed in a manner of converting from a non-cache coherent manner to a cache coherent manner).

[0093] Figure 8 The description provided in relates to an embodiment in which a determination is made whether data is dynamically shared based on data exchange between the CPU 410 and the GPU 420. However, alternatively or in addition, other criteria may be applied in making such a determination. Fig. 9 , Fig.10 and Fig.11 The embodiment is described.

[0094] Fig. 9 5 is a block diagram conceptually illustrating an operation of determining to dynamically share data between the CPU 510 and the GPU 520 according to some embodiments of the inventive concept. For better understanding, reference will be made to Figure 4 and Fig. 9 Provide a description along with it.

[0095] First, it is assumed that the kernel being executed is executed in a non-cache coherent manner and the processing results Data1 and Data2 of the CPU 510 and the GPU 520 are stored in the system memory 545. That is, data sharing between the CPU 510 and the GPU 520 is performed through the system memory 545.

[0096] If data exchange between the CPU 510 and the GPU 520 is frequent, commands and addresses for accessing a specific area of ​​the system memory 545 may be frequently generated. In this case, the second analyzer or the second consistency conflict tracker 536 may monitor commands and / or addresses for accessing the area of ​​the system memory 545 in which the shared data is stored. If it is determined that the area of ​​the system memory 545 in which the shared data is stored is frequently accessed, the second consistency conflict tracker 536 may determine that dynamic sharing of data is performed by the CPU 510 and the GPU 520. For example, the number of times or frequency at which commands and / or addresses are issued may be considered as a criterion for determining dynamic sharing of data.

[0097] In an example where it is determined that the processing result of the kernel being executed by the GPU 520 is frequently shared by the CPU 510, the data shared by the CPU 510 and the GPU 520 may be copied to at least one of the last level cache LLCs of the CPU 510 and the GPU 520. The second consistency conflict tracker 536 may update the cache consistency directory 532, and the CPU 510 and / or the GPU 520 may access the shared data with reference to the updated cache consistency directory 532.

[0098] Fig.10 6 is a block diagram conceptually illustrating further operations for determining dynamic sharing of data between the CPU 610 and the GPU 620 according to some embodiments of the inventive concept. Fig.10 In an embodiment of the present invention, snoop requests and replies issued to maintain cache coherence may be used when determining dynamic sharing of data between CPU 610 and GPU 620. For better understanding, reference will be made to Figure 4 and Fig.10 Provide a description along with it.

[0099] The CPU 610 may monitor the on-chip interconnect 690 in order to maintain cache coherence of the heterogeneous computing system 600 including the CPU 610 and the GPU 620. If cache coherence of data stored in the last level cache LLC of the GPU 620 is maintained, the on-chip interconnect 690 may send a reply corresponding to the cache coherence to the CPU 610, and vice versa (i.e., cache coherence of data stored in the last level cache LLC of the CPU 610).

[0100] For example, when snoop requests and replies are frequently generated, data sharing may be performed through the last level cache LLC of the CPU 610 and the GPU 620. Therefore, the shared data associated with the snoop requests and replies may be data that may benefit from fast processing.

[0101] If cache coherence is not maintained in the CPU 610 and / or the GPU 620 (i.e., a snoop miss), the on-chip interconnect 690 may access a region of the system memory 645 in which the shared data is stored. In this example, the second coherence conflict tracker 636 may monitor access to the system memory 645 in which the shared data is stored. As described above, because a snoop miss may occur while data is frequently shared between the CPU 610 and the GPU 620, it may be necessary to quickly process the kernel being executed in the GPU 620 in a cache coherent manner.

[0102] The second analyzer 636 may update the cache coherency directory (eg, Figure 4 As a result of the update, the shared data stored in the system memory 645 may be copied to the last level cache LLC of the CPU 610 and / or the GPU 620, so that cache coherence may be maintained. Then, the kernel being executed in the GPU 620 may be processed in a cache coherent manner.

[0103] Fig.11 7 is a block diagram conceptually illustrating other operations for determining dynamic sharing of data between the CPU 710 and the GPU 720 according to some embodiments of the inventive concept. Fig.11 In the embodiment of the present invention, shared virtual memory (SVM) may be used when determining to dynamically share data between CPU 710 and GPU 720. For better understanding, reference will be made to Figure 4 and Fig.11 Provide a description along with it.

[0104] In a heterogeneous computing system in which multiple (particularly heterogeneous) processors are implemented in one chip, shared virtual memory may be used for the heterogeneous processors to efficiently access system memory. For example, data sharing may be determined by monitoring write data processed by CPU 710 in the shared virtual memory and write data processed by GPU 720 in the shared virtual memory. Similarly, read data from the shared virtual memory may be monitored.

[0105] If data stored in the system memory 745 is frequently shared by the CPU 710 and the GPU 720, and the sharing is determined based on the result of monitoring the read / write to the shared virtual memory, the second consistency conflict tracker 736 may update the cache consistency directory (e.g., Figure 4 As a result of the update, the shared data stored in the system memory 745 may be copied to the last level cache LLC of the CPU 710 and / or the GPU 720. Then, the kernel being executed in the GPU 720 may be processed in a cache-coherent manner.

[0106] Various criteria may be used to determine whether to dynamically share data between the CPU 710 and the GPU 720. For example, the second coherency conflict tracker 736 may monitor the number of cache misses that occur and / or the frequency of accesses to the system memory 745.

[0107] Fig.12is a flow chart illustrating a method for controlling cache coherence of a heterogeneous computing system according to some embodiments of the present invention. Figure 4 , Figure 6 and Fig.12 Provide a description along with it.

[0108] In block S110, the GPU kernels offloaded from the CPU 410 may be input or provided to the GPU 420. The kernels offloaded from the CPU 410 may constitute a program, and the plurality of kernels are executed in sequence by the GPU 420.

[0109] At block S120, a first analysis is performed by the first analyzer 434 before executing the GPU kernel. The first analyzer 434 may classify the kernels into two groups based on the kernel instruction distribution received from the compiler 446. For example, the first group may include kernels in which data sharing is frequently performed between the CPU 410 and the GPU 420, and the second group may include kernels in which data sharing is rarely or infrequently performed between the CPU 410 and the GPU 420. For example, the instructions for determining dynamic sharing may be instructions associated with loading from the CPU 410 to the GPU 420 and / or input from the GPU 420 to the CPU 410.

[0110] At block S130, the GPU kernels may be executed. As described above, the GPU kernels may be executed in order. Additionally, the kernels of the first group may be executed in a cache-coherent manner, and the kernels of the second group may be executed in a non-cache-coherent manner.

[0111] At block S140, one or more of the kernels in the second group may be reclassified by the second analyzer 436. Even if the kernels are classified as belonging to the second group based on the kernel instruction distribution received from the compiler 446, there may be kernels associated with dynamic sharing of data with the CPU 410. Therefore, the second analyzer 436 may reclassify the kernels determined to dynamically share data into the first group.

[0112] A kernel reclassified as belonging to the first group (even if it is processed by GPU 420) may be changed so that it can be processed in a cache-coherent manner. Figure 2 In the embodiment of FIG. 5 , the on-chip network switch of router “R” may perform appropriate switching operations to handle the cores reclassified into the first group in a cache-coherent manner.

[0113] At block S150 , the results of the kernels processed by the GPU 420 may be collected and processed by the CPU 410 , and the rendered images or computational results associated with the GPU kernels may be provided to a user.

[0114] Fig.13is a flow chart illustrating a method for controlling cache coherence of a heterogeneous computing system according to some embodiments of the present invention. Figure 4 , Figure 6 and Fig.13 Provide a description along with it.

[0115] In block S205 , the GPU kernel offloaded from the CPU 410 may be input or provided to the GPU 420 .

[0116] At block S210, the GPU kernels are analyzed prior to execution to determine whether each kernel has a memory constraint characteristic. For example, the first analyzer 434 may determine the attributes of each kernel based on the kernel instruction distribution received from the compiler 446. For example, the attributes used for the determination may be instructions associated with loading from the CPU 410 to the GPU 420 and / or instructions associated with the results of processing output from the GPU 420 to the CPU 410.

[0117] When it is determined that the kernel has a memory-bound characteristic (Yes), block S215 is executed. This means that the data associated with the kernel processed by GPU 420 is frequently shared by CPU 410. On the contrary, when it is determined that the kernel has a compute-bound characteristic (No), block S235 is executed. This means that the data associated with the kernel processed by GPU 420 is rarely or infrequently shared by CPU 410.

[0118] At block S215, the kernel may be processed in a cache-coherent manner. That is, the result of processing the GPU kernel at GPU 420 may be shared via the last level cache LLC. Because data is frequently shared between CPU 410 and GPU 420, it is determined at block S210 that the kernel has a memory-constrained characteristic. The intermediate processing results of the GPU kernel may be input to CPU 410, and CPU 410 may accumulate the processing results or may perform the following additional processing (block S220).

[0119] In block S225, it is determined whether the kernel currently being executed is the last kernel. When it is determined that the kernel currently being executed is the last kernel (yes), block S230 is executed; when it is determined that the kernel currently being executed is not the last kernel (no), the process proceeds to block S205.

[0120] At block S230 , the results of the kernels processed by the GPU 420 may be collected and processed by the CPU 410 , and a rendered image or calculation results associated with the GPU kernels may be provided to a user.

[0121] When the kernel has a computationally bound characteristic, at block S235, the kernel is processed in a non-cache coherent manner. This means that data associated with the kernel processed by GPU 420 is rarely or infrequently shared by CPU 410. Data associated with the kernel processed by GPU 420 may be shared via system memory 445 instead of the last level cache LLC.

[0122] In block S240 , the second analyzer or second coherency violation tracker 136 may monitor data sharing between the CPU 410 and the GPU 420 .

[0123] At block S245, the second analyzer or second consistency conflict tracker 136 may determine whether data is frequently exchanged (i.e., dynamically shared) between the CPU 410 and the GPU 420. For example, the second consistency conflict tracker 436 may determine whether data is frequently exchanged between the CPU 410 and the GPU 420 based on, for example, data exchanges between the CPU 410 and the GPU 420, snoop requests and replies, read / write operations to a shared virtual memory, accesses to a system memory due to consecutive cache misses, and the like.

[0124] When it is determined that the data is dynamically shared (Yes), block S250 is executed; otherwise (No), the process proceeds to block S255.

[0125] At block S250, the cache coherence directory associated with the GPU kernel being executed may be updated. As a result, the GPU kernel may be processed in a cache coherent manner. That is, the result of processing the GPU kernel may be shared by the CPU 410 and the GPU 420 via the last level cache LLC.

[0126] At block S255, the GPU kernel being executed may be completely processed. Because it is determined that data associated with the GPU kernel being executed is not dynamically shared, the GPU kernel may be continuously processed in a non-cache coherent manner.

[0127] According to an embodiment of the inventive concept, a heterogeneous computing system may be provided to adaptively control cache coherence based on data sharing between a CPU and a GPU.

[0128] In addition, according to an embodiment of the inventive concept, the kernel can be classified based on the instruction attributes of the kernel. In some embodiments, the kernel can be reclassified based on data exchange between the CPU and the GPU while executing the kernel to allow adaptive control of cache coherence.

[0129] Other definitions and embodiments:

[0130] In the above-mentioned various embodiments of the inventive concept, various aspects of the inventive concept may be shown and described herein in any number of patentable classifications or contexts including any new and useful processing, machine, manufacturing or composition of matter, or any new and useful improvement. Therefore, various aspects of the inventive concept may be implemented entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or in combination with hardware and software embodiments (generally referred to as "circuits", "modules", "components", "components", "units" or "systems"). For example, hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit chips, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, or combinations thereof. In addition, various aspects of the inventive concept may take the form of a computer program product including one or more computer-readable media (having computer-readable program codes).

[0131] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium may be (but not limited to) an electronic, magnetic, optical, electromagnetic or semiconductor system, device or apparatus or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a suitable optical fiber with a repeater, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device or any suitable combination thereof. In the context of this document, a computer-readable storage medium may be a tangible medium that may contain or store a program that is used by or in conjunction with an instruction execution system, device or apparatus.

[0132] Computer readable signal media may include, for example, a propagated data signal in which a computer readable program code is implemented in a baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium, and may communicate, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or apparatus. The program code implemented on a computer readable signal medium may be transmitted using any suitable medium, including, but not limited to, wireless, wired, fiber optic cable, RF, etc., or any suitable combination thereof.

[0133] The computer program code for performing the operations of various aspects of the present invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc.), traditional procedural programming languages ​​(such as "C" programming languages, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, LabVIEW), dynamic programming languages ​​(such as Python, Ruby and Groovy) or other programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter scheme, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (for example, by utilizing the Internet of an Internet service provider), or in a cloud computing environment or as a service (for example, software as a service (SaaS)) Provided.

[0134] Various aspects of the inventive concept are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that instructions executed by a processor of a computer or other programmable instruction execution device create a mechanism for implementing the function / action specified in one or more boxes of a flowchart and / or block diagram.

[0135] These computer program instructions may also be stored in a computer-readable medium, which, when executed, may direct a computer, other programmable data processing device, or other apparatus to operate in a particular manner, such that when these instructions are stored in a computer-readable medium, an article of manufacture including instructions is generated, which, when executed, causes the computer to implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram. The computer program instructions may also be loaded onto a computer, other programmable instruction execution device, or other apparatus, so that a series of operating steps are performed on the computer, other programmable apparatus, or other apparatus to produce a computer-implemented process, such that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0136] The flowcharts and block diagrams in the figure illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various aspects of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment or code portion, which includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the block may not appear in the order noted in the accompanying drawings. For example, two blocks actually displayed in succession may be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block of the block diagram and / or flowchart illustration and the combination of blocks in the block diagram and / or flowchart illustration can be implemented by a dedicated hardware-based system or a combination of dedicated hardware and computer instructions that performs a specified function or action.

[0137] While the inventive concept has been described with reference to example embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A heterogeneous computing system, comprising: a first processor; a second processor configured to sequentially execute the plurality of kernels offloaded from the first processor, wherein the first processor and the second processor are heterogeneous; as well as A consistency controller configured to classify each of the plurality of cores into one of a first group and a second group based on attributes of instructions included in each of the plurality of cores before the plurality of cores are executed, and further configured to reclassify one of the plurality of cores from the second group to the first group based on an interaction between the first processor and the second processor during execution of the one of the plurality of cores.

2. The heterogeneous computing system according to claim 1, wherein: The first processor is a central processing unit and the second processor is a graphics processing unit.

3. The heterogeneous computing system according to claim 1, wherein: executing a first core of the plurality of cores classified into the first group in a cache-coherent manner in which sharing of first data between the first processor and the second processor is performed by utilizing at least one of last level caches of the first processor and the second processor, and The second core classified into the second group among the plurality of cores is executed in a non-cache consistent manner, and the sharing of the second data between the first processor and the second processor is performed by using an external system memory in the non-cache consistent manner.

4. The heterogeneous computing system according to claim 1, wherein: The consistency controller comprises: a first analyzer configured to classify each of the plurality of kernels into one of the first group and the second group based on a property of the instructions included in each of the plurality of kernels before the plurality of kernels are executed, a second analyzer configured to reclassify the one of the plurality of cores from the second group to the first group based on an extent to which data is shared by the first processor during execution of the one of the plurality of cores; and A cache coherence directory is configured to store information about the one of the plurality of cores.

5. The heterogeneous computing system according to claim 4, wherein: The cache coherence directory is configured to store at least one of a data type, a cache address, sharing information, and validity information of data referenced by the first processor or the second processor.

6. The heterogeneous computing system according to claim 1, wherein: The instructions include arithmetic commands, load commands from the first processor to the second processor, store commands from the second processor to the first processor, and texture commands.

7. The heterogeneous computing system according to claim 6, wherein: The consistency controller is further configured to: Each of the plurality of cores is classified into one of the first group and the second group based on a ratio of the number of the load commands and the store commands among the instructions included in each of the plurality of cores.

8. The heterogeneous computing system according to claim 1, wherein: The consistency controller is also configured to reclassify the one of the multiple cores from the second group to the first group based on at least one of the frequency at which data associated with the one of the multiple cores is exchanged by the first processor and the number of times the data associated with the one of the multiple cores is exchanged by the first processor.

9. The heterogeneous computing system according to claim 1, wherein: The first processor is further configured to: The execution results of the kernels executed in order are collected and provided to the user.

10. The heterogeneous computing system according to claim 1, wherein: The heterogeneous computing system is a system on a chip in which the first processor, the second processor, and the coherence controller are implemented using one chip.

11. A method of operating a heterogeneous computing system, the method comprising the following steps: offloading a plurality of cores from a first processor to a second processor, wherein the first processor and the second processor are heterogeneous; classifying each of the plurality of kernels into one of a first group and a second group based on attributes of instructions included in each of the plurality of kernels; executing the plurality of kernels in order using the second processor, wherein a first kernel belonging to the first group among the plurality of kernels is executed in a cache-coherent manner, and wherein a second kernel belonging to the second group among the plurality of kernels is executed in a non-cache consistent manner; and The one of the second cores in the plurality of cores is reclassified from the second group to the first group based on an interaction between the first processor and the second processor during execution of the second core in the plurality of cores.

12. The method according to claim 11, wherein: The first processor is a central processing unit and the second processor is a graphics processing unit.

13. The method according to claim 11, wherein: executing a first kernel of the plurality of kernels by sharing first data by the first processor and the second processor using at least one of the last level caches of the first processor and the second processor, and The second kernel among the plurality of kernels is executed by sharing second data by the first processor and the second processor using an external system memory.

14. The method according to claim 11, wherein: The step of classifying each of the plurality of cores includes classifying each of the plurality of cores into one of the first group and the second group based on a ratio of the number of load commands from the first processor to the second processor and the number of store commands from the second processor to the first processor among instructions included in each of the plurality of cores.

15. The method according to claim 14, wherein: The step of classifying each of the plurality of kernels includes classifying a corresponding kernel among the plurality of kernels, for which the ratio exceeds a threshold, into the first group.

16. A heterogeneous computing system, comprising: Central processing unit; a graphics processing unit configured to sequentially execute the plurality of kernels offloaded from the central processing unit; as well as A consistency controller configured to classify each of the plurality of cores into one of a first group and a second group based on attributes of instructions included in each of the plurality of cores before the plurality of cores are executed, and further configured to reclassify one of the plurality of cores from the second group to the first group based on an interaction between the central processing unit and the graphics processing unit during execution of the one of the plurality of cores.

17. The heterogeneous computing system according to claim 16, wherein: executing a first kernel of the plurality of kernels classified into the first group in a cache-coherent manner in which sharing of data between the central processing unit and the graphics processing unit is performed by utilizing at least one of last level caches of the central processing unit and the graphics processing unit, and The second core among the plurality of cores classified into the second group is executed in a non-cache coherent manner, in which data sharing between the central processing unit and the graphics processing unit is performed by using an external system memory.

18. The heterogeneous computing system according to claim 16, wherein: The consistency controller comprises: a first analyzer configured to classify each of the plurality of kernels into one of the first group and the second group based on a property of the instructions included in each of the plurality of kernels before the plurality of kernels are executed, a second analyzer configured to reclassify the one of the plurality of kernels from the second group to the first group based on an extent to which data is shared by the central processing unit during execution of the one of the plurality of kernels; and A cache coherence directory is configured to store information about the one core of the plurality of cores.

19. The heterogeneous computing system according to claim 18, wherein: The cache coherence directory is configured to store at least one of a data type, a cache address, sharing information, and validity information of data referenced by the central processing unit or the graphics processing unit.

20. The heterogeneous computing system according to claim 16, wherein: The consistency controller is also configured to reclassify the one of the multiple cores from the second group to the first group based on at least one of the frequency with which data associated with the one of the multiple cores is exchanged by the central processing unit and the number of times the data associated with the one of the multiple cores is exchanged by the central processing unit.

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