Apparatus and method for linearization of control input for dual output resonant converter

Abstract

A power converter comprises: a dual-output resonant converter, comprising a first output terminal, a second output terminal, a common-mode control input terminal and a differential-mode control input terminal, and controlling the voltage / current at the first output terminal and the second output terminal in response to a common-mode control signal and a differential-mode control signal; and a dual-output controller, comprising a first error signal input terminal, a second error signal input terminal, a delta power signal input terminal, a common-mode control output terminal and a differential-mode control output terminal, the dual-output controller being configured to generate a common-mode control signal and a differential-mode control signal in response to the first error signal and the second error signal, the first error signal being a function of the voltage / current at the first output terminal, and the second error signal being a function of the voltage / current at the second output terminal, and the common-mode control signal being output from the common-mode control output terminal, and the differential-mode control signal being output from the differential-mode control output terminal, and the common-mode control signal being generated using a feedback loop.

Description

Technical Field

[0001] Various exemplary embodiments disclosed herein generally relate to a method and apparatus for linearizing a control input of a dual output resonant converter. Background Art

[0002] For power converters operating at powers greater than about 100 watts (W) at full load, resonant topologies provide efficient and small / high power density solutions. At power levels above 100 watts, the additional costs (e.g., additional switches, additional secondary diodes, resonant capacitors) compared to other topologies are compensated by the additional advantages of the resonant topology. There are several types of resonant converters, such as series resonant converters, LLC converters, and LCC converters. The series resonant converter uses a resonant capacitor Cr and an inductor Ls as resonant components, while LLC and LCC converters use three resonant components. For the LLC converter, the magnetizing inductance of the transformer participates in the resonance, while for the LCC converter, the additional capacitor participating in the resonance is present on the secondary side of the transformer.

[0003] Resonant power supplies are used in light emitting diode (LED) television applications to provide a low voltage output of about 12V DC to supply low voltage circuits and a high voltage output of about 165V to supply LED strings for the backlight of the display. Such resonant power supplies typically contain a main regulation loop that senses the 12V output and adjusts the power level of the converter to keep the 12V output constant as the load changes. The 165V output then follows the 12V at a more or less fixed ratio as set by the turns ratio of the resonant transformer. Because the 165V output is unregulated, the output voltage of the 165V output can vary greatly as the load on the 165V output and the 12V output changes. Therefore, a second control stage is typically used after the 165V output to provide a more accurate supply voltage for the LED string. However, the second control stage increases the cost of such resonant power supplies. Summary of the invention

[0004] A brief summary of various exemplary embodiments is as follows. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of various exemplary embodiments, rather than to limit the scope of the present invention. A detailed description of exemplary embodiments suitable for allowing those of ordinary skill in the art to make and use the inventive concept will be carried out in the following sections.

[0005] Various embodiments relate to a power converter comprising: a dual-output resonant converter comprising a first output terminal, a second output terminal, a common-mode control input terminal, and a differential-mode control input terminal, wherein a voltage / current at the first output terminal and a voltage / current at the second output terminal are controlled in response to a common-mode control signal received at the common-mode control input terminal and a differential-mode control signal received at the differential-mode control input terminal; and a dual-output controller comprising a first error signal input terminal, a second error signal input terminal, a delta power signal input terminal, a common-mode control output terminal, and a differential-mode control output terminal, wherein the dual-output controller is configured to control a first error signal received at the first error signal input terminal and a differential-mode control signal received at the second error signal input terminal. The common-mode control signal and the differential-mode control signal are generated based on a second error signal received at an error signal input terminal, wherein the first error signal is a function of the voltage / current at the first output terminal, and the second error signal is a function of the voltage / current at the second output terminal, and wherein the common-mode control signal is output from the common-mode control output terminal, and the differential-mode control signal is output from the differential-mode control output terminal, wherein the common-mode control signal is generated using a feedback loop that uses a desired delta power signal based on the first error signal and the second error signal and a delta power signal that is a function of the difference in output power at the first output terminal and the second output terminal.

[0006] Various embodiments are described in which the dual output controller is configured to generate the common-mode control signal and the differential-mode control signal in response to the first error signal and the second error signal by pre-calculating a control variable matrix and generating the common-mode control signal and the differential-mode control signal as a function of the first and second error signals and the control variable matrix.

[0007] Various embodiments are described wherein the control variable matrix comprises variables k11, k12, k21, and k22, wherein the desired delta power signal and the differential mode control signal are generated as: desired_delta_power=first error signal·k21+second error signal·k22; and

[0008] Vdm=first error signal·k11+second error signal·k12.

[0009] Various embodiments are described wherein the feedback loop further comprises: an adder configured to calculate a difference between the desired delta power signal and a difference between the output powers at the first output terminal and the second output terminal; and a regulator configured to receive an output of the adder to generate the common mode control signal.

[0010] Various embodiments are described, further comprising a clamping circuit configured to clamp the common mode control signal to a range of values.

[0011] Various embodiments are described wherein the clamp circuit further comprises: a power detector configured to generate an indication signal when the output power at the first output terminal approaches zero; and a limit detector configured to receive the common mode signal and the indication signal to generate a limited common mode signal based on the range of values.

[0012] Various embodiments are described wherein the limit detector is further configured to generate an override signal that is received by the feedback loop and stops operation of the feedback loop when the common mode signal is limited.

[0013] Various embodiments are described, wherein the power detector comprises a reference input terminal configured to receive a reference signal and a voltage / current input terminal receiving a voltage / current signal from the first output terminal, wherein the indication signal is generated based on the reference signal and the voltage / current signal from the first output terminal.

[0014] Various embodiments are described wherein the power detector includes an auxiliary voltage input configured to receive an auxiliary voltage signal from an auxiliary coil coupled to a secondary of the dual output resonant converter, wherein the indication signal is generated based on the auxiliary voltage signal.

[0015] Various embodiments are described wherein the power detector is configured to detect that the auxiliary voltage is below a threshold based on a maximum detected auxiliary voltage value.

[0016] Various embodiments are described wherein the power detector comprises an auxiliary voltage input configured to receive an auxiliary voltage signal from an auxiliary coil coupled to a secondary of the dual-output resonant converter and a switching node voltage input receiving a switching node voltage signal from a switching node in the dual-output resonant converter, wherein the indication signal is generated based on the auxiliary voltage signal and the switching node voltage signal, which indicates starting a continuous conduction mode (CCM) of operation of the dual-output resonant converter.

[0017] Various embodiments are described, wherein the power detector further comprises: a zero crossing detector configured to determine a first time when the auxiliary voltage crosses zero; a start ramp detector configured to determine a second time when the switching node voltage starts to have a ramp; and a time difference detector configured to determine a difference between the first time and the second time, wherein the time difference indicates the start of CCM of operation of the dual output resonant converter.

[0018] Various other embodiments relate to a power converter comprising: a dual-output resonant converter comprising a first output terminal, a second output terminal, a duty cycle control input terminal, and a frequency control input terminal, wherein a voltage / current at the first output terminal and a voltage / current at the second output terminal are controlled in response to a duty cycle control signal received at the duty cycle control input terminal and a frequency control signal received at the frequency control input terminal; and a dual-output controller comprising a duty cycle control output terminal and a frequency control output terminal, wherein the dual-output controller is configured to generate the duty cycle control output terminal in response to the voltage / current at the first output terminal and the voltage / current at the second output terminal. A duty cycle control signal and a frequency control signal, wherein the duty cycle control signal is generated using a first feedback loop that uses a desired delta power signal based on the voltage / current at the first output terminal and the voltage / current at the second output terminal and a delta power signal that is a function of the difference between the output powers at the first output terminal and the second output terminal, and wherein the frequency signal is generated using a second feedback loop that uses a desired total power signal based on the voltage / current at the first output terminal and the voltage / current at the second output terminal and a total power signal that is a function of the total power at the first output terminal and the second output terminal.

[0019] Various embodiments are described, wherein: the first feedback loop further comprises: an adder configured to calculate a difference between the desired delta power signal and the difference between the output powers at the first output terminal and the second output terminal; and a regulator configured to receive the output of the adder to generate the duty cycle control signal; and the second feedback loop further comprises: an adder configured to calculate a difference between the desired total power signal and the total output power at the first output terminal and the second output terminal; and a regulator configured to receive the output of the adder to generate the frequency control signal.

[0020] Various embodiments are described, further comprising a clamping circuit configured to clamp the duty cycle control signal to a range of values.

[0021] Various embodiments are described, wherein the clamp circuit further comprises: a power detector configured to generate an indication signal when the output power at the first output terminal approaches zero; and a limit detector configured to receive the duty cycle control signal and the indication signal to generate a limited duty cycle control signal.

[0022] Various embodiments are described that further include a clamping circuit configured to clamp the frequency control signal to a range of values.

[0023] Various embodiments are described wherein the clamp circuit further comprises: a power detector configured to generate an indication signal when the output power at the first output terminal approaches zero; and a limit detector configured to receive the frequency control signal and the indication signal to generate a limited frequency control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Reference is made to the accompanying drawings for a better understanding of various exemplary embodiments, in which:

[0025] Figure 1 An embodiment of a dual output resonant converter is depicted;

[0026] Figure 2 is a block diagram of an example of a power converter including a dual-output resonant converter, a dual-output controller, and first and second comparison units according to an embodiment of the present invention;

[0027] Figure 3 is a graphical representation of simulation results of a power converter including a dual output resonant converter;

[0028] Figure 4 yes Figure 3 A table of some of the data points in the diagram of together with some of the corresponding partial derivative values;

[0029] Figure 5 shows an example of a control function performed by a dual output controller;

[0030] Fig. 6A is a block diagram of an example of a power converter configured for Vcap or Vcr control;

[0031] Figure 6B An embodiment of a dual output resonant converter configured for Vcap control is depicted;

[0032] Figure 6C is a block diagram of an example of a power converter configured for Vcr control;

[0033] Fig. 7A and Figure 7B shows a graph of Vcm and Vdm versus power supplied to a string of LEDs (Pled) for various LED voltage levels;

[0034] Figure 8 An embodiment of a dual output controller for a dual output resonant converter for linearizing Vcm is shown;

[0035] Fig. 9 The relationship between ΔEc_desired and Vcm as a result of the feedback loop is shown;

[0036] Fig.10The linear relationship between ΔEc_desired and Pled is shown;

[0037] Fig.11 A dual output resonant converter 1100 is shown that uses a feedback loop to linearize duty cycle and frequency control parameters;

[0038] Fig.12 A block diagram of a first embodiment of clamping Vcm is shown;

[0039] Fig.13 A block diagram showing a second embodiment of clamping Vcm;

[0040] Fig.14 shows a block diagram of an auxiliary voltage detector;

[0041] Fig.15 A graph showing the current in the primary coil and in the magnetic core when two power output terminals are loaded;

[0042] Fig.16 A graph showing the current on the primary coil and in the magnetic core in a situation where the output terminal has reached zero output power;

[0043] Fig.17 A block diagram showing a third embodiment of clamping Vcm;

[0044] Fig.18 shows a block diagram of a CCM detector;

[0045] Fig.19 shows the simulation results of a dual output resonant converter controlled by Vdm and Vcm signals;

[0046] Fig. 20 Shows Fig.19 A simplified model of the curve graph;

[0047] Fig.21 shows a block diagram of a dual output controller, the block diagram showing causing a Vdm_max value to be output from the controller when the measured current is zero; and

[0048] Fig.22A shows the situation where Vcm can no longer set the power division between the two outputs;

[0049] Fig. 22B An example of a dual output resonant converter controlled by Vdm and Vcm is shown;

[0050] Fig.23 An embodiment of a dual output controller that limits the Vdm value is shown;

[0051] Fig.24A first embodiment of a dual output controller using a Vcm offset is shown;

[0052] Fig.25 A second embodiment of a dual output controller using a Vcm offset is shown;

[0053] Fig.26 An embodiment of a Vcm_offset circuit is shown;

[0054] Fig. 27 An embodiment of a converter that limits an error signal is shown;

[0055] Fig.28 An embodiment of a zero output power processor is shown;

[0056] Fig.29 An embodiment of a zero output power processor based on slowly adapting Vcm offset levels is shown; and

[0057] Fig.30 An embodiment of a converter that limits the error signal using duty cycle and frequency control is shown.

[0058] To facilitate understanding, the same reference numerals are used to designate elements having substantially the same or similar structures and / or substantially the same or similar functions. DETAILED DESCRIPTION

[0059] This specification and the accompanying drawings illustrate the principles of the present invention. It will therefore be appreciated that those skilled in the art will be able to design various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included within the scope thereof. In addition, all examples listed herein are primarily intended to be used particularly for teaching purposes to help readers understand the principles of the present invention and the concepts that the inventors have contributed to promote this area, and should be interpreted as not being limited to such specific examples and conditions listed. In addition, unless otherwise specified (e.g., "otherwise" or "or alternatively"), the term "or" as used herein refers to non-exclusive or (i.e., and / or). Moreover, the various embodiments described herein are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments.

[0060] Dual output resonant converters are known. Examples of dual output resonant converters are disclosed in US Pat. No. 6,822,881 and US Pat. No. 6,829,151. Figure 1 An embodiment of a dual output resonant converter 100 is depicted in FIG. Figure 1In an embodiment of the invention, the circuit is a resonant LLC converter comprising a resonant capacitor Cr and an inductor Ls and a magnetizing inductance Lm as components forming part of a resonant circuit or tank. A transformer and rectifier circuit is used to generate DC output voltages Vout1 and Vout2. The output current can be made continuous by adding a series inductor (not shown). Figure 1 In an embodiment of the invention, the circuit comprises three parts. The first part 1 is a control part, which comprises a control logic 5 for generating a control signal, and the control signal is used to open and close switches 6 and 7 respectively through a high side driver (HSD) 8 and a low side driver (LSD) 9. The second part 2 is a primary circuit, and the third part 3 is a secondary circuit. The second part comprises a resonant capacitor Cr and inductors Ls and Lm. The resonant converter is connected to a voltage source Vsupply (also referred to as Vbus herein) so that electric energy can be supplied to a load that can be connected to the output terminal of the secondary side, for example. In an embodiment, switches 6 and 7 are controllable switches arranged in series connected to a voltage source Vsupply, the first switch is a high side switch (HSS), one pin of the high side switch is connected to the voltage source Vsupply, and the second switch is a low side switch (LSS), one pin of the low side switch is connected to the ground. Moreover, an embodiment with a full bridge configuration can be envisioned. As known in the art, the third part can comprise a diode and a capacitor.

[0061] The dual output resonant converter 100 is usually frequency controlled. The output power of the converter can be controlled by changing the signal frequency. It is also possible to use a duty cycle different from 50%. In this case, the duty cycle also affects how the output power is divided between the two output terminals. A disadvantage of frequency and duty cycle based control can be that for certain operating points, it becomes difficult to adjust the system to the desired operating point because of changes in gain factors and even changes in polarity due to the nonlinear control behavior of the frequency or duty cycle controlled resonant converter.

[0062] Various techniques for operating resonant converters are known. One technique disclosed in U.S. Patent No. 7,944,716, which is incorporated herein by reference for all purposes as if fully set forth herein, involves combining control of duty cycle and frequency in a manner that can achieve smooth regulation of output power. For example, the resonant converter is not directly controlled by frequency and duty cycle, but rather by current and voltage on the primary side of a transformer. In an embodiment, the current and voltage in the resonant tank, such as Iprim and Vcap, are compared to two control values ​​at each conduction interval so that the resonant converter is controlled in a cycle-by-cycle manner. In an embodiment, the current Iprim is the current flowing in the resonant tank in response to the opening and closing of the switch. The measurement of the current can be provided in a variety of different ways, such as based on the voltage across a sense resistor, the current in the switch, etc. The current Iprim is also referred to as the primary current. Vcap is also referred to as the capacitor voltage, which is a predetermined point, such as at Figure 1 The voltage at the node indicated as "Vcap" in Figure 1 In the example of FIG. 1 , the voltage at node Vcap is defined as Vhb−Vcr, where Vhb is the voltage at half-bridge node 11 and Vcr is the voltage across the resonant capacitor. In example operation, for each half cycle, the conductive primary switch is closed when the voltage Vcap crosses a predetermined value (e.g., VcapH for high-side switch closure and VcapL for low-side switch closure) for each half cycle. By controlling the primary switch in this manner, an almost linear relationship between the control parameter and the output power can be obtained.

[0063] In addition, a differential mode term Vdm and a common mode term Vcm can be defined for use in controlling the resonant converter. For example, the differential mode term can be expressed as Vdm = Vbus / 2 - (VcapH - VcapL) / 2, and the common mode term can be expressed as Vcm = (VcapH + VcapL) / 2. Using the differential mode term and the common mode term, the total power delivered to the output can be controlled using the differential mode term Vdm, while the difference in output power delivered to the output during each half cycle is determined by the common mode term Vcm.

[0064] A control scheme utilizing differential and common-mode terms can be implemented using the voltage Vcr across the resonant capacitor or the voltage at the node Vcap. Techniques involving Vcap and Vcr can produce similar control functions. However, the difference between using Vcap control and Vcr control is that the average value of Vcap is defined as zero, while for Vcr, there is a DC component Vbus / 2, which enables the use of a capacitive voltage divider to divide Vcap down to a low voltage signal compatible with a low voltage controller integrated circuit (IC). Although at 50% duty cycle, for Vcr control, the DC component is Vbus / 2, but for duty cycles other than 50%, the DC component is Vbus / 2×duty cycle, where the duty cycle is the high-side switch on-time divided by the cycle time.

[0065] Additional techniques for operating a resonant converter using a differential mode term Vdm and a common mode term Vcm to control a resonant converter are disclosed in U.S. Patent No. 9,065,350 and European Patent Application No. 11250662.1 (published as EP 2 547 176 A1 on January 16, 2013), which are incorporated herein by reference for all purposes as if fully set forth herein.

[0066] In addition to the 50% duty cycle mode or "high power mode", it is also known to be able to control the resonant converter using a "low power mode". Various examples of low power modes for controlling resonant converters are disclosed in, for example, U.S. Patent No. 8,339,817, international patent applications published under the Patent Cooperation Treaty (PCT) as publication numbers WO 2005 / 112238 and WO 2009 / 004582, and European Patent Application No. 15159086.6 (published as EP 3 068 027 A1 on March 13, 2015). In this low power mode, part of the switching sequence is similar to the high power mode, while during another part of the cycle, the resonant tank is in a mode where no energy is converted and relatively few losses are also generated.

[0067] As described above, the resonant power supply is used in LED TV applications to provide a low voltage output of about 12V DC for supplying low voltage circuits and a high voltage output of about 165V for supplying LED strings for backlighting of the display. Some known power supplies developed for these applications require a second control stage after the 165V output to provide a more accurate power supply voltage for the LED string. However, the second control stage increases the cost of such a resonant power supply. According to the embodiments described herein, a power converter having a dual output resonant converter that does not require a second stage controller for the 165V output is disclosed. The power converter is controlled using a "capacitor voltage" control technique so that the two output ends of the dual output resonant converter can be controlled independently of each other. In an embodiment, a differential mode control signal Vdm and a common mode control signal Vcm are used to independently control the two output ends of the dual output resonant converter. Specifically, the differential mode control signal Vdm and the common mode control signal Vcm are adjusted in response to an error signal generated according to the output voltage and / or current of each of the two output ends. For example, a first (e.g., linear) combination of the first and second error signals is used to generate a differential mode control signal, and a second (e.g., linear) combination of the first and second error signals is used to generate a common mode control signal. It should be noted that while the use of a dual output resonant converter in an LED TV application is described, the embodiments described herein may be used in any application using a dual output resonant converter.

[0068] First refer to Figure 2 Techniques for controlling a dual output resonant converter are described. Figure 2 2 is a block diagram of an example of a power converter 200 including a dual-output resonant converter 210, a dual-output controller 220, and first and second comparison units 230 and 232 according to an embodiment. The dual-output resonant converter 210, the first and second comparison units 230 and 232, and the dual-output controller 220 form a feedback loop for independently controlling the voltage and / or current at the two outputs of the dual-output resonant converter. For example, in an LED TV application, the output terminals can be independently controlled to provide a 12V output and a 165V output (e.g., within ±10% or ±5% of the target output) that can be used to drive different components of the LED TV. The dual-output resonant converter includes a common-mode control input terminal 212, a differential-mode control input terminal 214, a first output terminal 216, and a second output terminal 218. The common-mode control input terminal 212 receives a common-mode control signal Vcm, and the differential-mode control input terminal 214 receives a differential-mode control signal Vdm, while the first output terminal 216 provides an output voltage Vout1, and the second output terminal 218 provides an output voltage Vout2. It should be noted that the output can also be viewed in terms of output currents Iout1 and Iout2, respectively.

[0069] The comparison units 230 and 232 are configured to compare the input voltage with the reference voltage to generate an error signal that can be processed by the dual output controller 220. In an embodiment, the error signal reflects the difference between the output voltage and the reference voltage. For example, the use of the comparison unit allows 12V and 165V outputs to be converted into low voltage signals that can be managed by an IC-based dual output controller, which is typically operated at a voltage in the range of about 0.5 volts to 3 volts. The first comparison unit 230 is configured to compare the output Vout1 from the first output terminal 216 with the first reference signal Vref1 to generate a first error signal error1, and the second comparison unit 232 is configured to compare the output Vout2 from the second output terminal 218 with the second reference signal Vref2 to generate a second error signal error2. Although the comparison unit and the corresponding signal are described in terms of voltage, the comparison units 230 and 232 can be configured as current comparison units with corresponding current-based signals, such as Iout1, Iout2, Iref1 and Iref2.

[0070] The dual output controller 220 includes a first error signal input terminal 222, a second error signal input terminal 224, a common mode control output terminal 226, and a differential mode control output terminal 228. The first error signal input terminal 222 receives the first error signal error1, and the second error signal input terminal 224 receives the second error signal error2. The common mode control output terminal 226 outputs a common mode control signal Vcm, and the differential mode control output terminal 228 outputs a differential mode control signal Vdm.

[0071] A power converter with a dual output resonant converter can be controlled based on the voltage at the node Vcap (also referred to herein as "Vcap control") or based on the voltage across the resonant capacitor (also referred to herein as "Vcr control"). In an embodiment, the voltage Vcr across the resonant capacitor may also include a voltage drop Rsense across the sense resistor, but since the sense resistor is typically only in the range of 100mV and Vcr is in the range of greater than 100V, the voltage drop caused by the sense resistor is insignificant. Depending on the layout of the resonant capacitor, such as in series with the switching node or in series with the ground node, different signal shapes appear, so the common-mode control signal Vcm and the differential-mode control signal Vdm are defined slightly differently between the two configurations, but the basic principles applied to the power converter control are the same. For example, for Vcap control:

[0072] VcapH=Vbus / 2+Vcm–Vdm;

[0073] VcapL=–Vbus / 2+Vcm+Vdm;

[0074] Or written another way:

[0075] Vdm=Vbus / 2–(VcapH–VcapL) / 2 controls Pout1+Pout2, with only a small residual effect on Pout1–Pout2;

[0076] Vcm=(VcapH+VcapL) / 2 controls Pout1–Pout2, with only a small residual effect on Pout1+Pout2;

[0077] Where Pout1 is the power delivered at the first output 216 of the dual output resonant converter 210 , and Pout2 is the power delivered at the second output 218 of the dual output resonant converter.

[0078] For Vcr control compared to Vcap control, a one-to-one relationship exists between the values, e.g., for each value in VcapH and VcapL, one value in VcrH and VcrL exists. For example, for Vcr control:

[0079] Vhb=Vcap+Vcr Therefore;

[0080] The VcapH level depends on when the high-side switch is closed, then Vhb = Vbus, so Vcr = Vhb – Vcap, resulting in:

[0081] VcrH=Vbus–VcapH;

[0082] The VcapL level is related to when the low-side switch is closed, then Vhb = 0, so Vcr = Vhb – Vcap yields:

[0083] VcrL=–VcapL;

[0084] Vcm=(VcapH+VcapL) / 2=((Vbus–VcrH)+(-VcrL)) / 2=Vbus / 2–(VcrH+VcrL) / 2.

[0085] Using Vcap control, the common mode control signal Vcm does not depend on Vbus, while using Vcr control, the common mode control signal depends on Vbus, such as Vbus / 2. Therefore, in an embodiment using Vcap control, the differential mode control signal is defined as Vdm=Vbus / 2-(VcapH-VcapL) / 2, and the common mode term is defined as Vcm=(VcapH+VcapL) / 2, and in an embodiment using Vcr control, the differential mode control signal is defined as Vdm=(VcrH-VcrL) / 2, and the common mode term is defined as Vcm=Vbus / 2-(VcrH+VcrL) / 2. As described below, in an embodiment, the dual output controller has the same functions for Vcap control and Vcr control.

[0086] Considerations for choosing whether to use Vcap control or Vcr control are related to the specific implementation. For example, using Vcap control, the average voltage of Vcap is zero, Vcap=0 (because the voltage is sensed across the inductor). Therefore, it is easy to use a capacitive voltage divider to convert the amplitude of Vcap (e.g., several 100V) to an IC level of, for example, a few volts. A capacitive voltage divider cannot pass DC information, but because the DC information is defined as zero, there is no need to pass DC information. In an embodiment, the DC term can be set to zero, for example, by connecting a large resistor between the capacitive voltage divider and the ground reference to which VcapH and VcapL refer. Vcr control can be selected so that one side of the resonant capacitor can be connected to ground, which enables the resonant capacitor to be divided into two capacitors, which can produce less ripple current in the supply voltage Vsupply, also known as Vbus.

[0087] As described above, the differential mode control signal Vdm and the common mode control signal Vcm are used to independently control the two output terminals of the dual output resonant converter. Specifically, the differential mode control signal and the common mode control signal are adjusted in response to the error signals error1 and error2 generated according to the output voltage and / or current Vout1 / Iout1 and Vout2 / Iout2 of each of the two output terminals. An example of a technique for deriving a functional relationship between Vcm, Vdm, error1 and error2 is described below.

[0088] exist Figure 2In the power converter 200 depicted in FIG, the error signal generated for one of the output terminals should drive Vcm and Vdm to adopt a combination of appropriate proportions so that only the power to the desired output terminal changes and the power to the other output terminals remains constant. For example, the error signal error1 corresponding to the first output terminal should drive the change of the output Vout1 at the first output terminal of the dual-output resonant converter, with little effect (e.g., ±1% change) on the output Vout2 at the second output terminal of the dual-output resonant converter, while the error signal error2 corresponding to the second output terminal should drive the change of the output Vout2 at the second output terminal of the dual-output resonant converter, with little effect on the first output Vout1 of the dual-output resonant converter. This control scheme is referred to herein as "orthogonal" control. In order to achieve orthogonal control, in an embodiment, the first step is to describe how the output current at each output terminal (e.g., Iout1 and Iout2) changes with changes in Vcm and Vdm. The change in the output current at each output terminal according to the change in Vcm and Vdm can be described as the total differential based on the partial derivatives of each output, as follows:

[0089] dIout1=δiout1_dVcm·dVcm+δiout1_dVdm·dVdm

[0090] dIout2=δiout2_dVcm·dVcm+δiout2_dVdm·dVdm

[0091] These partial derivatives can then be determined for a specific configuration of a dual output resonant converter operating at a known set of operating points. Figure 3 As mentioned above Figure 1 and Figure 2 Figure 1 is a graphical representation of simulation results for a power converter including a dual output resonant converter as described in FIG. Figure 3 In the example of FIG. 1 , the output currents Iout1 and −Iout2 at the two output terminals are plotted for different values ​​of the common-mode control signal Vcm and different values ​​of the differential-mode control signal Vdm. Figure 3 In the example, Vcm and Vdm correspond to signals derived from the Vcap or Vcr nodes by a voltage divider to obtain voltages on a scale suitable for IC inputs. For example, the output currents Iout1 and -Iout2 are plotted over a range from 0V to 0.6V for the common-mode control signal Vcm and from 0V to 1.4V for the differential-mode control signal Vdm. Figure 4 yes Figure 3 A table of some of the data points in the graph along with some of the corresponding partial derivative values.

[0092] In an embodiment, it is desirable to determine the required change in the differential mode control signal Vdm and the change in the common mode control signal Vcm so as to obtain a certain output current change at only one output terminal (e.g., Iout1 or Iout2), while leaving the output current at the other output terminal unchanged, for example, unchanged within a range of about ±1% of the full power of the output terminal. In an embodiment, the differential mode control signal Vdm and the common mode control signal Vcm can be solved from the following set of equations:

[0093] dIout1=δiout1_dVcm·dVcm+δiout1_dVdm·dVdm

[0094] dIout2=δiout2_dVcm·dVcm+δiout2_dVdm·dVdm

[0095] Given a matrix operation:

[0096]

[0097] use Figure 3 and Figure 4 For the data in the example, at the operating points Vcm=0 and Vdm=0.4, the derivative is determined as:

[0098] δiout1_dVcm=45.28 δiout1_dVdm=25.7

[0099] δiout2_dVcm=-47.5 δiout2_dVdm=24.14

[0100] The above values ​​can then be applied to the following equation:

[0101]

[0102] as well as

[0103]

[0104] In an example, the required change in the value of the differential mode control signal Vdm and the common mode control signal Vcm to achieve a 1 amp output current change in each output can be determined from the above equation as a function of (dIout1, dIout2). For example, the required change in the value of Vdm and Vcm is calculated as:

[0105] dVcm(1,0)=-11.107ml dVcm(0,1)=10.433ml dVcm(1,1)=-0.674ml

[0106] dVdm(1,0)=19.569ml dVdm(0,1)=20.529ml dVdm(1,1)=40.098ml

[0107] Figure 5 An example control function of an embodiment of the dual output controller 220 is shown in FIG. Figure 5 As shown in , a common mode control signal Vcm and a differential mode control signal Vdm are generated as a function of the input error signals error1 (monitored as dIout1) and error2 (monitored as dIout2). The values ​​of the control parameters can be solved for and are generally referred to as control parameters k11, k12, k21 and k22. The control parameters can be represented by the following control parameter matrix:

[0108]

[0109] Reference Figure 5 , the determinant is used to solve a system of linear equations in a structural way, for example as the quotient of two determinants. The determinant can be expressed as:

[0110]

[0111] And the system of equations can be solved as:

[0112]

[0113]

[0114] Given the simulation values ​​determined above:

[0115] δiout1_dVcm=45.28 δiout1_dVdm=25.7

[0116] δiout2_dVcm=-47.5 δiout2_dVdm=24.14

[0117] The control parameters k11, k12, k21 and k22 for a specific configuration of a dual output resonant converter are pre-calculated as:

[0118]

[0119] k11=0.011

[0120]

[0121] k12=–0.011

[0122]

[0123] k21=0.019

[0124]

[0125] k22=0.019

[0126] As shown above, a set of control parameters can be pre-calculated for a specific configuration of a dual output resonant converter operating and / or simulating at a known set of operating points. In an embodiment, control parameters k11 and k12 are used by a dual output controller to set a common mode control signal Vcm, and control parameters k21 and k22 are used by a dual output controller to set a differential mode control signal Vdm. In an embodiment, for symmetry reasons, when adjusting a feedback loop starting from a symmetrical operating point where both outputs are equally loaded, k11 and k12 should be opposite, while k21 and k22 should be equal. Although certain values ​​of control parameters k11, k12, k21 and k22 are found for an example power converter and a set of example operating points, it should be understood that the specific values ​​of the control parameters are implementation specific. In the case of predetermined control parameter values, values ​​of common mode control signals Vcm and differential mode control signals Vdm can be generated using relatively simple calculations based on error signals error1 and error2. Therefore, the two outputs of a dual output resonant converter can be independently controlled in a feedback control loop utilizing two inputs and very little additional control circuitry.

[0127] Fig. 6A is a block diagram of an example of a power converter 300 configured for Vcap control. According to an embodiment of the present invention, the power converter may be connected to Figure 2 The power converter 200 is similar or identical to the power converter 200 of FIG. 1 and includes a dual output resonant converter 310, a dual output controller 320, and first and second comparison units 330 and 332. Figure 2 As described, the dual output resonant converter 310, the first and second comparison units 330 and 332, and the dual output controller 320 form a feedback loop. The dual output resonant converter 310 includes a common mode control input terminal 312, a differential mode control input terminal 314, a first output terminal 316, and a second output terminal 318. The common mode control input terminal 312 receives a common mode control signal Vcm, and the differential mode control input terminal 314 receives a differential mode control signal Vdm, while the first output terminal 316 provides an output voltage Vout1, and the second output terminal 318 provides an output voltage Vout2. It should be noted that the output can also be observed in terms of output currents Iout1 and Iout2, respectively.

[0128] The comparison units 330 and 332 are configured to compare an input voltage with a reference voltage to generate an error signal. The first comparison unit 330 is configured to compare the output Vout1 from the first output terminal with the first reference signal Vref1 to generate a first error signal error1, and the second comparison unit 332 is configured to compare the output Vout2 from the second output terminal with the second reference signal Vref2 to generate a second error signal error2. Although the comparison units 330 and 332 and the corresponding signals are described in terms of voltage, the comparison units 330 and 332 can be configured as current comparison units with corresponding current-based signals or as power-based comparison units for power-based regulation of the power converter.

[0129] The dual output controller 320 includes a first error signal input terminal 322, a second error signal input terminal 324, a common mode control output terminal 326, and a differential mode control output terminal 328. The first error signal input terminal 322 receives the first error signal error1, and the second error signal input terminal 324 receives the second error signal error2. The common mode control output terminal 326 outputs a common mode control signal Vcm, and the differential mode control output terminal 328 outputs a differential mode control signal Vdm. Fig. 6A As shown in , the dual output controller 320 generates a common mode control signal Vcm and a differential mode control signal Vdm in response to the error signals error1 and error2. To generate the common mode control signal Vcm and the differential mode control signal Vdm, the dual output controller 320 is configured with the following control parameter matrix:

[0130]

[0131] And the control function can be expressed as:

[0132]

[0133] The control parameter matrix includes parameters k11, k12, k21 and k22. The common mode control signal Vcm and the differential mode control signal Vdm can be generated as:

[0134] Vcm=error1·k21+error2·k22;

[0135] Vdm=error1·k11+error2·k12.

[0136] Therefore, the control parameters k11–k22 define how the differential mode control signal Vdm and the common mode control signal Vcm change in response to changes in the error signals error1 and error2. In an embodiment, the generation of the error signals error1 and error2 includes an amplifier with frequency-dependent behavior. Ultimately, the function is a specific linear combination of Vcm and Vdm to achieve orthogonal control. As described above, the relationship between the control parameters k11 and k21 determines how Vcm and Vdm change in response to changes in the error signal error1, so that a response is only seen at the first output terminal, such as Vout1 / Iout1, and the relationship between the control parameters k12 and k22 determines how Vcm and Vdm change in response to changes in the error signal error2, so that a response is only seen at the second output terminal, such as Vout2 / Iout2.

[0137] Figure 6B An embodiment of a dual output resonant converter 410 configured for Vcap control is depicted. The dual output resonant converter 410 is similar to the embodiment of the reference Figure 1 The dual output resonant converter described in Figure 6B The dual output resonant converter shown in FIG. 4 includes a controller 440 configured to generate a switch control signal in response to a common mode control signal Vcm, a differential mode control signal Vdm and a voltage at a node 442. Figure 6B As shown in , node 442 is identified as a "Vcap" node, e.g., a node at which Vcap is measured. Figure 6B In the circuit of FIG. 1 , the voltage at Vcap can be expressed as: Vcap=Vhb-Vcr, where Vhb is the voltage at the half-bridge node 11, and Vcr is the voltage across the resonant capacitor Cr. In operation, the output Vout1 at the first output terminal 416 and the output Vout2 at the second output terminal 418 are connected by the above reference. Figure 2 and Fig. 6A The comparison unit described is fed back to the dual output controller. The common mode control signal Vcm and the differential mode control signal Vdm are generated by the dual output controller in response to the error signals error1 and error2. The common mode control signal Vcm and the differential mode control signal Vdm are provided to the controller of the dual output resonant converter 410 and used to generate a switch control signal, which is used by the control logic 5 to control the switching of the high side and low side switches 6 and 7, so that the output voltages Vout1 and Vout2 at the first and second output terminals are controlled independently of each other.

[0138] Fig. 6AThe power converter 300 shown in FIG. 3 can also be configured as Vcr control. When operating according to Vcr control, the dual output controller 320 generates a common mode control signal Vcr_cm and a differential mode control signal Vcr_dm in response to the error signals error1 and error2. In order to generate the common mode control signal Vcr_cm and the differential mode control signal Vcr_dm, the dual output controller is configured with the following control parameter matrix:

[0139]

[0140] And the control function can be expressed as:

[0141]

[0142] The control parameter matrix above contains parameters k11, k12, k21 and k22. The common mode term Vcr_cm and the differential mode term Vcr_dm are generated as:

[0143] Vcr_cm=error1·k21+error2·k22; and

[0144] Vcr_dm=error1·k11+error2·k12.

[0145] Figure 6C An embodiment of a dual output resonant converter 510 configured for Vcr control is depicted. The dual output resonant converter 510 is similar to the embodiment of the reference Figure 1 The dual output resonant converter described in Figure 6C The dual output resonant converter shown in FIG. 5 includes a controller 540 configured to generate a switch control signal in response to a common mode control signal Vcr_cm, a differential mode control signal Vcr_dm and a voltage Vcr across the resonant capacitor. Figure 6C As shown in , the voltage is measured across the resonant capacitor Cr and is identified as Vcr. In operation, the output Vout1 at the first output terminal 516 and the output Vout2 at the second output terminal 518 are connected by the above reference Figure 2 and Fig. 6A The comparison unit described is fed back to the dual output controller. The dual output controller generates a common mode control signal Vcr_cm and a differential mode control signal Vcr_dm in response to the error signals error1 and error2. The common mode control signal Vcr_cm and the differential mode control signal Vcr_dm are provided to the controller of the dual output resonant converter and used to generate a switch control signal, which is used by the control logic 5 to control the switching of the high side and low side switches 6 and 7, so that the output voltages Vout1 and Vout2 at the first and second output terminals are controlled independently of each other.

[0146] The dual output controller essentially performs the opposite action of the dual output resonant converter, so that changes in the error1 signal only give changes in the power delivered to Vout1, and changes in the error2 signal only give changes in the power delivered to Vout2.

[0147] As mentioned above, this control method is called orthogonal control, which means that the power in the two output terminals can be changed independently of each other. Compared with the frequency-controlled resonant converters of US6822881 and US6829151B2, the control performed by the state variable gives an almost linear relationship between the Vdm control input and the output power. This makes it easy to obtain the desired orthogonal control, but the relationship between Vcm and power is nonlinear. Especially when the power in one output terminal is relatively low, the transfer from Vcm to power becomes lower and even becomes zero when the power in one output tends to zero. This makes it more difficult to obtain the desired orthogonal control and can even make it impossible to keep the two outputs well regulated when one output is low power.

[0148] A method will now be described that allows two outputs to be regulated at low power levels by making the transfer from control input to power more linear for the two control inputs. This embodiment may include the following features: a switch mode power converter having at least two outputs, the at least two outputs including a regulated system voltage output and a second regulated output, wherein the second output may be used for a higher voltage load with a regulated current; the switch mode power converter may be controlled by state variables Vcm, Vdm, wherein the Vcm variable is included in a local feedback loop to improve the linearity of the transfer from control input to power; and a method of how to limit the control variable when the local feedback loop cannot remain closed due to a zero gain situation.

[0149] Fig. 7A and Figure 7B A graph of Vcm and Vdm versus power supplied to a string of LEDs (Pled) for various LED voltage levels is shown. It should be noted that LED applications are only examples used herein and other applications are possible. More specifically, Fig. 7A and Figure 7B The measured results of an actual dual output resonant converter with a first output having a fixed load of 13V and a second output driving a variable current LED string are shown. Curves are shown for three different LED strings with forward voltages of 80V, 90V and 100V for a given nominal LED current of 200mA, and Vsupply = Vbus = 380V. Figure 7B As shown in , Vdm varies almost linearly with Pled. Fig. 7AAs shown in , Vcm has a non-linear relationship with Pled, and therefore how the power is divided between the two output terminals has a non-linear relationship with Pled.

[0150] This nonlinear relationship causes the values ​​of k12 and k22 of the controller matrix to depend on the operating point of the converter. Because the values ​​of k11, k12, k21 and k22 are based on the derivatives of the Vcm and Vdm curves, if the curves are linear, these values ​​remain constant over the entire operating range. If the curves are nonlinear, k11, k12, k21 and k22 will change according to the specific operating point. This makes it difficult or even practically impossible to maintain the orthogonal control required to prevent load jumps in the output of the dual output resonant converter. For example, load jumps in the output voltage of the dual output resonant converter of an LED TV cause visible light changes in the LCD backlight or interference caused by PWM regulation of the LED string in the 12V power supply.

[0151] Figure 8 An embodiment of a dual output controller for a dual output resonant converter for linearizing Vcm is shown. The dual output controller 800 is Figure 2 The dual output controller 800 includes a dual output controller 220. Figure 2 The error processor 805 operates like the dual output controller 220 of the dual output resonant converter. The error processor 805 receives an error signal that tracks the output of the dual output resonant converter described above. The error processor 805 calculates the Vdm value described above. The error processor 805 also calculates ΔEc_desired as ΔEc_desired=error1·k21+error2·k22. ΔEc_desired is related to the desired difference between the two output powers at the dual output terminals of the dual output resonant converter. This power difference can be based on the output voltage, the output current, or the energy difference converted during each half cycle; therefore, ΔEc_desired can be based on any of these metrics.

[0152] The dual output controller 800 also includes a feedback loop 810 that adjusts Vcm so that the variable related to the output power difference is based on ΔEc_desired. The local feedback loop includes an adder 815 that obtains the difference between ΔEc_desired and the measured difference between the two output powers of the dual output terminals. This difference is then fed to a regulator 820 that generates a value of Vcm that is then used by the dual output resonant converter described above. The regulator 820 is shown as a proportional integral (PI) regulator, but other types of regulators may also be used, such as, for example, a proportional integrator, a differential regulator, etc.

[0153] This feedback loop results in ΔEc_desired having a linear relationship with Pled as soon as the loop is closed. This results in a new dual output controller 800 with inputs Vdm and ΔEc_desired, resulting in orthogonal control of the overall system for each operating point without the need to change k11, k21, k12, k22 based on the specific operating point.

[0154] It will now be shown that this feedback loop results in the desired linear relationship between ΔEc_desired and Pled. First assuming that ΔEc_desired is expressed as the power difference between the two outputs, then assuming that the 13V output is loaded with 13V, 2A = 26 watts, then ΔEc_desired = 0, meaning that the power in the LED output is also equal to 26 watts. Also using the curve for the 90V led voltage, then Pled = 0 corresponds to Vcm = 215V, which is also the point above which power can no longer be defined due to all the power flowing into the 13V output. This results in a new curve defining the relationship between ΔEc_desired and Vcm as a result of the feedback loop 810. Fig. 9 The relationship between ΔEc_desired and Vcm as a result of the feedback loop is shown. Fig. 9 indicates the vertical asymptotic behavior for Vcm=f(ΔEc_desired) as the led power approaches zero. This then leads to Fig.10 , which shows a linear relationship between ΔEc_desired and Pled. This linear relationship means that Vcm will have the same original nonlinear relationship with Pled, because the path from Vcm to the resonant controller is not changed by adding local feedback, however the feedback loop 810 drives the error signal as the input of the regulator 820, so the regulator adjusts Vcm so that the desired behavior of the lower curve occurs until ΔEc_desired and ΔEc=poutLED-Pout13V are equal and the error signal tends to zero.

[0155] In a dual output resonant converter using duty cycle and frequency control, the output power has a nonlinear relationship with the duty cycle and frequency control parameters. Therefore, Figure 8 The feedback loop 810 can also be applied to duty cycle and frequency control parameters. Fig.11A dual output resonant converter 1100 is shown that uses a feedback loop to linearize duty cycle and frequency control parameters. The dual resonant converter 1100 includes a core 1105 for frequency and duty cycle control, PI regulators 1110 and 1115, and adders 1120 and 1125. The first feedback loop includes adder 1120 and PI regulator 1110 and receives an input with a desired total power and a measure of the total power generated. The first feedback loop drives the frequency control parameter to a value that causes the desired total power. Similarly, the second feedback loop includes adder 1125 and PI regulator 1120 and receives an input with a desired power difference and a measure of the power difference generated. The second feedback loop drives the duty cycle control parameter to a value that causes the desired power difference. Therefore, now the two new control inputs Power_desired and ΔEc_desired have a linear relationship with the output power, while the nonlinear relationship between the original control parameters-frequency, duty cycle is still nonlinear with power.

[0156] Fig. 9 and Fig.10 The curve of further shows that at the edge where one of the output powers approaches zero, the feedback loop 810 can no longer remain closed, because even for an infinite change in Vcm, zero change in ΔEc still occurs, i.e., vertical asymptotic behavior. Fig. 7A It can be seen that for Vcm values ​​above a certain level, the gain from Vcm to Pout1-Pout2 becomes zero. In that case, all power flows to one output terminal. This also means that the feedback loop 810 cannot remain closed, because changes in Vcm will no longer have any effect on the output current. The result will be that Pout1 or Pout2 (depending on which of the two is zero) is controlled only by the Vdm signal; however, without additional measurement, Vcm will continue to regulate while entering the dead zone.

[0157] Since one output can be controlled by one control signal, this case can be used in practice when the open feedback loop can be kept in a well-defined state as close as possible to the point where the effect of Vcm on the output power is lost. In this way, when zero power in one output case is left, it can be recovered quickly without too many transient effects on the closed loop case.

[0158] An embodiment will now be described in which the Vcm signal is clamped to a maximum or minimum value when it is detected that the output power at one power output has become zero. In this case of using a clamped Vcm, the output of the load can be kept regulated.

[0159] The clamping may be done, for example, at a predetermined level just outside the normal operating region. It is also possible to clamp based on information about the output current. An embodiment of clamping Vcm may use information such as: 1) actually sensing the output current and limiting Vcm when the output current approaches zero; 2) sensing the voltage at the auxiliary winding and detecting whether the voltage is greater than the reflected output voltage during a certain time interval during a half cycle; and 3) checking whether continuous conduction mode (CCM) operation occurs. This may be done with a power detector that detects when the power at one of the dual outputs approaches zero and then a limit detector that limits the Vcm value when the power detector indicates that the power at one of the dual outputs approaches zero.

[0160] Fig.12 A block diagram of a first embodiment of clamping Vcm is shown. In this embodiment, the output current is sensed and compared to a threshold value to generate an error signal that overrides the standard feedback loop, for example by replacing the normal Vcm signal with the maximum of the standard Vcm signal and the error signal to generate a signal Vcm_lim used by the dual output resonant converter. Fig.12 The block diagram contains Figure 8 The same as shown in Figure 8 12 and includes a feedback loop 1210 of a PI regulator 1215 and an adder 1220. A dual output resonant converter 1205 is also shown. A limit detector 1225 and a power detector 1230 are also included. The power detector 1230 is a circuit that receives a measurement of the output power of one of the output terminals of the dual output resonant converter 1205. This measurement can be a current, a voltage, or a power, depending on the specific implementation. The power detector 1230 is a circuit that also receives a reference value corresponding to a near zero power output of one output terminal. The power detector 1230 generates a value indicating that the output power is near zero. The limit detector 1225 outputs a Vcm_lim signal. This Vcm_lim signal corresponds to Vcm during normal operation, but when the output of the power detector 1230 indicates that the output power is within the zero power threshold, the limit detector 1225 outputs a Vcm_lim value that is a fixed maximum value of Vcm to thereby clamp the Vcm_lim value. The limit detector 1225 also outputs an override signal sent to the PI regulator 1215 to stop the operation of the PI regulator 1215 until the output power increases above the threshold again. In this case, further integration of Vcm and thus entering the dead band is prevented. Preventing such a dead band is preferred in order to prevent a long dead time when the output power increases above the threshold again.

[0161] Fig.12The basic block diagram for only one power output is shown. For the other power outputs, a similar circuit would be used, but the limit detector would instead detect the minimum Vcm value, since the Vcm term has an opposite effect on the power in each power output.

[0162] Fig.13 A block diagram of a second embodiment of clamping Vcm is shown. In this embodiment, the voltage at an auxiliary winding coupled to the secondary winding is monitored to generate an error signal for limiting the Vcm signal. Fig.13 The block diagram contains Figure 8 The same as shown in Figure 8 13 and includes a PI regulator 1315 and an adder 1320. A dual output resonant converter 1305 is also shown. A limit detector 1325 and an auxiliary voltage detector 1330 are also included.

[0163] The auxiliary coil is wound around the common core and coupled to the secondary winding. Thus, a voltage and current are induced on the auxiliary coil during operation of the dual output resonant converter 1305. This auxiliary voltage can be monitored to determine when the power at one output of the dual output resonant converter 1305 approaches zero.

[0164] It can be shown that the voltage across the auxiliary winding reaches a fixed value during the interval in which the output current flows. This is the reflected output voltage visible at the auxiliary winding. Outside this interval, the auxiliary voltage is lower, because the secondary diode is then not conducting. The auxiliary voltage is then equal to the voltage across the primary side of the transformer. Therefore, based on this observation, an interval in which no secondary current flows is associated with an auxiliary voltage during this interval that is lower than the auxiliary voltage during the interval in which the output current flows. This difference can be used to determine when no current flows to one of the output terminals.

[0165] although Fig.12 and Fig.13 Embodiments using a feedback loop are shown, but such a feedback loop is not necessary and the limit detector can be applied to systems that do not use such a feedback loop.

[0166] The auxiliary voltage detector 1330 is a circuit that receives the auxiliary voltage value from the auxiliary coil and acts as a power detector. Fig.1414 shows a block diagram of an auxiliary voltage detector. The auxiliary voltage detector comprises a low pass (LP) filter 1405, a sample and hold (S&H) circuit 1410, a peak detector 1415, an adder 1420, and an error amplifier 1425. The LP filter 1405 receives the auxiliary coil voltage Vaux and filters out any high frequency components from the auxiliary voltage signal. The output of the LP filter 1405 is fed to the peak detector 1415, the sample and hold circuit 1410, and the error amplifier 1425. The peak detector 1415 monitors the value of the filtered auxiliary coil voltage Vaux to detect when a peak value is reached, and when this value is reached, the peak detector 1415 sends a sampling signal to the sample and hold circuit 1410, which samples the filtered auxiliary coil voltage Vaux. This is done during the first cycle in which power is delivered. The sampled auxiliary coil voltage Vaux_sampled is then input to the adder 1420. The adder 1420 subtracts the Δ value from the Vaux_sampled value, and the result is fed into the error amplifier 1425. The output of the adder 1420 is a value used to determine when the filtered auxiliary coil voltage Vaux drops below a certain value related to the maximum Vaux value, which indicates that the monitored output power is approaching zero. In the next cycle when the output power can be close to zero. The error amplifier 1425 uses the output of the adder and the filtered auxiliary coil voltage Vaux to generate an error signal. Due to the sampled Vaux at the peak minus a small Δ, the error amplifier input from 1420 defines this clipping level relative to the other amplifier inputs that define the interval during the next switching cycle when the filtered Vaux is above the clipping level for a short interval around the top of Vaux. Therefore, the duration of this interval defines how close the output current is to zero and sets the output of the error amplifier. Therefore, the error output is a duty cycle based on the fact that Vaux above or below the sampled value minus Δ can be used to limit the Vcm signal. Therefore, the error signal output from the error amplifier 1425 is input to the limit detector 1325 .

[0167] The limit detector 1325 outputs a Vcm_lim signal. This Vcm_lim signal corresponds to Vcm during normal operation, but when the output of the auxiliary voltage detector 1330 indicates that the output power is within the zero power threshold, then the limit detector 1325 outputs a Vcm_lim value that is a fixed maximum value of Vcm to thereby clamp the Vcm_lim value. The limit detector 1325 also outputs an override signal that is sent to the PI regulator 1315 to stop the operation of the PI regulator 1315 until the output power increases above the threshold again. In this case, further integration of Vcm ends, thereby preventing entry into the dead zone, as with Fig.12 The embodiment is similar.

[0168] The more the output current decreases to zero, the smaller the interval that Vaux is greater than the sampled Vaux minus Δ becomes, and the smaller the duty cycle becomes.

[0169] Therefore, the duty cycle of the interval related to the half cycle can then be used as an error signal for limiting Vcm.

[0170] Also in this embodiment, when there is no load, the relationship between Vcm and the sensed signal is lost, since the peak value of the auxiliary voltage is no longer the output voltage when the secondary diode is not conducting. Therefore also here, the signal cannot be used directly for regulation to no load, since in no load situations, the actual distance of the no load point cannot be detected with respect to each further application of Vcm to the no load region, the Vaux peak value is no longer related to Vout, and therefore the duty cycle at the error amplifier output cannot be related to this distance.

[0171] For other power outputs, similar error signals with opposite polarities may be generated similar to the first embodiment.

[0172] It should be noted that using the output current directly has the following limitation: No information is available about the distance to the no-load point for a given Vcm. Therefore, it is not possible to regulate all the way to zero load.

[0173] A third embodiment of Vcm clamping using CCM monitoring will now be described. This third embodiment exploits the property that the half cycle with maximum output current will enter CCM when the asymmetry is greater than a certain maximum value.

[0174] Fig.15 A graph showing the current on the primary coil and the magnetizing current component as a result of magnetizing the core with two power output terminals loaded is shown. The secondary current is the difference between the primary current and the current in the core. Therefore, when the primary current and the core current are equal, the secondary current is zero. When the point A where the secondary current becomes zero is before the end of half cycle B, the half cycle is in discontinuous mode (DCM).

[0175] Fig.16 FIG. 1 shows a graph of the current in the primary coil and in the magnetic core when one output terminal has reached zero output power. Fig.16 In , the half cycle is in CCM because point A, where the secondary current becomes zero, is before the end of half cycle B. Moreover, as the asymmetry (set by the Vcm term) increases further, the depth of CCM (i.e., how large the secondary current is at the end of the secondary stroke) increases.

[0176] When the resonant tank of the dual output resonant converter is sized so that CCM operation occurs only when the output current during another half cycle has become zero, then the point at which CCM occurs (and also the CCM depth) can be used to limit the Vcm term. This sizing can be achieved by selecting an appropriate reflected output voltage (turns ratio) in combination with the required maximum supply voltage and minimum output voltage of the LLC converter. It should be noted that CCM operation first occurs at the maximum ratio between the supply voltage and the output voltage.

[0177] CCM operation can be detected by sensing the output current at the end of the secondary stroke. Alternatively, the auxiliary voltage at an auxiliary coil coupled to the secondary can be sensed and checked to determine whether the auxiliary voltage decreases before (DCM) or after (CCM) the end of the secondary stroke. The depth of CCM is related to the time it takes after the end of the half cycle before the auxiliary voltage reacts. By measuring the time difference between the end of the half cycle and the moment the auxiliary voltage starts to react, an error signal can be generated to determine that the output power is going to zero and then clamping the Vcm value.

[0178] Simulations can be used to show the behavior of Vaux and Vhb, which is the voltage of the switching node, when CCM occurs. Figure 8 In an example of simulation results of a dual output resonant converter with a controller of , the current in the LED output terminal is gradually reduced. In this case, Vaux crosses 0V 75ns after the start of the Vhb ramp. In this case, DCM occurs during the half cycle.

[0179] In another simulation scenario, CCM occurs with a 200ns delay between the start of the Vhb ramp and the intersection of Vaux and 0 V. Another simulation scenario shows CCM occurring with a 265ns delay between the start of the Vhb ramp and the intersection of Vaux and 0 V due to significant output current at the end of the secondary stroke. These characteristics can be used to determine when the output power is approaching zero.

[0180] Using this CCM detection method of determining the time difference between when Vaux crosses 0V and when the Vhb ramp begins allows the system to be regulated to no load because at no load the relationship between Vcm and the time difference is still defined.

[0181] Fig.17 A block diagram of a third embodiment of clamping Vcm is shown. In this embodiment, the voltage at the auxiliary winding coupled to the secondary winding and the switching node Vhb (see Figure 1 The voltage of 11) is monitored to generate an error signal for limiting the Vcm signal. Fig.17 The block diagram contains Figure 8 The same as shown in Figure 8 17 and includes a PI regulator 1715 and an adder 1720. A dual output resonant converter 1705 is also shown. A limit detector 1725 and a CCM detector 1730 are also included.

[0182] The CCM detector 1730 is a circuit that receives the auxiliary voltage value Vaux from the auxiliary coil and the voltage at the switching node Vhb and acts as a power detector. Fig.18 18 shows a block diagram of a CCM detector. The CCM detector 1730 includes a zero crossing detector 1805, a start ramp detector 1810, a time difference detector 1815, and an adder 1820. The zero crossing detector 1805 monitors the Vaux input voltage and outputs a time value when the Vaux input voltage intersects 0V. The start ramp detector 1810 monitors the Vhb input voltage and outputs a time value when the Vhb voltage begins to have a ramp. The time difference detector 1815 calculates the time difference between when Vaux intersects 0V and when Vhb begins to exhibit a ramp. The adder 1820 subtracts a reference value from the time difference calculated in the time difference detector 1815 to generate an error signal. The reference value is based on an expected time difference indicating that CCM operation has begun. The error signal output from the CCM detector 1730 is then input to the limit detector 1725.

[0183] The limit detector 1725 outputs a Vcm_lim signal. This Vcm_lim signal corresponds to Vcm during normal operation, but when the output of the CCM detector 1730 indicates that the output power is within the zero power threshold, then the limit detector 1725 outputs a Vcm_lim value that is a fixed maximum value of Vcm to thereby clamp the Vcm_lim value. The limit detector 1725 also outputs an override signal that is sent to the PI regulator 1715 to stop the operation of the PI regulator 1715 until the output power increases above the threshold again. In this case, further integration of Vcm ends, thereby preventing entry into the dead zone, as with Fig.12 The embodiment is similar.

[0184] As mentioned above, the three clamping embodiments can also be combined with Fig.11 Converters controlled by duty cycle and frequency are used together. In this case, the duty cycle primarily determines how the power is divided between the two outputs similar to the Vcm term.

[0185] In certain instances, it may be difficult to control a dual output resonant converter to ensure the full output power range for each of the outputs. Fig.19The simulation results of a dual output resonant converter controlled by the Vdm and Vcm signals as described above are shown. The output voltages are such that when Vcm = 0, equal power appears at both outputs. For simplicity, the turns ratio of the two outputs is the same so that the two output currents have the same weighting factor relative to the output power.

[0186] from Fig.19 It can be seen that for Vcm=0, the two output powers are equal and proportional to Vdm. For Vcm>0, Iout2 increases while Iout1 decreases, essentially transferring power from one output terminal to the other, especially for relatively small powers, such as Vdm<about 0.3. This process of transferring power stops rather abruptly when Iout1 becomes close to 0, while at larger values ​​of Vdm, the process of transferring power is smoother. For Vdm>0.6 in this example, undesirable effects occur, such as the switching frequency starts to change significantly, and other effects that require a detailed understanding of the resonant tank behavior due to large resonances and are therefore not discussed here. Therefore, the dual output resonant converter can therefore be designed preferably at less than Fig.19 The dual output resonant converter operates at some maximum Vdm between 0.3 and 0.6, called the scaling factor. In this operating range, the dual output resonant converter behaves in such a way that the symmetry is mainly set by Vcm, while the total power is mainly set by Vdm. Based on a simplified model that assumes a sudden change in power and some dimensioning of the resonant tank, the power in each output as a function of Vcm and Vdm can be given by Fig. 20 The modeling given in . Fig. 20 Shows Fig.19 Although this model is only a very simple approximation of the actual behavior, it can be used to gain a better understanding of the main problems of providing the full range of power control for each output and how to overcome those problems.

[0187] As mentioned above, the desired controller should have the opposite behavior of the converter, which can be generally written as:

[0188] Vcm=error1·k21+error2·k22;

[0189] Vdm=error1·k11+error2·k12.

[0190] These equations are small signal equations, so changes in the error signal cause changes in Vdm and Vcm. For a real controller driven by currents from two optocouplers, maximum power occurs when both optocoupler currents are zero. In this case, the maximum value of Vdm (Vdm_max) occurs. Fig.21A block diagram of a dual output controller is shown, which shows that when the measured error signal is zero, the Vdm_max value is output from the controller. As the error signal increases, the Vdm value decreases from Vdm_max because the power is less than the maximum value.

[0191] For the specific case where symmetrical behavior occurs for both outputs (i.e., same reflected output voltage, same coupling to the primary for both secondary windings, and both outputs operating at approximately the same output power), the symmetry or difference between the output powers is primarily set by Vcm, while the total power is primarily set by Vdm. This means that k11 and k12 are equal, while k21 and k22 have the same magnitude but opposite signs. This situation is valid for both output powers greater than zero and less than mid-power levels.

[0192] For the region where Vcm causes one of the output powers to go to zero, a controller based on the above equations for Vcm and Vdm, where k11 and k12 are equal, and k21 and k22 have the same magnitude but opposite signs, can cause problems because the two error signals can reduce the Vdm signal that sets the total power, and Vcm can no longer set the power division between the two output terminals. Fig.22A A situation is shown where Vcm can no longer set the power division between the two outputs.

[0193] Pout1 is the power in the first output terminal, and Pout2 is the power in the second output terminal. In region 1 2205, power flows to both input terminals, and the controller is set to the optimal parameters k11=k12 and k21=-k22, and Pout1 is set by the error signal error1, and error1 has no effect on Pout2. The reason why Pout2 can be kept constant is that error1 reduces Vdm, and error1 also adjusts Vcm in an appropriate proportion so that the power reduction of Pout2 caused by the reduction in Vdm is compensated by transferring power from Pout1 to Pout2 by changing the Vcm term.

[0194] However, in region 2 2210, Vcm loses its effect when Pout1 reaches zero. The result is that only the Vdm term can change power, so the two output powers are then set by only one variable. Since k11=k12, the error1 signal still continues to reduce the total power by reducing the Vdm term, while losing the compensating effect of k21 in conjunction with Vcm to transfer power from Pout1 to Pout2 because there is no remaining power to transfer from the first output terminal to the second output terminal when Pout1 is already zero. The result is a loss of quadrature control because Pout2 is also reduced by error1, which is undesirable.

[0195] An embodiment is described below that overcomes this problem of power loss at one output and loss of quadrature control by limiting the Vdm term reduced by each error signal to, for example, half of the maximum value so that the power in the other output can remain under the control of the other error signal.

[0196] As before, an embodiment of a dual-mode resonant converter with at least two output terminals including a regulated system voltage output terminal and a second regulated output terminal, wherein the second output terminal may be an LED string with a regulated current, will be used as an example. The dual-mode resonant converter is controlled by state variables Vcm and Vdm, wherein the Vdm variable is limited to a minimum value by each error signal so that the other error signal can increase the power to a desired value. In order to get a better understanding of the details of this embodiment, a more detailed analysis of the problem is first described.

[0197] Fig. 22B An example of a dual output resonant converter controlled by Vdm and Vcm is shown. In this example, the scaling factor of the converter is set so that Vdm = 100V gives 200 watts of total power (100 watts in each output in symmetrical operation at Vcm = 0), and 100V Vcm transfers 100 watts of power from Pout1 to Pout2.

[0198] Now assume a transient situation where the load changes from 100 Watts (Vdm=100V, Vcm=0V) in both outputs to no load at the Pout1 output and 100 Watts (Vdm=50V, Vcm=50V) at the Pout2 output. No load at Pout1 will cause the regulation loop to increase the error1 signal, however due to the overshoot the error signal may also overshoot and thus Vdm is reduced to below 50 times the factor k11, while Vdm=50V is required to make Pout2=100 Watts. Especially when this is a load jump to no load, the error signal may overreact due to the overshoot of the output voltage, while the converter cannot generate negative power to reduce the output voltage. The error2 signal can partially compensate for the power demand of the other channel by reducing its error signal, but since the optocoupler current cannot become negative, it must be measured through the error1 path so that at least Vdm=50V.

[0199] An embodiment of a dual output resonant converter will now be described in which the contribution of each error signal to the Vdm signal is limited so that the Vdm signal cannot be smaller than required for the maximum power level in the other channels. Fig. 22BFor a converter where the power required at each output ranges between 0 and 100 Watts (maximum 200 Watts giving Vdm_max=100V), the limit can be set to maintain at least half 50V of Vdm_max for the error1 path to ensure that 100 Watts of power can be delivered via the error2 path.

[0200] A limit should also be set to maintain at least half of 50V of the Vdm_max of the error2 path to ensure that 100 watts of power can be delivered through the error1 path. Even when the error signal overshoots, the inclusion of this limit and the following fact guarantee two power ranges: the Vcm term can completely transfer the available power between the two output terminals. However, some margin can be added so as not to use the full amplitude of the available Vcm term. There are two reasons for increasing this margin. First, due to the nonlinearity of the Vcm term when the power in one channel approaches zero, the margin provides benefits. Second, due to the fact that the output power decreases slightly when the symmetry increases, slightly less power becomes available than expected, so the margin can compensate for this reduction.

[0201] Therefore, Vdm_max based on the total power under symmetrical operation should be multiplied by an additional factor k slightly greater than 1, such as in the typical range of 1.1 to 1.2, to take into account the second effect. For the first effect, it is necessary to make the limit of the power based on the Vdm term slightly less than the required limit additional factor m, which is slightly greater than 1, such as in the typical range of 1.1 to 1.2, so that the error signal does not need the full amplitude of the Vcm term to make the power zero by transferring the residual power to the other output terminal.

[0202] Fig.23An embodiment of a dual output controller that limits Vdm values ​​is shown. Dual output controller 2300 includes multipliers 2305, 2310, 2315, and 2320, maximum detectors 2330 and 2335, Vdm limit blocks 2325 and 2340, adders 2345, 2350, and 2360, and a scaling Vdm_max block 2355. Dual output controller 2300 receives error signals error1 and error2. Multipliers 2305 and 2315 receive error1 signals as inputs and multiply error1 signals by k11 and k21, respectively. Multipliers 2310 and 2320 receive error2 signals as inputs and multiply error2 signals by k12 and k22, respectively. Adder 2350 adds the outputs of multipliers 2315 and 2320 to generate control signal Vcm. Maximum detectors 2330 and 2335 receive values ​​Vdm_max*α / m and Vdm_max*(1-α) / m from limit boxes 2325 and 2340, respectively. The purpose of factor m is described above. Maximum detectors 2330 and 2335 also receive outputs from multipliers 2305 and 2310, respectively. Maximum detectors 2330 and 2335 output the input maximum value of the received inputs. Adder 2345 then adds the outputs of maximum detectors 2330 and 2335. Adder 2360 then subtracts the output from adder 2345 from the value (Vdm_max*k) from the scaled Vdm_max box. The purpose of factor k is explained above.

[0203] If a value of 0.5 is chosen for α, each output can produce a power between zero and half the maximum power. If a larger range of powers is required for one output, a value of α other than 0.5 can be chosen. For example, with Fig.22A , which has a power range between 0 and 150 Watts for the first output (corresponding to error1) and between 0 and 50 Watts for the second output (corresponding to error2) (200 Watt maximum gives Vdm_max=100), the limit for the error1 path should be set so as to reserve at least 50 Watts of power for the error2 path (Vdm_max=25) to ensure that 50 Watts of power can be delivered through the error2 path when error2 is zero. The limit on the error2 path should also be set so as to reserve at least 150 Watts of power for the error1 path (Vdm_max=75) to ensure that 150 Watts of power can be delivered through the error1 path when error1 is zero. This power range can be set by a factor α between 0 and 1.

[0204] Fig.23 The embodiments can be combined in various ways with Figure 8 , Fig.12 , Fig.13 and Fig.17 In combination with the embodiments of the present invention, the dual output controller 2300 replaces the dual output controller in those embodiments so as to add the characteristic of limiting the power associated with each output terminal to the characteristic of linearizing and clamping the control variable Vcm. In this case, the output of the adder 2350 becomes the value ΔEc_desired used in the feedback loop.

[0205] also, Fig.23 The embodiments can be combined in various ways with Fig.11 , Fig.12 , Fig.13 and Fig.17 In the embodiment of the present invention, the dual output controller 2300 replaces the dual output controller in those embodiments, so as to add the characteristics of limiting the power associated with each output terminal to the characteristics of linearizing and clamping the control variables duty cycle and frequency. In this case, the output of adder 2350 becomes the ΔEc_desired value used in the feedback loop, and the output of adder 2360 becomes the total power value used in the feedback loop.

[0206] Figure 6B and Figure 6C A dual output resonant converter using Vcap control and Vcr control is shown. Both methods are used in practical resonant converters and are essentially compatible, although there are slight differences, for example with the Vcr method, the DC component of Vcr is equal to Vsupply / 2×duty cycle at the switching node, while the DC component with the Vcap method is zero (because it is the voltage across the inductor). Since capacitive voltage dividers are often used to reduce signal amplitudes of several 100 volts to a few volts as needed for further processing, using the Vcap method may be an advantage because the DC component does not have to be reconstructed afterwards.

[0207] For proper control of the Vcm control variable, an appropriate DC level needs to be applied. In the symmetrical case with equal power at both outputs, Vcm is equal to 0. However, in practical situations, there are several reasons why the operation of a dual output resonant converter is asymmetrical. First, there may be asymmetry in the transformer because the physical windings on the secondary side cannot be located in the same position. Second, the output voltage in a dual output resonant converter may be different from the symmetrical case with equal reflected output voltages. Third, when the resonant capacitor is placed on the ground side of the transformer, the DC value of the voltage across the resonant capacitor is equal to Vsupply / 2×duty cycle, where the duty cycle is the duration of a half cycle related to the total cycle. Typically a capacitive voltage divider is used to divide the voltage into low values ​​that can be processed by the controller IC. Since such a capacitive voltage divider cannot divide the DC component, the DC component of Vcm is also undefined or poorly defined. A resistive voltage divider can be placed in parallel to define the DC component, but the mismatch between the two factors of the two voltage dividers due to component tolerances still results in too much asymmetry. Furthermore, resistive voltage dividers can introduce phase shift due to parasitic capacitance or dissipate too much power due to their high impedance.

[0208] In a normal resonator with symmetrical operation, the DC component can be reconstructed by connecting a capacitive voltage divider to a fixed voltage resistor with high impedance and then adding a suitable DC component based on the measured duty cycle or the ratio of the current in the two half cycles. For a dual output resonant converter, different powers appear in each half cycle, so this reconstruction method cannot be used.

[0209] An embodiment of a dual output resonant converter that reconstructs the appropriate DC component so that the required power can be delivered to the two output terminals will now be described. Features of this embodiment include: checking whether one of the error signals is clipped to a minimum or maximum value as an indication that the desired power cannot be delivered; checking a signal associated with each output terminal indicating that the output terminal has reached a no-load condition; adding an additional offset term to the Vcm signal or to a value compared to Vcm; adjusting the additional offset based on a method of clipping one of the error signals; and setting the direction of adjusting the offset by clipping the error signal and the level of clipping combined with information about whether each output terminal has reached a no-load condition.

[0210] Fig.24The first embodiment of the dual output controller using Vcm offset is shown. This dual output controller 2400 is similar to other dual output controllers that implement calculations of Vdm and Vcm based on error1 and error2 signals described above. Multipliers 2405, 2410, 2415 and 2420 multiply error1 signal and error2 signal by constants k11, k12, k21 and k22 as shown in different ways. Adder 2425 adds the outputs of multipliers 2405 and 2410 together to generate Vdm. Adder 2430 subtracts each other's outputs from multipliers 2415 and 2420 to generate the initial value of Vcm. Adder 2435 then adds Vcm_offset value 2440 to the output of adder 2430 to generate Vcm.

[0211] When the DC component of the Vcm term is wrong, too much power can go to one output and too little power to the other, which is contrary to the desired output values ​​for both outputs. For this reason, an additional term Vcm_offset is added to the Vcm control variable to shift power from one output to the other when this mismatch situation occurs.

[0212] Fig.25 A second embodiment of a dual output controller using a Vcm offset is shown. This dual output controller 2500 is similar to the above Fig.24 2500 is similar to the dual output controller described in , but the difference is that the Vcm offset is implemented in the dual output resonant converter. The dual output controller 2500 generates Vdm and Vcm values ​​that are calculated based on the error1 and error2 signals as described above. In this second embodiment, Vcm_offset is used later in controlling the switching of the switches in the dual output resonant controller. This addition of Vcm_offset can be implemented by injecting current or charge into the capacitive voltage divider for measuring Vcr mentioned above. More specifically, this can be accomplished by combining the following: combination block 2505, comparators 2510 and 2515, adder 2520, Vcm_offset generator 2440 and drive control logic 2525.

[0213] Fig.26An embodiment of a Vcm_offset circuit is shown. The Vcm_offset circuit 2600 includes comparators 2605, 2610, 2615, and 2620, OR gates 2625 and 2630, AND gates 2635 and 2640, and an integrator 2645. Comparator 2605 receives the error1 signal and the error1 minimum value to generate an output signal A indicating that the maximum output power that can be delivered at output terminal 1 is very low. Comparator 2610 receives the error1 signal and the error1 maximum value to generate an output signal B indicating that the minimum output power that can be delivered at output terminal 1 is very high. Comparator 2615 receives the error2 signal and the error2 minimum value to generate an output signal C indicating that the maximum output power that can be delivered at output terminal 2 is very low. Comparator 2620 receives the error2 signal and the error2 maximum value to generate an output signal D indicating that the minimum output power that can be delivered at output terminal 2 is very high. Under normal conditions, the error signals error1 and error2 have values ​​between the minimum value and the maximum value. As long as the load connected to Vout1 matches the power delivered to the output by the converter, the regulated output Vout1, for example, causes the error signal error1 to be within the maximum-minimum range. When the load increases to a maximum power greater than the maximum power that can be delivered by the output, the error signal applies to the minimum or maximum value, depending on the polarity selected for the error signal. For example, assuming that the error1 signal at the maximum value causes the maximum power to be delivered, and the error1 signal at the minimum value causes the minimum power to be delivered. A properly sized converter is capable of delivering the required maximum and minimum power, so the error signal reaching the maximum or minimum value should not appear during a steady state situation and means that the offset level is incorrect. During transients, for short intervals, the minimum or maximum levels may intersect, but depending on the selected bandwidth of the main loop, this situation cannot take longer than a certain time, such as 500usec. It can take longer only during startup or after a specific fault condition.

[0214] Therefore, if it is detected that the error signal lasts longer than the expected time outside the limit, there may be a problem with the Vcm term, and then the action slowly adjusts the Vcm_offset signal in the required direction to transfer power from one output terminal to the other output terminal. Since the main regulation loop also controls the power delivery to the two output terminals, the Vcm_offset transfer mechanism is required to have a bandwidth significantly smaller than the bandwidth of the main loop to prevent instability caused by the interaction of the two loops. OR gate 2625 receives outputs A and D and counts to determine whether A or D or A and D indicate error1 and / or error2 are outside the range. If so, OR gate 2625 generates an output that changes the value of the Vcm_offset term. OR gate 2630 receives outputs B and C and counts to determine whether B or C or B and C indicate error1 and / or error2 are outside the range. If so, OR gate 2630 generates an output that changes the value of the Vcm_offset term.

[0215] AND gate 3635 receives the output of OR gate 2625 and an indication that the output current Iout2 at the second output terminal is greater than zero and generates an AND of the inputs. AND gate 3640 receives the output of OR gate 2630 and an indication that the output current Iout1 at the first output terminal is greater than zero and generates an AND of the inputs.

[0216] Integrator 2745 receives the output of AND gates 3635 and 3640 and generates a Vcm_offset value as an output. Integrator 2645 may be implemented as an up / down counter. As AND gates 2635 and 2640 generate output values, integrator 2645 adjusts the Vcm_offset value to compensate for errors in the output power. Fig.26 The logic function assumes a certain polarity of the error signals error1 and error2, so in case of different polarities, different logic combinations occur, but the concept remains the same. The signal Vcm_offset can be, for example, a voltage, a current, a charge or a digital value. Other implementations of the integrator 2645 can also be used.

[0217] The signals Iout1>0 and Iout2>0 are included to prevent activation of the Vcm_offset regulation when zero load occurs, because in this case the regulation loop usually reacts in this way, so when Iout=0 has been reached, the transfer action is prevented by logic, because it is already clear that the Vcm_offset term enables no load.

[0218] In another embodiment, an additional function can be added when the system cannot deliver enough power to both channels. First, the action can be to do nothing. Second, the k11 and k12 values ​​can be increased.

[0219] Fig.26 The embodiments using the Vcm_offset term can also be used in various combinations with Figure 8 , Fig.12 , Fig.13 and Fig.17 In addition, Fig.26 The embodiments can be combined in various ways with Fig.11 , Fig.12 , Fig.13 and Fig.17 In this embodiment, the signal duty cycle offset can be added to Fig.11 duty cycle.

[0220] exist Figure 8 In an embodiment of the invention, a dual output resonant converter with a local feedback loop is presented to improve the orthogonal control performance as needed to prevent cross regulation problems between the two output terminals. In the case where one of the two output terminals is unloaded, this new local feedback loop has a zero loop gain, so the local feedback loop then becomes an open loop, so that one of the resonant converter control variables (Vcm) gradually does not cause undesirable effects, such as time intervals where the output power cannot be properly controlled because the Vcm change has no effect on the output power, thereby disturbing the regulation loops of the two output terminals. Figure 24 to Figure 26 In the embodiments of , several solutions are proposed to limit the Vcm term so that the converter can handle a no-load condition at one output. Figure 8 The embodiments of the present invention significantly improve normal operation and no-load operation at one output, but one problem that remains is that the transition between the two conditions produces undesirable transient effects. Such transient effects can interfere with both outputs, such as the LED and low voltage output when used in an LCD TV with PWM dimming.

[0221] An embodiment will now be described which solves this problem in a more fundamental way by limiting the corresponding error signal rather than the Vcm signal. This embodiment results in better performance during transition situations between normal operation and no-load operation at one output terminal, since the required relationship between the Vcm and Vdm terms is also maintained during transitions.

[0222] This embodiment may include the following features: The dual output resonant converter is controlled by state variables Vcm and Vdm, where the Vcm variable is included in a local feedback loop to improve the above reference Figure 8The linearity of the transfer from the control input to the power discussed. An embodiment includes a detector that detects whether one of the output terminals is approaching a zero load condition. Moreover, an embodiment includes a processing box that includes a sampling function that samples the Vcm signal when a no-load condition is reached or almost reached. An embodiment includes a local regulation loop that uses the sampled Vcm signal as a reference and regulates / limits the actual Vcm value to a value slightly higher than the reference. This regulation loop generates a second error signal that is compared with the error signal from the main regulation loop. The smallest of the two error signals is then used as an input to the controller so that the controller generates appropriate Vcm and Vdm signals and an appropriate relationship between them to maintain orthogonal control.

[0223] Figure 8 The embodiment of using local feedback to control Vcm is used as the basis for this embodiment. Fig. 27 An embodiment of a converter that limits the error signal is shown. Converter 2700 includes a dual output resonant converter 2720, an error processor 805, and a feedback loop 810, wherein the feedback loop 810 includes the above reference Figure 8 The adder 815 and the regulator 820 described. The converter 2700 further includes a zero power detector 2705 and a zero output power processor 2710. The zero power detector 2705 detects when the power at either of the two output terminals of the dual output resonant converter 2720 becomes zero and outputs a signal indicating this condition. The zero power processor 2710 receives the two error signals error1 and error2 and generates limited error signals error1_lim and error2_lim based on the output signals from the zero power detector 2705.

[0224] Fig.28 An embodiment of a zero output power processor is shown. The zero output power processor 2800 includes a track and hold circuit 2805, an adder 2810, a regulator 2815, and a minimum detector 2820. The zero output power processor 2800 receives an error signal, which may be an error1 signal or an error2 signal. It is shown that only one error signal is processed, but the same processing will be performed on the other error signal in the same manner. The error signals error1 and error2 indicate the output state at the secondary side of the dual output resonant converter.

[0225] The track and hold circuit 2805 receives as input the current value of Vcm together with the output of the zero output detector and outputs a value Vcmreg. When the output power becomes zero, the track and hold circuit 2805 then sets the Vcmreg value to the value of Vcm at the time when the output power becomes zero. Otherwise, the track and hold circuit 2805 simply sets the Vcmreg value to the current value of Vcm in the tracking mode. Adder 2810 calculates the value Vcmreg+Vcmoffset-Vcm. The output of adder 2810 is input to regulator 2815, which then generates a signal indicating an error signal. The regulator can be any type of regulator, including, for example, a PI regulator, a proportional integrator, a differential regulator, etc. Minimum detector 2820 receives the error signal and the output of regulator 2815, and outputs the minimum value of the two inputs.

[0226] As long as power is delivered to the two outputs of the dual output resonant converter 2720, the track and hold circuit 2805 is in tracking mode, which means that the signal Vcmreg is equal to Vcm and the adder output is equal to the Vcmoffset signal as the input of the regulator 2815. The output of 2815 is then integrated to a high level, which is generally greater than the error signal, so that the error signal is directly passed to the limited error signal. As an optional feature, the Vcmreg output is updated only at a certain time during the switching cycle because Vcm contains ripples generated by the main regulation loop reacting to the output current pulse of the converter. The minimum detector 2820 input from the regulator 2815 is then high, and the error signal is directly passed to the limited error signal output. In this case, the zero power detector 2705 does not affect the operation of the dual output resonant converter 2720. In this embodiment, a minimum detector related to the polarity of the error signal is used. It should be noted that the opposite polarity of the error signal is also possible, and then the maximum detector will be used instead of the minimum detector.

[0227] When one output of the dual output resonant converter 2720 approaches zero load, this is detected by the zero power detector 2705. This detection event is then processed by the zero output power processor 2710 as follows. First, the track and hold circuit 2805 maintains the value of the Vcm term to the value Vcmreg. Now the difference between Vcm and Vcmreg drives the regulator 2815 and overrides the normal error signal as long as Vcm is on the wrong side of Vcmreg+Vcmoffset. The result is that this local feedback loop sets the limited error signal to an appropriate value so that the appropriate Vcm signal only appears when approaching no load. Due to the Vcmoffset term, Vcm will stabilize at a value just below the boundary of zero power. Since the local loop allows positive and negative values ​​of Vcmreg-Vcm+Vcmoffset, the system can be actually limited to zero output power with some margin.

[0228] The zero power detector 2705 can be as follows Fig.13 , Fig.14 , Fig.17 and Fig.18 It is implemented as described in , which includes: actually sensing the output current and limiting Vcm when the output current is close to zero; sensing the voltage at the auxiliary winding and detecting whether the voltage is greater than the reflected output voltage during a certain time interval during a half cycle; or checking whether CCM operation occurs.

[0229] Although according to Fig.28 The zero output power processor 2710 can actually regulate the output current to zero, but the relationship between Vcm and the output current may change due to, for example, changing the supply voltage of the converter or changing the output voltage because the load is connected to the output terminal where the output voltage is temperature and current dependent. Therefore, it is not sufficient to sample Vcm only once when zero load occurs.

[0230] This can be addressed by periodically driving the loop towards the point where power starts to flow and then resampling the corresponding Vcm value. There are several options for achieving this, such as by overriding an error signal that slowly adjusts the Vcmoffset level.

[0231] Fig.29 An embodiment based on slowly adjusting the Vcmoffset level is given in FIG. Fig.28 The zero output power processor 2710 shown in FIG. 1 is modified by adding the following items: a ramp generator 2905 and adders 2910, 2915, and 2920. The track and hold circuit 2805, the regulator 2815, and the minimum detector 2820 are connected to the reference Fig.28 Same as described.

[0232] An additional input resample is added driving the ramp generator 2905. This ramp generator 2905 generates an additional offset which is added to Vcmoffset by adder 2910 to produce a total offset Vcmoffset1. Because the idea is to get back to the boundary of delivering only power, the ramp generator 2905 produces a negative ramp that effectively compensates for Vcmoffset.

[0233] When a resampling pulse is received, the ramp generator 2905 generates a ramp signal starting from zero, slowly increasing its amplitude. The result will be that the regulator begins to adjust its output so that the limited error signal changes, causing the controller to begin to adjust Vcm in the direction of increasing the power at the unloaded output. Therefore, when the ramp reaches a sufficient amplitude, the Iout=0 signal will become zero, indicating that power begins to flow into the output.

[0234] When Iout=0 becomes false (output current starts flowing), then the track and hold circuit 2805 will enter tracking mode and thus start passing the actual value of Vcm to its output Vcmreg as long as Iout=0 is false.

[0235] At the same time, as a result of Iout=0 becoming false, the ramp stops and resets to zero. Therefore, the original Vcmoffset is then added to Vcmreg. This offset, integrated by regulator 2815, again overrides the error signal and reduces the voltage at the output until it eventually reaches zero again. Therefore, Iout=0 becomes true and causes the track and hold circuit 2805 to hold the last Vcm value, which now corresponds again to an output power equal to zero. The inclusion of the Vcmoffset term ensures that the local loop including regulator 2815 and minimum detector 2820 regulates Vcm to a level that gives no load again.

[0236] This process is repeated periodically. The power delivery can be detected within a few switching cycles, while due to the limited ramp-up speed, the generated power can be very low, and the generated effective power can be limited to less than 50 milliwatts for a 100 watt led power system. This small power can be easily dissipated in a parallel resistor or additional load connected to the second winding with a reflected output that generates power during the same half cycle as the LED output.

[0237] A process may also be activated upon detection of an event according to which it may be expected that the relationship between Vcm and the point at which no power is delivered has changed, such as after a power drop or a large load jump.

[0238] If for whatever reason power begins to flow into the output which is regulated to no load, this will automatically cause Iout=0 to go false and Iout=0 to go back true so that an automatic update to the appropriate Vcm and Vcmreg levels can occur.

[0239] Fig. 27 The embodiments of the invention may also be applied more generally, such as for example with a dual output resonant converter core, the dual output resonant converter core being composed of Fig.11 The duty cycle and switching frequency control are shown in FIG. Fig.30 An embodiment of a converter using duty cycle and frequency control to limit the error signal is shown. Such a converter can be controlled by a similar controller having one or more local feedback loops to linearize the transfer from the control input to the output variable, such as Fig.30 The circuit shown in contains two feedback loops for frequency and duty cycle. Fig.30 The converter in Figure 27 to Figure 29 The converter in 2800 operates identically. In this case, the duty cycle variable replaces the asymmetry of the Vcm driving converter and is therefore related to the point at which one output terminal tends to be unloaded. In this case, the duty cycle can then be used as an input to the input terminal of the track and hold circuit 2805.

[0240] Although the output of the resonant converter is described in terms of output voltages Vout1 and Vout2, it should be understood that the control techniques described herein are applicable to and may be implemented in response to the following: voltages Vout1 and Vout2 at the output terminals, currents Iout1 and Iout2 at the output terminals, powers Pout1 and Pout2 at the output terminals, or some combination thereof. In some instances, the term "voltage / current" is used to refer to voltage and / or current, such that the term may refer to voltage, may refer to current, or may refer to both voltage and current. The term may also refer to power, which is a function of voltage and / or current.

[0241] The method according to an embodiment of the present invention can be implemented on a computer as a computer-implemented method. The executable code for the method according to the present invention can be stored on a computer program medium. Examples of computer program media include memory devices, optical storage devices, integrated circuits, servers, online software, etc. Therefore, a white box system can include a white box computer program implemented by a computer. Such a system can also include other hardware elements, including storage devices, network interfaces for transmitting data with external systems, and other elements of the white box system.

[0242] In an embodiment of the invention, the computer program may contain computer program code adapted to perform all the steps of the method according to the invention when the computer program is run on a computer.Preferably, the computer program is embodied on a non-transitory computer readable medium.

[0243] Any combination of specific software running on a processor to implement embodiments of the invention constitutes a specific special purpose machine.

[0244] As used herein, the term "non-transitory machine-readable storage medium" will be understood to exclude transitory propagating signals but include all forms of volatile and non-volatile memory. In addition, as used herein, the term "processor" will be understood to include various devices, such as microprocessors, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and other similar processing devices. When software is implemented on a processor, the combination becomes a single specific machine.

[0245] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention.

[0246] Although various exemplary embodiments are described in detail with particular reference to specific exemplary aspects, it should be understood that the present invention can have other embodiments and its details can be modified in various obvious aspects. It is obvious to those skilled in the art that various changes and modifications can be made within the spirit and scope of the present invention. Therefore, the above disclosure, description and drawings are only for illustrative purposes and do not limit the present invention in any way. The scope of the present invention is limited only by the claims.

Claims

1. A power converter, characterized in that: It includes: A dual output resonant converter comprising a first output terminal, a second output terminal, a common mode control input terminal and a differential mode control input terminal, wherein a voltage / current at the first output terminal and a voltage / current at the second output terminal are controlled in response to a common mode control signal received at the common mode control input terminal and a differential mode control signal received at the differential mode control input terminal; as well as a dual output controller comprising a first error signal input, a second error signal input, a delta power signal input, a common mode control output, and a differential mode control output, wherein the dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to a first error signal received at the first error signal input and a second error signal received at the second error signal input, wherein the first error signal is a function of the voltage / current at the first output, and the second error signal is a function of the voltage / current at the second output, and wherein the common mode control signal is output from the common mode control output, and the differential mode control signal is output from the differential mode control output; wherein the common mode control signal is generated using a feedback loop using a desired delta power signal ΔEc_desired based on the first error signal and the second error signal and a delta power signal ΔEc as a function of a difference in output power at the first output terminal and the second output terminal; Wherein, expected delta power = first error signal·k21+second error signal·k22, wherein k21 and k22 are variables included in the control variable matrix.

2. The power converter according to claim 1, characterized in that: The dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to the first error signal and the second error signal by pre-calculating a control variable matrix and generating the common mode control signal and the differential mode control signal as a function of the first and second error signals and the control variable matrix.

3. The power converter according to claim 2, characterized in that: The control variable matrix includes variables k11, k12, wherein the differential mode control signal is generated as: Vdm=first error signal·k11+second error signal·k12.

4. The power converter according to claim 1, characterized in that: The feedback loop further comprises: an adder configured to calculate a difference between the expected delta power signal and a difference between output powers at the first output terminal and the second output terminal; and A regulator is configured to receive the output of the adder to generate the common mode control signal.

5. The power converter according to claim 1, characterized in that: It further includes a clamping circuit configured to clamp the common mode control signal to a range of values.

6. The power converter according to claim 5, characterized in that: The clamping circuit further comprises: a power detector configured to generate an indication signal when the output power of the first output terminal approaches zero; and A limit detector is configured to receive the common mode control signal and the indication signal to generate a limited common mode signal based on the range of values.

7. The power converter according to claim 6, characterized in that: The power detector includes a reference input terminal configured to receive a reference signal and a voltage / current input terminal receiving a voltage / current signal from the first output terminal, wherein the indication signal is generated based on the reference signal and the voltage / current signal from the first output terminal.

8. The power converter according to claim 6, characterized in that: The power detector includes an auxiliary voltage input configured to receive an auxiliary voltage signal from an auxiliary coil coupled to a secondary of the dual output resonant converter, wherein the indication signal is generated based on the auxiliary voltage signal.

9. The power converter according to claim 6, characterized in that: The power detector includes an auxiliary voltage input terminal and a switching node voltage input terminal, the auxiliary voltage input terminal is configured to receive an auxiliary voltage signal from an auxiliary coil coupled to the secondary of the dual-output resonant converter, and the switching node voltage input terminal receives a switching node voltage signal from a switching node in the dual-output resonant converter, wherein the indication signal is generated based on the auxiliary voltage signal and the switching node voltage signal, which indicates starting a continuous conduction mode (CCM) of operation of the dual-output resonant converter.

10. A power converter, characterized in that: It includes: A dual output resonant converter comprising a first output terminal, a second output terminal, a duty cycle control input terminal and a frequency control input terminal, wherein a voltage / current at the first output terminal and a voltage / current at the second output terminal are controlled in response to a duty cycle control signal received at the duty cycle control input terminal and a frequency control signal received at the frequency control input terminal; as well as a dual output controller comprising a duty cycle control output and a frequency control output, wherein the dual output controller is configured to generate the duty cycle control signal and the frequency control signal in response to the voltage / current at the first output and the voltage / current at the second output, wherein the duty cycle control signal is generated using a first feedback loop that uses a desired delta power signal ΔEc_desired based on the voltage / current at the first output terminal and the voltage / current at the second output terminal and a delta power signal ΔEc that is a function of the difference in output power at the first output terminal and the second output terminal, and wherein the frequency control signal is generated using a second feedback loop that uses a desired total power signal based on the voltage / current at the first output terminal and the voltage / current at the second output terminal and a total power signal that is a function of the total power at the first output terminal and the second output terminal; Wherein, expected delta power = first error signal·k21+second error signal·k22, wherein k21 and k22 are variables included in the control variable matrix.

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