Semiconductor memory device and repair method thereof

Abstract

Disclosed are a semiconductor memory device and a repair method thereof. The semiconductor memory device includes a memory cell array and an error correction code logic. The memory cell array includes a main cell array and a redundant cell array. The method includes: detecting a fault bit of each of a main repair cell of the main cell array and a redundant repair cell of the redundant cell array; determining whether the fault bit detected from each of the main repair cell and the redundant repair cell is correctable using the error correction code logic, and determining a first correctable state or a second correctable state; calculating a first cumulative correctable fault bit count of the main repair cell and a second cumulative correctable fault bit count of the redundant repair cell; determining whether to replace the main repair cell with a redundant repair cell according to the first correctable state, the second correctable state, the first cumulative correctable fault bit count, and the second cumulative correctable fault bit count; and performing a repair operation according to the determination result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0012900 filed on February 1, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments described herein relate to a semiconductor memory device, and more particularly, to a semiconductor memory device that can perform a repair operation based on an error correction code and a repair method thereof. Background Art

[0004] The capacity and speed of semiconductor memory devices used in various electronic systems are increasingly dependent on the high performance requirements of users. Specifically, a typical example of a volatile memory device may be a dynamic random access memory (DRAM). DRAM stores data in the form of charges charged in a cell capacitor.

[0005] After the DRAM is manufactured, a technique for repairing defective cells that occur during the manufacturing process is used. For example, a row or column including a defective memory cell is replaced with a normal row or column using a redundant repair technique. As the size of semiconductor memory devices is reduced, the number of defective memory cells increases dramatically. When the redundancy for replacing defective cells is ensured using conventional redundant repair techniques, the size of the memory device increases. In addition, the row or column redundant circuit is configured to replace the row of each row group (e.g., two or four word lines) or the column of each column group (e.g., four or eight bit lines). Therefore, a large amount of resources are unnecessarily consumed to repair single bit failures.

[0006] In the disclosed embodiments, a repair technique associated with an error correction code may be provided to improve the efficiency of the above-described redundancy repair technique by utilizing a more limited amount of resources. Summary of the invention

[0007] Example embodiments provide a semiconductor memory device and a repair method thereof, which can achieve high repair efficiency using an error correction code while minimizing resource consumption.

[0008] In some aspects, the present disclosure relates to a repair method for a semiconductor memory device, the semiconductor memory device including a memory cell array and an error correction code (ECC) logic, the memory cell array including a main cell array and a redundant cell array, the method including the following steps: detecting a fault bit of each of a main repair cell of the main cell array and a redundant repair cell of the redundant cell array; determining whether the fault bit detected from each of the main repair cell and the redundant repair cell is correctable using the ECC logic to determine a first correctable state for the main repair cell or a second correctable state for the redundant repair cell; calculating a first cumulative correctable fault bit count for the main repair cell and a second cumulative correctable fault bit count for the redundant repair cell; determining whether to replace the main repair cell with a redundant repair cell based on the first correctable state, the second correctable state, the first cumulative correctable fault bit count, and the second cumulative correctable fault bit count; and performing a repair operation based on the determination result.

[0009] In some aspects, the present disclosure relates to a semiconductor memory device, which includes: a main cell array, which includes a plurality of main repair cells; a redundant cell array, which includes a plurality of redundant repair cells; an error correction code logic, which is configured to correct errors in data output from each of the main repair cells and the redundant repair cells; and a testable block, which is configured to detect failure bits of each of the plurality of main repair cells and the plurality of redundant repair cells, and replace at least one main repair cell in which a defect exists with at least one redundant repair cell with reference to the number of failure bits detected and the correction capability of the error correction code logic.

[0010] In some aspects, the present disclosure relates to a semiconductor memory device, which includes: a memory cell array, which includes multiple main repair units and multiple redundant repair units; an error correction code logic, which is configured to perform error detection and correction operations on data stored in the memory cell array; and a testable block, which is configured to replace at least one main repair unit in the multiple main repair units with at least one redundant repair unit in the multiple redundant repair units according to the correction capability of the error correction code logic. At least one of the primary repair units has a fault bit count greater than a fault bit count of the at least one redundant repair unit, and the fault bit of the at least one redundant repair unit can be corrected by the error detection and correction operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features will become apparent by describing in detail exemplary embodiments with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating a configuration of a semiconductor memory device according to an example embodiment;

[0013] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of a schematic structure of a cell array;

[0014] Figure 3 is a circuit diagram illustrating an example codeword unit according to an example embodiment;

[0015] Figure 4A and Figure 4B is a diagram illustrating a repair method according to an example embodiment;

[0016] Figure 5A and Figure 5B is a diagram illustrating another example of a repair method according to an example embodiment;

[0017] Figure 6 is a flowchart illustrating a repair method of a semiconductor memory device according to an example embodiment;

[0018] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 Flow chart of operation S140;

[0019] Figure 8 is a diagram illustrating another example embodiment;

[0020] Fig. 9 is a diagram showing a reference according to an example embodiment Figure 8 A flowchart of a method for accumulating correctable fault bit counts to perform repair operations is shown;

[0021] Fig.10 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an exemplary construction of a testable block;

[0022] Fig.11A and Fig. 11B Is used to describe Fig.10 A diagram of the characteristics of the master unit register;

[0023] Fig. 12A and Fig. 12B is used to describe the Fig.10 A diagram of characteristics of a redundant cell register;

[0024] Fig.13A and Fig. 13B is used to describe the Fig.10 A diagram of another feature of a master unit register;

[0025] Fig.14A and Fig. 14B is used to describe the Fig.10 A diagram of another feature of a redundant cell register;

[0026] Fig.15 is a block diagram showing a structure of a stacked memory chip including a semiconductor memory device according to another example embodiment;

[0027] Fig.16 is a block diagram illustrating a computing system including a semiconductor memory device according to example embodiments. DETAILED DESCRIPTION

[0028] It should be understood that the above overall description and the following detailed description are provided as examples. The reference numerals will be specifically indicated in the disclosed embodiments, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the specification to refer to the same or similar parts.

[0029] Below, synchronous DRAM (SDRAM) can be used as an example of a semiconductor device for describing the features and functions of the inventive concept. However, those skilled in the art can easily understand other advantages and performances of the inventive concept based on the content disclosed herein. The inventive concept can be implemented or applied through other embodiments. In addition, the specific implementation can be changed or modified according to the viewpoint and application without departing from the claims, scope and spirit of the inventive concept and any other purpose.

[0030] Figure 1 is a block diagram showing a configuration of a semiconductor memory device according to an example embodiment. Figure 1 , the semiconductor memory device 100 may include a main cell array 110, a redundant cell array 120, a testable (hereinafter referred to as “design for test” or “DFT”) block 130, a repair logic 140, and an error correction code (ECC) logic 150.

[0031] The main cell array 110 includes a plurality of memory cells connected to word lines and bit lines and arranged in row and column directions. Each of the memory cells may include a cell capacitor and an access transistor. In each memory cell, the gate of the access transistor is connected to one of the word lines WL extending in the row direction. The first end of the access transistor is connected to a bit line (BL) or a complementary bit line (BLB) extending in the column direction. The second end of the access transistor is connected to the cell capacitor.

[0032] The redundant cell array 120 includes a plurality of redundant cells for replacing failed (or defective) cells of the main cell array 110. The configuration and operation of the redundant cells may be the same as those of the main cells. In a test operation, the main cell array 110 and the redundant cell array 120 are tested by the DFT block 130. Failure bit information FBI_M of the main cell array 110 and failure bit information FBI_R of the redundant cell array 120 corresponding to the test results may be provided to the DFT block 130, respectively.

[0033] The DFT block 130 is a block for testing, and the DFT block 130 applies repair based on the function of the ECC logic 150. The DFT block 130 performs a repair operation by using the fault bit information FBI_M of the main cell array 110 and the fault bit information FBI_R of the redundant cell array 120. The DFT block 130 may select a repair unit RU that can maximize the repair efficiency from the main cell array 110 and the redundant cell array 120, respectively. For example, the DFT block 130 may select one repair unit RU in the main cell array 110 in which there is a defect that is uncorrectable by the ECC logic 150 or has a relatively large number of fault bits. The DFT block 130 may select another repair unit RU in the redundant cell array 120 that has no fault bits or has a relatively small number of fault bits. A strategy for selecting a repair unit RU for repair in each of the main cell array 110 and the redundant cell array 120 will be described more fully with reference to the accompanying drawings.

[0034] Based on the determination of the DFT block 130, the repair logic 140 may perform an operation of replacing the repair unit RU of the main cell array 110 in which a defect exists with the repair unit RU of the redundant cell array 120 in which a defect does not exist. For example, the repair logic 140 may replace the address of the selected repair unit RU of the main cell array 110 with the address of the selected repair unit RU of the redundant cell array 120. For example, the repair logic 140 may be implemented with a circuit or a read-only memory (ROM) that replaces an address by using fuse logic (e.g., an electronic fuse or an antifuse).

[0035] The ECC logic 150 performs error correction encoding on the data DQ input to the semiconductor memory device 100. For example, the ECC logic 150 performs error correction encoding on the data DQ input from the external device, and stores the encoding result in the main cell array 110 or the redundant cell array 120 in units of codewords. In addition, the ECC logic 150 performs error correction decoding on the data output from the main cell array 110 or the redundant cell array 120. When there is an error in the read data read out from the main cell array 110 or the redundant cell array 120, the ECC logic 150 may output the read data after correcting the error.

[0036] The DFT block 130 may replace the repair unit RU of the main cell array 110 in which a defect exists with the repair unit RU of the redundant cell array 120 based on the error correction capability of the ECC logic 150. For example, the repair unit RU of the main cell array 110 that cannot be corrected by the ECC logic 150 may be replaced by the repair unit RU of the redundant cell array 120 that does not have a defect or has a defect that can be corrected by the ECC logic 150 through the DFT block 130. For example, since the defective cell is repaired according to the error correction capability of the ECC logic 150, the semiconductor memory device 100 may be provided as a normal device.

[0037] Figure 2 is a diagram showing a method according to a specific example embodiment Figure 1 A block diagram of the schematic structure of a cell array. Figure 2 , the main cell array 110 includes word lines MWL <0> To MWL <3> , the redundant cell array 120 includes a word line RWL. The memory cells of the code word units CWij and CWj are connected to the word line MWL <0> To MWL <3> and RWL. This is described in more detail below.

[0038] The main cell array 110 includes a plurality of word lines MWL connected to the <0> To MWL <3> 1 and 2, respectively. Each of the codeword units CWij is a group of memory cells corresponding to a codeword of an error correction code corresponding to the ECC logic 150. For example, the codeword unit CW00 includes a memory cell connected to the main word line MWL. <0> The bits stored in the memory cells constitute a codeword that detects and corrects errors through the ECC logic 150. In this way, the codeword units CW01 to CW03 can be connected to the main word line MWL <0> Similarly, the codeword units CW1j, CW2j and CW3j are connected to the main word line MWL respectively. <1> , MWL <2> and MWL <3> . Main word line MWL <0> , MWL <1> , MWL <2> and MWL <3> Each of the repair units RU is a repair unit, and a repair operation can be performed for the entire word line. <0> The data in the code word units CW00 to CW03 constitute the data for detecting and correcting the word line MWL <0> A code word of error is stored in the word line MWL connected to <1> The data in the code word units CW10 to CW13 constitute the data for detecting and correcting the word line MWL <1> A code word of error is stored in the word line MWL connected to <2> The data in the code word units CW20 to CW23 constitute the data for detecting and correcting the word line MWL <2> The error code word is stored in the word line MWL. <3> The data in the code word units CW30 to CW33 constitute the data for detecting and correcting the word line MWL <3> The number of erroneous bits or failed bits of the data stored in each of the plurality of codeword units CWij may be detected by the DFT block 130.

[0039] A plurality of codeword cells CW0, CW1, CW2, and CW3 are connected to a redundant word line RWL of the redundant cell array 120. The plurality of codeword cells CWj are also connected to the redundant word line RWL in substantially the same manner as the connection manner of the codeword cells of the main cell array 110. Data stored in each of the plurality of codeword cells CWj connected to the redundant word line RWL constitutes one codeword for detecting and correcting errors by the ECC logic 150. The number of error bits or failed bits of the data stored in each of the plurality of codeword cells CWj may be detected by the DFT block 130.

[0040] The DFT block 130 detects whether the codeword cells CWij of the main cell array 110 and the codeword cells CWj of the redundant cell array 120 are defective for the repair operation. The DFT block 130 may detect the number of failed bits included in each codeword cell through an error detection operation. Alternatively, the DFT block 130 may detect the number of failed bits of each codeword cell through a comparison operation using a replication logic. For example, the DFT block 130 may detect the number of failed (or defective) bits by storing test data in the codeword cell and comparing the data read from the codeword cell with the test data. The DFT block 130 may add the number of failed bits detected from each codeword cell for each word line, and may use the added result as basic data for the repair operation.

[0041] The main cell array 110 and the redundant cell array 120 are constructed as described above. However, it should be understood that a column-replacement method may be used instead of the above-described row-replacement method.

[0042] Figure 3 is a circuit diagram showing a codeword unit according to a specific example embodiment. Figure 3 , connected to the main word line MWL <0> The code word unit CW00 may include a plurality of memory cells and a plurality of bit line sense amplifiers.

[0043] The codeword unit CW00 includes a plurality of memory cells 111, 112, and 113 and bit line sense amplifiers (BLSA) 116, 117, and 118. The memory cell 111 is connected to the bit line BL <0> Connected to the bit line sense amplifier 116. The memory cell 111 may include an access transistor ST and a cell capacitor Cs. The gate of the access transistor ST is connected to the main word line MWL <0> , and the first terminal of the access transistor ST is connected to the bit line BL <0> The cell capacitor Cs of the memory cell 111 is charged with an amount of charge corresponding to the stored data. The bit line sense amplifier 116 can sense the bit line BL <0> The data stored in the memory cell 111 is sensed and restored. Figure 3 Although not shown in the figure, it should be understood that the bit line sense amplifier 116 can be connected to the memory cell in an open bit line structure. The bit line sense amplifier 116 can sense the bit line BL <0> The memory cell 112 and the bit line sense amplifier 117 can transmit the charge shared by the bit line BL in the above manner. <1> The memory cell 113 and the bit line sense amplifier 118 can output the data D1 through the bit line BL in the above manner. <n-1>Similarly, the memory cell 114 and the bit line sense amplifier 119 of the code word unit CW01 can be connected through the bit line BL in the same manner as the memory cell 111 and the bit line sense amplifier 116. <n>Connect, output data Dn.

[0044] In the case where there is no defect in the memory cells 111 to 113 or the bit line sense amplifiers 116 to 118, no error may be detected in the data D0 to Dn-1 read from the code word unit CW00. In this case, the DFT block 130 determines that there is no faulty bit. For example, the DFT block 130 may indicate that the state of the code word unit CW00 is the no-fault bit NFB.

[0045] On the contrary, a defect may exist in the memory cells 111 to 113 or the bit line sense amplifiers 116 to 118 included in the code word unit CW00. In the case of reading data from the memory cells 111 to 113, an error may be included in the data bits D0 to Dn-1. However, when the error (or error bit) of the read data bits D0 to Dn-1 can be corrected by the ECC logic 150, the DFT block 130 marks the state of the code word unit CW00 with the correctable fault bit CFB. The DFT block 130 stores the number of fault bits included in the code word unit CW00. In addition, when the error (or error bit) of the read data bits D0 to Dn-1 cannot be corrected by the ECC logic 150, the DFT block 130 marks the state of the code word unit CW00 with the uncorrectable fault bit UFB.

[0046] The DFT block 130 performs the above-mentioned operation of detecting the number of error bits or failure bits with respect to all codeword cells CWij and CWj of the main cell array 110 and the redundant cell array 120, respectively. The DFT block 130 determines a defect state of each of the codeword cells CWij and CWj, and stores the number of failure bits. Here, the error bits detected by the DFT block 130 are referred to as "failure bits".

[0047] Figure 4A and Figure 4B is a diagram illustrating a repairing method according to example embodiments. Figure 4A 1 is a diagram showing a defect state of each of the main cell array 110 and the redundant cell array 120 detected by the DFT block 130 for each of the codeword cells CWij and CWj. Here, it is assumed that the ECC logic 150 corrects a 1-bit error for each codeword cell and detects only a 2-bit error without correction. For example, when the DFT block 130 detects a 2-bit error, the ECC logic 150 does not correct such an error. In an embodiment, each codeword cell may be set to a non-fault bit NFB state where there is no fault bit, a correctable fault bit CFB state where there is a correctable fault bit (i.e., a 1-bit error), or an uncorrectable fault bit UFB state indicating an uncorrectable fault bit.

[0048] First, in Figure 4A In the example, from top to bottom, the detection is connected to the main word line MWL <0> The failure bit count of the code word unit is "1001". In addition, from top to bottom, the detection is connected to the main word line MWL <1> The failure bit count of the code word unit is "1112"; from top to bottom, the detection is connected to the main word line MWL <2> The failure bit count of the code word unit is "1000"; and from top to bottom, the detection is connected to the main word line MWL <3> The failure bit count of the code word cell connected to the redundant word line RWL is “0111”. From top to bottom, the failure bit count of the code word cell connected to the redundant word line RWL is detected as “0011”. Here, the DFT block 130 detects the code word cell 115a corresponding to the uncorrectable failure bit UFB present in the main cell array 110.

[0049] The number of failed bits can be added together for each word line. <0> The number of accumulated correctable failure bits CCFB in the code word unit is "2". In addition, the main word line MWL <1> The number of accumulated correctable failure bits CCFB in the code word unit is "3". Similarly, the number of correctable failure bits CCFB in the code word unit is "3". <2> The number of accumulated correctable fault bits CCFB in the code word unit is "1", including the main word line MWL <3> The number of cumulative correctable fail bits CCFB in the code word unit of the main cell array 110 is "3", and the number of cumulative correctable fail bits CCFB included in the code word unit of the redundant word line RWL is "2". According to the above description, the total number of cumulative correctable fail bits obtained by adding the number of cumulative correctable fail bits CCFB of the main cell array 110 may be "9".

[0050] Figure 4B is a diagram illustrating a repair method according to an example embodiment. Figure 4B , the main word line MWL having an uncorrectable defect or having the most or maximum accumulated count of correctable fault bits CCFB can be replaced by a redundant word line RWL <0> To MWL <3> Any one of .

[0051] For example, the DFT block 130 may select the main word line MWL <0> To MWL <3> A word line with an uncorrectable defect or a correctable fault bit CCFB with the most (or maximum) cumulative count. Figure 4B In the example shown, the main word line MWL <1> The codeword unit 115a ( Figure 4A The main word line MWL cannot be repaired by the error correction operation of the ECC logic 150. <1> Therefore, the main word line MWL can be replaced by only the redundant word line RWL. <1> to repair defects of the main cell array 110. Through the repair operation, the total number of accumulated fail bits obtained by adding the number of accumulated correctable fail bits CCFB of the main cell array 110 may be "8".

[0052] Figure 5A and Figure 5B is a diagram illustrating another example of a repairing method according to example embodiments. Figure 5A is a diagram showing a defect state of each of the codeword cells CWij and CWj of each of the main cell array 110 and the redundant cell array 120 detected by the DFT block 130. Here, it is assumed that the error detection and correction capability of the ECC logic 150 is the same as that of the reference Figure 4A Same as described.

[0053] exist Figure 5A In the example, from top to bottom, the detection is connected to the main word line MWL <0> The failure bit count of the code word unit is "1001"; from top to bottom, the detection is connected to the main word line MWL <1> The failure bit count of the code word unit is "1111"; from top to bottom, the detection is connected to the main word line MWL <2> The failure bit count of the code word unit is "1000"; and from top to bottom, the detection is connected to the main word line MWL <3> The failure bit count of the code word cell connected to the redundant word line RWL is "0111". In addition, from top to bottom, the failure bit count of the code word cell connected to the redundant word line RWL is detected to be "0011". Figure 4A Different, in Figure 5A In the case of main word line MWL <1> There may be no codeword unit having an error (i.e., a failed bit) that cannot be corrected by the ECC logic 150. For example, the ECC logic 150 may correct Figure 5A The reason is that code word unit 115b includes only 1 bit error.

[0054] For each word line, the number of failed bits of the code word cells can be added together. Figure 5A As shown, including the main word line MWL <0> The number of accumulated correctable failure bits CCFB in the code word unit is "2". <1> The number of accumulated correctable failure bits CCFB in the code word unit is "4". Similarly, the number of correctable failure bits CCFB in the code word unit is "4". <2> The number of accumulated correctable fault bits CCFB in the code word unit is "1", including the main word line MWL <3> The number of accumulated correctable fail bits CCFB in the code word unit of the main cell array 110 is "3", and the number of accumulated correctable fail bits CCFB in the code word unit included in the redundant word line RWL is "2". According to the above description, the total number of accumulated fail bits obtained by adding the number of accumulated correctable fail bits CCFB of the main cell array 110 may be "10".

[0055] Figure 5B It is shown in Figure 5A FIG. 1 is a diagram of a repair method according to an exemplary embodiment under an error condition shown in FIG. Figure 5B , the redundant word line RWL can be used to replace the main word line MWL <0> To MWL <3> Any one of the correctable fault bits CCFB with the most or maximum cumulative count.

[0056] For example, the DFT block 130 may be configured to receive the main word line MWL <0> To MWL <3> Any word line having the most (or maximum) count of accumulated correctable fault bits CCFB is selected. Figure 5B In the example shown, the main word line MWL <1> The cumulative correctable fault bit CCFB with the largest count is “4”. Therefore, the main word line MWL can be repaired by the ECC logic 150. <1> However, since the cumulative number of failed bits of the redundant word line RWL is "2", if the redundant word line RWL is used to repair the main word line MWL <1> , it can provide higher reliability with respect to the progressive defects that may appear later. Therefore, if the main word line MWL is replaced by the redundant word line RWL <1> , then the defect of the main cell array 110 can be repaired, and thus, the total number of failed bits corresponding to the sum of the counts of the cumulative correctable fail bits CCFB of the main cell array 110 can be “8”.

[0057] Figure 6 is a flowchart illustrating a repair method of a semiconductor memory device according to an example embodiment. Figure 6 Even if an error that cannot be corrected using the error correction code occurs, the error can be corrected by using the correctable repair unit RRU of the redundant unit array 120.

[0058] In operation S110, the DFT block 130 detects a failure bit of the main cell array 110 and the redundant cell array 120. For example, the DFT block 130 may write error correction coded data in the main cell array 110 and the redundant cell array 120, and may perform an error detection operation on the read data to detect whether there is a failure bit and the number of the failure bits. Alternatively, the DFT block 130 may detect the number of failure bits for each codeword unit in a manner of writing data in the main cell array 110 and the redundant cell array 120 and comparing the read data with the write data.

[0059] In operation S120, the DFT block 130 may determine the fault bit state of each codeword unit based on the number of detected fault bits: no fault bit NFB, correctable fault bit CFB, or uncorrectable fault bit UFB. For example, the DFT block 130 may determine the fault bit state NFB, CFB, or UFB of each codeword unit according to the error detection and correction capability of the ECC logic 150. It is assumed that the ECC logic 150 can correct a 1-bit error included in the codeword, and can only detect errors of two or more bits. Based on this assumption, the DFT block 130 may determine a codeword unit including a 1-bit error as a correctable fault bit CFB error, and may determine a codeword unit including two or more bit errors as an uncorrectable fault bit UFB error.

[0060] In operation S130, the DFT block 130 calculates the number of cumulative correctable fault bits CCFB for each repair unit RU of the main cell array 110 and the redundant cell array 120 based on the number of detected fault bits and the fault bit state NFB, CFB, or UFB of each codeword unit. For example, the DFT block 130 calculates the main word line MWL <0> To MWL <3> and the number of cumulative correctable fault bits CCFB for each of the redundant word lines RWL. In this case, the DFT block 130 may also calculate the number of cumulative correctable fault bits CCFB with respect to the repair unit including the uncorrectable fault bit UFB error. The fault bit state of the repair unit including the uncorrectable fault bit UFB error may be designated as the uncorrectable fault bit UFB state. Alternatively, in any embodiment, only the number of correctable fault bits may be included in the number of cumulative correctable fault bits CCFB.

[0061] In operation S140, the DFT block 130 performs a repair operation with reference to the number of accumulated correctable fault bits CCFB of each main repair unit MRU included in the main cell array 110 and each redundant repair unit RRU in the redundant cell array 120. First, the DFT block 130 determines whether the redundant repair unit RRU of the redundant cell array 120 can be corrected by the ECC logic 150. According to an example embodiment, in a case where the redundant repair unit RRU of the redundant cell array 120 is not correctable by the ECC logic 150, it is not necessary to apply a repair strategy. However, in a case where the redundant repair unit RRU of the redundant cell array 120 is correctable by the ECC logic 150, the uncorrectable main repair unit MRU of the main cell array 110 or the correctable main repair unit MRU of the main cell array 110 having the largest accumulated count of correctable fault bits CCFB may be repaired. Figure 7 A method of performing a repair operation based on the number of accumulated correctable fail bits CCFB is described in detail.

[0062] Figure 7 It is shown Figure 6 Flow chart of operation S140. Figure 7 , the DFT block 130 may repair the main repair unit MRU of the main cell array 110 based on the number of accumulated correctable fault bits CCFB for each main repair unit MRU. Figure 7 The repair process using one repair cell of the redundant cell array 120 will be described. Figure 8 A method of performing a repair operation using the redundant unit array 120 including at least two or more redundant repair units RRU is described.

[0063] In operation S141, the DFT block 130 checks whether the redundant repair unit RRU of the redundant unit array 120 includes a correctable fault bit CFB or a non-fault bit NFB. For example, the DFT block 130 may determine whether an uncorrectable fault bit UFB error that cannot be corrected by the ECC logic 150 is included in the redundant repair unit RRU. In the case where the fault bit state of the redundant repair unit RRU indicates a correctable fault bit CFB state or a non-fault bit NFB state (S141, yes), the process proceeds to operation S142. On the contrary, in the case where the fault bit state of the redundant repair unit RRU indicates an uncorrectable fault bit UFB state (S141, no), the method of performing repair by using the redundant repair unit RRU ends.

[0064] In operation S142, the DFT block 130 checks the failure bit state of the master repair unit MRU of the master cell array 110. In the case where the master repair unit MRU of the master cell array 110 does not include a failure bit (S142, No), the method ends because no repair operation needs to be performed. In the case where the master repair unit MRU includes at least one failure bit (S142, Yes), the process proceeds to operation S143.

[0065] In operation S143, the DFT block 130 selects any one of the main repair units MRU including the fault bit. Specifically, the DFT block 130 may preferably select the main repair unit MRU having the uncorrectable fault bit UFB state. In the case where the main repair unit MRU does not have the uncorrectable fault bit UFB state, the DFT block 130 may select the main repair unit MRU having the largest count of cumulative correctable fault bits CCFB. In the case where the main repair unit MRU selected by the DFT block 130 is correctable by the ECC logic 150 (S143, Yes), the process proceeds to operation S144. On the contrary, in the case where the main repair unit MRU selected by the DFT block 130 is not correctable by the ECC logic 150 (S143, No), the process proceeds to operation S145.

[0066] In operation S144, the DFT block 130 compares the cumulative correctable fault bit count CCFB_M of the selected main repair unit MRU with the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU. In the case where the cumulative correctable fault bit count CCFB_M of the selected main repair unit MRU is not greater than the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU (S144, No), the repair method ends. In the case where the cumulative correctable fault bit count CCFB_M of the selected main repair unit MRU is greater than the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU (S144, Yes), the process proceeds to operation S145.

[0067] In operation S145, the DFT block 130 repairs the selected main repair unit MRU with the redundant repair unit RRU. For example, the DFT block 130 may set the repair logic 140 (or program its fuses) so that the address of the main repair unit MRU is changed to point to the redundant repair unit RRU.

[0068] The method of repairing the main repair unit MRU of the main cell array 110 using one redundant repair unit RRU of the redundant cell array 120 is briefly described above. According to the exemplary embodiment, even if there is a defect in the redundant repair unit RRU, the redundant repair unit RRU can be used to repair the main repair unit MRU of the main cell array 110. In addition, even if there is a main repair unit MRU that cannot be repaired by the ECC logic 150 among the main repair units MRU, the main repair unit MRU can be repaired using the redundant repair unit RRU.

[0069] Figure 8 is a diagram showing another example embodiment. Figure 8 , a strategy may be provided to perform a repair operation based on the count of the accumulated correctable fault bits CCFB when the redundant unit array 120 includes a plurality of redundant repair units RRU.

[0070] Assume that the master unit array 110 includes eight master repair units MRU <0> To MRU <7> A master repair unit MRU having an uncorrectable fault bit UFB error that cannot be corrected by the ECC logic 150 may be included in the master cell array 110. <0> In addition, master repair units MRU each having a correctable fault bit CFB error that can be corrected by the ECC logic 150 may be included in the master unit array 110. <1> To MRU <6> and a master repair unit MRU with no fault bit (e.g., CCFB=0) <7> . Master Repair Unit MRU <1> To MRU <7> The cumulative correctable fault bit CCFB count may have Figure 8 The values ​​shown.

[0071] In addition, it is assumed that the redundant unit array 120 includes four redundant repair units RRU <0> to RRU <3> The redundant cell array 120 may include a redundant repair unit RRU having an uncorrectable fault bit UFB error that cannot be corrected by the ECC logic 150. <2> The redundant cell array 120 may include redundant repair units RRU each having a correctable fault bit CFB error that can be corrected by the ECC logic 150. <1> and RRU <3> and a redundant repair unit RRU without a fault bit (e.g., CCFB=0) <0> Assume that the redundant repair unit RRU <0> to RRU <3> The cumulative correctable fault bit CCFB count has Figure 8 The values ​​shown.

[0072] Based on the failure bit status of the main cell array 110 and the redundant cell array 120, the main repair unit MRU is preferentially selected. <0> To MRU <7> Master repair unit MRU with uncorrectable fault bit UFB status <0> Used for repair. From the Redundant Repair Unit RRU <0> to RRU <3> Select a redundant repair unit RRU with a no-fault bit NFB state (e.g., CCFB=0) <0> . Use the selected redundant repair unit RRU <0> Alternative Master Repair Unit (MRU) <0> The process is marked by an identification number ① indicating the repair priority. <0> To MRU <7> If there is also a main repair unit MRU with an uncorrectable fault bit UFB state in the system, the redundant repair unit RRU can be used <1> Repair the main repair unit MRU with the uncorrectable fault bit UFB state. Except for the redundant repair unit RRU used for repair <0> In addition, the redundant repair unit RRU <1> Can be a redundant repair unit RRU <0> to RRU <3> The redundant repair unit RRU with the minimum count of cumulative correctable fault bits CCFB.

[0073] Repairing the Master Repair Unit (MRU) <0> After that, any one of the remaining master repair units MRU can be selected to perform the next repair operation. Specifically, the master repair unit MRU is selected. <1> To MRU <7> Any one of the master repair units MRU with the largest cumulative correctable fault bit CCFB count. For example, the master repair unit MRU with the cumulative correctable fault bit CCFB count of "50" is selected. <6> . From the redundant repair unit RRU <1> and RRU <3> The redundant repair unit RRU with the minimum count of cumulative correctable fault bits CCFB is selected from <1> . Use the selected redundant repair unit RRU <1> Alternative Master Repair Unit (MRU) <6> The process is marked by an identification number ② indicating the repair priority.

[0074] Repairing the Master Repair Unit (MRU) <6> After that, select the Master Repair Unit (MRU). <1> To MRU <5> and MRU <7> Any one of them can be selected to perform the next repair operation. The remaining master repair units MRU can be selected <1> To MRU <5> and MRU <7> For example, the master repair unit MRU with the cumulative correctable fault bit CCFB count of "40" is selected. <3> . From the redundant repair unit RRU <2> and RRU <3> The redundant repair unit RRU with the minimum count of cumulative correctable fault bits CCFB is selected from <3> However, the selected master repair unit MRU <3> The cumulative correctable fault bits CCFB count and the selected redundant repair unit RRU <3> The counts of the cumulative correctable fault bits CCFB are the same as each other, that is, "40". Therefore, even if the repair operation is performed, there is no benefit. In this case, the DFT block 130 may terminate the repair operation. This process is marked by an identification number ③ indicating the repair order.

[0075] Fig. 9 It shows that Figure 8 The flowchart of the method of accumulating the correctable fault bit count to perform the repair operation is shown. Fig. 9 A repair process using a count of accumulated correctable fault bits CCFB in a case where a plurality of redundant repair units RRU are included is described.

[0076] In operation S210, the DFT block 130 detects a failure bit of the main cell array 110 and the redundant cell array 120. For example, the DFT block 130 may write error correction coded data into the main cell array 110 and the redundant cell array 120, and may perform error detection and decoding operations on the read data to detect whether there is a failure bit and the number of the failure bits. Alternatively, the DFT block 130 may detect the number of failure bits in a manner of writing data into the main cell array 110 and the redundant cell array 120 and comparing the read data with the written data for each codeword unit.

[0077] In operation S220, the DFT block 130 checks a failed bit state of the main cell array 110. For example, the DFT block 130 may select any one of the main repair units MRU including a failed bit error that is uncorrectable by the ECC logic 150.

[0078] In operation S222, the DFT block 130 selects a redundant repair unit RRU that can be used to replace the selected main repair unit MRU. In this case, the DFT block 130 may select any one of the redundant repair units RRU that has no fault bit or has a minimum count of cumulative correctable fault bits CCFB.

[0079] In operation S224, the DFT block 130 may determine whether there is a redundant repair unit RRU having a no-fault bit NFB state or a correctable fault bit CFB state. In the case where there is no redundant repair unit RRU having a no-fault bit NFB state or a correctable fault bit CFB state (S224, No), the method ends. On the contrary, in the case where there is a redundant repair unit RRU having a no-fault bit NFB state or a correctable fault bit CFB state (S224, Yes), the process proceeds to operation S226.

[0080] In operation S226, the primary repair unit MRU selected in operation S220 is replaced with the redundant repair unit RRU selected in operation S222. For example, by performing a fuse programming operation on the repair logic 140, the selected primary repair unit MRU may be replaced with the selected redundant repair unit RRU.

[0081] In operation S228, the DFT block 130 checks whether there is a master repair unit MRU with an uncorrectable fault bit UFB state in the main cell array 110. In the case where there is still a master repair unit MRU with an uncorrectable fault bit UFB state in the main cell array 110 (S228, Yes), the process proceeds to operation S220. On the contrary, in the case where there is no longer a master repair unit MRU with an uncorrectable fault bit UFB state in the main cell array 110 (S228, No), the process proceeds to operation S230.

[0082] In operation S230, the DFT block 130 may select any one of the main repair units MRU having the largest count of accumulated correctable fault bits CCFB.

[0083] In operation S232, the DFT block 130 may select a redundant repair unit RRU having a no-fault bit NFB state among the redundant repair units RRU. However, in the case where there is no redundant repair unit RRU having a no-fault bit NFB state, a redundant repair unit RRU having a minimum count of accumulated correctable fault bits CCFB may be selected.

[0084] In operation S234, the DFT block 130 compares the cumulative correctable fault bit count CCFB_M of the main repair unit MRU selected in operation S230 with the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU selected in operation S232. In the case where the cumulative correctable fault bit count CCFB_M of the main repair unit MRU is not greater than the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU (S234, No), the method ends. In the case where the cumulative correctable fault bit count CCFB_M of the selected main repair unit MRU is greater than the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU (S234, Yes), the process proceeds to operation S236.

[0085] In operation S236, the DFT block 130 repairs the main repair unit MRU selected in operation S230 with the redundant repair unit RRU selected in operation S232. Then, the process proceeds to operation S230 to select a new main repair unit MRU.

[0086] The above describes the repair process in the case of multiple redundant repair units RRU. For example, the main repair unit MRU with the uncorrectable fault bit UFB state or the most counted cumulative correctable fault bits CCFB is preferentially selected to perform the repair operation using the error correction code. On the contrary, the redundant repair unit RRU with the no fault bit NFB state or a small number of fault bits has priority in selecting the redundant repair unit RRU and can be selected before other redundant repair units RRU with a larger number of fault bits.

[0087] Fig.10 It is shown Figure 1 A block diagram of an exemplary configuration of the DFT block 130 is shown in FIG. Fig.10 , the DFT block 130 includes an ECC circuit 131 , a main cell register 133 , a redundant cell register 135 , and a repair controller 137 .

[0088] The ECC circuit 131 may detect the fault bit state CFB, UFB, or NFB and the count of the cumulative correctable fault bit CCFB of each main repair unit RU from the test data RD_Main read from the main cell array 110. The detected fault bit state CFB, UFB, or NFB and the count of the cumulative correctable fault bit CCFB of each main repair unit RU are provided to the main cell register 133. In addition, the ECC circuit 131 may detect the fault bit state CFB, UFB, or NBF and the count of the cumulative correctable fault bit CCFB of each redundant repair unit from the test data RD_Redundant read from the redundant cell array 120. The detected fault bit state CFB, UFB, or NBF and the count of the cumulative correctable fault bit CCFB of each redundant repair unit RU are provided to the redundant cell register 135.

[0089] The main unit register 133 stores the fault bit state CFB, UFB or NBF received from the ECC circuit 131 and the count of the cumulative correctable fault bit CCFB of each main repair unit MRU. The main unit register 133 may also store the address ADDR of the main repair unit MRU provided from the address decoder (not shown). For example, the main unit register 133 may include a content addressable memory (CAM) storing the address ADDR of the main repair unit MRU and a counter that may store and update the count of the cumulative correctable fault bit CCFB of the relevant address.

[0090] The redundant unit register 135 stores the fault bit state CFB, UFB or NBF received from the ECC circuit 131 and the count of the cumulative correctable fault bit CCFB of each redundant repair unit RRU. The redundant unit register 135 may also store the address ADDR of the redundant repair unit RRU provided from the address decoder (not shown). For example, the redundant unit register 135 may include a content addressable memory (CAM) that may store the address ADDR of the redundant repair unit RRU and a counter that may store and update the count of the cumulative correctable fault bit CCFB of the relevant address.

[0091] The repair controller 137 may perform a repair operation using data stored in the main unit register 133 and the redundant unit register 135. The repair controller 137 determines whether to perform a repair operation based on a comparison result of the count of the cumulative correctable fault bits CCFB of each repair unit MRU stored in the main unit register 133 and the count of the cumulative correctable fault bits CCFB of each repair unit RRU stored in the redundant unit register 135. In the case where it is determined that the repair operation needs to be performed, the repair controller 137 may convert the address stored in the CAM of the main unit register 133 into the address stored in the CAM of the redundant unit register 135 by mapping. In this way, the repair controller 137 may include a comparator 132 and an address converter 134. The address converted for repair may be used in a programming operation of the repair logic 140.

[0092] Fig.11A and Fig. 11B Is used to describe Fig.10 Figure 2 shows the characteristics of the master unit register. Fig.11A is a table showing an exemplary configuration of the main unit register 133a. Fig.11A The master unit register 133a may include a register corresponding to a CAM storing an address of a master repair unit MRU, a register storing a count of accumulated correctable fault bits CCFB, and a register storing a fault bit status (CFB, UFB, NFB) of each master repair unit MRU. For example, Figure 8 The main cell register 133a of the main cell array 110 may include 8 register groups.

[0093] Master Repair Unit MRU including Uncorrectable Fault Bit UFB Error <0> The address ADDR, the count (=200) of the accumulated correctable fault bits CCFB_M corresponding to the address ADDR and the fault bit status can constitute a register group. <1> To MRU <7> The associated register set can be configured to communicate with the Master Repair Unit (MRU). <0> The relevant register groups are the same.

[0094] Fig. 11B It is shown Fig.11A Flow chart of the updating method of the main unit register 133a. Fig. 11B , when the number of register groups is sufficient, all information of the master repair unit MRU can be stored in the master unit register 133a.

[0095] In operation S311, any one of the master repair units MRU is selected. For example, the master repair unit MRU may be selected according to the order of the address ADDR (eg, lowest to highest, highest to lowest, etc.).

[0096] In operation S313, the test data stored in the selected main repair unit MRU may be read. For example, a plurality of codewords stored in the main repair unit MRU may be read, and the read codewords may be provided to the ECC circuit 131. The ECC circuit 131 detects an error bit included in each of the provided plurality of codewords.

[0097] In operation S315, the ECC circuit 131 determines the failure bit state CFB / UFB / NFB of the selected main repair unit MRU with reference to the number of error bits detected for each codeword. In the case where an error bit is detected, the ECC circuit 131 may count the number of correctable error bits included in each codeword, and may calculate a count of cumulative correctable failure bits CCFB.

[0098] In operation S317, the address ADDR, the fail bit status CFB / UFB / NFB, and the count of the accumulated correctable fail bits CCFB of the selected master repair unit MRU may be stored in a corresponding register group of the selected repair unit.

[0099] In operation S319, it is determined whether the currently selected repair unit MRU is the last repair unit of the main repair unit MRU. For example, the main unit array 110 is checked to determine whether the main repair unit MRU for which the count of the detected fault bit status CFB / UFB / NFB and the accumulated correctable fault bit CCFB is targeted exists. In the case where the currently selected main repair unit MRU is the last repair unit of the main repair unit (S319, yes), the update operation of the main unit register 133a is terminated. On the contrary, in the case where the currently selected main repair unit MRU is not the last repair unit of the main repair unit (S319, no), the process proceeds to operation S131, where a new main repair unit MRU can be selected.

[0100] Fig. 12A and Fig. 12B Is used to describe Fig.10 Figure 2 shows the characteristics of a redundant cell register. Fig. 12A is a table showing an exemplary configuration of the redundant unit register 135a. Fig. 12A The redundant unit register 135a may include a register corresponding to a CAM storing an address of a redundant repair unit RRU, a register storing a count of accumulated correctable fault bits CCFB, and a register storing a fault bit status (CFB, UFB, NFB) for each redundant repair unit RRU. For example, Figure 8 The redundant cell register 135a of the redundant cell array 120 may be composed of four register groups.

[0101] Redundant repair unit RRU including uncorrectable fault bit UFB error <2> The address ADDR, the cumulative correctable fault bit count CCFB_M (=150) corresponding to the address ADDR and the fault bit status can constitute a register group. <0> , RRU <1> and RRU <3> The associated register set can be configured to be associated with a redundant repair unit RRU <2> The associated register set is the same.

[0102] Fig. 12B It is shown Fig. 12A Flow chart of a method for updating the redundant unit register 135a. Fig. 12B , when the number of register groups is sufficient, all information of the redundant repair unit RRU can be stored in the redundant unit register 135a.

[0103] In operation S321, any one of the redundant repair units RRU is selected. For example, the redundant repair unit RRU may be selected according to the order of the address ADDR (eg, lowest to highest, highest to lowest, etc.).

[0104] In operation S323, the test data stored in the selected redundant repair unit RRU may be read. For example, a plurality of codewords stored in the redundant repair unit RRU may be read, and the read codewords may be provided to the ECC circuit 131. The ECC circuit 131 detects an error bit included in each of the provided plurality of codewords.

[0105] In operation S325, the ECC circuit 131 determines the fault bit (FB) state CFB / UFB / NFB of the selected redundant repair unit RRU for the number of error bits detected from each codeword. In the case where an error bit is detected, the ECC circuit 131 may count the number of correctable error bits included in each codeword, and may calculate a count of cumulative correctable fault bits CCFB.

[0106] In operation S327, the address ADDR, the fault bit (FB) status CFB / UFB / NFB, and the count of the accumulated correctable fault bits CCFB of the selected repair unit RRU may be stored in a corresponding register group of the redundant unit register 135a.

[0107] In operation S329, it is determined whether the currently selected repair unit RRU is the last repair unit of the redundant repair unit RRU. For example, the redundant unit array 120 is checked to determine whether the redundant repair unit RRU for which the fault bit state CFB / UFB / NFB and the count of the accumulated correctable fault bit CCFB are detected exists. In the case where the currently selected redundant repair unit RRU is the last repair unit of the redundant repair unit RRU (S329, yes), the update operation of the redundant unit register 135a is terminated. On the contrary, in the case where the currently selected redundant repair unit RRU is not the last repair unit of the redundant repair unit RRU (S329, no), the process proceeds to operation S321, where a new redundant repair unit RRU can be selected.

[0108] Reference Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B A method of setting the register set of the main unit register 133 and the redundant unit register 135 is briefly described.

[0109] Fig.13A and Fig. 13B Is used to describe Fig.10 FIG. 5 is a diagram of another feature of the master unit register. Fig.13A is a table showing the configuration of the main unit register 133b according to another embodiment. Fig.13A , the master unit register 133b may include a register corresponding to a CAM storing an address of a master repair unit MRU, a register storing a count of accumulated correctable fault bits CCFB, and a register storing a fault bit state (CFB, UFB, NFB) of each master repair unit MRU. However, Fig.13A A case where the number of register sets included in the main unit register 133b is insufficient compared with the number of main repair units MRU is shown.

[0110] For example, Figure 8 The number of master repair unit MRUs shown is 8, but 4 register groups may be included in the master unit register 133b. In this case, the master repair unit MRU with the uncorrectable fault bit UFB state may be first stored in the master unit register 133b. The master repair unit MRU with the largest cumulative correctable fault bit count CCFB_M may be stored in the master unit register 133b with the next priority.

[0111] In an embodiment, a master repair unit MRU with an uncorrectable fault bit UFB state <0> The address ADDR, the cumulative correctable fault bit count CCFB_M (=200) corresponding to the address ADDR, and the fault bit status are stored in one register group. In the case of the remaining master repair units MRU, the cumulative correctable fault bit count CCFB_M is stored in the master unit register 133b in descending order from the maximum value to the minimum value together with the corresponding address. For example, the cumulative correctable fault bit count CCFB_M may be stored in the master unit register 133b in the following order together with the corresponding address: The master repair unit MRU with the cumulative correctable fault bit count CCFB_M of "50" <6> , the master repair unit MRU with the cumulative correctable fault bit count CCFB_M being "40" <3> and the master repair unit MRU with the cumulative correctable fault bit count CCFB_M being "30" <1> .

[0112] Fig. 13B It is shown Fig.13A Flow chart of the updating method of the main unit register 133b. Fig. 13B In the case where the number of register groups set in the main unit register 133b is insufficient, the priority of the repair unit to be allocated to the register group of the main unit register 133b may be determined according to the value of the cumulative correctable fault bit count CCFB_M.

[0113] In operation S331, any one of the master repair units MRU is selected. For example, the master repair unit MRU may be selected according to the order of the address ADDR.

[0114] In operation S333, the test data stored in the selected main repair unit MRU may be read. For example, a plurality of codewords stored in the main repair unit MRU may be read, and the read codewords may be provided to the ECC circuit 131. The ECC circuit 131 detects an error bit included in each of the provided plurality of codewords.

[0115] In operation S335, the ECC circuit 131 determines a failure bit (FB) state CFB / UFB / NFB of the selected master repair unit MRU with respect to the number of error bits detected from each codeword. In the case where an error bit is detected, the ECC circuit 131 may count the number of correctable error bits included in each codeword, and may calculate a count of cumulative correctable error bits CCFB.

[0116] In operation S336, the repair controller 137 compares the cumulative correctable fault bit count CCFB_M of the selected master repair unit MRU with the minimum cumulative correctable fault bit count Min CCFB_M of the cumulative correctable fault bit count CCFB_M of the master repair unit MRU currently stored in the master unit register 133b. In the case that the cumulative correctable fault bit count CCFB_M of the selected master repair unit MRU is not greater than the minimum cumulative correctable fault bit count Min CCFB_M (S336, No), the process proceeds to operation S331. On the contrary, in the case that the cumulative correctable fault bit count CCFB_M of the selected master repair unit MRU is greater than the minimum cumulative correctable fault bit count Min CCFB_M (S336, Yes), the process proceeds to operation S337.

[0117] In operation S337, the repair controller 137 overwrites the information of the master repair unit MRU selected in operation S331 in the register group of the master unit register 133b having the minimum cumulative correctable fault bit count Min CCFB_M. For example, the address ADDR, the cumulative correctable fault bit count CCFB_M, and the fault bit (FB) status CFB / UFB / NFB of the selected master repair unit MRU are written in the register group having the minimum cumulative correctable fault bit count Min CCFB_M.

[0118] In operation S338, it is determined whether the currently selected main repair unit MRU is the last repair unit of the main repair unit MRU. For example, the main unit array 110 is checked to determine whether there is a main repair unit MRU for which the count of the detected fault bit state CFB / UFB / NFB and the accumulated correctable fault bit CCFB is targeted. In the case where the currently selected main repair unit MRU is the last repair unit of the main repair unit MRU (S338, yes), the update operation of the main unit register 133b is terminated. On the contrary, in the case where the currently selected main repair unit MRU is not the last repair unit of the main repair unit MRU (S338, no), the process proceeds to operation S331, where a new main repair unit MRU can be selected.

[0119] Fig.14A and Fig. 14B Is used to describe Fig.10 FIG. 4 is a diagram of another feature of a redundant cell register. Fig.14A is shown with Fig. 12A The redundant unit register 135a has a structured table of redundant unit registers 135b having different characteristics. Fig.14A The redundant unit register 135b may include a register corresponding to a CAM storing an address of a redundant repair unit RRU, a register storing a count of cumulative correctable fault bits CCFB, and a register storing a fault bit status (CFB, UFB, NFB) for each redundant repair unit RRU. The number of register groups of the redundant unit register 135b may be less than Fig. 12A The number of register groups of the redundant unit register 135a.

[0120] Since the number of register sets is limited, the information of the redundant repair unit RRU to be stored in the redundant unit register 135b is also limited. Figure 8 There are four redundant repair units RRU in the redundant unit array 120. However, only information of two redundant repair units RRU among the four redundant repair units RRU may be stored in the redundant unit register 135b. Under this condition, information of the redundant repair unit RRU having the no-fault bit NFB state is preferably stored in the redundant unit register 135b. In the absence of a redundant repair unit RRU having the no-fault bit NFB state, a redundant repair unit RRU having a relatively small cumulative correctable fault bit count CCFB_R may be stored in the redundant unit register 135b with a high priority.

[0121] According to the strategy for setting the redundant unit register 135b, the repair unit RRU with the no-fault bit NFB state is firstly <0> The information of is stored in the redundant unit register 135b. Then, the repair unit RRU including the fault bit but having the minimum cumulative correctable fault bit count CCFB_R (=20) may be <1> The information is stored in the redundant cell register 135b.

[0122] Fig. 14B It is shown Fig.14A Flow chart of the updating method of the redundant unit register 135b. Fig. 14B In the case where the number of register groups is insufficient, only the information of the redundant repair unit RRU with the highest priority may be stored in the redundant unit register 135b.

[0123] In operation S341, any one of the redundant repair units RRU is selected. For example, the redundant repair unit RRU may be selected according to the order of the address ADDR.

[0124] In operation S343, the test data stored in the selected redundant repair unit RRU may be read. For example, a plurality of codewords stored in the redundant repair unit RRU may be read, and the read codewords may be provided to the ECC circuit 131. The ECC circuit 131 detects an error bit included in each of the provided plurality of codewords.

[0125] In operation S345, when an error bit is detected, the ECC circuit 131 determines the fault bit (FB) state CFB / UFB / NFB of the selected redundant repair unit RRU relative to the number of error bits detected from each codeword, and the ECC circuit 131 can count the number of correctable error bits included in each codeword, and can calculate the cumulative count of correctable fault bits CCFB.

[0126] In operation S346, the repair controller 137 compares the cumulative correctable fault bit count CCFB_R of the selected redundant repair unit RRU with the maximum cumulative correctable fault bit count Max CCFB_R of the cumulative correctable fault bit count CCFB_R of the redundant repair unit RRU currently stored in the redundant unit register 135b. In the case where the cumulative correctable fault bit count CCFB_R of the selected redundant repair unit RRU is not less than the maximum cumulative correctable fault bit count Max CCFB_R (No), the process proceeds to operation S341. On the contrary, in the case where the cumulative correctable fault bit count CCFB_R of the selected redundant repair unit RRU is less than the maximum cumulative correctable fault bit count Max CCFB_R (Yes), the process proceeds to operation S347.

[0127] In operation S347, the repair controller 137 overwrites the information of the redundant repair unit RRU selected in operation S341 in the register group of the redundant unit register 135b having the maximum cumulative correctable fault bit count Max CCFB_R. For example, the address ADDR, the cumulative correctable fault bit count CCFB_R, and the fault bit (FB) state CFB / UFB / NFB of the selected redundant repair unit RRU are written in the register group having the maximum cumulative correctable fault bit count Max CCFB_R.

[0128] In operation S348, it is determined whether the currently selected redundant repair unit RRU is the last repair unit of the redundant repair unit RRU. For example, it is checked whether there is no redundant repair unit RRU for which the fault bit state CFB / UFB / NFB and the cumulative correctable fault bit count CCFB_R are detected in the redundant unit array 120. In the case where the currently selected redundant repair unit RRU is the last repair unit of the redundant repair unit RRU (S348, yes), the update operation of the redundant repair unit RRU is terminated. On the contrary, in the case where the currently selected redundant repair unit RRU is not the last repair unit of the redundant repair unit RRU (S348, no), the process proceeds to operation S341, where a new redundant repair unit RRU can be selected.

[0129] Reference Fig.13A , Fig. 13B , Fig.14A and Fig. 14B A method of efficiently performing a repair operation when the number of register groups included in the main unit register 133 and the redundant unit register 135 is insufficient is briefly described.

[0130] Fig.15 is a block diagram showing a structure of a memory chip including a stack of DRAMs according to example embodiments. Fig.15 , the stacked memory chip 1000 may include a printed circuit board (PCB) 1100 , a through silicon via (TSV) insertion layer 1150 , a host wafer 1200 , and a high bandwidth memory (HBM) 1300 .

[0131] The stacked memory chip 1000 connects the HBM 1300 with the host wafer 1200 using the TSV interposer 1150. The TSV interposer 1150 is disposed on the PCB 1100 and is electrically connected to the PCB 1100 through the flip chip bumps FB.

[0132] The host wafer 1200 and the DRAM wafers 1310 to 1340 constituting the HBM 1300 are arranged on the TSV insertion layer 1150. In order to implement the structure of the HBM 1300, TSV lines are formed in the plurality of DRAM wafers 1310 to 1340. The TSV lines of each of the DRAM wafers 1310 to 1340 may electrically connect the TSV lines to other DRAM wafers 1310 to 1340 having micro bumps MB formed between each of the plurality of DRAM wafers 1310 to 1340.

[0133] Here, you can Figure 1 The semiconductor memory device 100 implements each of the plurality of DRAM chips 1310 to 1340. For example, an error correction code based repair method may be applied to each of the plurality of DRAM chips 1310 to 1340 at a semiconductor manufacturing level.

[0134] Fig.16 is a block diagram illustrating a computing system including a semiconductor memory device according to example embodiments. Fig.16 , the computing system 2000 includes a processor 2100 , an input / output hub (IOH) 2200 , an input / output controller hub (ICH) 2300 , at least one DRAM module 2400 , and a graphic card 2500 .

[0135] The processor 2100 may perform various computing functions, such as specific calculations or tasks. For example, the processor 2100 may be a microprocessor or a central processing unit (CPU). The processor 2100 may include a single processor core, or may include multiple processor cores (or multi-cores). The processor 2100 may include a memory controller 2150 that controls the operation of the DRAM module 2400. The memory controller 2150 included in the processor 2100 is referred to as an "integrated memory controller (IMC)". The memory interface between the memory controller 2150 and the DRAM module 2400 may be implemented by a channel including multiple single lines or by multiple channels. In addition, one or more DRAM modules may be connected to each channel. In some embodiments, the memory controller 2150 may be arranged in the input / output hub 2200. The input / output hub 2200 including the memory controller 2150 may be referred to as a "memory controller hub (MCH)".

[0136] The DRAM module 2400 may include a plurality of DRAM devices that store data provided from the memory controller 2150. Each of the DRAM devices may be Figure 1 The semiconductor memory device 100 is implemented as shown in FIG.

[0137] The input / output hub 2200 can manage data exchange between the processor 2100 and other devices such as the graphics card 2500. The input / output hub 2200 can be connected to the processor 2100 through various interfaces. The input / output hub 2200 can provide interfaces for various devices. For example, the input / output hub 2200 can provide an accelerated graphics port (AGP) interface, an express peripheral component interface (PCIe), a communication stream architecture (CSA) interface, etc.

[0138] The graphic card 2500 may be connected to the input / output hub 2200 through AGP or PCIe. The graphic card 2500 may control a display device (not shown) for displaying an image. The graphic card 2500 may include an internal processor for processing image data and an internal semiconductor memory device.

[0139] The input / output controller hub 2300 may perform data buffering and interface arbitration to allow various system interfaces to operate efficiently. The input / output controller hub 2300 may be connected to the input / output hub 2200 via an internal bus. For example, the input / output hub 2200 and the input / output controller hub 2300 may be connected via a direct media interface (DMI), a hub interface, an enterprise south bridge interface (ESI), PCIe, etc.

[0140] The input / output controller hub 2300 may provide various interfaces with peripheral devices. For example, the input / output controller hub 2300 may provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general purpose input / output (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc.

[0141] According to example embodiments, repair efficiency can be improved by considering defects that can be corrected by using error correction codes in a semiconductor memory device including an on-chip error correction circuit. Therefore, a semiconductor memory device can be manufactured at a yield that is currently unrealized by using only a redundant repair scheme.

[0142] While the inventive concepts have been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the invention as set forth in the following claims.< / n>

Claims

1. A method for repairing a semiconductor memory device, the semiconductor memory device comprising a memory cell array and an error correction code logic, the memory cell array comprising a main cell array and a redundant cell array, the method comprising the following steps: detecting a failure bit of each of a primary repair unit of the primary unit array and a redundant repair unit of the redundant unit array; determining, using the error correction code logic, whether the failed bit detected from each of the primary repair unit and the redundant repair unit is correctable to determine a first correctable state for the primary repair unit or a second correctable state for the redundant repair unit; Calculating a first cumulative correctable fault bit count of the primary repair unit and a second cumulative correctable fault bit count of the redundant repair unit; determining whether to replace the primary repair unit with the redundant repair unit according to the first correctable state, the second correctable state, the first cumulative correctable fault bit count, and the second cumulative correctable fault bit count; as well as A repair operation is performed according to the determination result.

2. The method according to claim 1, further comprising: When the first correctable state corresponds to an uncorrectable state and the second correctable state corresponds to a correctable state, the primary repair unit is replaced with the redundant repair unit.

3. The method according to claim 1, further comprising: When each of the first correctable state and the second correctable state corresponds to a correctable state and the first cumulative correctable fault bit count is greater than the second cumulative correctable fault bit count, the primary repair unit is replaced with the redundant repair unit.

4. The method according to claim 1, further comprising: When each of the first correctable state and the second correctable state corresponds to a correctable state and the first cumulative correctable fault bit count is not greater than the second cumulative correctable fault bit count, replacing the primary repair unit with the redundant repair unit is blocked.

5. The method according to claim 1, further comprising: When the first correctable state corresponds to a no-failure-bit state in which no failed bit exists, and the second correctable state corresponds to an uncorrectable state, replacing the primary repair unit with the redundant repair unit is blocked.

6. The method according to claim 1, wherein: The step of determining the first correctable state and the second correctable state further comprises: When at least one of the plurality of main codeword units included in the main repair unit is uncorrectable, determining the first correctable state to be an uncorrectable state; and When at least one of the plurality of redundant codeword units included in the redundant repair unit is uncorrectable, the second correctable state is determined to be an uncorrectable state.

7. The method according to claim 6, wherein: The first cumulative correctable failure bit count is a value of a sum of failure bits of the plurality of main codeword units, and the second cumulative correctable failure bit count is a value of a sum of failure bits of the plurality of redundant codeword units.

8. A semiconductor memory device comprising: a master unit array, comprising a plurality of master repair units; a redundant unit array including a plurality of redundant repair units; an error correction code logic configured to correct errors in data output from each of the plurality of primary repair units and the plurality of redundant repair units; as well as A testable block is configured to detect a faulty bit of each of the plurality of primary repair units and the plurality of redundant repair units, determine a faulty bit state of whether the detected faulty bit of each of the plurality of primary repair units and the plurality of redundant repair units is a correctable faulty bit state according to the correction capability of the error correction code logic, calculate a cumulative correctable faulty bit count of each of the plurality of primary repair units and the plurality of redundant repair units, and replace at least one primary repair unit in which a defect exists with at least one redundant repair unit with reference to the calculated cumulative correctable faulty bit count and the determined faulty bit state.

9. The semiconductor memory device according to claim 8, wherein: Each of the plurality of primary repair units or the plurality of redundant repair units includes at least one dynamic random access memory unit.

10. The semiconductor memory device according to claim 8, wherein: The testable blocks include: an error detection circuit configured to output first defect information by detecting the failure bits of the plurality of primary repair units, and to output second defect information by detecting the failure bits of the plurality of redundant repair units; a main unit register, configured to store a first address corresponding to the first defect information, and to store the first defect information; a redundant cell register configured to store a second address corresponding to the second defect information and to store the second defect information; and A repair controller is configured to perform a repair operation based on a comparison result of the first defect information and the second defect information.

11. The semiconductor memory device according to claim 10, wherein: The first defect information includes the cumulative correctable fault bit count or the fault bit status of each of the plurality of primary repair units, and the second defect information includes the cumulative correctable fault bit count or the fault bit status of each of the plurality of redundant repair units.

12. The semiconductor memory device according to claim 11, wherein Information of a master repair unit having an uncorrectable fail bit error or a large cumulative correctable fail bit count is stored in the master unit register with a high priority, and Among them, information of redundant repair cells having no failed bit or having a small cumulative correctable failed bit count is stored in the redundant cell register with a high priority.

13. The semiconductor memory device according to claim 12, wherein: The repair controller is further configured to replace an address of a primary repair unit with an address of a redundant repair unit, wherein the address of the primary repair unit is selected according to a priority stored in each of the primary unit register and the redundant unit register.

14. The semiconductor memory device according to claim 12, wherein: Each of the main unit register and the redundant unit register includes a content addressable memory.

15. The semiconductor memory device according to claim 8, further comprising: A repair logic is configured to repair the at least one primary repair unit selected from the plurality of primary repair units with the at least one redundant repair unit selected from the plurality of redundant repair units under control of the testable block.

16. A semiconductor memory device comprising: a memory cell array including a plurality of primary repair cells and a plurality of redundant repair cells; error correction code logic configured to perform error detection and correction operations on data stored in the memory cell array; as well as a testable block configured to determine whether a detected fault bit of each of the plurality of primary repair units and the plurality of redundant repair units is a correctable fault bit state according to the correction capability of the error correction code logic, calculate a cumulative correctable fault bit count of each of the plurality of primary repair units and the plurality of redundant repair units, and replace at least one primary repair unit having a fault bit in the plurality of primary repair units with at least one redundant repair unit of the plurality of redundant repair units with reference to the calculated cumulative correctable fault bit count and the determined fault bit state, The cumulative correctable fault bit count of the at least one primary repair unit is greater than the cumulative correctable fault bit count of the at least one redundant repair unit, and the fault bit of the at least one redundant repair unit can be corrected through error detection and correction operations.

17. The semiconductor memory device according to claim 16, wherein: The at least one primary repair unit is a primary repair unit having an uncorrectable failed bit count among the plurality of primary repair units.

18. The semiconductor memory device according to claim 16, wherein: At least one redundant repair unit of the plurality of redundant repair units does not include a failed bit.

19. The semiconductor memory device according to claim 16, wherein: The testable block includes a content addressable memory that stores a failed bit count and an address of the at least one primary repair unit and a failed bit count and an address of the at least one redundant repair unit.

20. The semiconductor memory device according to claim 16, wherein Information of master repair cells having uncorrectable fail bit errors or large cumulative correctable fail bit counts is stored in a master cell register of the memory cell array with high priority, and Among them, information of redundant repair cells having no failed bit or having a small cumulative correctable failed bit count is stored in a redundant cell register of the memory cell array with a high priority.

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