Photoelectric devices

Abstract

Disclosed herein is an optoelectronic device comprising a rib waveguide including a ridge portion including a temperature-sensitive optically active region and a slab portion positioned adjacent to the ridge portion. The device also includes a heater positioned atop the slab portion, wherein a portion of the heater closest to the ridge portion is at least 2 μm from the ridge portion. The device may also include a heater provided with a bottom cladding layer and various thermally insulating enhanced cavities.

Description

Technical Field

[0001] The present invention relates to heaters in optoelectronics and, in particular, to heaters in electro-absorption modulators. Background Art

[0002] Optoelectronic devices, particularly electroabsorption modulators (EAMs), can be temperature-sensitive. For example, the operating wavelength of an EAM can shift significantly when the device's temperature changes. The underlying mechanism is that the band edge wavelength of the material forming the EAM can exhibit temperature dependence.

[0003] This temperature dependence can be beneficial, for example, when operating in coarse wavelength division multiplexing (CWDM) mode. However, in this mode of operation, the temperature of the device must be precisely controlled.

[0004] In conventional devices, the heater is placed immediately adjacent to or on top of the EAM (relative to the substrate). In such devices, severe temperature gradients may form across the EAM, which may significantly degrade the performance of the EAM. Summary of the Invention

[0005] In general, the present disclosure relates to providing heaters in photovoltaic devices in a manner that provides more uniform heating and to thermally isolating the heaters to effectively increase thermal conductivity. In one aspect, the present invention relates to providing cavities or trenches to thermally isolate the heater from the optically active area.

[0006] In a first aspect, the present invention provides a photovoltaic device comprising:

[0007] A rib waveguide, comprising:

[0008] a ridge portion comprising an optically active region that is sensitive to temperature,

[0009] and a plate portion positioned adjacent to the spine portion;

[0010] The device further includes a heater disposed on top of the plate portion, wherein a portion of the heater closest to the ridge portion is at least 2 μm away from the ridge portion.

[0011] By placing the heater at least 2 μm from the ridge portion, a much more uniform temperature can be established within the ridge portion of the waveguide including the temperature sensitive optically active region. In some examples, the portion of the heater closest to the ridge portion is at least 3 μm from the ridge portion.

[0012] In a second aspect, the present invention provides a photovoltaic device comprising:

[0013] A rib waveguide, comprising:

[0014] a ridge portion comprising an optically active region that is sensitive to temperature,

[0015] and a plate portion positioned adjacent to the spine portion;

[0016] The apparatus also includes a heater disposed in the epitaxial crystalline cladding layer below the slab portion.

[0017] By providing a heater within the epitaxial crystalline cladding, better temperature uniformity can be achieved. Furthermore, the heater can be provided while minimizing the increase in the device footprint. The heater also does not utilize exposed surface area of ​​the device and may not suffer from electromigration or self-Joule heating (both of which are failure mechanisms in heaters).

[0018] The heaters of the first and second aspects may allow the electro-absorption modulator included in the rib waveguide to operate over a range of wavelengths. For example, when the optically active region provides an electro-absorption modulator, the device may operate at wavelengths from at least 1450 nm to no more than 1610 nm, and preferably from at least 1550 nm to no more than 1610 nm. This may allow the use of coarse wavelength division multiplexing schemes. The optically active region may be made of Si x Ge 1-x Formed, where 0.005 ≤ x ≤ 0.01, and preferably, where 0.005 < x < 0.01.

[0019] In a third aspect, the present invention provides a photovoltaic device comprising:

[0020] A rib waveguide, comprising:

[0021] a ridge portion comprising an optically active region that is sensitive to temperature,

[0022] and a plate portion positioned adjacent to the spine portion;

[0023] The device further comprises:

[0024] a heater for heating the temperature-sensitive optically active region;

[0025] a bottom cladding layer disposed adjacent to the flat panel portion;

[0026] and a thermal insulation trench, wherein the thermal insulation trench is located adjacent to the bottom cladding layer.

[0027] The insulation trench is used to thermally isolate the heater and optically active area from the rest of the device, thereby increasing the efficiency of the heater. As a result, less energy may be required to maintain the optically active area at the desired temperature.

[0028] In a fourth aspect, the present invention provides a photovoltaic device, comprising:

[0029] A rib waveguide, comprising:

[0030] a ridge portion comprising an optically active region that is sensitive to temperature,

[0031] and a plate portion positioned adjacent to the spine portion;

[0032] The device further comprises:

[0033] a heater for heating the temperature-sensitive optically active region;

[0034] a bottom cladding layer disposed adjacent to the plate portion; and

[0035] The heat-insulating cavity is located on a side of the bottom covering layer opposite to the flat plate portion.

[0036] The insulating cavity is used to thermally isolate the heater and optically active area from the rest of the device, thereby increasing the efficiency of the heater. As a result, less energy may be required to maintain the optically active area at the desired temperature.

[0037] In a fifth aspect, the present invention provides a photovoltaic device, comprising:

[0038] A rib waveguide, comprising:

[0039] a ridge portion comprising an optically active region that is sensitive to temperature,

[0040] and a plate portion positioned adjacent to the spine portion;

[0041] The device further comprises:

[0042] a heater for heating the temperature-sensitive optically active region; and

[0043] an electrode electrically connected to the ridge portion or the plate portion, and a heater located between the electrode and the ridge portion;

[0044] The electrode comprises at least one thermally insulating cavity.

[0045] The or each insulating cavity in the electrode serves to thermally insulate the heater and optically active area from the rest of the device, thereby improving the efficiency of the heater. Consequently, less energy may be required to maintain the optically active area at the desired temperature.

[0046] A rib waveguide may mean that the waveguide is used to confine the optical mode of the waveguide within the ridge portion of the waveguide. Alternatively, the device may be a ridge waveguide, which may mean that the optical mode of the waveguide is confined within the slab portion of the waveguide, and the ridge portion may be used to guide light passing through the waveguide. As another alternative, it may mean that the optical mode is confined in both the ridge portion and the slab portion. In all aspects discussed above, the bottom cladding layer may be an epitaxial crystalline cladding layer. Adjacent may mean that the slab portion of the waveguide is adjacent to the ridge portion. The entire rib waveguide may be viewed as forming an inverted 'T' shape, wherein the legs of the T are provided by the ridge portion and the strips of the T are provided by the slab portion. The slab portion may be adjacent to the ridge portion in a direction perpendicular to the guiding direction of the waveguide. The ridge portion may be viewed as the portion of the waveguide extending from the slab portion in a direction away from the silicon substrate. The slab portion may also include a portion of the waveguide located directly below the ridge portion (relative to the upper surface of the device). Alternatively, the plate portion may be considered to have two sub-portions, one on either side of the spine portion, such that the spine portion bisects the entire plate portion.

[0047] The optional features of the present invention will now be described. These features may be used alone or in any combination with any aspect of the invention.

[0048] The width of the first zone of the heater can gradually decrease from a first width to a second width in a direction parallel or substantially parallel to the guiding direction of the rib waveguide. The width of the second zone of the heater can increase from the second width to the first width in a direction parallel or substantially parallel to the guiding direction of the rib waveguide. The tapered region can be used to reduce the junction current density below a threshold, thereby helping to avoid electromigration (a cause of some heater failures).

[0049] The heater may be formed of any one of Ti, TiN, TiW, NiCr, or W, and may preferably be formed of Ti or TiN.

[0050] The heater can include multiple metal strips, one end of each metal strip connected to an adjacent metal strip to form a serpentine shape. This can increase the electrical length of the heater without increasing the heater's footprint in the device. This increase in electrical length can increase the heater's resistivity, which can reduce the current density in the waveguide. If powered by a constant current source, the serpentine heater can exhibit increased heat generation compared to a non-serpentine heater. The heater can include at least two metal strips and no more than nine metal strips, and preferably at least two metal strips and no more than five metal strips. The heater can include first and second electrodes for the heater, with the electrodes electrically connected to the heater on the same side. "On the same side" can mean that the heater can be generally rectangular, and the electrodes can be electrically connected to the heater on the same side of the rectangle. Each metal strip can have a width of at least 0.5 μm and no more than 15 μm, and preferably at least 2.0 μm and no more than 4.0 μm. The gap between adjacent metal strips may have a width of at least 0.5 μm and not more than 10 μm, and preferably may have a width of at least 1.0 μm and not more than 2.0 μm.

[0051] The heater can be placed above the electrical contacts of the flat panel portion and separated from the electrical contacts by an insulator. By doing so, the overall footprint of the device can be maintained while ensuring that the heater does not electrically interfere with the flat panel portion.

[0052] The apparatus may include a second heater that is identical or substantially identical to the first heater and is positioned on an opposite side of the spine portion. Opposite sides may mean that the plate portion has two zones, one on a first side of the spine portion and one on a second side of the spine portion. The opposite side may be the second side, and the first heater may be positioned on the first side. Identical may mean that the second heater is structurally identical to the first heater but is a mirror image of the first heater in a plane aligned with the spine portion.

[0053] The heater may comprise a doped region of an epitaxial crystalline cladding layer or a doped region of a silicon-on-insulator layer disposed below the slab portion of the waveguide. The epitaxial crystalline cladding layer may be formed of silicon. The doped region of the epitaxial crystalline cladding layer may extend in a direction parallel or substantially parallel to the guiding direction of the rib waveguide. The doped region may have a width of at least 1 μm and not more than 30 μm, and preferably a width of at least 3 μm and not more than 20 μm. The doped region may have a height of at least 0.1 μm and not more than 0.3 μm, and preferably a height of at least 0.15 μm and not more than 0.2 μm. The doped region may have a thickness of at least 1×10 20 cm -3 and not more than 2.5×10 20 cm-3 The device may further include an undoped region of the epitaxial crystalline cladding layer, the undoped region being located between the doped region and the slab portion.

[0054] The insulation grooves may be filled with air or silicon dioxide, and are preferably filled with air. The insulation grooves may have a width of at least 0.5 μm and no more than 2.0 μm. The device may include a plurality of insulation grooves arranged around the periphery of the plate portion. Peripheral may mean that the insulation grooves are positioned around the outermost edge of the plate portion. The outermost edge may be the edge farthest from the ridge portion, as measured in the plane of the device. For example, the plate portion may be generally rectangular, and the insulation grooves would therefore be positioned along the edges of the rectangle.

[0055] The device may further include a buried oxide layer disposed adjacent to a lower surface of the bottom cladding layer, wherein the thermal isolation cavity is located on an opposite side of the buried oxide layer and adjacent to the silicon substrate. The thermal isolation cavity may have a width greater than a width of the slab portion. A crystalline rare earth oxide (CREO) or rare earth oxide (REO) layer may be present between the bottom cladding layer and the slab portion. The CREO or REO layer and the bottom cladding layer may have a (111) crystallographic orientation.

[0056] The electrode used for the modulator may include a plurality of thermally isolated cavities in an array, wherein the array extends in a direction parallel or substantially parallel to the guiding direction of the rib waveguide. The array may extend for a length of at least 50 μm and no more than 100 μm, and preferably at least 50 μm and no more than 70 μm. The electrode may include at least 2 cavities and no more than 30 cavities, and preferably at least 5 cavities and no more than 10 cavities. The or each cavity in the electrode may have a length of at least 2 μm and no more than 30 μm, and preferably at least 5 μm and no more than 10 μm. The or each cavity in the electrode may have a width of at least 1 μm and no more than 10 μm, and preferably at least 3 μm and no more than 5 μm. The gap between adjacent cavities in the electrode may have a length of at least 1 μm and no more than 20 μm, and preferably at least 1 μm and no more than 3 μm. The or each cavity in the electrode may be filled with air or SiO2. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0058] Figure 1 A top view of a photovoltaic device is shown;

[0059] FIG. 2A(i) shows Figure 1 A cross-sectional view of the device along line AA';

[0060] FIG2B(i) shows a top view of a heater for a photovoltaic device;

[0061] Figure 2C Show Figure 1 A cross-sectional view of the device along line BB';

[0062] FIG2A(ii) shows Figure 1 A modified cross-sectional view of the device along line AA';

[0063] FIG2B(ii) shows a top view of a variant of a heater for a photovoltaic device;

[0064] Figure 3 A top view showing a modified optoelectronic device;

[0065] Figure 4A A top view showing a modified optoelectronic device;

[0066] Figure 4B A top view showing a modified optoelectronic device;

[0067] Figure 5A Show Figure 4A A cross-sectional view of the device along line AA;

[0068] Figure 5B Show Figure 4A A cross-sectional view of the device along line BB';

[0069] Figure 5C A top view showing a modified heater for a photovoltaic device;

[0070] Figure 6A A top view showing a modified optoelectronic device;

[0071] Figure 6B Show Figure 6A A cross section of the device along line AA';

[0072] Figure 6C A top view showing a modified heater used in a photovoltaic device 6A;

[0073] 7A to 7C 1. A top view of a modified heater element for a photovoltaic device is shown;

[0074] Figure 8A and Figure 8B respectively showing cross-sectional views of modified optoelectronic devices;

[0075] Figure 9 Two examples of thermal insulation trenches are shown;

[0076] Figure 10A top view showing a modified optoelectronic device;

[0077] Figure 11A A cross-sectional view showing a modified optoelectronic device;

[0078] Figure 11B Show Figure 11A A top view of a photovoltaic device;

[0079] Figure 12A A cross-sectional view of a modified optoelectronic device is shown, and Figure 12B Show Figure 12A an enlarged section of the device shown in ;

[0080] Figure 13 A top view showing a modified optoelectronic device;

[0081] Figure 14 Show Figure 13 A magnified top view of

[0082] Figure 15A A top view showing a modified optoelectronic device;

[0083] Figure 15B Show Figure 15A A cross-sectional view of the device along line AA';

[0084] Figure 16 Show Figure 15A A cross-sectional view of a variation of the device along line AA';

[0085] Figure 17A A top view showing a modified optoelectronic device;

[0086] Figure 17B Show Figure 16 A cross-sectional view of the device of A along line AA'; and

[0087] 18A to 18D is a graph showing simulation results for various devices; and

[0088] 19A to 19D Graphs showing simulation results for various devices. DETAILED DESCRIPTION

[0089] Figure 1A top view of an optoelectronic device 100 is shown. An input waveguide 101 guides light into a rib waveguide comprising a ridge portion 102 and a slab portion 103 atop a silicon-on-insulator layer 202. The ridge portion may, for example, comprise or provide an electro-absorption modulator (EAM) or photodiode structure. Depending on the properties of the ridge portion of the rib waveguide, light may exit the device via an output waveguide 104. Electrical pads 105, which may be formed of titanium or aluminum, connect to the rib and slab portions. Typically, the electrodes are formed of 1 μm thick aluminum, and a 10 nm thick titanium layer may be included between the aluminum and the slab as an electrical barrier. A heater 106 is positioned atop a portion of the slab portion 103. The heater is formed of a generally elongated metal strip located no less than 2 μm from the ridge portion 102 of the rib waveguide. The heater is connected at either end to junctions 107, which connect the ends of the heater 106 to metal traces 109. Metal traces 109 are then connected to electrical pads 108 for the heater. In this example, the electrical pads are formed from aluminum, and the heater is formed from Ti or TiN. The metal traces can also be formed from aluminum and typically introduce a resistance of less than 1 Ω, for example, approximately 0.6 Ω. The total length of each metal trace can be approximately 400 μm, the width of each metal trace can be approximately 20 μm, and the metal traces can have a height of approximately 1 μm. The dimensions of some portions of the optoelectronic device are indicated in the figure.

[0090] A change of 35°C in the rib waveguide can cause a wavelength shift of about 27 nm or 30 nm. This change in the average temperature in the rib waveguide can be referred to as ΔT. The heater as an embodiment of the present invention has the following characteristics:

[0091]

[0092] Where w is the width of the heater. R is the resistance; I is the current, J is the current density, V in is the input voltage, and T heater is the temperature, all of which are measured inside the heater at ΔT = 35°C. The heater thickness t can be at least 30 nm and not more than 500 nm, and preferably at least 50 nm and not more than 200 nm. The values ​​in this table are examples only, where there is no buried oxide layer under the plate.

[0093] At this stage, it's worth discussing the principal directions associated with device 100. One principal direction, indicated by y, is generally aligned with the guiding directions of input waveguide 101 and output waveguide 104. At 90 degrees to y, but still within the plane of the device, is principal direction x. And at 90 degrees to both the y and x directions is direction z, extending out of the plane of the device.

[0094] As shown in FIG2A(i), FIG2A(i) is Figure 1 In the device shown in FIG, a cross section along line AA' is shown, with heater 106 extending across the width of electrical pads 105 for the waveguide and a portion of slab portion 103 to connect each end to metal trace 109. Electrical pads 105 can be electrically connected to slab portion 103, which can be doped, for example, n++ doped. The electrical pads in this example are approximately 1 μm high, measured in the z-direction. As can be seen from this cross section, the device also includes a buried oxide (BOX) layer 203 (which can be 400 nm thick) located above silicon substrate 204, and a silicon-on-insulator layer 202 (which can be 400 nm thick) located above the buried oxide layer. Typically, these devices are covered by an upper cladding layer 201, which can be formed of silicon dioxide (SiO2) and can be 500 nm thick. The upper cladding layer can be approximately 0.5 μm thick. This upper cladding layer can be used for passivation, i.e., to prevent oxidation. It can be seen that the central portion of the heater extends approximately 38 μm along the y-direction, and the corresponding connector adds approximately 10 μm to the length of the heater. Beneath the silicon substrate 204 may be another buried oxide layer, and beneath the further buried oxide layer may be another silicon substrate, i.e., the entire device is provided on a DSOI (double silicon on insulator) wafer.

[0095] FIG2B(i) is a partial top view of heater 106. As can be seen in region 106a of the heater, the width of the heater, as measured in direction x, tapers from approximately 17 μm to 2 μm in a direction parallel to the guide direction (i.e., direction y). The width of the heater then increases from 2 μm to approximately 17 μm in region 106b. These tapered regions 106a and 106b allow the heater to be connected to metal trace 109 while ensuring that the current density in any given region is not too high. Figure 2C Show Figure 1 FIG2 is a cross-sectional view of the device in FIG2 taken along line BB'. As can be seen, the electrode 105 for the waveguide is positioned below the heater 106 and is electrically connected to the doped region of the slab 103. In some examples, the buried oxide layer 203 below the slab 103 can be etched away and replaced with an epitaxial crystalline semiconductor such as Si or SiGe.

[0096] Figures 2A(ii) and 2B(ii) show variations of the devices shown in Figures 2A(i) and 2B(i), and therefore like features are represented by like reference numerals. The difference between the two devices is that the aluminum trace 109A for the heater includes a portion that extends away from the silicon-on-insulator layer 202 and then over the upper surface of the heater 106. Thus, the junction 107A and the electrical connection from the trace 109 to the heater 106 are formed on the upper surface of the heater. In Figures 2A(i) and 2B(i), the electrical connection is between the lower surface of the heater and the trace. The electrical junction 107A described with respect to Figures 2A(ii) and 2B(ii) can be more reliable than the equivalent disclosed in Figures 2A(i) and 2B(i).

[0097] Figure 3 A variant optoelectronic device is shown in FIG, in which two identical heaters 106A and 106B are placed on either side of a rib waveguide. The heaters are identical except that they are mirror images in a plane aligned with the ridge portion of the waveguide. The following table gives the two heaters ( Figure 3 shown) is an indication of the difference compared to a single heater

[0098]

[0099] The heater has a thickness t of 100 nm (measured in the z direction) and a narrowest width w of 2 μm (measured in the x direction). In the table, R is the resistance of the heater, I is the input current, V is the input voltage, and T heater is the temperature of the heater. I, V in , power and T heater The values ​​of refer to values ​​when ΔT (change in average temperature of the waveguide) is 35°C. The values ​​in Table 1 are for an example when the buried oxide layer located below the silicon substrate 204 has a thickness of approximately 0.4 μm and when the buried oxide layer 203 located between the silicon substrate and the plate 103 has been replaced with silicon. It is worth noting that by including a second heater, the temperature increase within each heater is approximately half that of the single heater embodiment. Moreover, the input voltage required for the two heaters in the two heater embodiment is approximately 70% of the voltage required in the single heater embodiment. The parameters 'undercut' and 'trench' indicate the presence of a cavity or thermal insulation trench, as described below.

[0100] Figure 4A A modified photovoltaic device is shown, wherein like features are indicated by like reference numerals. Figure 1The difference between the optoelectronic device shown in is that heater 406A comprises a plurality of metal strips extending in the y-direction and connected at one end to an adjacent metal strip. In this example, heater 406A is formed from four metal strips and formed into a generally serpentine shape. By doing so, the electrical length of the heater can be increased, and therefore the available heat output will similarly increase. This increase in electrical length can increase the resistivity of the heater, which can reduce the current density in the waveguide. If the serpentine heater is powered by a constant current source, the serpentine heater can show an increase in the amount of heat generated compared to a non-snake heater. Figure 1 As with heater 106 in FIG. 1 , no portion of heater 406A is closer than 2 μm to the ridge portion of waveguide 102. Also shown in this figure are electrical traces 109 that are all on the same side of the heater, for example, contacting heater 406A on the side closest to input waveguide 101. This can be used to further reduce the footprint of a device including the heater. Figure 4B Show Figure 4A In this figure, the heater 406B comprises an odd number of metal strips, so the metal trace 109 is connected to the heater at the opposite end relative to the input waveguide 102.

[0101] Typically, the process flow for providing such a device includes the following steps: (i) depositing electrical pads and depositing metal traces for the heater at the same time as the electrical pads for the waveguide; (ii) depositing an upper cladding layer and etching vias to connect to the electrical pads and the metal traces for the heater; (iii) depositing a heater layer at least 50 nm and not more than 200 nm thick, for example, a 100 nm thick heater layer, and patterning the layer; and (iv) depositing an oxide having a thickness of about 0.5 μm for passivating the heater layer. The heater can be provided by depositing titanium.

[0102] Figure 5A yes Figure 4A 2A(i) along the line AA'. This is similar to the cross section shown in FIG2A(i) and therefore like features are denoted by like reference numerals. Notable changes include that the heater now comprises a plurality of metal strips having a total width of approximately 17 μm measured in the x-direction. This width is an example, but many other total widths may be used. In general, the width may be calculated as ,in is the number of stripes, is the width of a single strip, and is the width of the gap between adjacent strips. Also noteworthy, but also present in FIG2A(i), is the insulating layer 407, which serves to electrically isolate the heater 406 from the waveguide's electrical pad 105. A via is present in the upper cladding layer 201 so that the electrode 105 for the waveguide can make electrical contact with the slab region. This via has a width of approximately 18 μm and a length of approximately 38 μm.

[0103] Figure 5B yes Figure 4A , along line BB'. Here, the extension of heater 406 can be more easily seen. The connection distance from metal trace 109 to heater 406 does not exceed 5 μm. In this example, the material comprising the heater extends away from the core region of the heater and contacts metal trace 109 through a separate via in upper cladding layer 201. Figure 5C is included in Figure 4A is a partial top view of the heater 406 in the device shown in . It can be seen that the core region of the heater is defined by a rectangular region with a width of 17 μm and a length of 38 μm. The length of the core region of the heater can be between 2 μm and 4 μm less than the length of the through hole of the EAM electrode-SiGe plate. The width of the core region of the heater can be between 1 μm and 5 μm less than half the width of the through hole. Although the heater here has a width of 17 μm, as mentioned above, other values ​​can be used. In general, the width of the heater is defined as: .

[0104] Figure 6A A partial top view of another variant device is shown. Here, heater 506 is similar to heater 406 disclosed previously, except that metal traces 109 extend away from silicon-on-insulator layer 202 in the z-direction and then further onto the slab region. Figure 6B This is most clearly shown in FIG, where metal trace 109 contacts heater 506 through a via in upper cladding layer 201 that is located above electrode 105 for the waveguide. Figure 6C A partial top view of heater 506 is shown. Here, the core region of the heater is still defined by a rectangular region that is 17 μm wide and 38 μm long. However, in this example, metal traces 109 extend to some extent into this core region.

[0105] Typically, the process flow for providing these devices includes (i) depositing electrical contacts for the waveguides, patterning them, and depositing an oxide coating; (ii) depositing 1 μm thick electrical contacts and metal traces for the heater, which can be formed from aluminum, and patterning them; (iii) depositing and patterning a heater layer, which can be at least 50 nm and no more than 200 nm thick, such as 100 nm thick; and (iv) depositing an oxide to passivate the heater layer. Steps (ii) and (iii) can be interchanged.

[0106] 7A to 7C The partial top view of three variant heaters is shown. In each figure, the number of metal strips 810 is varied. For example, in Figure 7A In the example shown, there are eight metal strips. Since the total footprint of the heater remains constant, for example, 38 μm × 17 μm, the gap g The thickness of the strips increases with the number of strips n Typically, if n Minimize the , the heater can be more efficient. Changing these characteristics will change the parameters, as shown in Table 2 below:

[0107]

[0108] Where 'undercut' and 'groove' indicate undercuts and grooves as described below; I is the current through the heater when ΔT (increase in average temperature of the waveguide) is 35°C; J is the current density when ΔT is 35°C; and T max is the maximum temperature of the heater when ΔT is 35°C. The above example includes a heater on only one side of the waveguide. There is no buried oxide layer directly between the slab portion of the waveguide and the silicon layer, which is replaced by an epitaxial crystalline cladding layer as described previously. The buried oxide layer below the silicon layer 605 has a thickness of 0.4 μm, and the heater has a thickness of 100 nm (measured in the z direction) and a width of 2 μm. As described above, the width of the heater is typically n The width of the heater is therefore not necessarily constant for all examples in Table 2.

[0109] Further characterization was performed by varying the closest distance D between the heater and the ridge portion of the waveguide, as shown in the following table:

[0110]

[0111] The above example includes a heater on only one side of the waveguide. There is no buried oxide layer directly between the slab portion of the waveguide and the silicon layer; as previously described, it is replaced by an epitaxial crystalline cladding layer. The buried oxide layer below the silicon layer 605 has a thickness of 0.4 μm, and the heater has a thickness of 100 nm (measured in the z direction) and a width of 2 μm. This gives the heater a resistance of 80 Ω. I, V in , power and T heater It is measured when ΔT = 35℃.

[0112] Figure 8A Show Figure 4A , along cross-sectional view of the device shown in FIG. 1 , along cross-sectional view A-A'. In this view, more details of the ridge portion 102 are shown, which includes a first doped region 601 and a second doped region 602. The first doped region 601 of the ridge can be n-type doped, and the second doped region 602 of the ridge can be p-type doped. The slab portion also includes a first doped region 603 and a second doped region 604. The first doped region 603 of the slab can be n-type doped, and the second doped portion 604 of the slab can be p-type doped. Of course, the first and second doped regions of the slab and ridge portions can have alternative doping types. The first doped region 603 and the second doped region 604 of the slab can be more heavily doped than the doped regions of the ridge.

[0113] Directly below the slab portion is an epitaxial crystalline cladding layer 605. The epitaxial crystalline cladding layer can be substantially the same as disclosed in US 62 / 528,900 or US 15 / 700,055, the entire contents of which are incorporated herein by reference. Essentially, the original buried oxide layer in the silicon-on-insulator wafer has been etched away and replaced with an epitaxially grown crystalline structure (typically a semiconductor). As clearly shown in this view of the device, the heater 406 is no less than 2 μm away from the rib waveguide portion 102. Also shown are electrical pads 105 for connecting to the doped regions 603 and 604 of the slab portion. Table 2 below shows the changes in the parameters listed in Table 1 when there is an epitaxial crystalline cladding layer 605 directly below the slab portion:

[0114]

[0115] Where I, J, ΔT vert (vertical temperature difference in the waveguide), and T metal It is the value at ΔT = 10℃.

[0116] As can be seen in Table 4, the efficiency of the heater in the embodiment without buried oxide is slightly lower than that of the heater with buried oxide layer. Otherwise, the operation of the heater is similar to that of the heater implemented above the buried oxide layer.

[0117] Figure 8B A modified example is shown in Figure 8A Same cross-sectional view as shown in . Figure 8A In contrast to the embodiment shown, this example includes thermal isolation trenches 701 located on either side of a bottom cladding layer 605. As described above, the bottom cladding layer can be an epitaxial crystalline cladding layer. The thermal isolation trenches 701 can be formed entirely of silicon dioxide, or formed by silicon dioxide outer walls that define a volume filled with air. Directly below the bottom cladding layer region 605 is another buried oxide layer 704, on the other side of which is a cavity 702. This other buried oxide layer can also be present in the Figure 8A , but in this example there would be a silicon substrate on the other side. Cavity 702 is characterized by the absence of any silicon and is formed between silicon sidewalls 703. Cavity 702 (which may be referred to as an undercut) may be as wide as or wider than the width of the slab portion.

[0118] Both the insulation grooves 701 and the cavity 702 can be used to thermally isolate the heater and rib waveguide portion from the rest of the device. This insulation can improve the efficiency of the heater and also ensure a more uniform temperature distribution through the rib and plate portion.

[0119] like Figure 9 As shown on the left side of the figure, the thermal insulation trench can include a silicon dioxide outer wall 801 that surrounds an air-filled volume 802; alternatively, the thermal insulation trench can be completely filled with silicon dioxide 801, as shown on the right side. The trench width can be at least 0.5 μm and at most 2.0 μm. If the width is ≤ 1.0 μm, the trench can be completely filled with SiO2. If the width is > 1.0 μm, the trench can have an air-filled volume.

[0120] By changing the design parameters of these devices, the embodiments according to the present invention have the following characteristics:

[0121]

[0122] In the embodiments disclosed in this table, there is no buried oxide layer directly beneath the slab portion of the waveguide. As described above, the buried oxide layer is replaced by an epitaxial crystalline cladding layer. In addition, the heater comprises a single metal strip having a thickness of 100 nm, a width of 2 μm and a length of 38 μm, the resistance of the metal strip being 80 Ω. 'BOX' indicates the height of the buried oxide layer 704 between the cavity 702 and the slab portion of the waveguide (as measured in the z-direction). 'Undercut' and 'Trench' indicate if a trench or undercut (also called a cavity) is present in the example. I, V in , power and T heater The values ​​are given when ΔT is 35°C.

[0123] Alternatively, there may be a buried oxide layer 203 extending between the slab portion of the waveguide 603 and the silicon-on-insulator layer 605. Typically, this buried oxide layer will be about 0.4 μm thick (as measured in the z-direction). Again, by varying the design parameters of the device, the device according to the present invention has the following characteristics:

[0124]

[0125] In the example disclosed in this table, the buried oxide layer 203 extends across the entire width of the device, and is therefore present directly beneath the slab portion of the waveguide and has a width of 0.4 μm. The heater comprises a single metal strip with a thickness of 100 nm and a width of 2 μm, and a resistance of 80 Ω. I, V in , power and T heater The values ​​are given for a ΔT of 35°C. In the examples in the above two tables, the heater length (L) is 38 μm. It can be understood that the efficiency of the heater is 1 / L, and the power required for a given ΔT is L.

[0126] Figure 10 Another variant device is shown and like features are indicated by like reference numerals. Compared to the previous device, Figure 10 The device shown in FIG also includes a heat protection ring 901, which includes a plurality of heat insulation grooves 701 as described above. These heat insulation grooves extend around the periphery of the flat plate portion 103, thereby defining a heat protection ring.

[0127] Figure 11A Another variant device is shown, and like features are indicated by like reference numerals. Compared to the previous device, the heater in this example includes a doped region 1006 in the bottom cladding layer 605. As previously described, the bottom cladding layer 605 can be an epitaxial crystalline bottom cladding layer. In this example, the doped heating region 1006 is less than 2 μm from the rib waveguide 102, but of course the skilled person will understand that (as in the previous example) all parts of the heater can be at least 2 μm from the rib waveguide portion. In this example, the metal trace 109 connecting the heater to the electrical pad extends through the upper cladding layer region so as to electrically contact the doped region 1006. The doped region comprising the heater can be a heavily doped region, for example, n++ or p++.

[0128] Figure 11B yes Figure 11A Here, the dashed area indicated by reference numeral 1006 shows the approximate location of the doped heating element relative to the plate portion 103. Metal traces 109 contact the doped regions 1006 at either end of the buried heater. This example also includes the thermal protection ring 901 as described above.

[0129] Figure 12A Another example of the doped heater 1006 discussed above is shown. In this example, there are thermal isolation trenches 701 and cavities 702 as described above. Figure 12A As can be more clearly seen in the figure, there is a portion of the undoped bottom cladding layer region 605 in the middle of the first doped region 603 of the slab to electrically isolate the first doped region from the doped heater 1006. This undoped portion of the bottom cladding layer can be approximately 400 nm thick. In this example, the efficiency of the heater is approximately 0.9°C / mW. The efficiency without the isolation trench but with the cavity is approximately 0.35°C / mW. The efficiency without the cavity but with the isolation trench is approximately 0.24°C / mW. The efficiency of the heater without either the cavity or the isolation trench is approximately 0.20°C / mW.

[0130] Figure 12B Show Figure 12A An enlarged portion of the device shown in FIG. The width of the heater 1006 is indicated here, as is its height T and the thickness d of the undoped region. Changing some parameters of the device will change the characteristics listed in Table 4 below:

[0131]

[0132] In these examples, the buried oxide layer below the heater 1006 has a height of 0.4 μm measured in the z direction, and all examples include cavities or undercuts and thermal isolation trenches. Parameters I, V in , power and T heater For the case where ΔT is 35°C. It can be seen that the efficiency does not depend primarily on W or T. It can also be seen that a nearly uniform temperature distribution is achieved inside the waveguide (the variation is less than 0.3°C at an average ΔT of 35°C). Possible values ​​for W range from at least 1 μm to no more than 20 μm, and possible values ​​for T range from at least 100 nm to no more than 300 nm. Preferably, W falls within the range of at least 2 μm and no more than 7 μm, and T falls within the range of at least 150 nm and no more than 200 nm. It is observed that larger values ​​of W, T, or larger doping concentrations result in smaller resistance and larger current. For a value of about 10 at 300K 20 cm -3 The resistivity of doped Si was measured to be 3Ω·μm.

[0133] Figure 13 A partial top view of another variant device is shown. Here, the electrodes for the waveguide 105 include one or more cavities 1101 disposed therein. The cavities may be filled with silicon dioxide or air (as in the case of the thermally insulating trenches discussed above).

[0134] Figure 14 Show Figure 13 An enhanced partial view of the electrodes shown in . The relative sizes of the cavities are discussed here. a indicates the length of each cavity, b indicates the gap between adjacent cavities, and c indicates the width of each cavity. The total length of the electrode L imposes the following constraint: L = (N+1)×b +(N×a), where N is the number of cavities. L can take a value of at least 50 μm and not more than 100 μm, and preferably can be at least 50 μm and not more than 70 μm. Accordingly, n can be at least 2 and not more than 30, or preferably at least 5 and not more than 10. a can take a value of at least 2 μm and not more than 30 μm, or preferably at least 5 μm and not more than 10 μm. b can take a value of at least 1 μm and not more than 20 μm, or preferably at least 1 μm and not more than 3 μm. c can take a value of at least 1 μm and not more than 10 μm, or preferably at least 3 μm and not more than 5 μm. By providing such cavities, an increase in heater efficiency of approximately 30% can be achieved. This is mainly due to the enhanced thermal insulation relative to the heater and waveguide.

[0135] Figure 15A and Figure 15B Another variation of the photovoltaic device is shown. Figure 15A In the embodiment of the present invention, a serpentine heater 406 formed of a plurality of metal strips is located directly above the first doped region 603 of the slab portion. The closest portion of this heater is at least 2 μm from the rib waveguide portion 102. The entire device is located within a cavity in the silicon-on-insulator layer, which has a height of approximately 3 μm (as measured from the buried oxide layer). Figure 15B A cross section along line A-A' is shown. As can be seen here, between the epitaxial crystalline cladding layer 605 and the slab portion is a crystalline rare earth oxide (CREO) or rare earth oxide (REO) layer 1203, which can be used to further improve the crystalline quality of the slab when grown. Layer 1203 can have a thickness of at least 20 nm to no more than 400 nm. The lattice orientation of the epitaxial crystalline cladding layer and the CREO or REO layer can be (111). In addition, the device includes heavily doped regions 1201 and 1202, which are respectively connected to the electrical pad 105. The heavily doped regions can reduce the series resistance of the doped portions of the slab and ribs.

[0136] Figure 16 Show Figure 15B The difference here is that the upper cladding layer 201 completely surrounds the heater 406 on the upper surface.

[0137] Figure 17A and Figure 17B Another variant device is shown. Figure 16In contrast to the example disclosed in , this device also includes a thermal protection ring 2101 (as described above) and also includes a cavity 702 located on the side of the buried oxide layer opposite the bottom cladding layer 605.

[0138] With respect to the heater formed from a plurality of metal strips discussed above, in some examples, the heater may be formed from Ti or TiN according to the following:

[0139]

[0140] 18A to 18D Graphs showing simulation results of various devices according to the present invention. Figure 18A is a graph of efficiency versus minimum distance D between the heater and the ridge portion, and Figure 18B is a graph of power versus D to obtain a ΔT value of 35°C. Although the efficiency decreases as D increases, and the power required increases as D increases, Figure 18C Temperature uniformity (ΔT vert ) has been greatly improved. Figure 18D is a graph of heater temperature versus D to obtain a ΔT value of 35°C. 18A to 18D The device simulated in has the following parameters: a heater; ; ; no undercuts and no grooves are provided. Multiple lines on each graph indicate different Value device.

[0141] 19A to 19D are graphs showing simulation results of various devices according to the present invention. 18A to 18D However, as mentioned above, 19A to 19D The simulated device is provided with undercuts and grooves. As will be seen later, when these tables are compared with 18A to 18D When compared to the graphs in , efficiency increases and the power required decreases.

[0142] Although the present invention has been described in conjunction with the above exemplary embodiments, those skilled in the art will understand many equivalent modifications and variations when using this disclosure. Therefore, the exemplary embodiments of the present invention set forth above are considered to be illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the present invention.

[0143] Feature List

[0144] Optoelectronic device 100

[0145] Input waveguide 101

[0146] Rib waveguide ridge portion 102

[0147] The slab portion 103 of the rib waveguide

[0148] Output waveguide 104

[0149] Electrical pads 105 for waveguides

[0150] Heaters 106, 406, 506, 1006

[0151] E107

[0152] Electrical pads 108 for heaters

[0153] Metal trace 109

[0154] Upper cladding layer 201

[0155] Silicon-on-insulator layer 202

[0156] Buried oxide 203

[0157] Silicon substrate 204

[0158] Insulator layer 407

[0159] The first doped region 601 of the rib

[0160] The second doped region 602 of the rib

[0161] The first doped region 603 of the plate

[0162] The second doped region 604 of the plate

[0163] Silicon layer 605

[0164] Thermal insulation groove 701

[0165] Thermal insulation cavity 702

[0166] Silicon substrate 703

[0167] SiO2 wall 801

[0168] Air cavity 802

[0169] Thermal protection ring 901

[0170] Cavity 1101 in the electrical pad.

Claims

1. A photovoltaic device, comprising: A rib waveguide, comprising: a ridge portion comprising an optically active region that is sensitive to temperature, and a plate portion positioned adjacent to the spine portion; a heater disposed on top of the plate portion, wherein a portion of the heater closest to the ridge portion is at least 2 μm away from the ridge portion; a bottom cladding layer disposed adjacent to the flat panel portion; an insulation trench, wherein the insulation trench is positioned adjacent to the bottom cladding layer; an insulating cavity located on a side of the bottom cladding layer opposite the flat plate portion; and a buried oxide layer disposed adjacent to a lower surface of the bottom cladding layer, wherein the heat-insulating groove is at least partially filled with air, and The thermal isolation cavity is located on the opposite side of the buried oxide layer and adjacent to the silicon substrate. 2 . The photovoltaic device according to claim 1 , wherein a width of the first region of the heater gradually decreases from a first width to a second width in a direction substantially parallel to a guiding direction of the rib waveguide. 3 . The optoelectronic device of claim 2 , wherein a width of the second region of the heater increases from the second width to the first width along the direction substantially parallel to the guiding direction of the rib waveguide.

4. The photovoltaic device of claim 1, wherein the heater comprises a plurality of metal strips, one end of each metal strip being connected to an adjacent metal strip to form a serpentine pattern.

5. The photovoltaic device of claim 4, wherein the heater comprises at least 2 metal strips and no more than 20 metal strips.

6. The photovoltaic device of claim 4 or 5, further comprising first and second electrodes for the heater, the electrodes being electrically connected to the heater on the same side.

7. The photovoltaic device of claim 4, wherein each metal strip has a width of at least 0.5 μm and not more than 10 μm.

8. The photovoltaic device of claim 4, wherein a gap between adjacent metal strips has a width of at least 0.5 μm and not more than 10 μm.

9. The photovoltaic device of claim 4, wherein the heater is formed of any one of the following: Ti, TiN, TiW, NiCr, or W.

10. The photovoltaic device of claim 1, wherein the heater is positioned above the electrical contacts of the plate portion and is separated from the electrical contacts by an insulator.

11. The photovoltaic device of claim 1, further comprising an upper cladding layer disposed on the heater.

12. The photovoltaic device of claim 1, further comprising a second heater substantially identical to the heater and disposed on an opposite side of the ridge portion.

13. The photovoltaic device according to claim 1, wherein the thermal isolation trench is further filled with silicon dioxide.

14. The photovoltaic device of claim 1 or 13, wherein the heat-insulating trench has a width of at least 0.5 μm and not more than 2.0 μm.

15. The photovoltaic device of claim 1, wherein the device comprises a plurality of thermal insulation grooves arranged around a periphery of the plate portion. The photovoltaic device according to claim 1 , wherein a width of the thermal insulation cavity is greater than a width of the flat plate portion.

17. The photovoltaic device of claim 1, further comprising an electrode electrically connected to the ridge portion or the plate portion, wherein the electrode comprises at least one thermally insulating cavity.

18. The optoelectronic device of claim 17, wherein the electrode comprises a plurality of thermally isolated cavities in an array, wherein the array extends in a direction substantially parallel to a guiding direction of the rib waveguide.

19. The optoelectronic device of claim 18, wherein the array extends over a length of at least 50 μm and no more than 100 μm.

20. The optoelectronic device of claim 17, wherein the electrode comprises at least 2 cavities and no more than 30 cavities.

21. An optoelectronic device as claimed in claim 17, wherein the or each cavity in the electrode has a length of at least 2 μm and no more than 30 μm.

22. An optoelectronic device as claimed in claim 17, wherein the or each cavity in the electrode has a width of at least 1 μm and no more than 10 μm.

23. The optoelectronic device of claim 18, wherein a gap between adjacent cavities in the electrode has a length of at least 1 μm and not more than 20 μm.

24. An optoelectronic device as claimed in claim 17, wherein the or each cavity in the electrode is filled with air or SiO2.

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