Semiconductor structure and method for forming the same

Abstract

Embodiments of the present invention disclose a semiconductor structure and a method for forming the same. In one embodiment, the semiconductor structure includes an active region having source / drain regions on a substrate; a dielectric layer located on the active region and having sidewalls aligned with the sidewalls of the source / drain regions; and a conductive structure extending along the sidewalls of the dielectric layer to the source / drain regions. The source / drain regions have sidewalls and lateral surfaces extending laterally from the sidewalls of the source / drain regions, and the source / drain regions further include nitride regions extending laterally from the sidewalls of the source / drain regions into the source / drain regions. The conductive structure includes a silicide region along the lateral surfaces of the source / drain regions and along at least a portion of the sidewalls of the source / drain regions.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure and a method for forming the same, and more particularly to a surface treatment process. Background Art

[0002] As the semiconductor industry progresses to nanometer technology process nodes to achieve higher device density, higher performance, and lower cost, challenges arising from process and design issues have led to the development of three-dimensional designs, such as the FinFET. FinFET devices typically include a high-aspect-ratio semiconductor fin in which a channel region and source / drain regions are formed. The gate is formed on the fin structure and along its sidewalls (e.g., wrapping the fin structure). This has the advantage of increasing the surface area of ​​the channel region, resulting in faster, more reliable, and easier-to-control semiconductor transistor devices.

[0003] FinFET devices typically include a semiconductor region that forms source and drain regions. Metal silicide is then formed on the surface of the semiconductor region to reduce the contact resistance between the metal contact plug (which contacts the silicide region) and the semiconductor region. However, as device dimensions shrink, this structure presents new challenges. Summary of the Invention

[0004] A semiconductor structure provided by one embodiment of the present invention includes: an active region, a dielectric layer, and a conductive structure. The active region is located on a substrate and includes a source / drain region. The source / drain region has sidewalls and a lateral surface extending laterally from the sidewalls of the source / drain region. The source / drain region further includes a nitride region extending laterally from the sidewalls of the source / drain region into the source / drain region. The dielectric layer is located on the active region and has sidewalls aligned with the sidewalls of the source / drain region. The conductive structure is arranged along the sidewalls of the dielectric layer to the source / drain region. The conductive structure includes a silicide region, and the silicide region is arranged along the lateral surface of the source / drain region and along at least a portion of the sidewalls of the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a flow chart of an exemplary method for fabricating a semiconductor device in some embodiments.

[0006] Figure 2 FIG2 is a perspective view of a semiconductor device according to a corresponding fabrication stage in some embodiments.

[0007] Figure 3A 、 Figures 3B to 8A 、 Figure 8B as well as Figure 11A 、 Figures 11B to 12A 、 Figure 12B In some embodiments, according to Figure 1 Flowchart of fabrication of a semiconductor device with partial cross-sectional views at various stages.

[0008] Figure 9 and Figure 10 FIG. 5 is a diagram illustrating a portion of a source / drain region having a surface nitride layer or a nitride portion in some embodiments.

[0009] Figure 13 In some embodiments, Figure 8A Additional details of the cutaway section.

[0010] Figure 14 FIG. 1 is a flow chart of an exemplary method for processing a semiconductor device in some embodiments.

[0011] Figure 15 and Figure 16 In some embodiments, according to Figure 14 Flowchart of fabrication of a semiconductor device with partial cross-sectional views at various stages.

[0012] The description of the accompanying drawings is as follows:

[0013] AA, BB sections

[0014] D1 first dimension

[0015] D2 Second size

[0016] D3 third size

[0017] D4 fourth size

[0018] D5 Fifth size

[0019] D6 Sixth size

[0020] D7 Seventh Size

[0021] D8 eighth size

[0022] D9 Ninth Size

[0023] G1, G2, G3, G4, G5 sizes

[0024] 100, 1400 flow chart

[0025] Steps 102, 104, 106, 108, 110, 112, 114, 116, 118, 1402, 1404

[0026] 210 Metal Layer

[0027] 211 Surface Treatment

[0028] 213 Diffusion Barrier

[0029] 214 silicide layer

[0030] 215 surface nitride layer

[0031] 217 Nitride Zone

[0032] 219 barrier layer

[0033] 220 interface dielectric layer

[0034] 221 Conductive Materials

[0035] 222, 280 gate dielectric layer

[0036] 224 Compliance Layer

[0037] 226 Gate

[0038] 228a, 228b replacement gate structure

[0039] 230 Second interlayer dielectric layer

[0040] 231 U-shaped groove

[0041] 232 Source / Drain Contact Opening

[0042] 237 bottom

[0043] 239 sidewall

[0044] 240 Semiconductor devices

[0045] 251 Gate Structure

[0046] 253 Grooves

[0047] 270 semiconductor substrate

[0048] 274 Fins

[0049] 278 Quarantine Zone

[0050] 282 gate layer

[0051] 284 Mask

[0052] 286 Gate Spacer

[0053] 292 Source / Drain Region

[0054] 296 Contact Etch Stop Layer

[0055] 297 First interlayer dielectric layer

[0056] 1502, 1514 barrier layer

[0057] 1504 First Floor

[0058] 1506 Second Floor

[0059] 1508 Oxidized surface layer

[0060] 1509 Surface

[0061] 1510, 1516 illustrations

[0062] 1512 Pre-cleaning process DETAILED DESCRIPTION

[0063] The following disclosure provides many different embodiments or examples for implementing various structures of the present invention. The following examples of specific components and arrangements are intended to simplify the present invention and are not intended to limit the present invention. For example, a description of a first component being formed on a second component includes both components being in direct contact, or having additional components between them rather than in direct contact. In addition, multiple embodiments of the present invention may use repeated reference numerals and / or symbols to simplify and clarify the description, but such repetition does not necessarily mean that the same corresponding relationship exists between the components with the same reference numerals in the various embodiments.

[0064] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify the description of an element relative to another element in the drawings. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90 degrees or other angles, so directional terms are only used to describe orientations in the drawings.

[0065] The structures and methods provided in various embodiments described below form an effective metal diffusion barrier layer on the sidewalls of the contact opening without growing an additional film in the contact opening. This prevents the sidewalls of the epitaxial source / drain regions exposed by the contact opening from reacting with the contact metal to produce unwanted metal silicide. In additional or other examples, a non-destructive cleaning method is also provided to remove oxide from the metal barrier layer formed on the silicide. The metal barrier layer can be restored to its original state and reused through subsequent processing.

[0066] The foregoing summarizes some embodiments of the present invention. It is contemplated that planar transistor devices or three-dimensional transistor devices, such as the semiconductor device 201 described in the embodiments of the present invention, can implement the concepts of the embodiments of the present invention. Some exemplary devices for the embodiments described herein may include fin field effect transistors, horizontal all-around gate field effect transistors, vertical all-around gate field effect transistors, nanowire channel field effect transistors, strained semiconductor devices, silicon-on-insulator devices, or other devices that can benefit from pre-treatment processes to reduce loading effects and / or substrate-dependent growth-related issues.

[0067] Figure 1 FIG. 1 is a flow chart 100 illustrating an exemplary method of fabricating a semiconductor device 240 in various embodiments. Figure 2A three-dimensional diagram of an example of a semiconductor device 240 . Figure 3A 、 Figures 3B to 8A 、 Figure 8B and Figure 11a, Figures 11B to 12A 、 Figure 12B , based on Figure 1 1 shows a cross-sectional view of a portion of a semiconductor device 240 fabricated at various stages of the process flow. It is important to note that process 100 can be used to form any other semiconductor structure not described herein. Those skilled in the art will recognize that the complete process for forming a semiconductor device and its associated structures are not depicted or described herein. Although various steps are depicted and described herein, the order of these steps or the presence of steps between them is not intended to be limiting. The order of steps depicted or described herein is for illustrative purposes only, unless otherwise specified, and does not preclude the possibility that individual steps may be performed simultaneously or at least partially simultaneously.

[0068] Process 100 begins with step 102 by providing a semiconductor device 240. The semiconductor device 240 has fins 274 formed on a semiconductor substrate 270. The semiconductor substrate 270 may be or may include a bulk semiconductor substrate, a semiconductor-on-insulator substrate, or the like, and may be undoped or doped with p-type or n-type dopants. In some embodiments, the semiconductor material of the semiconductor substrate 270 may include a semiconductor element such as silicon or germanium; a semiconductor compound; a semiconductor alloy; or a combination thereof. Each fin 274 may provide an active region, i.e., where one or more devices are formed. The fins 274 may be fabricated using a suitable process performed on the semiconductor substrate 270, including masking, photolithography, and / or etching processes, to form trenches 253 in the semiconductor substrate 270 and retain the fins extending upward from the semiconductor substrate 270. The trenches 253 may then be filled with an insulating material such as an oxide (e.g., silicon oxide), a nitride, or the like, or a combination thereof. The insulating material may be recessed to form the isolation regions 278 , and the recessing method may adopt an acceptable etching process. After the insulating material is recessed, the fins 274 may protrude upward from between adjacent isolation regions 278 .

[0069] The semiconductor device 240 has a gate structure 251 formed on the upper surface of the fin 274. Each gate structure 251 includes a gate dielectric layer 280, a gate layer 282 on the gate dielectric layer 280, and a mask 284 on the gate layer 282, such as Figure 2 The semiconductor device 240 further includes source / drain regions 292 in regions on both sides of the fin 274 opposite to the gate structure 251 . Figure 2Reference cross sections used in subsequent figures are also shown. Cross section AA may be a plane along the channel between the source / drain regions 292 on either side of the fin 274. Cross section BB is a plane perpendicular to cross section AA and traverses the source / drain regions 292 in the fin 274. Subsequent figures correspond to these reference cross sections for clarity. The following figures ending with "A" refer to cross-sectional views corresponding to cross section AA in various examples of the process. The following figures ending with "B" refer to cross-sectional views corresponding to cross section BB in various examples of the process.

[0070] like Figure 3A 、 Figure 3B As shown, a gate structure 251 is formed on the fin 274. The gate structure 251 is located on the fin 274 and extends perpendicular to the fin 274. The gate structure 251 can be an operational gate stack in a gate-first process, or a dummy gate stack in a replacement gate process. To simplify the description, the flowchart 100 will be described based on the replacement gate process. In the replacement gate process, the gate dielectric layer 280 can be an interface dielectric layer, and the gate layer 282 can be a dummy gate. The gate dielectric layer 280, the gate layer 282, and the mask 284 for the gate structure 251 can be formed in sequence as individual layers, and then these layers are patterned into the gate structure 251. For example, the layer for the interface dielectric layer can include or can be silicon oxide, silicon nitride, the like, or a multilayer thereof. The layer for the dummy gate can include or can be silicon (such as polysilicon) or another material. The mask layer may include or be silicon nitride, silicon oxynitride, silicon carbide nitride, or the like, or a combination thereof. The layers may be formed or deposited using any suitable deposition technique. For example, the layers for the gate dielectric layer 280, the gate layer 282, and the mask 284 may then be patterned to form the gate dielectric layer 280, the gate layer 282, and the mask 284 for each gate stack 251. The patterning may be performed using photolithography and one or more etching processes.

[0071] Step 104 forms a gate spacer 286 along the sidewalls of the gate structure 251 (e.g., the sidewalls of the gate dielectric layer 280, the gate layer 282, and the mask 284), and the gate spacer 286 is also formed on the fin 274. For example, the gate spacer 286 may be formed by conformally depositing one or more layers for the gate spacer 286, rather than isotropically etching the one or more layers. The one or more layers for the gate spacer 286 may comprise a material that is different from the material used for the gate structure 251. In some embodiments, the gate spacer 286 may comprise or be a dielectric material such as silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbide nitride, the like, multiple layers thereof, or combinations thereof, and may be deposited by any suitable deposition technique. An anisotropic etching process may then be performed to remove portions of the spacer layer to form the gate spacer 286, such as Figure 4A 、 Figure 4B shown.

[0072] After forming the gate spacers 286, source / drain regions 292 may be formed in the fin 274, as shown in FIG. Figure 4A 、 Figure 4B As shown. In some examples, the gate structure 251 and gate spacers 286 can be used as a mask to etch recesses into the fin (e.g., forming recesses on both sides of the gate structure 251). Material can then be epitaxially grown in the recesses to form source / drain regions 292. The source / drain regions 292 can be formed by, instead of or in addition to, implanting dopants into the fin 274 and / or the epitaxial source / drain regions 292, using the gate structure 251 as a mask to form source / drain regions on both sides of the gate structure 251.

[0073] The material used for the source / drain regions 292 depends on the conductivity type of the transistor and may include or may be silicon germanium (Si x Ge 1-x , which may be between approximately 0 and 1), silicon carbide, silicon phosphide, silicon carbon phosphide, pure or substantially pure germanium, a III-V semiconductor compound, a II-VI semiconductor compound, or the like. For example, materials for the III-V semiconductor compound may include indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like. In some examples, the source / drain regions 292 for p-type devices may include silicon germanium, while the source / drain regions 292 for n-type devices may include silicon carbon phosphide or silicon phosphide. Figure 4A 、 Figure 4BAs shown, due to the blocking effect of isolation region 278, the material in source / drain regions 292 initially grows vertically within the recesses, preventing the source / drain regions 292 from growing horizontally. After the recesses are completely filled, the material for source / drain regions 292 can grow vertically and horizontally to form crystal planes that correspond to the crystallographic planes of semiconductor substrate 270. In some cases, different materials are used for the epitaxial source / drain regions of p-type and n-type devices. Using appropriate masks during the recess process or epitaxial growth allows for the use of different materials in different devices.

[0074] Step 106 optionally sequentially forms a contact etch stop layer 296 and a first interlayer dielectric layer 297 on the surfaces of the source / drain regions 292, the sidewalls and upper surfaces of the gate spacers 286, the upper surface of the mask 284, and the upper surface of the isolation region 278. These layers are formed using any suitable deposition technique. The conformally deposited contact etch stop layer 296 may include or be silicon nitride, silicon carbide nitride, silicon oxycarbide, carbon nitride, the like, or a combination thereof. The first interlayer dielectric layer 297 may include or be tetraethoxysilane oxide, silicon oxide, or a low-k dielectric material (e.g., a material having a lower dielectric constant than silicon oxide). A chemical mechanical polishing process may then be performed to planarize the first interlayer dielectric layer 297 and the contact etch stop layer 296 and remove the mask 284 of the gate structure 251 so that the upper surfaces of the first interlayer dielectric layer 297 and the contact etch stop layer 296 are flush with the upper surface of the gate layer 282 .

[0075] The gate structure 251 can be removed by one or more etching processes. After the gate structure 251 is removed, a recess is formed between the gate spacers 286 (i.e., where the gate structure 251 is removed), and the channel region of the fin 274 is exposed through the recess. Then, replacement gate structures 228a and 228b are formed in the recess (i.e., where the gate structure 251 is removed). The replacement gate structures 228a and 228b each include an interface dielectric layer 220, a gate dielectric layer 222, one or more optionally formed compliant layers 224, and a gate 226, as shown in FIG. Figure 5A As shown, an interfacial dielectric layer 220 is formed on the upper surface of the fin 274 along the channel region. The interfacial dielectric layer 220 can be an oxide, such as silicon oxide, formed by thermally or chemically oxidizing the fin 274, and / or an oxide (such as silicon oxide), a nitride (such as silicon nitride), and / or another dielectric layer formed using any suitable deposition technique.

[0076] The gate dielectric layer 222 can be conformally deposited in the recess (i.e., where the gate stack is removed), such as on the interfacial dielectric layer 220 and on the sidewalls of the gate spacer 286. The gate dielectric layer 222 can also be conformally deposited on the first interlayer dielectric layer 297, the contact etch stop layer 296, and the gate spacer 286. The gate dielectric layer 222 can be or include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other dielectric materials. The high-k dielectric material can have a dielectric constant greater than approximately 4.0 and can include metal oxides or metal silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, multiple layers thereof, or combinations thereof.

[0077] The one or more compliant layers 224 may include one or more barrier and / or capping layers and one or more work function adjustment layers. The one or more barrier and / or capping layers may include tantalum nitride, titanium nitride, or the like, or combinations thereof. The one or more work function adjustment layers may include or be titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, or the like, or combinations thereof. The materials used for the one or more work function adjustment layers, barrier layers, and / or capping layers may be selected to achieve a desired threshold voltage for the transistor, such as a p-type field effect transistor or an n-type field effect transistor. A layer for gate 226 is formed on the one or more compliant layers 224 (if implemented) and / or on gate dielectric layer 222. The layer for gate 226 may fill the remaining recess (i.e., where the gate stack was removed). The layer for gate 226 may be or include a metal-containing material, such as tungsten, cobalt, aluminum, ruthenium, copper, multiple layers thereof, combinations thereof, or the like.

[0078] A planarization process such as chemical mechanical polishing can remove portions of the layers for the gate 226, the one or more compliant layers 224, and the gate dielectric layer 222 that are above the upper surfaces of the first interlayer dielectric layer 297, the contact etch stop layer 296, and the gate spacer 286. In this way, replacement gate structures 228a and 228b including the gate 226, the one or more compliant layers 224, the gate dielectric layer 222, and the interfacial dielectric layer 220 can be formed. Figure 5A shown.

[0079] Step 108 forms a second interlayer dielectric layer 230 on the gate 226, the one or more compliant layers 224, the gate dielectric layer 222, the first interlayer dielectric layer 297, the gate spacer 286, and the contact etch stop layer 296, as shown in FIG. Figure 6A The second interlayer dielectric layer 230 may include or be silicon oxide, a low-k dielectric material (e.g., silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, the like, or combinations thereof.

[0080] After forming the second interlayer dielectric layer 230, source / drain contact openings 232 are formed through the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296 to reach the source / drain region 292 and expose at least a portion of the source / drain region 292. Figure 6A As shown in the example. For example, the method of patterning the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296 to have the source / drain contact opening 232 can use photolithography and one or more etching processes. The one or more etching processes can be a dry etching process, a deep reactive ion etching process, or any suitable anisotropic etching process. In one example, the dry etching process uses an inductively coupled plasma or a capacitively coupled plasma, which contains oxygen, argon, and one or more fluorine-based chemicals (such as hexafluorobutadiene, octafluorocyclobutane, or carbon tetrafluoride) to form the source / drain contact opening 232. In this way, the sidewalls of the source / drain contact opening 232 are vertical, although they can have a small tilt angle. The source / drain contact opening 232 can be used to form an electrical contact to the source / drain region 292 of the transistor.

[0081] After forming the source / drain contact openings 232, a silicide pre-cleaning process may be performed to remove native oxide (such as silicon oxide) from the surface of the exposed source / drain region 292. The native oxide is formed because the source / drain region 292 is exposed to a variety of etchants when the source / drain contact openings 232 are formed. An exemplary silicide pre-cleaning process may include wet cleaning using a dilute hydrofluoric acid aqueous solution, dry cleaning using a plasma (such as nitrogen trifluoride and ammonia plasma), or a combination thereof. The chemical agent used in the silicide pre-cleaning can remove native oxide such as the upper portion of the source / drain region 292 to form a U-shaped trench 231 on the upper surface of the source / drain region 292. The U-shaped trench 231 has a bottom 237 and sidewalls 239, such as Figure 6A shown.

[0082] Step 110 forms a compliant metal layer 210 on the surface of the exposed source / drain region 292 (such as the sidewall 239 and bottom 237 of the U-shaped trench 231), as well as on the surface of the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296. Figure 7A Figure 7BThe thickness of the metal layer 210 at the bottom 237 of the U-shaped trench 231 is greater than the thickness of the metal layer 210 on the sidewalls 239 of the U-shaped trench 231, the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the surface of the contact etch stop layer 296. For example, the ratio between the thickness of the metal layer 210 at the bottom 237 of the U-shaped trench 231 and the thickness of the metal layer 210 on the sidewalls 239 of the U-shaped trench 231, the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the surface of the contact etch stop layer 296 can be between about 2:1 and about 10:1, such as between about 4:1 and about 6:1. The metal layer 210 can be a single layer or a multi-layer stack. When the metal layer 210 is a single layer, the metal layer 210 can be or include titanium, tantalum, or the like. When the metal layer 210 is formed as a multi-layer stack (e.g., a double layer), the first layer may be or may include titanium, tantalum, or the like, and the second layer may be or may include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or the like. The first layer may be formed on the second layer, or vice versa. In any case, the thickness of the first layer may be between about to about Between, such as to about Between, for example The thickness of the second layer can be between about to about Between, such as about to about Between, for example The metal layer 210 may be deposited by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or any other suitable deposition technique. In some examples employing a dual-layer structure, the first layer may be formed by physical vapor deposition, while the second layer may be formed by atomic layer deposition. In some embodiments, the metal layer 210 is a titanium layer. In another embodiment, the metal layer 210 is a stack of a titanium layer and a titanium nitride layer.

[0083] In step 112, the upper portion of the source / drain region 292 reacts with the metal layer 210 to form a silicide layer 214 on the source / drain region 292. Figure 8A 、 Figure 8BAs shown. For example, an annealing process is then performed to heat the substrate to cause a silicidation reaction to occur in the metal layer 210 contacting the source / drain region 292. The silicidation reaction may occur at the interface between the source / drain region 292 and the metal layer 210, as well as around and / or outside the interface between the source / drain region 292 and the metal layer 210. In some examples where the metal layer 210 is a layer stack (such as titanium and titanium nitride), the bottom layer (such as titanium) may react with the source / drain region 292 and completely transform into a silicide layer, while a portion of the top layer (such as titanium nitride) may transform into a silicide layer. For example, the annealing process may be a rapid thermal annealing process, the temperature of which may be between about 400°C and about 650°C (such as about 500°C) and the duration of which may be between about 10 seconds and about 60 seconds. The unreacted metal layer 210 is then removed by a selective etching process that attacks the unreacted metal layer 210 but does not attack the silicide layer 214. Since the thickness of the metal layer 210 at the bottom 237 may be greater than the thickness of the metal layer 210 on the sidewalls 296, the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the surface of the contact etch stop layer 296, in some examples, after the selective etching process (such as removing the unreacted metal layer 210 from the surface of the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296), a portion of the unreacted metal layer 210 (such as the titanium nitride layer in the titanium and titanium nitride stack) may still remain on the silicide layer 214. The metal layer 210 remaining on the silicide layer 214 has some advantages because it can act as a barrier layer to prevent oxidation of the silicide layer 214 in subsequent processes. Figure 9 、 Figure 10 In the example shown, the silicide layer 214 has the metal layer 210 remaining thereon.

[0084] The selective etching process may be any suitable wet etching or dry etching process. Suitable wet etching processes may use deionized water, hydrofluoric acid-based etching chemicals, hydrogen peroxide, hydrogen chloride, or a combination thereof to selectively remove the unreacted metal layer 210. Suitable dry etching processes may use a mixture of an oxygen-containing gas (such as oxygen) and a fluorine-based or carbon fluorine-based etching chemical to selectively remove the unreacted metal layer 210. Figure 8A 、 Figure 8B Also shown is the removal of the metal layer 210 from the exposed surfaces of the second interlayer dielectric layer 230 , the first interlayer dielectric layer 297 , and the contact etch stop layer 296 .

[0085] Due to the high aspect ratio (greater than or equal to about 3:1) of the source / drain contact opening 232, the silicide layer 214 is significantly formed on the bottom 237 of the U-shaped trench 231, and is minimally formed or not formed on the upper portion of the sidewall 239. The poor coverage of the metal layer 210 on the upper portion of the sidewall 239 may result in only a small amount or no silicide being formed on the upper portion of the sidewall 239 after annealing. In other words, the silicide layer 214 does not cover the upper portion of the sidewall 239, and a portion of the source / drain region 292 is exposed through the source / drain contact opening 232 after the silicidation process, as shown in FIG. Figure 9 、 Figure 10 The terms “exposed source / drain region” or “exposed surface of the source / drain region” as used herein generally refer to the surface region of the source / drain region 292 exposed by the source / drain contact opening 232 and not covered by the silicide layer 214, or the surface region of the source / drain region 292 exposed by the source / drain contact opening 232 and not physically contacted or minimally contacted by the silicide layer 214.

[0086] Exposed source / drain regions 292 at the upper portions of the sidewalls can be problematic because contact metal subsequently filled into source / drain contact openings 232 may diffuse through the subsequently deposited metal barrier layer (formed between the contact metal and source / drain regions 292 after the silicidation process) and react with the exposed source / drain regions 292. Consequently, unwanted metal silicide may form on and / or near the upper portions of sidewalls 239, which can lead to device reliability issues. While thicker metal barrier layers (e.g., greater than or equal to about 2 nm) can be used to prevent contact metal from diffusing and reacting with the exposed source / drain regions 292, this can result in poor gap-filling capability for subsequent contact metal. Various embodiments described below include surface treatments that convert a surface layer of the source / drain regions 292 into a barrier layer. The surface treatment forms an effective metal diffusion barrier on the exposed surfaces of the source / drain regions without sacrificing the gap-filling capability of the contact metal.

[0087] Self-aligned diffusion barrier for source / drain regions

[0088] Step 114 performs surface treatment 211 on the exposed source / drain regions 292 to form a diffusion barrier layer 213 on the surface of the exposed source / drain regions 292. Figure 8AAs shown. The diffusion barrier layer 213 prevents the contact metal subsequently filled into the source / drain contact opening 232 from diffusing into the underlying source / drain region 292 through the upper portion of the sidewall 239 uncovered by the silicide layer 214 and reacting with the underlying source / drain region 292. In various embodiments, the surface treatment 211 is a nitridation process. The nitridation process may include exposing the exposed source / drain region 292 to a nitrogen-containing plasma or nitrogen-containing environment, causing nitrogen atoms to react with atoms located on the exposed surface of the source / drain region 292 to form a nitride layer or nitride region on the upper portion of the source / drain region 292. The nitridation process thus forms a self-aligned sidewall barrier layer on the exposed surface of the source / drain region 292. The nitridation process may additionally or alternatively include exposing the surface of the exposed source / drain region 292 to nitrogen molecules or atomic nitrogen radicals and ions to implant nitrogen into the surface of the exposed source / drain region 292, whereby the surface or region of the upper side of the source / drain region 292 reacts with nitrogen to form a nitrided source / drain region (as a result of the implantation process).

[0089] Figure 9 、 Figure 10 In the embodiment, Figure 8A A partial enlarged view of the source / drain region after surface treatment. Figure 9 、 Figure 10 The exposed areas or surface layers of the source / drain regions 292 after nitridation are shown. Specifically, the nitridation reaction occurs in the exposed source / drain regions 292 not covered by the silicide layer 214. The depth of the nitridation reaction in the exposed source / drain regions 292 may vary depending on the application and surface treatment performed. Figure 9 In one embodiment, nitrogen is diffused into the exposed surface of the source / drain region 292 in the upper portion of the sidewall 239 of the U-shaped trench 231, converting at least the surface layer of the source / drain region 292 into a surface nitride layer 215. In various embodiments, the thickness of the surface nitride layer 215 (measured from the surface of the sidewall 239) is between about 0.1 nm and about 5 nm, such as between about 0.5 nm and about 1.8 nm, for example, between about 0.8 nm and about 1.5 nm. Figure 10 As another example, after the surface treatment is completed, nitrogen diffuses through the exposed surfaces of the source / drain regions 292 and converts the entire upper portion of the source / drain regions 292 into the nitride regions 217 . Figure 10 It is also shown that the nitrogen can extend through the entire upper portion of the source / drain region 292 (e.g., from the surface of the sidewall 239 to the Figure 8A The interface between the source / drain regions 292 and the gate spacer 286 is shown and passes down to below the top of the silicide layer 214.

[0090] The nitride region 217 may have a dimension G1 from the upper surface of the nitride region 217 (which may be coplanar with the top of the source / drain region 292) to the bottom of the nitride region. The source / drain region 292 may have a dimension G2 from the top of the source / drain region 292 to the bottom of the source / drain region 292. In various embodiments, the ratio between the dimension G1 and the dimension G2 may be between about 1:3 and about 1:20, such as between about 1:5 and about 1:8, for example, between about 1:6 and about 1:7. This ratio may vary depending on the parameters used in the nitridation process and the size of the source / drain region 292. The metal layer 210 remaining on the silicide layer 214 may have a dimension G3 from the top of the metal layer 210 to the bottom of the metal layer 210. The silicide layer 214 may have a dimension G4 from the top of the silicide layer 214 to the bottom of the silicide layer 214. In various embodiments, the ratio between dimension G3 and dimension G4 may be between about 1:2 and about 1:6, such as between about 1:3 and 1:5, for example, about 1:4. Sidewall 239 may have a dimension G5 from the top of sidewall 239 (which may be coplanar with source / drain region 292) to the bottom of sidewall 239 (which may be coplanar with the bottom of silicide layer 214). In various embodiments, the ratio between dimension G1 and dimension G5 may be between about 1:2 and about 1:10, such as between about 1:4 and about 1:8, for example, between about 1:5 and 1:6. In some cases, sidewall 239 need not extend to the full depth of silicide layer 214. The ratio between dimension G4 and dimension G5 may be between about 1:1 and about 8:1, such as between about 2:1 and about 6:1, for example, between about 3:1 and about 5:1. In the nitride region (such as the surface nitride layer 215 and / or the nitride region 217), the nitrogen atom density may be between 1×10 21 cm -3 to 3×10 21 cm -3 and the nitrogen atomic % may be between 0% and 60%.

[0091] Nitriding the surface layer or the entire upper portion of the source / drain region has several advantages, as it forms an effective metal diffusion barrier within the exposed surface and / or within the exposed source / drain region 292, eliminating the need to grow an additional barrier layer to block contact metal diffusion. Consequently, the total barrier layer thickness within the source / drain contact opening 232 can be reduced, thereby providing more space for the subsequently formed contact metal. This, in turn, increases the tolerance of the contact metal gapfill process.

[0092] The nitridation process may be a plasma nitridation process using capacitively coupled plasma or inductively coupled plasma. The nitrogen plasma may be generated in situ in the process chamber where the semiconductor substrate 270 is located, or may be formed in a remote plasma chamber and then flowed into the process chamber where the semiconductor substrate 270 is located. The exposed source / drain regions 292 may be exposed to a radio frequency plasma, which may be formed from a process gas. The process gas may consist of, consist essentially of, or include a nitrogen-containing gas such as nitrogen, ammonia, nitric oxide, nitrous oxide, a combination of nitrogen and hydrogen, and / or any mixture thereof. The pressure in the process chamber may be maintained between approximately 1 mTorr and approximately 20 Torr, such as between approximately 10 mTorr and approximately 10 Torr, such as between approximately 60 mTorr and approximately 1 Torr. Optionally, an inert gas such as argon, helium, or neon may be added to the process gas. In one example, the process gas comprises nitrogen and argon. In another example, the process gas comprises ammonia and argon. In yet another embodiment, the process gas comprises nitrogen and helium. In some embodiments, a nitrogen-containing gas is flowed into the process chamber at a first volumetric flow rate, and an inert gas is flowed into the process chamber at a second volumetric flow rate. The ratio between the first volumetric flow rate and the second volumetric flow rate can be controlled to be between about 1:2 and about 1:10, such as between about 1:3 and 1:8, or for example, between about 1:4 and about 1:6. For a 300 mm substrate, the flow rate of the nitrogen-containing gas can be between about 50 sccm and about 6000 sccm, such as between about 200 sccm and about 2000 sccm, or for example, between about 600 sccm and about 1000 sccm. If an inert gas is used, the flow rate of the inert gas can be between about 25 sccm and about 12000 sccm, such as between about 400 sccm and about 8000 sccm, or for example, between about 800 sccm and about 5000 sccm. Other gas compositions and / or flow rates may be used depending on the application and process chamber configuration. The temperature of the semiconductor substrate 270 can be maintained between about 20°C and about 600°C, such as between about 50°C and about 450°C, or for example, between about 80°C and about 200°C. After the process gas is introduced into the process chamber, a radio frequency (RF) source can be coupled to the process gas to form a plasma. The RF source power can be between about 20 W and about 5000 W, such as between about 50 W and about 1000 W, or for example, between about 100 W and about 300 W. The RF source power can have any suitable RF frequency, such as between about 2 MHz and about 60 MHz, for example, about 13.56 MHz. The plasma can be applied in a pulsed or continuous manner, with an effective power of up to about 1200 W. For example, the plasma can be applied continuously at a power of up to about 400 W for a duration of between about 10 seconds and about 300 seconds, such as between about 20 seconds and about 120 seconds, or for example, between about 40 seconds and about 90 seconds. The duration of the RF source power can be adjusted to control the amount of nitrogen diffused or incorporated into the exposed surfaces of the source / drain regions.In examples where a pulsed plasma is used, the plasma can be pulsed at a frequency between about 2 kHz and about 20 kHz, such as between about 4 kHz and about 15 kHz. The duty cycle of the plasma can be between about 2% and about 50%, such as between about 6% and about 30%, or, for example, about 20%, at a peak power of up to 3000 W. Similarly, the duty cycle and / or RF source power can be adjusted to control the diffusion or incorporation of nitrogen into the exposed surfaces of the source / drain regions 292. In some examples, the duty cycle of the pulsed plasma can be between about 5% and 20% at a peak power of up to 2000 W.

[0093] During the plasma nitridation process, no bias may be applied to the semiconductor substrate 270. In this case, ionized nitrogen species may be accelerated by the plasma potential and subsequently implanted or merged into the exposed surface of the source / drain regions 292. Additionally or alternatively, a bias may be applied to the semiconductor substrate 270 to further accelerate the ions from the plasma, causing them to be implanted or merged deeper into the exposed surface of the source / drain regions 292. The bias also helps minimize reactions between the nitrogen ions and the dielectric materials of the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296. Either a direct current (DC) or an RF bias may be used to provide the bias to the semiconductor substrate 270. The bias may be between approximately 10 W and approximately 500 W, such as between approximately 50 W and approximately 300 W, for example, between approximately 100 W and approximately 250 W, and the frequency may be between approximately 10 MHz and approximately 30 MHz, for example, approximately 13.56 MHz. In some cases, nitrogen ions may be filtered or removed from the plasma so that only nitrogen-containing radicals such as N, NH, or NH 2 are directed toward the exposed surfaces of the source / drain regions 292 .

[0094] In any case, the nitrogen-containing radicals and / or nitrogen ions generated by the plasma may be incorporated into the exposed source / drain regions 292 to convert the surface or at least the upper portion of the source / drain regions into nitrided source / drain regions, such as Figure 9 、 Figure 10 A surface nitride layer 215 or nitride region 217 is shown. In instances where the exposed source / drain regions 292 comprise silicon germanium, the nitridation process may convert at least a portion of the silicon germanium into nitrided silicon germanium.

[0095] The above is a plasma nitridation process, but the nitridation process may be any other suitable technique such as a thermal nitridation process, an ion implantation process, or any suitable process that can generate nitrogen species or radicals. For example, some embodiments perform thermal nitridation, and the semiconductor device 240 may be located in a thermal process chamber having a nitrogen environment. The thermal process chamber may be a furnace or a rapid thermal process chamber. The nitrogen environment may be formed by providing a process gas that may consist of, essentially consist of, or include a nitrogen-containing gas such as nitrogen, ammonia, nitric oxide, nitrous oxide, a combination of nitrogen and hydrogen, and / or any mixture thereof. The temperature in the thermal process chamber may be maintained between about 650°C and about 1200°C, such as between about 750°C and about 1000°C. In one example, the exposed source / drain region 292 includes silicon germanium, and the thermal nitridation may convert at least a portion of the silicon germanium into silicon germanium nitride.

[0096] In another embodiment, an ion implantation process is performed to implant nitrogen ions into the exposed surfaces of the source / drain regions 292 to form a nitride layer, such as a silicon germanium nitride layer, on the surfaces of the exposed source / drain regions 292. During the ion implantation process, a process gas may consist of, consist essentially of, or include a nitrogen-containing gas, such as nitrogen, ammonia, nitric oxide, nitrous oxide, a combination of nitrogen and hydrogen, and / or any mixture thereof, which may form nitrogen ions and be provided to a process chamber in which the semiconductor substrate 270 is located. The process gas is then energized to form nitrogen ions and implanted into the exposed source / drain regions 292. The ion implantation energy for implanting the nitrogen ions may be between about 5 eV and about 650 eV, such as between about 20 eV and about 250 eV, for example, between about 50 eV and about 150 eV.

[0097] Step 116 optionally deposits a barrier layer 219 on the source / drain contact openings 232 on the silicide layer 214, the diffusion barrier layer 213 (eg, Figure 9 、 Figure 10 The exposed surface of the surface nitride layer 215 and the nitride region 217 as shown, as well as the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296, as shown in FIG. Figure 11A 、 Figure 11BAs shown. The thickness of barrier layer 219 may be about 2 nm or less, such as about 1.9 nm or less, or such as about 1.6 nm. In some embodiments, the thickness of barrier layer 219 is between about 1.30 nm and about 1.87 nm. Barrier layer 219 may be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, any suitable transition metal nitride or oxide, the like, or any combination thereof, and may be deposited by atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, low-pressure chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. In one example, the barrier layer is titanium nitride, and is deposited by atomic layer deposition.

[0098] Since the diffusion barrier layer 213 (such as Figure 9 、 Figure 10 The surface nitride layer 215 (or nitride region 217) is formed within and / or on the surface of the exposed source / drain regions 292. The barrier layer 219 can have a thickness that is less than the thickness of a conventional barrier layer (formed on the exposed source / drain regions 292 without the diffusion barrier layer 213 formed therebetween). For example, the thickness of the barrier layer 219 can be reduced by approximately 18% to approximately 23%, such as approximately 20%, compared to the thickness of conventional barrier layers. The barrier layer 219, together with the diffusion barrier layer 213, formed on the exposed surface of the source / drain regions 292, can provide an effective barrier to the upper portions of the source / drain regions 292 (e.g., the upper portions of the sidewalls 239 of the U-shaped trench 231), thereby preventing contact metal subsequently filled in the source / drain contact openings 232 from diffusing through the barrier layer 219 and reacting with the underlying source / drain regions 292 to form any undesirable metal silicide. Unwanted metal silicide will cause reliability issues for the device. When the total thickness of the barrier layer is kept below 2 nm, the barrier layer 219 and the diffusion barrier layer 213 can have good barrier properties, which can ensure good gap filling capability for the subsequently deposited metal contacts. In addition, the diffusion barrier layer 213 (e.g. Figure 9 The surface nitride layer 215 (or nitride region 217) shown contains nitrogen, which ensures that the layers subsequently deposited on the nitride surface of the source / drain regions 292 have excellent compliance, thereby minimizing the impact of the gap-filling ability of the layers subsequently deposited in the source / drain contact openings 232. When the barrier layer 219 is subsequently formed and deposited by atomic layer deposition, the nitrogen-containing diffusion barrier layer 213 can promote its reaction with one or more precursors of the atomic layer deposition to form the barrier layer 219, such as a transition metal nitride (e.g., titanium nitride), thereby shortening the completion time of the barrier layer 219 on the diffusion barrier layer 213.

[0099] Step 118 may deposit a conductive material 221 (e.g., a contact metal) on the barrier layer 219 (if formed) and fill the source / drain contact openings 232. The conductive material 221 may be or include cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys thereof, the like, or combinations thereof, and may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, electrochemical plating, or any suitable deposition technique. For example, after depositing the conductive material 221, a planarization process such as chemical mechanical polishing may be performed to remove excess conductive material 221 and barrier layer 219. The planarization process may remove excess conductive material 221 and barrier layer 219 that are above the top surface of the first interlayer dielectric layer 297. As a result, the conductive material 221, barrier layer 219, and the top surface of the first interlayer dielectric layer 297 may be coplanar.

[0100] Figure 13 In some embodiments, Figure 8A , to further illustrate additional details. Source / drain contact openings 232 penetrate the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296 to reach the source / drain region 292. The source / drain contact openings 232 have a first dimension D1 in the plane of the upper surface of the second interlayer dielectric layer 230 and in a direction extending vertically from a replacement gate structure to an adjacent replacement gate structure. The source / drain contact openings 232 also have a second dimension D2 from the plane of the upper surface of the second interlayer dielectric layer 230 to the upper surface of the source / drain region 292. The source / drain contact openings 232 have a third dimension D3 along the upper surface of the source / drain region 292 and in a direction extending vertically from a replacement gate structure to an adjacent replacement gate structure. The first dimension D2 may be between about 10 nm and about 30 nm, the second dimension D2 may be between about 30 nm and about 100 nm, and the third dimension D3 may be between about 8 nm and about 30 nm. The ratio (e.g., aspect ratio) between the second dimension D3 and the first dimension D1 may be greater than 2, such as between about 3 and about 10. The ratio between the second dimension D2 and the third dimension D3 may be between about 2 and about 10.

[0101] The silicide layer 214 extends laterally along the upper surface of the source / drain region 292 and has a fourth dimension D4 in a direction extending vertically from one replacement gate structure to an adjacent replacement gate structure. The silicide layer 214 has a fifth dimension D5 extending from the upper surface of the silicide layer 214 to the lower surface of the silicide layer 214. The diffusion barrier layer 213 has a sixth dimension D6 extending from the upper surface of the source / drain region 292 to the upper surface of the silicide layer 214. The diffusion barrier layer 213 has a seventh dimension D7 extending from the sidewall surface of the source / drain region 292 into the source / drain region 292. The source / drain region 292 has an eighth dimension D8 extending from the upper surface of the source / drain region 292 to the bottom of the source / drain region 292. The fourth dimension D4 may be between about 8 nm and about 40 nm, the fifth dimension D5 may be between about 3 nm and about 20 nm, the sixth dimension D6 may be between about 0.5 nm and about 10 nm, the seventh dimension D7 may be between about 0.1 nm and about 5 nm (e.g., between about 0.2 nm and about 3 nm, for example, about 1 nm), the eighth dimension D8 may be between about 20 nm and about 70 nm, and the ninth dimension D9 may be between about 1 nm and about 6 nm (e.g., between about 1 nm and about 4 nm, for example, 3 nm). The ratio between the fourth dimension D4 and the third dimension D3 may be greater than 1, such as between about 1 and about 1.3. The ratio between the fourth dimension D4 and the fifth dimension D5 may be greater than 1, such as between about 1 and about 5. The ratio between the sixth dimension D6 and the seventh dimension D7 may be greater than 1, such as between about 1 and 3. The ratio between the fourth dimension D4 and the seventh dimension D7 may be greater than 3, such as between about 5 and 20, for example, between about 8 and 12. The ratio between the sixth dimension D6 and the eighth dimension D8 may be less than about 0.8, such as between about 0.1 and about 0.6, for example, between about 0.3 and about 0.5. The ratio between the ninth dimension D9 and the seventh dimension D7 may be greater than 1, such as between about 2 and 15, for example, about 12. In some examples, the seventh dimension D7 may extend laterally into the source / drain region 292 to reach the edge of the source / drain region 292 (such as the interface between the source / drain region 292 and the gate spacer 286).

[0102] The metal layer 210 remaining on the silicide layer may have a ninth dimension D9 from the top of the metal layer 210 to the bottom of the metal layer 210. In some examples, the ratio between the ninth dimension D9 and the fifth dimension D5 may be between about 1:2 and about 1:6, such as between about 1:3 and about 1:5, for example, about 1:4.

[0103] After fabricating the semiconductor device 240 according to flowchart 100, subsequent processes may be performed to form various structures and regions. For example, subsequent processes may form multiple layers of various contacts / vias / lines and interconnect structures (e.g., metal layers and interlayer dielectric layers or intermetallic dielectric layers) on a substrate 270 including the semiconductor device 240, which are configured to connect the various structures to form a functional circuit. The functional circuit may include one or more devices such as one or more semiconductor devices 240. The various interconnect structures may use a variety of conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual damascene process may be used to form a copper-related multilayer interconnect structure. In addition, additional process steps may be performed before, during, and after flowchart 100, and some of the above steps may be replaced or omitted depending on the application.

[0104] Plasma treatment for oxide removal and passivation of oxidized metal barriers

[0105] As described in step 112 above, a selective etching process may be used to remove the remaining unreacted metal layer 210 in the source / drain contact openings 232. However, due to the high aspect ratio of the source / drain contact openings 232, the metal layer 210 has a greater thickness at the bottom 237 and a smaller thickness on the sidewalls 239, the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the surface of the contact etch stop layer 296. As a result, in some examples, after the unreacted metal layer 210 is completely removed from the sidewalls 239, the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the surface of the contact etch stop layer 296, a portion of the unreacted metal layer 210 (e.g., the titanium nitride layer in the stack of titanium layer and titanium nitride layer) may still remain on the silicide layer 214. Because the unreacted metal layer 210 remaining on the silicide layer 214 acts as a barrier layer to prevent oxidation of the silicide layer 214, various processes between and / or during the silicidation process and the contact metal formation process may significantly oxidize the barrier layer. For example, when a dual-layer metal layer 210 is used (e.g., a stack of titanium and titanium nitride layers), a selective etching process may remove a surface portion of the titanium nitride layer while leaving the bottom portion of the titanium nitride layer (and, in some cases, the underlying titanium layer) intact. Exposure of the titanium nitride layer to the etchant used in the selective etching process (used to remove the unreacted metal layer 210 in step 112) and / or to the precursor used to deposit the barrier layer 219 (when a transition metal oxide is used as the barrier layer 219 in step 116) may significantly oxidize the titanium nitride layer remaining on the silicide layer 214 (particularly the surface layer of the titanium nitride layer). A significantly oxidized barrier layer on the silicide layer 214 may significantly increase the contact resistance between the silicide layer and the contact metal region. Doing so may degrade or jeopardize device reliability.

[0106] The various embodiments described below provide an efficient and non-destructive method for removing oxide from a barrier layer formed on a silicide layer. In particular, the barrier layer can be restored to its original state and reused after processing. Figure 14 In various embodiments, an exemplary method of processing a semiconductor device, such as semiconductor device 240 , is shown in flow chart 1400 . Figure 15 、 Figure 16 In some embodiments, according to Figure 14 Partial cross-sectional views (along the channel direction) of a semiconductor device 240 at various stages of fabrication are shown in FIG.

[0107] Flowchart 1400 begins at step 1402 by providing a semiconductor device (such as semiconductor device 240 ) into a process chamber (such as a chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, or any suitable plasma chamber). Figure 15 The semiconductor device 240 is in an intermediate stage between the formation of silicide (step 112) and the surface treatment (step 114). Figure 15 The semiconductor device 240 is shown with Figure 8A The semiconductor device 240 shown is substantially the same, except that the silicide layer 214 has a substantially oxidized barrier layer 1502 formed thereon. As described above, the barrier layer 1502 may be substantially oxidized due to the exposure of the metal layer 210 to the etchant and precursors used in the selective etching process (step 112) and / or the redeposition of the barrier layer 219 (step 116). As previously described, the metal layer 210 may be a bilayer, wherein the first layer may be or include titanium, tantalum, or the like, and the second layer may be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or the like. Figure 15 In the example shown, the substantially oxidized barrier layer 1502 includes a first layer 1504 of titanium and a second layer of titanium nitride. In some examples, the first layer 1504 is not present between the silicide layer 214 and the second layer 1506. For example, the silicidation process may consume all of the first layer 1504 in the source / drain regions 292 to form the silicide layer 214. Figure 15 1510 in Figure 15 The partially enlarged view of the portion enclosed by the dashed circle shows a first titanium layer 1504 positioned between the silicide layer 214 and a second titanium nitride layer 1506, wherein the second titanium nitride layer 1506 has an oxidized surface layer 1508. The oxidized surface layer 1508 is formed by substantially oxidizing the second layer 1506. Although titanium is used for illustration, the concept is equally applicable to any metal or dielectric material.

[0108] In step 1404, the semiconductor device 240 is placed in a process chamber for a pre-cleaning process 1512. The pre-cleaning process 1512 may include a first plasma treatment to reduce the metal barrier oxide, followed by a second plasma treatment to passivate the reduced metal barrier layer to prevent further oxidation of the metal barrier layer. During the reduction process, a reducing agent may be introduced into a vacuum chamber, and a frequency power may be coupled to the reducing agent to initiate a plasma. The plasma may excite the reducing agent to an energized ion state. The energized ions may chemically react with the metal oxide to remove oxygen from the oxidized surface layer 1508 and reduce the metal oxide to metal.

[0109] In various embodiments, the reducing agent may be hydrogen atoms (e.g., hydrogen atoms formed by dissociation of hydrogen molecules), hydrogen radicals, and / or energetically excited neutral hydrogen species, which may be generated from an in-situ hydrogen-containing gas or generated from a hydrogen-containing gas in a remote plasma reaction. The remote plasma reactor is separate from the process chamber in which the semiconductor device 240 is located. Suitable hydrogen-containing gases may include hydrogen, ammonia, hydrazine, or any combination thereof.

[0110] When second layer 1506 is titanium nitride, oxidized surface layer 1508 may have Ti-ON bonds and / or Ti-O bonds in the surface portion of the crystal lattice. During the first plasma treatment, energized ions, radicals, and / or neutral species of hydrogen from the reducing agent may disrupt the Ti-ON bonds and / or Ti-O bonds in the surface portion of oxidized surface layer 1508, thereby chemically reacting with oxidized surface layer 1508. Oxygen removed from oxidized surface layer 1508 may react with hydrogen to produce byproducts such as water and leave oxygen vacancies in the crystal lattice. The first plasma treatment removes oxygen without damaging the crystal lattice of the surface portion of barrier layer 1502. Thus, the crystal lattice and thickness of the barrier layer may be preserved.

[0111] After reducing the oxidized surface layer 1508, the semiconductor device 240 may be subjected to a second plasma treatment (e.g., a nitrogen plasma) to incorporate nitrogen into the oxygen vacancies created by removing oxygen from the crystal lattice. The nitrogen bonds with titanium to form titanium nitride in the surface of the barrier layer 1502. As a result, a portion of the surface of the barrier layer 1502 may be restored to its original state (e.g., titanium nitride). The nitrogen plasma also passivates the surface of the barrier layer 1502 with nitrogen to prevent reoxidation of the barrier layer 1502 during subsequent processing. The nitrogen plasma may be formed from a nitrogen-containing gas in situ or in a remote plasma reactor separate from the process chamber in which the semiconductor device 240 is located. Suitable nitrogen-containing gases may include nitrogen, ammonia, or a combination thereof.

[0112] In addition to using two different plasma processes, in some embodiments, pre-cleaning process 1512 is a single plasma treatment that may utilize a hydrogen- and nitrogen-containing reactant to chemically reduce and passivate the oxidized surface layer 1508 during the pre-cleaning process. In this example, the reactant may be one or more of the aforementioned hydrogen-containing and / or nitrogen-containing gases, or a mixture of gases. In some embodiments, the reactant is ammonia. In some embodiments, the reactants are hydrogen and nitrogen. In some embodiments, the reactants are hydrogen and ammonia. In some embodiments, the reactants are nitrogen and ammonia. In some embodiments, the reactant is hydrogen. In some embodiments, the reactant is nitrogen.

[0113] In any case, no bias may be applied to the semiconductor substrate 270. In this case, ionized hydrogen and / or nitrogen species may be accelerated by the plasma potential and then incorporated into the oxidized surface layer 1508 during the pre-clean process 1512. A bias may additionally or alternatively be applied to the semiconductor substrate 270 to further accelerate the ions from the plasma and implant or incorporate the ions deeper into the oxidized surface layer 1508. The bias also helps minimize reactions between the hydrogen and / or nitrogen ions and the dielectric materials of the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296. Either a direct current or an RF bias may be used to provide the bias to the semiconductor substrate 270. If desired, the pre-clean process may be performed in one or more processing cycles, with the pre-clean process purged between cycles.

[0114] In at least some embodiments, when hydrogen and nitrogen are used to reduce the oxide surface layer 1508 (e.g., titanium oxide), exemplary process parameters include substrate temperature and chamber pressure. The substrate temperature can be maintained between about room temperature and about 450°C, such as between about 150°C and about 350°C, or about 200°C. The chamber pressure can be maintained between about 1 mTorr and about 10 Torr, such as between about 1.5 mTorr and about 10 mTorr, or about 2 mTorr and about 5 mTorr. The plasma can be generated by applying power from a dual-frequency RF power source, wherein a first RF power has a frequency between about 1 MHz and about 60 MHz, such as about 13.56 MHz, and a power between about 200 W and about 1000 W, such as about 600 W and about 950 W, or about 900 W. The second RF power has a frequency between about 10 kHz and about 20 MHz, such as between about 100 kHz and about 500 kHz, and a power between about 1 W and about 200 W, such as about 150 W. The power density of the plasma can be between about 1 W / cm 2 to about 10W / cm 2 between, such as about 2W / cm 2 to about 8W / cm 2 between, for example, about 4W / cm2 to about 6W / cm 2 The bias voltage provided may be between about 10 W and about 500 W, such as between about 50 W and about 300 W, for example, between about 100 W and about 250 W, and the frequency may be between about 10 MHz and about 30 MHz, for example, about 13.56 MHz. The spacing between the electrodes (e.g., the distance between the substrate and the showerhead) may be between about 200 mils and about 1000 mils, for example, between about 280 mils and about 300 mils. The first flow rate of hydrogen gas provided to the process chamber may be between about 100 sccm and about 12,000 sccm, and the second flow rate of nitrogen gas provided to the process chamber may be between about 100 sccm and about 8,000 sccm. The ratio between the first flow rate and the second flow rate may be controlled to be between about 1:1 and about 6:1, such as between about 2.5:1 and about 5:1, for example, between about 3:1 and about 4:1. Furthermore, the carrier gas may be combined with the aforementioned process parameters to help stabilize the gas flow and plasma reaction. The flow rate of a carrier gas, such as helium, argon, or nitrogen, may be between approximately 0 sccm and 2000 sccm. The pre-clean process may last between approximately 25 seconds and approximately 180 seconds, such as between approximately 50 seconds and approximately 80 seconds, or for example, between approximately 60 seconds and approximately 70 seconds. It is contemplated that these parameters may vary depending on the application, process chamber configuration, and the materials being processed.

[0115] Whether the pre-cleaning process 1512 is a single step or a double step plasma treatment, the oxidized surface layer 1508 can be reduced, treated, or modified. After the pre-cleaning process 1512, the oxidized surface layer 1508 can be restored to its original state (e.g., titanium nitride). The treated barrier layer 1502 has a minimized oxygen content in its surface. For example, the surface of the barrier layer after the pre-cleaning process (e.g., the surface of the barrier layer after the pre-cleaning process) can be measured by X-ray photoelectron spectroscopy. Figure 16 The barrier layer 1514 shown (with its passivated surface 1509) can be found to have an oxygen concentration reduced to 6% or less (e.g., 3% or less). For example, when hydrogen and nitrogen are used as reactants in the pre-clean process, the surface oxygen concentration can be reduced to 2.42%. When ammonia is used as a reactant in the pre-clean process, the surface oxygen concentration can be reduced to 2.48%. When hydrogen is used as a reactant in the pre-clean process, the surface oxygen concentration can be reduced to 5.76%. When nitrogen is used as a reactant in the pre-clean process, the surface oxygen concentration can be reduced to 3.45%. In any case, the contact resistance at the interface between the silicide layer and the contact metal can be reduced, thereby improving device reliability.

[0116] The process described in flowchart 1400 can be incorporated into flowchart 100 and performed in any desired order or combination. For example, the process described in flowchart 1400 can be performed between steps 112 and 114. In some embodiments, the surface treatment described in step 114 can be omitted or eliminated. Thus, after step 112, the process described in flowchart 1400 can be performed, followed by step 116. Figure 16 An example of a semiconductor device 240 is shown, in which a barrier layer and a conductive material (eg, barrier layer 219 and conductive material 221 ) are sequentially formed on a processed barrier layer 1514 (eg, a titanium nitride layer or a stack of titanium and titanium nitride layers). Figure 16 1516 in Figure 16 The enlarged view of the portion of the dotted circle in the middle shows that the first layer 1504 of titanium is located between the silicide layer 214 and the second layer 1506 of titanium nitride, and the second layer 1506 of titanium nitride is subjected to the pre-cleaning process described in process 1400. In this example, no diffusion barrier layer (such as the diffusion barrier layer 213 described in step 114) is provided on the surface of the exposed source / drain region 292. Therefore, the second layer 1506 (such as a reduced barrier layer) can have a treated or passivated surface 1509. For example, although Figure 16 The first layer 1504 is shown. In some examples, the first layer 1504 may not exist between the silicide layer 214 and the second layer 1506 . That is, the silicidation process may consume the first layer 1504 in the source / drain regions 292 to form the silicide layer 214 .

[0117] The various embodiments described herein may provide various advantages. It should be understood that not all advantages need be described herein, any embodiment need not have a particular advantage, and other embodiments may provide different advantages. For example, the embodiments described herein include methods and structures regarding a surface treatment process that nitrides the exposed source / drain regions to form an effective metal diffusion barrier on the surface of the exposed source / drain regions, and forms a barrier layer on the nitrided regions. The above process can prevent the contact metal subsequently filled in the source / drain contact openings from diffusing through the barrier layer and reacting with the underlying source / drain regions to form unwanted metal silicides. Unwanted metal silicides may cause reliability issues for the device. The barrier layer and the metal diffusion barrier layer still maintain excellent barrier properties while maintaining the total thickness of the barrier layer to less than 2 nm, which ensures that the subsequently deposited metal contacts have excellent gap filling capabilities.

[0118] In another example, embodiments described herein include a method for a pre-cleaning process comprising a first plasma treatment to reduce a metal barrier oxide, followed by a second plasma treatment to passivate the reduced metal barrier layer to prevent further oxidation of the metal barrier layer. The pre-cleaning process removes oxygen from the metal barrier oxide without damaging the crystal lattice of the surface portion of the metal barrier layer. This maintains the thickness of the barrier layer. Specifically, it reduces the contact resistance at the interface between the silicide and the subsequently deposited contact metal. The less oxidized, purified interface also improves adhesion between the silicide and the contact, enhancing reliability.

[0119] In one embodiment, a semiconductor structure is provided. The semiconductor structure includes an active region on a substrate, the active region including source / drain regions, the source / drain regions having sidewalls and lateral surfaces extending laterally from the sidewalls of the source / drain regions, the source / drain regions further including nitride regions extending laterally from the sidewalls of the source / drain regions into the source / drain regions; a dielectric layer located on the active region and having sidewalls aligned with the sidewalls of the source / drain regions; and a conductive structure extending along the sidewalls of the dielectric layer to the source / drain regions, the conductive structure including a silicide region, the silicide region extending along the lateral surfaces of the source / drain regions and along at least a portion of the sidewalls of the source / drain regions.

[0120] In some embodiments, the conductive structure of the semiconductor structure further includes a barrier layer formed on the silicide region, wherein the barrier layer is a transition metal nitride or a transition metal oxide.

[0121] In some embodiments, the conductive structure of the semiconductor structure further includes a conductive material formed on the barrier layer, and the barrier layer is in physical contact with the conductive material.

[0122] In some embodiments, the nitride region of the semiconductor structure has a first thickness, the barrier layer has a second thickness, and a ratio between the first thickness and the second thickness is between 1:2 and 1:15.

[0123] In some embodiments, the nitride region of the semiconductor structure has a first dimension from the upper surface of the source / drain region to the upper surface of the silicide region, and the source / drain region has a second dimension from the upper surface of the source / drain region to the lower surface of the source / drain region, and the ratio between the first dimension and the second dimension is between 0.1 and 0.6.

[0124] In another embodiment, a method is provided that includes forming source / drain regions in an active region on a substrate, forming a dielectric layer on the active region, forming an opening through the dielectric layer, and the opening extending into the source / drain region to form a trench in the source / drain region, with the lower surface and sidewalls at least partially defining the trench, forming a silicide region on the lower surface of the trench, nitriding at least a portion of the source / drain region through the sidewalls of the trench, and filling the opening with a conductive material.

[0125] In some embodiments, the method further comprises nitriding at least a portion of the source / drain regions along the sidewalls of the trench, thereby exposing the sidewalls not covered by the silicide region to nitrogen ions from the plasma.

[0126] In some embodiments, the method further comprises nitriding at least a portion of the source / drain regions along the sidewalls of the trench, thereby exposing the sidewalls not covered by the silicide to nitrogen-containing radicals generated from the plasma.

[0127] In some embodiments, before filling the opening with the conductive material, the method further includes forming a compliant barrier layer in the opening, wherein the compliant barrier layer covers the nitrided portion of the source / drain region.

[0128] In some embodiments, the method further includes applying a bias voltage to the substrate when nitriding at least a portion of the source / drain region through the sidewalls of the trench.

[0129] In some embodiments, the method further includes nitriding at least a portion of the source / drain region through the sidewalls of the trench by ion implantation to implant nitrogen into the sidewalls of the trench not covered by the silicide region.

[0130] In another embodiment, a method is provided that includes forming source / drain regions in an active region on a substrate, allowing a metal barrier layer formed on a surface of the source / drain region to react with the source / drain region to form a metal silicide on the surface of the source / drain region, wherein the metal barrier layer has a metal oxide on the surface of the metal barrier layer, and performing a pre-cleaning process on the metal barrier layer, wherein the pre-cleaning process includes reducing the metal oxide and passivating the reduced metal barrier layer.

[0131] In some embodiments, the metal barrier layer of the above method comprises titanium nitride, and the metal oxide is formed on the titanium nitride.

[0132] In some embodiments, the reduction process of the above method includes exposing the metal oxide to a plasma including a hydrogen-containing gas and a nitrogen-containing gas.

[0133] In some embodiments, the hydrogen-containing gas is introduced into the process chamber at a first flow rate, and the nitrogen-containing gas is introduced into the process chamber at a second flow rate. The ratio of the first flow rate to the second flow rate is between about 1:1 and about 6:1.

[0134] In some embodiments, the passivation process of the above method includes incorporating nitrogen into the reduced metal barrier layer.

[0135] In some embodiments, the reduction process of the above method includes exposing the metal oxide to hydrogen radicals or neutral species of hydrogen.

[0136] In some embodiments, the hydrogen radicals or neutral hydrogen species of the above methods are formed from a gas comprising ammonia or a gas comprising hydrogen and nitrogen.

[0137] In some embodiments, the method further comprises applying a bias voltage to the substrate during the pre-cleaning process.

[0138] In another embodiment, a semiconductor structure is provided, including an active region on a substrate, wherein the active region includes a source / drain region; a dielectric layer is located on the active region; and a conductive structure passes through the dielectric layer to reach the source / drain region, and the conductive structure includes a silicide region on the surface of the source / drain region; a first barrier layer is formed on the silicide region, and the first barrier layer includes a transition metal nitride layer on the silicide region; a second barrier layer is located on the first barrier layer, wherein the surface oxygen concentration of the interface between the first barrier layer and the second barrier layer is less than or equal to 3%; and a conductive material is located on the second barrier layer and contacts the second barrier layer.

[0139] In some embodiments, the transition metal nitride layer of the semiconductor structure is titanium nitride or tantalum nitride.

[0140] In some embodiments, the second barrier layer of the semiconductor structure is titanium nitride, tantalum nitride, or a combination thereof.

[0141] In some embodiments, the first barrier layer of the semiconductor structure further includes a second transition metal layer on the silicide region, and the second transition metal layer is located between the silicide region and the transition metal nitride layer.

[0142] In some embodiments, the second transition metal layer of the semiconductor structure is titanium or tantalum.

[0143] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the embodiments of the present invention may be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and may be altered, replaced, or modified without departing from the spirit and scope of the claims of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming a source / drain region in an active region on a substrate; forming a dielectric layer on the active region; forming an opening through the dielectric layer, the opening extending into the source / drain region to form a trench in the source / drain region, with a lower surface and a sidewall at least partially defining the trench; forming a silicide region on the lower surface of the trench; nitriding at least a portion of the source / drain region through the sidewall of the trench; as well as A conductive material is filled into the opening.

2. The method for forming a semiconductor structure according to claim 1 , wherein the step of nitriding at least the portion of the source / drain region through the sidewall of the trench exposes the sidewall not covered by the silicide region to nitrogen ions from a plasma.

3. The method for forming a semiconductor structure according to claim 1 , wherein the step of nitriding at least the portion of the source / drain region through the sidewall of the trench exposes the sidewall not covered by the silicide to nitrogen-containing radicals generated from a plasma. 4 . The method for forming a semiconductor structure according to claim 1 , wherein before filling the opening with the conductive material, the method further comprises forming a compliant barrier layer in the opening, wherein the compliant barrier layer covers the nitrided portion of the source / drain region. 5 . The method for forming a semiconductor structure as claimed in claim 1 , further comprising applying a bias voltage to the substrate when nitriding at least the portion of the source / drain region through the sidewall of the trench.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of nitriding at least the portion of the source / drain region through the sidewall of the trench comprises ion implantation to implant nitrogen into the sidewall of the trench not covered by the silicide region.

7. A method for forming a semiconductor structure, comprising: forming a source / drain region in an active region on a substrate; forming a dielectric layer on the source / drain region; forming an opening through the dielectric layer, wherein the opening extends into the source / drain region to form a trench in the source / drain region; Allowing a metal layer formed on the surface of the source / drain region to react with the source / drain region to form a metal silicide on the surface of the source / drain region at the lower surface of the trench, wherein the metal layer has a metal oxide on the surface of the metal layer; removing an unreacted portion of the metal layer, wherein a remaining portion of the metal layer remains on the metal silicide layer; performing a pre-cleaning process on the remaining portion of the metal layer, wherein the pre-cleaning process includes performing a reduction process on the metal oxide and performing a passivation process on the reduced metal layer; as well as After the pre-cleaning process is performed on the remaining portion of the metal layer, a barrier layer is formed on the remaining portion of the metal layer. 8 . The method for forming a semiconductor structure as claimed in claim 7 , wherein the metal layer comprises titanium nitride, and the metal oxide is formed on the titanium nitride. 9 . The method for forming a semiconductor structure according to claim 7 , wherein the reduction process comprises exposing the metal oxide to a plasma comprising a hydrogen-containing gas and a nitrogen-containing gas.

10. The method for forming a semiconductor structure according to claim 9, wherein the hydrogen-containing gas is introduced into a process chamber at a first flow rate, the nitrogen-containing gas is introduced into the process chamber at a second flow rate, and a ratio between the first flow rate and the second flow rate is 1:1 to 6:

1. 11 . The method for forming a semiconductor structure as claimed in claim 7 , wherein the passivation process comprises incorporating nitrogen into the reduced metal layer. 12 . The method for forming a semiconductor structure as claimed in claim 7 , wherein the reduction process comprises exposing the metal oxide to hydrogen radicals or neutral hydrogen species. 13 . The method for forming a semiconductor structure as claimed in claim 12 , wherein the hydrogen radicals or neutral hydrogen species are formed from a gas comprising ammonia or a gas comprising hydrogen and nitrogen. 14 . The method for forming a semiconductor structure as claimed in claim 7 , further comprising applying a bias voltage to the substrate during the pre-cleaning process.

15. The method for forming a semiconductor structure according to claim 7, further comprising: nitriding at least a portion of the source / drain region through a sidewall of the trench; as well as After forming the barrier layer, a conductive material is filled into the opening.

16. A method for forming a semiconductor structure, comprising: forming a source / drain region on an active region on a substrate; forming a dielectric layer on the active region; forming an opening through the dielectric layer, wherein the opening extends into the source / drain region to form a trench in the source / drain region; forming a metal layer along the sidewalls and bottom of the trench; forming a silicide region on the surface of the source / drain region along the bottom of the trench; removing an untreated portion of the metal layer along a sidewall of the trench, wherein at least one untreated portion of the metal layer remains at a bottom of the trench; nitriding at least a portion of the source / drain region through a sidewall of the trench; performing a pre-cleaning process on the unreacted portion of the metal layer, the pre-cleaning process comprising a reduction process of the metal oxide on the unreacted portion of the metal layer and a passivation process on the reduced unreacted portion of the metal layer; as well as A conductive material is filled into the opening. 17 . The method for forming a semiconductor structure according to claim 16 , wherein the reduction process comprises exposing the metal oxide to a plasma comprising a hydrogen-containing gas and a nitrogen-containing gas. 18 . The method for forming a semiconductor structure as claimed in claim 17 , wherein the passivation process comprises incorporating nitrogen into unreacted portions of the reduced metal layer. 19 . The method for forming a semiconductor structure according to claim 18 , wherein the step of nitriding at least the portion of the source / drain region through the sidewall of the trench exposes the sidewall not covered by the silicide region to nitrogen ions from a plasma. 20 . The method for forming a semiconductor structure according to claim 18 , wherein the step of nitriding at least the portion of the source / drain region through the sidewall of the trench exposes the sidewall not covered by the silicide region to nitrogen-containing radicals generated from a plasma.

21. A semiconductor structure, characterized in that include: an active region located on a substrate, the active region including a source / drain region having a sidewall and a lateral surface extending laterally from the sidewall of the source / drain region, the source / drain region further including a nitride region extending laterally from the sidewall of the source / drain region into the source / drain region; a dielectric layer located on the active region and having a sidewall aligned with the sidewall of the source / drain region; as well as A conductive structure is arranged along the sidewall of the dielectric layer to the source / drain region, the conductive structure including a silicide region, and the silicide region is along the lateral surface of the source / drain region and along at least a portion of the sidewall of the source / drain region.

22. The semiconductor structure of claim 21, wherein the conductive structure further comprises: A barrier layer is formed on the silicide region, wherein the barrier layer comprises a transition metal nitride or a transition metal oxide. 23 . The semiconductor structure of claim 22 , wherein the barrier layer comprises a first sublayer and a second sublayer located on the first sublayer, wherein the first sublayer comprises a transition metal, and the second sublayer comprises a transition metal nitride or a transition metal oxide.

24. The semiconductor structure of claim 22, wherein the conductive structure further comprises: A conductive material is formed on the barrier layer, and the barrier layer physically contacts the conductive material. 25 . The semiconductor structure of claim 22 , wherein the nitride region has a first thickness, the barrier layer has a second thickness, and a ratio of the first thickness to the second thickness is 1:2 to 1:

15.

26. The semiconductor structure of claim 21 , wherein the nitride region has a first dimension measured from an upper surface of the source / drain region to an upper surface of the silicide region, the source / drain region has a second dimension measured from an upper surface of the source / drain region to a bottom of the source / drain region, and a ratio of the first dimension to the second dimension is 0.1 to 0.

6.

27. A semiconductor structure comprising: An active region located on a substrate, and the active region includes a source / drain region; a dielectric layer located on the active region; an opening passing through the dielectric layer and extending into the source / drain region to form a trench in the source / drain region; as well as a conductive structure extending through the dielectric layer to the source / drain region, and comprising: a silicide region located on a surface of the source / drain region at a lower surface of the trench; a first barrier layer formed on the silicide region, wherein the first barrier layer comprises a transition metal nitride layer on the silicide region; a second barrier layer disposed on the first barrier layer, wherein a surface oxygen concentration at an interface between the first barrier layer and the second barrier layer is less than or equal to 3%; and A conductive material is located on the second barrier layer and contacts the second barrier layer.

28. The semiconductor structure of claim 27, wherein the transition metal nitride layer is titanium nitride or tantalum nitride.

29. The semiconductor structure of claim 27, wherein the second barrier layer is titanium nitride, tantalum nitride, or a combination thereof. 30 . The semiconductor structure of claim 27 , wherein the first barrier layer further comprises a second transition metal layer located on the silicide region and between the silicide region and the transition metal nitride layer. The semiconductor structure of claim 30 , wherein the second transition metal layer is titanium or tantalum.

32. The semiconductor structure of claim 27, wherein the silicide region is recessed below a top surface of the active region, and wherein the active region comprises a nitride region along a sidewall of the active region extending from the silicide region to a top surface of the active region.

33. The semiconductor structure of claim 32, wherein the nitride region extends along a sidewall of the silicide region.

34. A semiconductor structure comprising: a semiconductor region comprising a first semiconductor material; a silicide region located on the semiconductor region and comprising a silicide of the first semiconductor material; a metal layer located on the silicide region and comprising a first metal, wherein the silicide region comprises a silicide of the first metal; a nitride layer along the sidewalls of the semiconductor region, and the nitride layer extends from the silicide region to the upper surface of the semiconductor region; as well as A conductive structure is located on the metal layer. 35 . The semiconductor structure as claimed in claim 34 , further comprising a barrier layer interposed between the conductive structure and the metal layer. 36 . The semiconductor structure of claim 35 , wherein the barrier layer is interposed between the conductive structure and the nitride layer.

37. The semiconductor structure of claim 35, wherein the nitride layer extends along sidewalls of the silicide region. 38 . The semiconductor structure of claim 34 , wherein a ratio of a thickness of the nitride layer to a thickness of the silicide region is 1:2 to 1:

6. The semiconductor structure of claim 34 , wherein a sidewall of the metal layer does not have the nitride layer. The semiconductor structure of claim 34 , wherein a lower surface of the metal layer does not have the nitride layer.

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