System and method for pulse width modulation using adjustable comparison criteria

Abstract

The present application relates to systems and methods for pulse width modulation using an adjustable comparison criterion. A pulse width modulation control circuit includes a first transistor and a signal generator. The first transistor includes a first terminal coupled to a power supply and a second terminal coupled to a first input terminal of a controlled component. The signal generator includes a first node coupled to a gate of the first transistor. The signal generator is configured to receive a comparison value and a comparison criterion, and compare the comparison value with a counter value based on the comparison criterion. In response to the comparison value satisfying the comparison criterion relative to the counter value, the signal generator is configured to send a control signal to the gate of the first transistor to generate a pulse edge of a pulse of a pulse width modulated signal.

Description

Technical Field

[0001] The present disclosure relates generally to pulse width modulation and gimbaled inertial measurement units. Background Art

[0002] Gimbaled inertial measurement units are used for vehicle navigation and object tracking. A gimbaled inertial measurement unit includes multiple gimbals, each of which rotates along a single axis to position the sensor along the path of the vehicle. By using multiple gimbals (e.g., three or four gimbals), the inertia of the vehicle can be monitored by sensors on multiple axes and used for inertial navigation. Inertial navigation continuously calculates the position, orientation, and velocity of a moving object by dead reckoning without an external reference. Dead reckoning (or deductive reckoning) involves calculating the current position of a vehicle by using a previously determined position and advancing that position based on an estimated velocity and heading.

[0003] The gimbal inertial measurement unit includes additional sensors, such as resolvers, to determine the position of the motors that drive each of the multiple gimbals and locate the sensors that track the inertia of the vehicle. The resolver is an analog sensor used to determine the rotational position (e.g., angle). The resolver receives an excitation signal and generates analog output signals, which are converted into digital samples. The digital samples are used to determine the position of the motor and the gimbal. During the conversion from analog to digital or during the processing of the digital samples into an angle output, the position output determined based on the output analog signal may lose accuracy. In addition, interference from current switching during the operation of the gimbal motor can increase noise and errors. In inertial navigation, reduced accuracy and errors can accumulate over time, resulting in incorrect data or navigation.

[0004] Complex discrete solutions are often used to increase the accuracy or bandwidth of a gimbaled inertial measurement unit as required by the mission or design requirements. However, these solutions do not usually provide both increased accuracy and increased bandwidth. In addition, these solutions increase the complexity, cost, weight, and volume of the vehicle design. In the context of flying vehicles (aircraft, spacecraft, etc.), weight and volume significantly increase cost and reduce performance. Summary of the invention

[0005] In a particular embodiment, a device includes a coarse resolver configured to output a coarse position signal representing a coarse position of a drive shaft of a motor. The device also includes a fine resolver configured to output a fine position signal representing a fine position of the drive shaft of the motor. The device also includes a control circuit. The control circuit is configured to receive the coarse position signal from the coarse resolver and the fine position signal from the fine resolver, and generate an initial position output indicating an initial position of the drive shaft based on the coarse position signal. The control circuit is also configured to generate a subsequent position output indicating a subsequent position of the drive shaft based on the fine position signal.

[0006] In another specific embodiment, a method of determining a rotational position includes receiving a coarse position signal from a coarse resolver and a fine position signal from a fine resolver. The coarse position signal indicates a coarse position of a drive shaft of a motor, and the fine position signal indicates a fine position of the drive shaft of the motor. The method also includes generating an initial position output indicating an initial position of the drive shaft based on the coarse position signal. The method also includes generating a subsequent position output indicating a subsequent position of the drive shaft based on the fine position signal.

[0007] In yet another specific embodiment, a non-transitory computer readable medium stores instructions that, when executed by a processor, cause the processor to receive a coarse position signal from a coarse resolver and a fine position signal from a fine resolver. The coarse position signal indicates a coarse position of a drive shaft of a motor, and the fine position signal indicates a fine position of the drive shaft of the motor. The instructions also cause the processor to generate an initial position output indicating an initial position of the drive shaft based on the coarse position signal, and to generate a subsequent position output indicating a subsequent position of the drive shaft based on the fine position signal.

[0008] In a particular embodiment, a pulse width modulation control circuit includes a first transistor and a signal generator. The first transistor includes a first terminal coupled to a power supply and a second terminal coupled to a first input of a controlled component. The signal generator includes a first node coupled to a gate of the first transistor. The signal generator is configured to receive a comparison value and a comparison criterion, and compare the comparison value with a counter value based on the comparison criterion. In response to the comparison value satisfying the comparison criterion relative to the counter value, the signal generator is configured to send a control signal to the gate of the first transistor to generate a pulse edge of a pulse of a pulse width modulation signal.

[0009] In another specific embodiment, a system includes a motor and a pulse width modulation control circuit coupled to the motor. The pulse width modulation control circuit is configured to output a pulse width modulated signal to the motor. The pulse width modulation control circuit includes a first transistor and a signal generator. The first transistor includes a first terminal coupled to a power supply and a second terminal coupled to a first input of the motor. The signal generator includes a first node coupled to a gate of the first transistor. The signal generator is configured to receive a comparison value and a comparison criterion, and compare the comparison value with a counter value based on the comparison criterion. In response to the comparison value satisfying the comparison criterion relative to the counter value, the signal generator is configured to send a control signal to the gate of the first transistor to generate a pulse edge of a pulse of the pulse width modulated signal.

[0010] In yet another specific embodiment, a method of pulse width modulation includes receiving a comparison value and a comparison criterion, and includes comparing the comparison value to a counter value based on the comparison criterion. The method also includes: in response to the comparison value satisfying the comparison criterion relative to the counter value, sending a control signal to a gate of a first transistor to generate a pulse edge of a pulse of a pulse width modulation signal.

[0011] In a particular embodiment, the feedback control circuit includes a rate limiter circuit configured to generate a rate limited position command based on a position command of the controlled component and based on a speed command of the controlled component. The feedback control circuit also includes an error adjustment circuit configured to apply a control gain to an error signal to generate an adjusted error signal. The error signal is based on the position feedback and the rate limited position command, and the position feedback indicates a position of the controlled component. The feedback control circuit also includes an output terminal configured to output a current command generated based on the adjusted error signal.

[0012] In another specific embodiment, a system includes a motor and a feedback control circuit coupled to the motor. The feedback control circuit includes a rate limiter circuit configured to generate a rate limited position command based on a position command of the motor and based on a speed command of the motor. The feedback control circuit also includes an error adjustment circuit configured to apply a control gain to an error signal to generate an adjusted error signal. The error signal is based on position feedback and the rate limited position command, and the position feedback indicates a position of the motor. The feedback control circuit also includes an output terminal configured to output a current command generated based on the adjusted error signal.

[0013] In yet another specific embodiment, a method for feedback control includes receiving a position command of a controlled component and a velocity command of the controlled component, and includes generating a rate-limited position command based on the velocity command and the position command. The method also includes receiving position feedback indicating a position of the controlled component, and applying a control gain to an error signal to generate an adjusted error signal. The error signal is based on the position feedback and the rate-limited position command. The method also includes outputting a current command based on the adjusted error signal.

[0014] In a particular embodiment, the demodulation circuit includes an input terminal configured to be coupled to an analog-to-digital converter (ADC) and configured to receive a plurality of ADC outputs. The plurality of ADC outputs are generated based on the resolver output. The demodulation circuit also includes a rectifier configured to rectify the plurality of ADC outputs. Rectifying the plurality of ADC outputs preserves the phase of the plurality of ADC outputs. The demodulation circuit includes an amplitude determination circuit configured to determine a demodulated amplitude value corresponding to the resolver output based on the rectified plurality of ADC outputs. The demodulation circuit also includes an angle calculation circuit configured to generate a position output based on the demodulated amplitude value.

[0015] In another specific embodiment, a system includes a resolver, an ADC coupled to the resolver, and a demodulation circuit coupled to the ADC. The demodulation circuit is configured to generate a demodulated resolver output and includes an input terminal configured to be coupled to the ADC and configured to receive multiple ADC outputs. Multiple ADC outputs are generated based on the resolver output. The demodulation circuit also includes a rectifier configured to rectify multiple ADC outputs. Rectifying multiple ADC outputs retains the phase of multiple ADC outputs. The demodulation circuit includes an amplitude determination circuit configured to determine a demodulated amplitude value corresponding to the resolver output based on the rectified multiple ADC outputs. The demodulation circuit also includes an angle calculation circuit configured to generate a position output based on the demodulated amplitude value.

[0016] In yet another specific embodiment, a method for demodulating a resolver output includes receiving a plurality of ADC outputs from an ADC. The plurality of ADC outputs are generated based on the resolver outputs. The method also includes rectifying the plurality of ADC outputs, and rectifying the plurality of ADC outputs preserves the phase of the plurality of ADC outputs. The method includes determining a demodulated amplitude value corresponding to the resolver output based on the rectified plurality of ADC outputs. The method also includes generating a position output based on the demodulated amplitude value.

[0017] In a particular embodiment, the jitter circuit includes a harmonic signal generating circuit configured to generate high-order even harmonics of a fundamental excitation signal. The jitter circuit also includes a combiner configured to generate a jitter excitation signal based on the high-order even harmonics and the fundamental excitation signal. The jitter circuit also includes an output terminal configured to output the jitter excitation signal to the sensor device.

[0018] In another specific embodiment, a system includes a solver, a digital-to-analog converter (DAC) coupled to the solver, and a jitter circuit coupled to the DAC. The jitter circuit is configured to output a jitter excitation signal to the DAC. The jitter circuit includes a harmonic signal generating circuit, which is configured to generate high-order even harmonics of a fundamental excitation signal. The jitter circuit also includes a combiner, which is configured to generate a jitter excitation signal based on the high-order even harmonics and the fundamental excitation signal. The jitter circuit also includes an output terminal, which is configured to output the jitter excitation signal to the solver.

[0019] In yet another specific embodiment, a method of generating an excitation signal for a sensor device includes generating higher-order even harmonics of a fundamental excitation signal. The method also includes generating a dithered excitation signal based on combining the higher-order even harmonics and the fundamental excitation signal, and outputting the dithered excitation signal to the sensor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram showing an example of an inertial measurement unit;

[0021] Figure 2 is a schematic diagram showing an example of a system of an inertial measurement unit;

[0022] Figure 3 is a schematic diagram showing an example of the operation of an inertial measurement unit;

[0023] Figure 4A A schematic diagram showing an example of a transformer;

[0024] Figure 4B A schematic diagram showing an example of a solver;

[0025] Figure 4C An exemplary graph showing signals of a dual speed resolver;

[0026] Figure 5 is a schematic diagram showing an example of a flow process for processing a resolver output of a dual speed resolver;

[0027] Figure 6 is a logic diagram showing an overview of an example of logic for processing a resolver output of a dual speed resolver;

[0028] Figure 7 is a logic diagram showing an overview of the logic used for demodulation and angle estimation;

[0029] Figure 8 is a logic diagram showing an example of logic for voltage regulation;

[0030] Fig. 9 is a logic diagram illustrating an example of recursive median analysis logic for recursive median analysis;

[0031] Fig.10 It is shown Figure 8 A logic diagram of an example of demodulation logic;

[0032] Fig.11 is a logic diagram showing an example of logic for rectification with phase preservation;

[0033] Fig.12 A schematic diagram showing exemplary signals generated during demodulation;

[0034] Fig.13 Show Figure 4B An exemplary graph of a signal of a resolver of;

[0035] Fig.14 It is shown Fig.10 A logic diagram of an example of mask logic;

[0036] Fig.15 is a schematic diagram showing an example of mask data and accumulated data for demodulation;

[0037] Fig.16 It is shown Fig.10 A logic diagram of an example of output logic;

[0038] Fig.17 is a schematic diagram showing an example of an accumulator input and an accumulator output for demodulation;

[0039] Fig.18 is a logic diagram showing an example of logic for combining resolver outputs of a dual speed resolver;

[0040] Fig.19 is a logic diagram showing an example of the logic of a drift corrector of a dual speed resolver;

[0041] Fig. 20 Including shown by Figure 2 Schematic diagram of the mechanical angle estimated by the solver system and the actual angle of the motor;

[0042] Fig.21 Including depiction Fig. 20 a schematic diagram of an enlarged view of a schematic diagram of;

[0043] Fig.22A is a schematic diagram showing an angle determined based on a resolver output using an excitation signal without jitter;

[0044] Fig. 22B is a schematic diagram showing an analog-to-digital converter (ADC) output generated based on a resolver output generated by an excitation signal without jitter;

[0045] Fig.23 is a schematic diagram showing an example of a jitter excitation signal;

[0046] Fig.24 is a schematic diagram showing an ADC output generated based on a dithered excitation signal;

[0047] Fig.25 is a schematic diagram showing an angle determined based on a jitter excitation signal;

[0048] Fig.26 is a logic diagram showing an example of logic for stimulus signal generation;

[0049] Fig. 27 is a circuit diagram showing an example of a resolver driver circuit;

[0050] Fig.28 is a circuit diagram showing an example of a motor driver circuit;

[0051] Fig.29 is a schematic diagram showing an example of cascade feedback logic for velocity feedback and position feedback;

[0052] Fig.30 is a logic diagram showing an example of logic for combined speed and position feedback control;

[0053] Fig.31 is a logic diagram showing an example of logic for combined speed and position feedback control including a direct speed command mode;

[0054] Fig.32 is a logic diagram showing an example of logic for combined speed and position feedback control including an initialization mode;

[0055] Fig.33 is a schematic diagram showing an example of pulse width modulation (PWM) operation with an adjustable comparison standard;

[0056] Fig.34 is a schematic diagram showing an example of dual channel PWM operation with adjustable comparison criteria;

[0057] Fig.35 is a logic diagram showing an example of logic for a PWM with adjustable comparison criteria and deadband control;

[0058] Fig.36 is a flow chart of an example of a method of determining rotational position using a dual speed resolver;

[0059] Fig.37 is a flow chart of an example of a pulse width modulation method;

[0060] Fig.38 is a flow chart of an example of a feedback control method;

[0061] Fig.39 is a flow chart of an example of a method for demodulating an output of a calculator;

[0062] Fig.40 is a flow chart of an example of a method of generating an excitation signal for a sensor device; and

[0063] Fig.41 is a block diagram illustrating an example of an aircraft including an inertial measurement unit. DETAILED DESCRIPTION

[0064] Embodiments disclosed herein relate to a gimbaled inertial measurement unit. The gimbaled inertial measurement unit includes sensors, such as accelerometers and gyroscopes, to determine vehicle inertial data, such as linear acceleration and angular velocity. In a gimbaled inertial measurement unit, the inertial measurement unit is mounted on a multi-axis gimbaled device. The gimbaled device includes a plurality of gimbals, each having a corresponding motor. The motor is used to drive and position the gimbals so that the sensors are oriented along the path of the vehicle. When the gimbals move based on the inertial changes of the vehicle, the control system of the vehicle tracks the position of the vehicle based on the output from the sensors. The control system then outputs commands to the gimbaled inertial measurement unit to adjust (readjust) the sensors so that the sensors are oriented along the updated path of the vehicle.

[0065] In some embodiments, the gimbal inertial measurement unit uses a dual-speed resolver to determine the position of the motor (e.g., the drive shaft of the motor) to determine the position of the sensor attached to the corresponding gimbal. The dual-speed resolver uses two resolvers, each with a different "speed", to determine the position of the drive shaft of the motor. The first resolver (e.g., a coarse resolver) can have a first speed corresponding to the speed and position (e.g., absolute position) of the drive shaft. The resolver speed corresponds to multiple electrical cycles (e.g., sine waves or cosine waves) generated by a single mechanical revolution of the resolver. In a specific embodiment, the first resolver is driven or rotated at the same rotational speed as the drive shaft, so the electrical cycle of the first resolver corresponds to the mechanical revolution of the drive shaft. Therefore, the absolute position of the drive shaft can be determined from the first resolver.

[0066] The second resolver (e.g., a fine resolver) has a second speed that is greater than the first speed and corresponds to the position of the drive shaft. For example, the second resolver may include multiple poles (e.g., coil pairs) that generate multiple electrical cycles (e.g., sine waves) for a single mechanical revolution of the resolver (and the drive shaft). Alternatively, the second resolver may complete multiple mechanical revolutions for each revolution of the drive shaft. The second resolver (fine resolver) has increased accuracy compared to the first resolver (e.g., a coarse resolver) at the expense of not being able to determine a starting position (e.g., an absolute starting position). The second resolver can determine a more precise position of the drive shaft, but cannot determine in which quadrant of the 360-degree rotation the drive shaft is.

[0067] A dual-speed resolver (or dual resolver) uses the outputs of two resolvers to determine the position of a drive shaft. For example, in a conventional dual-speed resolver, the outputs of the two resolvers are input into a Kalman filter to improve the accuracy beyond a single resolver. However, the output of the coarse resolver has an accuracy and precision lower than that of the fine resolver, and the use of both the coarse output and the fine output will reduce the accuracy and precision of the dual resolver to an accuracy lower than that of the fine resolver. By using the coarse resolver output to determine the starting position (e.g., during an initialization process or time period) and using the fine resolver output to determine the subsequent position (e.g., the position after the initialization process or time period), the accuracy and precision of the dual-speed resolver is improved compared to the conventional dual-speed resolver. This dual-speed resolver can be used to determine an absolute starting position and has the accuracy and precision of a fine resolver. In addition, the fine resolver output can also be used to correct the starting offset (error) of the coarse resolver. In addition, other methods described herein can be combined to further improve the accuracy and precision of the dual-speed resolver.

[0068] As described above, the resolver receives an excitation signal and generates an output signal in response. By adding jitter (e.g., zero mean jitter) to the excitation signal, the accuracy of the angle determined from the resolver output is increased without increasing the speed of the resolver (e.g., the number of poles of the resolver) or the bandwidth of the processing circuit (e.g., the sampling frequency of the output of the resolver or the number of bits of the resolver output). The zero mean jitter includes or corresponds to noise that does not change the intermediate amplitude value of the basic excitation signal. In addition, by time-coordinating the jitter excitation signal and the current drive switching signal of the universal joint motor, the jitter excitation signal can produce an output with less noise and interference. Therefore, the accuracy of the angle determined from the resolver output is increased without increasing the speed of the resolver or the bandwidth of the processing circuit.

[0069] As described above, the resolver output is converted to digital samples by an analog-to-digital converter (ADC), and the digital samples are demodulated during processing to determine the angle of the resolver and the drive shaft. During demodulation, the digital samples are rectified to produce a rectified signal. In some embodiments, the digital samples are rectified so that the phase of the excitation signal is retained in the rectified signal. For example, a conventional demodulator multiplies the digital samples by the excitation signal so that the phase is retained when the digital samples are rectified. However, multiplying the digital samples by the excitation signal can generate noise. To illustrate, multiplying the sinusoidal values ​​of the angle together reduces the accuracy of the data between the peaks of the sine wave, that is, it squares any noise or error.

[0070] Rectifying the digital samples with a square wave improves the signal-to-noise ratio of the data between the peaks of the sine wave, i.e., away from the peak voltage. Additionally, by flipping the sign of the square wave according to the phase of the excitation signal, the phase of the digital samples and the excitation signal can be preserved without adding additional noise or reducing the signal-to-noise ratio. Thus, the accuracy of the angle determined from the resolver output is increased without increasing the speed of the resolver or the bandwidth of the processing circuitry.

[0071] In addition, recursive median analysis and masked portions of the data further improve accuracy during demodulation. Recursive median analysis can be applied to the input digital samples and the output amplitude of the demodulator to further improve accuracy. For example, the demodulator can use the median (intermediate value) of the last n input samples as the input value, where n is any integer greater than 1. As another example, the demodulator can output the intermediate value of the last m output samples, where m is any integer greater than 1. Additionally or alternatively, the demodulator can output the intermediate value of 3 different signals as the output value. The output value is used to determine the angle of the resolver and the drive shaft.

[0072] In some embodiments, the demodulator masks a portion of the data to eliminate noise and interference, which further improves the accuracy of the gimbal inertial measurement. The masked portion includes noise data (data that occurs during current drive switching and includes current drive interference), data corresponding to transitions between peak amplitudes, or both. Therefore, the demodulation improves the results by using data close to the peak amplitude of the excitation signal. In addition or alternatively, the demodulated output is based on a synchronized (synchronized with the excitation signal) accumulator output to further improve accuracy and reduce errors. For example, by synchronizing the accumulator with an excitation signal that is time-coordinated with the current drive signal, the output of the accumulator can mask at least a portion of the current drive interference, offset the effects of the current drive interference, or both, thereby improving precision and accuracy.

[0073] The gimbaled inertial measurement unit also includes a feedback control system for controlling the gimbaled motor. The gimbaled motor is usually commanded or controlled by a direct rate command or a position command and a rate command. These commands can be received from a user input or a controller (e.g., a flight computer) of the vehicle. The feedback control system usually uses a cascade (e.g., multi-loop) tracking control method to process the position command and the rate command and provide feedback. By using a combined rate and position feedback system (e.g., a single-loop feedback system), a slightly damped gimbaled motor with a dense rate gain can be used to achieve higher accuracy.

[0074] A pulse width modulator (PWM) is used to drive a gimbal motor. The PWM controls the activation of the gimbal motor based on a feedback control system. For example, when the gimbal motor corresponds to a three-phase motor, the PWM controls the power delivery to the gimbal motor based on a current command generated by the feedback control system. For illustration, the current command is converted into a duty cycle value or signal. For example, the current command represents the amount of current to be supplied to the motor. The duty cycle value (e.g., 50%) is determined based on the amount of current and the voltage of the power supply or motor. A duty cycle signal (e.g., a set point signal) indicates the duty cycle value. For illustration, for an 8-bit duty cycle signal, a value of 31 or 32 can indicate a duty cycle of 50%, depending on which comparison condition is used. The duty cycle signal is sent to the PWM, which generates pulses; the width of the pulses controls the power delivery to the gimbal motor.

[0075] PWM generates pulses based on comparing a counter value to a comparison value (representing a duty cycle value, such as 50%, 51%, etc.). For example, PWM generates pulses based on determining whether the counter value is greater than or less than the comparison value. To illustrate, when the counter value is greater than the comparison value, the PWM generates a first pulse edge of the pulse (e.g., activates the gate of the transistor), and when the counter value is no longer greater than (does not exceed) the comparison value, the PWM generates a second pulse edge of the pulse (e.g., deactivates the gate of the transistor). In conventional PWM, increasing precision or reducing the granularity of control adjustments requires increasing the operating frequency of the PWM components.

[0076] By utilizing an adjustable comparison standard, the PWM control accuracy can be improved and the control granularity can be reduced without increasing the operating frequency of the PWM component. The adjustable comparison standard can be indicated by a set point signal. The adjustable comparison standard includes other comparison conditions or rules, such as a greater than or equal to condition and a less than or equal to condition. PWM utilizes an up-down counter to generate a counter signal, which is a triangular wave. Therefore, when the comparison value is adjusted by a counter value (clock pulse), PWM generates a first pulse before a clock pulse and generates a second pulse after a clock pulse, resulting in an increase in the pulse width of the two clock pulses. However, when the comparison standard is adjusted, PWM can generate a first pulse before a clock pulse and generate a second pulse at the same time, resulting in an increase in the pulse width of a clock pulse. Therefore, by using an adjustable comparison standard, PWM improves the accuracy of the control adjustment of the motor and reduces the granularity of the control adjustment without increasing the operating frequency of the PWM component.

[0077] By utilizing one or more of the above improvements, a gimbaled inertial measurement unit can provide higher accuracy in a smaller footprint than a conventional gimbaled inertial measurement unit. Additionally, the gimbaled inertial measurement unit can achieve increased accuracy without increasing hardware capabilities. Thus, the gimbaled inertial measurement unit enables safer inertial navigation of a vehicle due to the increased accuracy. Additionally, a vehicle using a gimbaled inertial measurement unit can be smaller and lighter, thereby reducing cost.

[0078] Figure 1 1 is a schematic diagram 100 showing an example of an inertial measurement unit 102 (e.g., a gimbaled inertial measurement unit). In some embodiments, the inertial measurement unit 102 is included in a vehicle (e.g., a ship, a submarine, an aircraft, a rocket, a satellite, a spacecraft, etc.) and coupled to its control system, such as Figure 2 and Fig.41 shown.

[0079] The inertial measurement unit 102 includes an inverter 112 and a gimbal device 114. The inverter 112 includes inverter electronics and firmware. The inverter 112 is configured to receive direct current (DC) power, convert the DC power to alternating current (AC) power, and provide the AC power to the gimbal device 114. For example, the inverter 112 is configured to provide power to control the operation of a motor 124 of the gimbal device 114. The inverter electronics may include or correspond to a processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof. The firmware is configured to control the operation of the inverter electronics. In some embodiments, the inverter electronics and firmware include or correspond to a PWM, for example Figure 2The PWM 242 is configured to control power delivery (eg, current drive switching) to the motor 124 .

[0080] The gimbal device 114 includes or corresponds to a multi-axis gimbal or a set of gimbals 122. The gimbal device 114 is configured to point the sensor 128 relative to the path of the vehicle. In some embodiments, the gimbal device 114 includes a three-axis gimbal. In a specific embodiment, the three-axis gimbal includes a ball (e.g., a first axis gimbal 122), an inner shell (e.g., a second axis gimbal 122), and an outer shell (e.g., a third axis gimbal 122). In other embodiments, the gimbal device 114 includes a dual gimbal system or a quad gimbal system.

[0081] The gimbal device 114 includes a motor 124. Each motor 124 is configured to drive or control the position of a corresponding gimbal 122 of the gimbal device 114 so that a sensor 128 attached to the corresponding gimbal 122 is aligned with the path of the vehicle. The motor 124 may include or correspond to an electric motor, such as a brushed electric motor or a brushless electric motor.

[0082] The gimbal device 114 includes a plurality of resolvers 126. Each resolver 126 is configured to determine the position of a corresponding gimbal 122 of the gimbal device 114 so that a sensor 128 attached to the corresponding gimbal 122 can be oriented to align with the path of the vehicle. For example, each resolver 126 is coupled to a drive shaft of a corresponding motor 124, and the output of each resolver 126 is used to determine the position of the drive shaft, and therefore the position of the corresponding gimbal 122 and a set of sensors 128.

[0083] The sensors 128 include an accelerometer 132 and a gyroscope 134. The accelerometer 132 is configured to determine linear acceleration, and the gyroscope 134 is configured to determine angular velocity. For example, the accelerometer 132 and the gyroscope 134 generate sensor data representing linear acceleration and angular velocity or changes in linear acceleration and angular velocity. In some embodiments, each gimbal 122 includes a set of sensors 128. Each set of sensors 128 includes one or more accelerometers 132 and one or more gyroscopes 134.

[0084] In some embodiments, the sensor 128 also includes a magnetometer. In a specific embodiment, each gimbal 122 of the gimbal device 114 also includes a magnetometer. The magnetometer is configured to detect the direction, strength, or relative change of the magnetic field. The output of the magnetometer can be used to determine the heading and / or position of the vehicle.

[0085] During operation of the vehicle, the vehicle may change its direction (e.g., path, heading, or route). For example, the vehicle may change its direction from a first direction (e.g., original direction) to a second direction (e.g., updated direction). In response to the vehicle changing direction to the second direction, the inertial measurement unit 102 positions (e.g., repositions) the gimbal 122 of the gimbal device 114 to orient (e.g., point) the sensor 128 attached to the gimbal 122 along the second direction (e.g., current path or heading of the vehicle). When the vehicle changes from the first direction to the second direction, the inertial measurement unit 102 positions the gimbal 122 of the gimbal device 114 based on the sensor data generated by the sensor 128.

[0086] The vehicle may change its direction again. For example, the vehicle may change its direction from the second direction to a third direction. In response to the vehicle changing direction for the second time, the inertial measurement unit 102 positions (e.g., repositions) the gimbal 122 of the gimbal device 114 to orient (e.g., point) the sensor 128 attached to the gimbal 122 along the third direction (e.g., the current path of the vehicle). When the vehicle changes from the second direction to the third direction, the inertial measurement unit 102 positions the gimbal of the gimbal device 114 based on the sensor data generated by the sensor 128. Although the above example utilizes a change in direction, the gimbal device 114 can sense any change in the inertia of the vehicle (such as a change in speed along the same direction or heading), and the inertial measurement unit 102 can position the gimbal device 114 in response to the change in the inertia of the vehicle. The inertial measurement unit 102 and its components will be further described with reference to subsequent figures.

[0087] Figure 2 Show Figure 1 Schematic diagram 200 of an example of a system of an inertial measurement unit 102. In schematic diagram 200, gimbal device 114 is not shown for clarity. Figure 2 In the particular example shown, the inertial measurement unit 102 includes an excitation signal generation system 202, a resolver system 204, and a control system 206. Each of these systems or subsystems thereof, alone and in combination with other systems, improves the functionality of the inertial measurement unit 102, as will be described in more detail in subsequent figures. In addition, the inertial measurement unit 102 includes a reference Figure 1 The inverter 112 and the motor 124 are depicted.

[0088] Inertial measurement unit 102 and its components may be coupled to other equipment of the vehicle. Figure 2As shown, the inertial measurement unit 102 and its components are coupled to a power supply 252 and a flight computer 254. In some embodiments, the power supply 252 corresponds to a DC power supply of the vehicle, such as a battery or a generator. In other embodiments, the power supply 252 can be included in the inertial measurement unit 102, for example, as an internal battery. The flight computer 254 can include or correspond to a flight control computer (FCC) or guidance system, which is configured to control the vehicle, such as in response to user input or autonomously causing a change in the route or direction of the vehicle.

[0089] The excitation signal generation system 202 is configured to generate an excitation signal and output the excitation signal to the resolver system 204. The excitation signal is configured to cause the resolver 126 to generate an output signal representative of the position of the drive shaft of the corresponding motor 124, as further described with reference to FIG.

[0090] The excitation signal generation system 202 includes a jitter generator 212 and a coordination system 214. The jitter generator 212 is configured to generate jitter and add the jitter to the excitation signal (base excitation signal) to generate a jittered excitation signal. The jittered excitation signal enables more accurate demodulation and more accurate gimbal / motor control, which results in better sensor output and higher accuracy of the inertial measurement unit 102, as further described with reference to FIGS. 22-29.

[0091] The coordination system 214 is configured to coordinate the excitation signal (or dithering excitation signal) with the current drive switching of the motor 124 to generate a coordinated excitation signal (or coordinated dithering excitation signal). To illustrate, turning on and off the transistor that provides power to the motor 124 can produce spikes, positive spikes and negative spikes, respectively. The waveform of the excitation signal can be coordinated with (e.g., offset from) the current drive switching so that the same number of transitions from off to on and from on to off occur during each waveform. In addition, the current drive switching can be offset from the peak amplitude of the waveform of the excitation signal. The coordinated excitation signal reduces noise and contamination of the solver output, which results in better sensor output and increased accuracy of the inertial measurement unit 102.

[0092] The resolver system 204 is configured to generate a resolver output representing the position of the drive shaft of the motor 124 in response to the excitation signal. The resolver output is an analog signal that is converted into digital samples by the ADC and processed to determine the position (angle) of the drive shaft. The resolver system 204 includes the resolver 126, the demodulation system 222, and the dual resolver combination system 224.

[0093] The demodulation system 222 is configured to demodulate the digital samples output by the ADC, such as reference Figure 7-17Further described. In some embodiments, the demodulation system 222 performs a recursive median analysis to reduce or eliminate spikes in digital samples input to the demodulation system 222, such as spikes caused by current drive switching and other interference. Additionally or alternatively, the demodulation system 222 includes an accumulator to reduce or eliminate spikes in the demodulated output of the demodulation system 222. The accumulator can also preform the recursive median analysis and mask (e.g., filter) noise data to reduce or eliminate spikes in the demodulated output.

[0094] The dual resolver combination system 224 is configured to generate angle estimates based on the demodulated outputs and to combine the angle estimates from each resolver to determine the position of the drive shaft, as referenced Fig.18 and Fig.19 Further described. The dual resolver combination system 224 uses a coarse resolver to determine the starting position of the drive shaft during an initialization process (e.g., initialization mode). The starting position corresponds to the initial position of the drive shaft in absolute value (0 to 360 degrees). The dual resolver combination system 224 uses the more accurate and precise fine resolver output to determine the subsequent position of the drive shaft after the initialization process. In some embodiments, the dual resolver combination system 224 includes a drift corrector to correct drift. The drift corrector can use the fine resolver output to correct the initial error (offset) of the starting position determined by the coarse resolver and correct the integral error of the fine resolver output.

[0095] Control system 206 includes feedback control system 232. Feedback control system 232 is configured to receive flight control inputs from flight computer 254, position feedback from resolver system 204, and speed feedback (e.g., revolutions per minute (RPM) feedback) from resolver system 204. Position feedback indicates the position (angle) of motor 124, and speed feedback indicates a rate, such as motor speed in RPM.

[0096] The flight control inputs include speed commands (eg, RPM commands), position commands, or both. The feedback control system 232 generates current commands based on the flight control inputs, position feedback, and speed feedback, as shown in FIG. Fig.30 and 31 As further described, the control system 206 converts the current command into a duty cycle setting or value for controlling the motor 124. In some embodiments, the duty cycle setting is indicated by a set point signal that indicates a comparison value and a comparison standard.

[0097] The inverter 112 includes a PWM 242 configured to apply an adjustable comparison criterion. The PWM is configured to receive a comparison value and one or more comparison criteria and generate pulses of a pulse width modulated signal based on the comparison value and the one or more comparison criteria, such as a reference Figure 33-35The pulse width modulated signal has an increased control accuracy or a reduced control granularity and is used to more accurately provide power from the power source 252 to the motor 124. Figure 3 describe Figure 2 Operation of the inertial measurement unit 102 .

[0098] Figure 3 is a schematic diagram 300 illustrating an example of the operation of the inertial measurement unit 102. The schematic diagram 300 corresponds to the operation of a single motor 124 of the inertial measurement unit 102 and its positioning sensor 128 of a particular gimbal 122 (corresponding to the motor 124) of the gimbal device 114. Figure 3 In FIG. 1 , cross-hatching indicates operations or steps that can be time-coordinated with each other. Time coordination can be achieved by using the same clock or counter, by synchronizing two or more clocks or counters, by offsetting two or more clocks or counters, or a combination thereof, as shown in FIG. Fig. 27 and Fig.28 Further described.

[0099] During operation of the inertial measurement unit 102, the excitation signal generation system 202 generates a jitter excitation signal 352, coordinates the jitter excitation signal with other components of the inertial measurement unit 102 (e.g., one or more cross-hatched components), and provides the jitter excitation signal 352 to a digital-to-analog converter (DAC) 310. The DAC 310 converts the jitter excitation signal 352 into an analog signal and provides the analog jitter excitation signal 352 to each resolver 342, 344 of the dual-speed resolver 312. For example, the dual-speed resolver 312 includes a 1x speed resolver and a 16x speed resolver. Each resolver 342, 344 generates an output, such as a differential voltage output 354. For example, as Figure 3 As shown, the coarse resolver 342 outputs a differential voltage output 354A (ie, a coarse position signal representing the route position) and the fine resolver outputs a differential voltage output 354B (ie, a fine position signal representing the fine position).

[0100] The differential voltage output 354 is measured by the corresponding differential voltage sensor 314, 316 to generate a differential voltage signal 356. The differential voltage signal 356 generated by the differential voltage sensor 314, 316 is sampled by the corresponding ADC 318, 320. The ADC 318, 320 outputs digital samples of the voltage value (referred to as ADC output 358) to the voltage regulation circuit 322, 324, which corrects the voltage offset of the inertial measurement unit 102. The regulated voltage value 360 ​​is demodulated by the demodulation system 222 to generate a demodulated output 362. The angle estimation circuit 326 generates angle estimates 364 for the two resolvers based on the demodulated output 362. The angle estimate 364 is used to generate an estimated position 366 of the motor based on the demodulated output 362, such as the initial position and subsequent position of the motor. One or more estimated positions 366 are used to determine an estimated RPM 368 of the motor. In addition, the estimated position 366 can be adjusted (tare) to account for the motor 124, for example, to account for commutation and servo offsets. Adjusting (tare) the estimated position 366 generates a magnetic rotor position and a mechanical rotor position, for example, a tared position output. An estimated RPM 368 can be further determined based on the magnetic rotor position and the mechanical rotor position. The estimated position 366 and the estimated RPM 368 of the motor 124 are provided to the feedback control system 232 to be used as feedback for controlling the motor 124, i.e., position feedback and RPM feedback.

[0101] The feedback control system 232 receives commands 370, such as position commands and RPM commands, from the flight computer 254. The feedback control system 232 generates a rate-limited position command based on the position command and the RPM command. The feedback control system 232 generates a current command 372 based on the rate-limited position command, the position feedback, and the RPM feedback. The current command 372 may correspond to a torque command or indicate the amount of torque of the motor 124. The current command 372 is provided to the current tracker 330 to generate a duty cycle value 374. The duty cycle value 374 may be represented as a two-phase reference frame (e.g., a direct and quadrature two-phase reference frame, where quadrature corresponds to torque). An inverse Park / Clark transform 332 may be applied to the duty cycle value 374 to convert the duty cycle value 374 to one or more duty cycle settings 376 for a three-phase motor, such as the duty cycles of the A, B, and C lanes (phases) of the three-phase motor. One or more duty cycle settings 376 (e.g., set point signals) are sent to the PWM 242.

[0102] The PWM 242 receives one or more duty cycle settings 376, each duty cycle setting 376 indicating a comparison value and two comparison criteria. The PWM 242 may receive one duty cycle setting 376 for each channel (A, B, and C), or may receive one duty cycle setting 376 for a particular channel and generate a duty cycle setting 376 for each other channel based on the received duty cycle setting. Based on comparing the comparison value and the counter value based on the two comparison criteria for each channel, the PWM 242 controls the gate driver 334 of the transistor 336 (metal oxide semiconductor field effect transistor (MOSFET)) of the inverter 112.

[0103] The PWM 242 is configured to generate (or cause the gate driver 344 to generate) a pulse width modulated signal 378. The PWM 242 generates pulses of the pulse width modulated signal 378 for each channel (one pulse for each comparison standard), and the pulses activate and deactivate the transistor 336 (i.e., current drives the switching). By activating the gate driver 334, the PWM 242 controls the power delivery from the power supply 252 to the motor 124. The PWM 242 and the inverter 112 convert the DC power from the power supply 252 into a three-phase AC power signal 380, which has a higher precision for controlling the motor 124.

[0104] Figures 4A-4C An example operation of the solver is shown. Figure 4A A schematic diagram of an example of a transformer 402 is shown in which two coils 412, 414 of wire (referred to as "windings") are wrapped around a magnetic core. Changes in the current applied to the input coil 412 produce a changing magnetic flux and a changing magnetic field at the output coil 414. The changing magnetic field at the output coil 414 induces a voltage in the output coil 414. The resolver operates using a rotatable transformer and outputs an induced voltage.

[0105] Figure 4B Schematic diagram showing an example of a resolver 404. The resolver 404 is an analog sensor that is configured to determine the rotational position of a rotating component. The resolver 404 is an active sensor, i.e., it receives an excitation signal (e.g., Figure 3 A jitter excitation signal 352 is generated, which causes (induces) an output signal.

[0106] The resolver 404 includes three coils 422-426 that form a rotatable transformer. The resolver 404 includes a rotatable primary coil 422 (first coil) and two secondary coils 424, 426 (sine and cosine coils). The secondary coils 424, 426 may include or correspond to pairs of poles, for example 2n poles. Each pole is angularly offset from the other pole, for example 90 degrees. Each pair of poles has one pole configured to deliver a sine output and another pole configured to deliver a cosine output. When the primary coil 422 rotates, the primary coil 422 receives the excitation signal 352 and induces a voltage in the secondary coils 424, 426. Each of the secondary coils 424, 426 may output a differential output, for example Figure 3 The differential voltage output 354 is obtained. The ratio between the voltages of the secondary coils 424, 426 represents the angle 430 of the resolver 404 (which is indicative of the angle of the motor 124). Figure 4B The resolver 404 in is a two-pole resolver and is a single-speed resolver, e.g. Figure 3 A coarse solver 342 of .

[0107] In a multi-speed resolver, the multi-speed resolver (e.g., fine resolver 344) has a higher number of electrical cycles per rotation of the multi-speed resolver (and the component being tracked). For example, the multi-speed resolver can be a multi-pole resolver, and additional pole pairs (coils) can be added to the resolver 404 to produce more electrical cycles per mechanical rotation of the primary coil 422 (and the component being tracked). As another example, the primary coil 422 of the multi-speed resolver can be geared relative to the component being tracked so that one mechanical rotation of the component being tracked causes more than one rotation of the primary coil 422.

[0108] Figure 4C Show Figure 3 462 - 468 are exemplary graphs of signals of the dual speed resolver 312 . Figure 4C Each of the graphs 462-468 corresponds to the same time interval, which corresponds to a partial rotation of the resolvers 342, 344 of the dual speed resolver 312. The first graph 462 depicts the voltage of the excitation signal 452 (AC signal) supplied to the two resolvers 342, 344 during the time interval. Figure 4C As shown, the excitation signal 452 has a frequency of 2442 Hz. In other embodiments, the excitation signal is a jitter excitation signal (e.g. Figure 3 The jitter excitation signal 352) and Fig.23 For illustrative purposes, an excitation signal 452 (basic excitation signal) is depicted in FIG4 .

[0109] The second graph 464 depicts the voltage output of the sinusoidal secondary coil 424 of the coarse resolver 342 (e.g., resolver 404) during the time interval. The third graph 466 and the fourth graph 468 depict the voltage output of the fine resolver 344 during the time interval. Figure 4C As shown, the fine resolver 344 is a 16x speed resolver, and the third graph 466 depicts the voltage output of the sine secondary coil 424, while the fourth graph 468 depicts the voltage output of the cosine secondary coil 426 of the fine resolver 344. The voltage output of the sine secondary coil 424 of the fine resolver 344 of the third graph 466 has a higher voltage, a higher cycle frequency, and completes multiple electrical cycles within the time interval compared to the voltage output of the sine secondary coil 424 of the coarse resolver 342 of the second graph 464. The voltage output of the cosine secondary coil 426 of the fine resolver 344 of the fourth graph 468 has the same cycle frequency as the voltage output of the sine secondary coil 424 of the fine resolver 344 of the third graph 466, but is offset (e.g., out of phase) relative to the third graph 466. The voltage output of the cosine secondary coil 426 of the fine resolver 344 of the fourth graph 468 also deviates from the excitation signal 452 of the first graph 462. Figure 5-21 Processing of the resolver outputs, such as demodulation and angle combining, is described. Generation of excitation signals for the resolver 404 is described with reference to Figures 22-28.

[0110] Figure 5 is shown for processing Figure 3 Schematic diagram 500 of an example of a flow process of the solver output of the dual speed solver 312. Figure 5 As shown, the resolver system 204 includes two processing chains 502, 504, one for each resolver of the dual speed resolver 312. The processing chains 502, 504 include ADCs 318, 320, demodulation circuits 514, 524, and angle calculation circuits 516, 526. The output from each processing chain 502, 504 is input to output circuit 532.

[0111] like Figure 5 As shown, the output circuit 532 includes an angle combination circuit 542 and a drift correction circuit 544. Based on the outputs from the angle combination circuit 542 and the drift correction circuit 544, the position of the drive shaft of the motor can be determined.

[0112] During operation, Figure 3 The coarse resolver 342 (eg, a first resolver or a single speed resolver) outputs a coarse position signal to the input of the first ADC 318, and Figure 3The fine resolver 344 (eg, a second resolver or a multi-speed resolver) outputs a fine position signal to the input of the second ADC 320. Figure 5 In the example shown, ADC 318, 320 receives Figure 3 The differential voltage signal 356 is obtained. In a specific embodiment, the fine position signal is 16 times faster. The coarse position signal and the fine position signal include analog sine and cosine waves. In a specific embodiment, the coarse position signal and the fine position signal each include a differential sine signal and a differential cosine signal.

[0113] ADC 318, 320 converts the analog output of the resolver into digital samples. The digital samples output by ADC 318, 320 are received by the corresponding demodulation circuit 514, 524. Demodulation circuit 514, 524 demodulates the digital samples to produce the amplitude of the sine and cosine waves. In a particular embodiment, the amplitude includes sign information, that is, it is "signed" and indicates whether the sample is positive or negative. Figure 6-17 The details of demodulation are further described.

[0114] The magnitude output of the demodulation circuits 514, 524 is received by the corresponding angle calculation circuits 516, 526. The angle calculation circuits 516, 526 use the sine and cosine magnitudes to calculate the estimated angle of the drive shaft. In a specific embodiment where the magnitude includes sign information, the angle calculation circuits 516, 526 use arctan2 (often abbreviated as atan2) to calculate the estimated angle (which represents the angle of the drive shaft) of the resolver 342, 344. The atan2 function is a four-quadrant inverse tangent function that can determine the quadrant in which the drive shaft is located based on the magnitude with a sign.

[0115] The estimated angle of the drive shaft from each angle calculation circuit 516, 526 is provided to the output circuit 532. Figure 5 In the example shown, angle combination circuit 542 receives two estimated angle outputs, and drift correction circuit 544 receives the multi-speed estimated angle output.

[0116] Angle combination circuit 542 combines the estimated angles (e.g., Figure 3 Angle estimation 364 of the drive shaft is used to determine the starting position of the drive shaft ( Figure 3In certain embodiments, the angle combination circuit 542 uses the estimated angle output from the first angle calculation circuit 526 to determine the starting position and uses the estimated angle output from the second angle calculation circuit 526 to determine the subsequent position of the drive shaft. Alternatively, the angle combination circuit 542 uses both estimated angle outputs to determine the starting position and uses the estimated angle output from the second angle calculation circuit 526 to determine the subsequent position of the drive shaft.

[0117] Drift correction circuit 544 corrects errors that occur when combining two estimated angles. For example, when determining the starting position and subsequent positions of the drive shaft includes differentials of multi-speed estimated angles, noise and integer errors may be introduced into the output of angle combination circuit 542. To correct for noise and integer errors, angle combination circuit 542 receives an estimated position from angle combination circuit 542. Drift correction circuit 544 generates a drift correction output based on the multi-speed estimated angles from the second angle calculator. Drift correction circuit 544 provides the drift correction output to angle combination circuit 542. Angle combination circuit 542 adjusts subsequent outputs ( Figure 3 The subsequent estimated position 366 of Figure 6 , Figure 7 and Fig.18 The details of the angle combination circuit 542 are further described and referenced Figure 6 , Figure 7 and Fig.19 The details of drift correction circuit 544 are further described.

[0118] Figure 6 is shown for processing Figure 3 Logic diagram 600 is an overview of an example of logic 602 for the solver output of the dual speed solver 312. Logic diagram 600 depicts an overview of the conversion of the solver output to an ADC output, demodulation of the ADC output, an angle estimate based on the demodulated output, and a combined position output based on the angle estimate. Figure 7-19 Each circled portion of logic diagram 600 is described in more detail. Figure 6 The logic of the following figures and parts thereof may be performed by one or more dedicated circuits (circuits), FPGAs, firmware (such as firmware of FPGAs), software executed by a processor, or a combination thereof. In addition, the logic (or parts thereof) disclosed herein may be replaced by equivalent logic. For example, any logic gate may be represented by one or more NOR logic gates.

[0119] Figure 7 7 is a logic diagram 700 showing an overview of an example of logic 702 for demodulation and angle estimation. The logic 702 depicts demodulation and angle estimation for a single resolver of the dual speed resolver 312. Figure 7As shown, logic 702 corresponds to the Figure 3 The demodulation and angle estimation logic of the fine resolver 344 (e.g., 16x speed) is provided.

[0120] Logic 702 includes demodulation logic 712 and angle estimation logic 714. Demodulation logic 712 is configured to receive the resolver output (e.g., differential voltage output 354) via ADC 320 as ADC output 358 and output the demodulated output 362 to angle estimation logic 714, as shown in FIG. Figure 8-17 The angle estimation logic 714 is configured to receive the demodulated output 362 (demodulated amplitude value) and calculate the resolver angle estimate 364, as described in reference Fig.18 and Fig.19 Further described.

[0121] In some implementations, the angle estimation logic 714 is configured to calculate the angle estimate 364 based on the function atan2 (e.g., four-quadrant inverse tangent). For example, the angle estimation logic 714 is configured to generate the angle estimate 364 based on the product of the demodulated output 362 (demodulated amplitude value) and based on the sine and cosine feedback angle values ​​742, 744.

[0122] By calculating the angle estimate 364 based on the function atan2, the angle estimate 364 indicates the quadrant that the motor is in. For illustration, the angle output by atan2 is in the range of 0-360 degrees (rather than 0 to 90 degrees). The function atan2 uses the signed input angle to determine the specific quadrant (i.e., 0-90 degrees, 90-180 degrees, 180-270 degrees, or 270-360 degrees).

[0123] In some embodiments, the demodulation logic 712 is also configured to adjust (balance) for voltage bias and other biases of the hardware, such as reference Figure 8 In some embodiments, the angle estimation logic 714 is further configured to output estimated angle outputs of sine and cosine values ​​in addition to the angle estimate 364 .

[0124] During operation, the demodulation logic 712 receives digital samples from the ADC. For example, the demodulation logic 712 receives the ADC output 358 from one of the ADCs 318, 320. The digital samples represent the voltages of the sine and cosine coils 424, 426 of the resolvers 342, 344 of the dual speed resolver 312. Figure 7As shown, the digital samples correspond to the sine and cosine inputs from the fine resolver 344. The digital samples are demodulated to produce demodulated sine and cosine outputs 362. The plurality of demodulated outputs 362 may be referred to as demodulation feedback or a demodulation feedback signal. In a particular embodiment, the demodulation logic 712 generates a median of the previous three demodulation outputs 362 and outputs the median as the next demodulation output 362 of the demodulation feedback signal. Figure 8-16 The detailed operation of the demodulation logic 712 is further described.

[0125] The demodulated output 362 is multiplied by the sine and cosine feedback angle values ​​742, 744 to generate products 752, 754. For illustration, the sine demodulated output 362 is multiplied by the cosine feedback angle value 744 to generate a first product 752. The cosine demodulated output 362 is multiplied by the sine feedback angle value 746 to generate a second product 754. The sine and cosine feedback angle values ​​742, 744 may be generated by the angle estimation logic 714 as sine and cosine estimated angle values ​​762, 764 and provided to the logic 702. For example, the sine and cosine estimated angle values ​​762, 764 are generated based on the demodulated output 362. For illustration, the sine estimated angle value 762 is calculated based on a first product 752 of the sine feedback angle value 742 and the value (amplitude) of the sine demodulated output 362.

[0126] The angle estimation logic 714 receives the product 752, 754 of the demodulated output 362 and the sine and cosine feedback angle values ​​742, 744 and generates an angle estimate 364 based on the demodulated output 362. For example, the angle estimation logic 714 generates the angle estimate 364 based on the function atan2 (i.e., four-quadrant inverse tangent). For illustration, the particular angle estimate 364 is calculated by applying the function atan2 to the value (angle) of the integral of the product 752 minus the product 754, i.e., the integral (sine_amplitude*cos(θ)-cosine_amplitude*sin(θ)-0). In this embodiment, the demodulated output 362 is signed, i.e., includes sign information. As shown in reference to Figure 7 , Fig.18 and Fig.19 As explained, the angle estimate 364 indicated by the fine resolver 344 may be used in combination with the angle indicated by the coarse resolver 342 to generate an initial position and subsequent positions of the drive shaft of the motor 142 .

[0127] In some embodiments, the demodulation logic 712, the angle estimation logic 714, or both are configured to receive an interrupt service routine (ISR) input 730. The ISR input 730 is a Boolean value indicating an interrupt service routine mode. The demodulation logic 712, the angle estimation logic 714, or both stop generating output in response to receiving the ISR input 730.

[0128] Figure 8 8 is a logic diagram 800 illustrating an example of logic 802 for voltage regulation. The logic 802 is configured to receive a voltage value from a sensor, regulate the voltage value to remove hardware bias, and output a demodulated output value. Figure 8 In the particular example shown, the logic 802 receives the voltage value measured by the differential voltage sensor 316 corresponding to the sine coil 424 of the fine resolver 344 and calculates the demodulated output 362 of the fine resolver 344 .

[0129] Logic 802 includes recursive median value analysis (RMVA) logic 812, voltage filter 818, and combiner 816. RMVA logic 812 is configured to determine the median (middle value) of the last n input values ​​or samples, where n is an integer greater than 1. Fig. 9 The RMVA logic 812 is further described.

[0130] During operation, the logic 802 receives a plurality of voltage values ​​from the ADC 320 corresponding to the voltage at the sine coil 424 of the fine resolver 344 (e.g., a 16x resolver) measured by the differential voltage sensor 316. The RMVA logic 812 receives the plurality of voltage values ​​and outputs a median voltage value 814 to the combiner 816. The voltage filter 818 (e.g., a low pass filter) generates a voltage signal based on the median voltage value 814 and the counter input 852. Figure 8 Voltage bias output 820, sin_tare, is shown. Voltage bias output 820 corresponds to a voltage bias by or applied by hardware of inertial measurement unit 102. For example, voltage bias output 820 may correct for voltage drops associated with an FPGA of inertial measurement unit 102.

[0131] In certain embodiments, the median voltage value 814 is converted to a higher bit value, such as from a 16-bit value to a 32-bit value. Converting from 16 bits to 32 bits (increasing the number of bits) reduces or eliminates the loss of precision caused by the voltage filter 818. For example, any right shift of the voltage filter 818 does not result in a loss of precision.

[0132] Combiner 816 generates an adjusted voltage value 822 (eg, Figure 3 The adjustment voltage value is 360). Figure 8 As shown, the adjusted voltage value 822 is the difference between the median voltage value 814 and the voltage offset output 820. The adjusted voltage value 822 can be converted into a signed integer and shifted before demodulation. The adjusted voltage value 822 can be output to the demodulation logic 826 and stored as the input voltage value 824.

[0133] The demodulation logic 826 generates the demodulation output 362 based on the input voltage value 824, the counter input 852, the width input 854, and the center input 856. The generation of the demodulation output 362 and the example reference of the RMVA logic 812 and the demodulation logic 826 Figure 9-17 Further description.

[0134] Fig. 9 is shown for input (e.g. Figure 7 and Figure 8 Logic diagram 900 of an example of RMVA logic 812 for recursive median analysis of an ADC output 358). The RMVA logic 812 includes sliding window logic 904, which is configured to receive inputs and store the last n inputs. The sliding window logic 904 may include one or more registers (e.g., memory, cache, buffer, etc.) to store the last n inputs. The sliding window logic 904 may perform a zero-order hold (ZOH) to store the last n inputs. The zero-order hold (ZOH) holds each sample value for one sampling interval. When a new sample is received, each stored sample is moved back one position and the last stored sample is pushed out. Fig. 9 In the example shown, sliding window logic 904 stores the last seven inputs (p0-p6).

[0135] RMVA logic 812 includes cascaded median logic 906 configured to determine the median of the last n inputs, ie Figure 8 The median voltage value 814 is obtained by cascading the median logic 906, which includes a plurality of logic blocks 912-916, each of which is configured to determine the median value of a subset of the last n inputs. The output of the first logic block 912 is used as the input of the second logic block 914, the output of the second logic block 914 is used as the input of the third logic block 916, and so on. The output of the final logic block (i.e. Fig. 9 The third logic block 916 in the illustrated embodiment is the median of the last n samples. Fig. 9 A specific example of RMVA logic 812 is shown in which multiple logic blocks 912-916 each determine the median of three inputs and three logic blocks 912-916 are used. In other embodiments, more than three logic blocks or less than three logic blocks may be used and / or each logic block may process a different number of inputs from another logic block. Additionally or alternatively, each of logic blocks 912 and 914 may determine the median of three samples, and logic block 916 may determine the median of two outputs and a single sample.

[0136] Fig. 9Also shown is an example of logic 922 for three-value median determination, such as first logic block 912. Logic 922 allows for parallel processing and faster determination of the median for larger values ​​of n. First logic block 912 receives three inputs corresponding to combinations of sample and median outputs. Fig. 9 In the first logic block 912 shown, the first logic block receives samples five, six, and seven (p4-p6) at inputs 1, 2, and 3, respectively. Fig. 9 The samples are compared to each other using the greater than condition shown in Figure 9. Three comparisons are used because three samples are used in the example shown. These comparisons produce Boolean outputs, which are used to control the switch output. For illustration, logic 922 compares the first input ([x]) with the third input ([z]) to generate a first Boolean condition ([xgz]) indicating whether the first input ([x]) is greater than the third input.

[0137] Logic 922 uses a series of switches (h-h5) to determine the median output. Each switch (h-h5) receives two input sample values ​​and a corresponding Boolean condition. For example, the first switch (h2) receives a first input ([x]) and a third input ([z]) and a corresponding Boolean condition generated by comparing the first input and the third input, namely, the first condition ([xgz]). Based on the first condition indicating false (i.e., x is not greater than z), the first switch (h2) outputs the third input ([z]). The second switch (h4) receives the second input ([y]), the output of the first switch (h2) (the third input ([z])) and the Boolean condition corresponding to the second input (e.g., the second Boolean condition or the third Boolean condition). Based on one of the Boolean conditions corresponding to the second input (i.e., Fig. 9 The second switch (h4) compares the second input with the third input. Based on the first condition indicating that the first condition is true (i.e., y is greater than z), the second switch (h4) outputs the second input ([y]) to the fifth switch (h3), such as an output switch.

[0138] The operation of the third switch (h) and the fourth switch (h5) mirrors the operation of the first switch (h2) and the second switch (h4). For example, the third switch (h) receives the same input and the conditions in the opposite order, so the third switch (h) outputs the opposite output value based on the first condition to the fourth switch (h5). For illustration, if the first switch (h2) outputs the third output ([z]), the third switch (h) will output the first output ([x]). One of the second switch (h4) and the fourth switch (h5) will always output the second input ([y]).

[0139] The fifth switch (h3) receives the outputs of the second and fourth switches (h4 and h5) and compares them based on another Boolean condition corresponding to the second input ([y]). The fifth switch (h3) outputs an intermediate value based on the second input ([y]), and the top switches (h2 and h4) will output the intermediate value when the first input ([x]) is greater than the second input ([y]). When the second input ([y]) is greater than the first input ([x]), the bottom switch (h and h5) output will be the intermediate value (assuming the Boolean condition is true or high, the top input is selected at each switch). Compared to sorting the last n inputs (e.g., by a sorting function), the RMVA logic 812 and logic 922 reduce firmware, circuit area, and processing speed.

[0140] Fig.10 It is shown Figure 8 1000 is a logic diagram of an example of a demodulation logic 826. The demodulation logic 826 is configured based on Figure 8 The demodulation logic 826 includes the accumulator logic 1014, the mask logic 1018, and the output logic 1026.

[0141] The accumulator logic 1014 is configured to output an accumulated output 1024 based on the input voltage value 824. For example, the accumulator logic 1014 is configured to accumulate the values ​​of the input voltage values ​​824 and output the accumulated output 1024 as an accumulation of the input voltage values ​​824. To illustrate, the accumulation includes adding the current voltage value 824 to the sum of the previous voltage values ​​824. Additionally, the accumulator logic 1014 is configured to determine and adjust the sign of the accumulated output 1024 based on the flip input 1022.

[0142] In some embodiments, the accumulator logic 1014 adjusts and filters the plurality of input voltage values ​​824 to determine a particular accumulated output 1024. For example, the accumulator logic 1014 is configured to determine which input voltage value 824 of the plurality of input voltage values ​​824 to consider (or filter out) based on the count enable input 1020. The selected input voltage value 824 is accumulated and the filtered input voltage value 824 is discarded (not accumulated). In addition, the accumulator logic 1014 is also configured to be reset in response to receiving a reset input 1016. The details of the accumulator logic 1014 will be referred to in detail. Fig.11 Described in further detail.

[0143] The mask logic 1018 is configured to generate a count enable input 1020 based on the counter input 852, the width input 854, and the center input 856. The details of the mask logic 1018 will be described in detail in Fig.14 Described in further detail.

[0144] The output logic 1026 is configured to generate the demodulated output 362 based on the accumulated output 1024 and the counter input 852. For example, the output logic 1026 is configured to determine the demodulated output 362 as the median value of the accumulated output 1024 based on the counter input 852. The details of the output logic 1026 will be described in detail below. Fig.16 Described in further detail.

[0145] During operation, mask logic 1018 generates a captured data output (i.e., count enable input 1020) based on counter input 852, width input 854, and center input 856. Examples of the generation of masked captured data output (count enable input 1020) and mask logic 1018 will be referred to in detail below. Fig.14 and Fig.15 Further description.

[0146] The accumulator logic 1014 receives a signal 1012 including a plurality of input voltage values ​​824. The accumulator logic 1014 also receives a reset input 1016, a masked data output (count enable input 1020), and a flip input 1022. The accumulator logic 1014 generates an accumulated output 1024 based on the plurality of input voltage values ​​824, the reset input 1016, the masked data output (count enable input 1020), and the flip input 1022. The accumulator logic 1014 rectifies the plurality of input voltage values ​​824 based on the flip input 1022 to generate rectified values. These rectified values ​​are output as accumulated outputs 1024 based on the reset input 1016 and the masked data output (count enable input 1020). Examples of the generation of the accumulated output 1024 and the accumulator logic 1014 will be referred to in detail below. Fig.11 and Fig.12 Further description.

[0147] The flip input 1022 is a Boolean value that indicates when to change the sign of the square wave used in the rectification. The flip input 1022 is configured to change the sign of the square wave used to rectify the plurality of input voltage values ​​824. The flip input 1022 tracks the excitation signal of the solver (e.g. Figure 3 and one of the excitation signals 352, 452 of FIG. 4). For example, when the value of the counter input 852 is less than half of the counter period ( Fig.10 When the value of counter input 852 is greater than half of the counter period, the sign of the square wave is negative because the second half of the sine wave (i.e., 181 to 360 degrees) is negative.

[0148] Fig.111 is a logic diagram 1100 showing an example of logic 1102 for rectification with phase preservation. The logic 1102 includes Fig.10 The flip generation logic 1104 and the accumulator logic 1014. The flip generation logic 1104 is configured to generate the reference Fig.10 The flip input 1022.

[0149] The accumulator logic 1014 is configured to rectify the plurality of input voltage values ​​824 based on the flipped input 1022 to generate rectified values. The accumulator logic 1014 is configured to accumulate the rectified values ​​to generate an accumulated output 1024. Fig.11 As shown, the accumulator logic 1014 includes an inverter 1112 , a plurality of switches 1114 , 1118 , and 1120 , and an adder 1116 .

[0150] The inverter 1112 is configured to invert the plurality of input voltage values ​​824. For example, the inverter 1112 is configured to multiply the plurality of input voltage values ​​824 by -1. The plurality of switches 1114, 1118, and 1120 are configured to output numerical values ​​based on control inputs (i.e., the flip input 1022, the count enable input 1020, and the reset input 1016), respectively. The adder 1116 is configured to add the output of the first switch 1114 to the delayed output of the third switch 1120. The unit delay 1122 is configured to delay the output of the third switch 1120 by one sample. For example, the unit delay 1122 performs a zero-order hold.

[0151] During operation, the toggle generation logic 1104 generates the toggle input 1022 based on comparing the counter input 852 to the counter intermediate value (e.g., 2^7-1 for the 8-bit counter 842). When the counter input 852 is greater than the counter intermediate value, the toggle generation logic 1104 generates a sign indicating the toggle input 1022 is true (e.g., 1) or the toggle input voltage value 824.

[0152] The first switch 1114 receives the input voltage value 824 of the signal 1012, the inverted input voltage value 824 from the inverter 1112, and the flip input 1022. Based on the flip input indication 1, which corresponds to the second half of the sine wave of the excitation signal (where the amplitude of the sine wave is negative), the first switch 1114 outputs the inverted input voltage value 824. Therefore, the flip generation logic 1104, the inverter 1112, and the first switch 1114 are used to rectify the input voltage value 824 and preserve the phase of the excitation signal. The flip generation logic 1104, the inverter 1112, and the first switch 1114 are used to multiply the input voltage value 824 by a [1, -1] square wave that is in phase with the excitation signal.

[0153] The adder 1116 receives the rectified input voltage value 1152 from the first switch 1114 and combines the rectified input voltage value 1152 with the delayed output 1158 of the unit delay 1122 to generate a combined output 1154. The combined output 1154 is provided to the second switch 1118. The second switch 1118 outputs the combined output 1154 or the delayed output 1158 based on the count enable input 1020. When the count enable input 1020 indicates true or acquires data, the second switch 1118 outputs the combined output 1154, as shown in FIG. Fig.11 Alternatively, when the count enable input 1020 indicates false or no data is acquired, the second switch 1118 outputs the delay output 1158 .

[0154] The output of the second switch 1118 is provided to the third switch 1120. When the reset input 1016 indicates true or resets the accumulator logic 1014, the third switch 1120 outputs a null value 1124 (e.g., 0). When the reset input 1016 indicates false or does not reset the accumulator logic 1014, the third switch 1120 outputs the output of the second switch 1118 as the output 1156 of the third switch. The output 1156 of the third switch 1120 is provided to the unit delay 1122. The unit delay 1122 delays the output 1156 of the third switch 1120 and provides the delayed output 1158 to the adder 1116 and the second switch 1118. The delayed output 1158 is also output as the accumulated output 1024.

[0155] The delayed output 1158 is provided to the adder 1116 and the second switch 1118 outputs the combined output 1154 in response to the count enable input 1020 indicating true to be used to iteratively increase the delayed output 1158 when a new input voltage value 824 is received. Therefore, when the delayed output 1158 is output as the accumulated output 1024 (i.e., before the accumulator logic 1014 is reset), the accumulated output 1024 represents the accumulation of the input voltage value 824, which corresponds to the time period when the mask logic 1018 outputs the count enable input 1020 indicating that data is to be acquired or accumulated. Fig.10 As shown and referenced Fig.16 and Fig.17 To further describe, the output logic 1026 generates the demodulated output 362 based on the accumulated output 1024 and outputs the demodulated output 362 based on the counter input 852 .

[0156] Although many of the inputs have been described as Boolean inputs that control logic gates or switches, the logic gates or switches may be implemented as transistors and receive logic high and low signals (eg, high and low voltages) representing the Boolean inputs.

[0157] Fig.12Schematic diagram 1200 shows an exemplary signal generated during demodulation. Schematic diagram 1200 includes three graphs 1202-1206. The first graph 1202 shows the corresponding Figure 3 The ADC output signal 1212 (demodulator input) is a sine wave output of the fine solver 344 of FIG. 1 . The ADC output signal 1212 includes Figure 3 The ADC output 358 (or adjusted voltage value 360) is obtained by calculating the ADC output 358 (or adjusted voltage value 360) of the first graph 1202. The second graph 1204 shows a rectified ADC output signal 1214 corresponding to the first graph 1202. In the second graph, the rectified ADC output signal 1214 has the same phase as the ADC output signal 1212. The ADC output signal 1212 is square wave rectified (e.g., multiplied by a square wave) rather than rectified by an excitation signal (e.g., a sine wave) to preserve the phase of the ADC output signal 1212 during rectification and improve accuracy. The rectified ADC output signal 1212 includes or corresponds to Fig.11 The rectified input voltage value 1152, such as a plurality of rectified ADC outputs. The third graph 1206 shows a demodulated output signal 1216 of the demodulated sinusoidal amplitude value. The demodulated sinusoidal amplitude value (including the sign information, i.e., positive or negative) is used to calculate the position of the drive shaft of the motor and corresponds to Figure 3 The demodulated output 362 is shown in the third graph, the demodulated output signal 1216 has a delay (is out of phase) relative to the ADC output signal 1212 and the rectified ADC output signal 1214. Fig.13 This delay is shown and explained in more detail.

[0158] Rectification using a square wave may introduce an error in region 1222 where the amplitude of the excitation signal changes from a positive value to a negative value (i.e., crosses zero) and the amplitude of the ADC output signal 1212 approaches zero. Accumulation of voltage values, masking voltage values, outputting a median accumulated value, or a combination thereof reduces or eliminates this error or defect, as shown by the demodulated output signal 1216, which does not include an error in the region corresponding to region 1222.

[0159] Fig.13 Show Figure 3 1302 and 1304 of the coarse resolver 342 of FIG. 1302 includes a representation of the sine and cosine values ​​output by the coarse resolver 342. The first graph 1302 may represent the sine and cosine values ​​output by the ADC 318, 320 from FIG. Figure 3 The sine and cosine values ​​1312, 1314 sampled in the differential voltage output of the coarse resolver 342. Before the first time T1, the coarse resolver 342 does not move. After the first time T1, the coarse resolver 342 starts to move and causes the sine and cosine values ​​1312, 1314 to change.

[0160] The second graph 1304 includes representations of demodulated sine and cosine values ​​1322, 1324 corresponding to the sine and cosine values ​​1312, 1314 of the first graph 1302. Demodulating the sine and cosine values ​​1312, 1314 to generate the demodulated sine and cosine values ​​1322, 1324 involves removing or attenuating the excitation signal, e.g. Figure 3 and one of the excitation signals 352, 452 of FIG. 4. The sine and cosine values ​​1312, 1314 correspond to the coarse resolver 342 associated with Figure 3 The demodulated sine and cosine values ​​1322, 1324 correspond to the ADC output 358 (or adjusted voltage value 360) associated with the coarse resolver 342. Figure 3 The demodulated output is 362. Fig.12 Compared to signals 1212 - 1216 of , values ​​1312 , 1314 , 1322 , and 1324 correspond to coarse solver 342 (in contrast to signals 1212 - 1216 corresponding to fine solver 344 ).

[0161] As shown in the second graph 1304, changes in the sine and cosine values ​​1312, 1314 are reflected back two cycles in the demodulated sine and cosine values ​​1322, 1324, i.e., these changes are delayed by two cycles. It takes one cycle (e.g., from the peak amplitude to the peak amplitude of the sine wave or cosine wave) to measure the sine and cosine values ​​1312, 1314, and takes a second cycle to process intermediate values ​​of the measured values ​​during demodulation. For illustration, changes in the values ​​of the sine and cosine values ​​1312, 1314 that occur during the first cycle from the first time T1 to the second time T2 (caused by the movement of the coarse resolver 342) are not reflected in the demodulated sine and cosine values ​​1322, 1324 until the third cycle from the third time T3 to the fourth time T4. Thus, the demodulation logic 826 imposes a relatively small delay (two cycles) and is able to achieve a relatively large improvement in accuracy (many orders of magnitude) compared to conventional demodulation systems, see Figure 20-25 Further description.

[0162] Fig.14 It is shown Fig.10 1400 is a logic diagram of an example of a mask logic 1018 of FIG. The mask logic 1018 is configured to generate a count enable input 1020 based on a counter input 852, a width input 854, and a center input 856. Fig.14 As shown in the example of , the mask logic 1018 includes a plurality of combiners 1410 - 1418 , comparison conditions 1422 - 1428 , and logic gates 1432 - 1436 .

[0163] During operation, mask logic 1018 receives width input 854, center input 856, and counter input 852. Mask logic 1018 also receives or determines offset input 1402. Offset input 1402 can be determined based on the number of bits of inputs 852-856. For example, when inputs 852-856 correspond to 8-bit values, the value of offset input 1402 is 128, i.e., 2^(8-1). In a particular embodiment, inputs 852-856 are 8-bit unsigned integer values. The difference between center input 856 and width input 854 represents half of width input 854.

[0164] The mask logic 1018 includes two logic chains 1404, 1406 configured to generate Boolean outputs. The mask logic 1018 generates outputs based on a logical operation of the Boolean outputs from the two logic chains 1404, 1406. Fig.14 As shown, the mask logic 1018 generates the acquired data Boolean output based on the "OR" logic operation of the Boolean outputs from the two logic chains 1404, 1406. In other embodiments, other logic operations, such as NOR, AND, etc., may be used. The value of the acquired data Boolean output (i.e., the count enable input 1020) indicates whether the accumulator logic 1014 acquires data or does not acquire data, as shown in FIG. Fig.10 described.

[0165] During operation, the mask logic 1018 receives three inputs 852-856. The value of the counter input 852 may change each time the counter value of the counter 842 is incremented, for example, based on a clock pulse. The counter input 852 is reset based on a reset pulse or reaching a maximum counter value. The width input and the center input 854, 856 may be constant and input by a user or fixed prior to operation. The offset input 1402 may be input by a user, fixed prior to operation, or determined based on one or more of the inputs 852-856.

[0166] The first combiner 1410 of the first logic chain 1404 generates a center input 856 and half of the width input 854 (i.e., a [width] / 2 input, which indicates a deviation or increment from the center input 856 that defines the data window 1514, as shown in FIG. Fig.15 The first comparator 1422 compares the counter input 852 with the difference between the center input 856 and half of the width input 854 based on the first comparison condition. The second combiner 1412 generates the sum of the center input 856 and half of the width input 854. The second comparator 1424 compares the counter input 852 with the sum of the center input 856 and half of the width input 854 based on the second comparison condition. Fig.14As shown, the first comparison condition is a greater than or equal to condition, and the second comparison condition is a less than or equal to condition. In other embodiments, other comparison conditions may be used. The outputs of comparators 1422 and 1424 are input to a first logic gate 1432. The first logic gate 1432 outputs a first intermediary output to a third logic gate 1436 (output logic gate) based on the logic rule of the first logic gate 1432.

[0167] The third combiner 1414 of the second logic chain 1406 generates the sum of the center input 856 and the offset input 1402. The fourth combiner 1416 generates the difference between the sum of the center input 856 and the offset input 1402 and half of the width input 854. The third comparator 1426 compares the counter input 852 with the difference between the sum and half of the width input 854 based on a third comparison condition. Fig.14 As shown, the third comparison condition is the same as the first comparison condition. The fifth combiner 1418 generates the sum of the center input 856, the offset input 1402, and half of the width input 854. The fourth comparator 1428 compares the counter input 852 with the sum of the inputs 854, 856, and 1402 (i.e., the sum of the center input 856 and the offset input 1402 plus half of the width input 854) based on the fourth comparison condition. Fig.14 As shown, the fourth comparison condition is the same as the second comparison condition. The outputs of the comparators 1426 and 1428 are input to the second logic gate 1434. The second logic gate 1434 outputs the second intermediate output to the third logic gate 1436 (output logic gate) based on the logic rule of the second logic gate 1434.

[0168] The third logic gate 1436 generates an acquisition data output (count enable input 1020) based on the logic rule of the third logic gate 1436, and provides the acquisition data output (count enable input 1020) to Fig.10 The accumulator logic 1014. Fig.14 As shown, the logic rules of the first and second logic gates include AND logic, while the logic rule of the third logic gate 1436 includes OR logic. In other implementations, other logic rules, additional logic gates, or both may be used to regenerate the acquired data output (count enable input 1020).

[0169] Fig.151500 is a schematic diagram illustrating an example of mask data and accumulated data for demodulation. Schematic diagram 1500 shows an example diagram depicting an accumulator signal 1522 (representing the output 1156 of the third switch 1120) and a demodulated output signal 1524 (representing the accumulated output 1024) of the accumulator logic 1014 and a mask region 1512. Schematic diagram 1500 also shows a width input 854 and a center input 856 in a data window 1514 between two particular mask regions 1512. In schematic diagram 1500, the center input 856 is located at a position corresponding to Fig.14 The first data window 1514 of the cycle of the first logic chain 1404 (generated by its output), and the width input and offset input 854, 1402 are located corresponding to Fig.14 1406 (generated by its output). This cycle corresponds to the period of the sine wave, and the counter input 852 is reset.

[0170] When the count enable input 1020 indicates to acquire or accumulate data filter data, that is, in the data window 1514 between the mask regions 1512, the accumulator signal 1522 increases. When the count enable input 1020 indicates to avoid acquiring or accumulating data, the accumulator signal 1522 does not increase during the mask region 1512. After stopping acquiring data in the mask region 1512, the accumulator logic 1014 outputs the demodulated output signal 1524 (its value) during the mask region 1512 (that is, every second mask region 1512). After outputting the value of the demodulated output signal 1524, the accumulator logic 1014 is reset (that is, the value of the accumulator signal 1522 is restored to 0) during the mask region 1512. Therefore, during Fig.15 In the example shown, the accumulator logic 1014 accumulates data during two data windows 1514 in one cycle and outputs the accumulated output 1024 once in each cycle.

[0171] Fig.16 It is shown Fig.10 1600 is a logic diagram of an example of output logic 1026 of the embodiment of the present invention. The output logic 1026 is configured to output the median of the accumulated output 1024 values ​​determined by the accumulator logic 1014 based on the accumulated output 1024 and the counter input 852 as the demodulated output 362. The operations of the accumulator logic 1014 and the output logic 1026 may be performed by an accumulator (e.g., an accumulator circuit).

[0172] like Fig.16 As shown in the example, the output logic 1026 includes a switch 1612 and RMVA logic 812. Figure 8 and Fig. 9In contrast, the RMVA logic 812 is configured to output a numerical value in response to or based on the Boolean input value 1628. The RMVA logic 812 outputs the demodulated output 362 in response to the Boolean input value 1628 indicating true.

[0173] The output logic 1026 is also configured to generate a Boolean input value 1628 based on the counter input 852. Fig.16 As shown, unit delay 1622 delays counter input 852 by one sample to synchronize the timing with the input of RMVA logic 812. Boolean input value 1628 is generated based on the comparison of delay counter value 1626 with comparison condition 1624. Fig.16 As shown, the comparison condition 1624 is an equal to zero condition, and when the delayed counter value 1626 satisfies the comparison condition 1624 (i.e., is equal to zero), the Boolean input value 1628 indicates true. When the delayed counter value 1626 does not satisfy the comparison condition 1624 (i.e., is not equal to zero), the Boolean input value 1628 indicates false.

[0174] During operation, the output logic 1026 receives the counter input 852. The counter input 852 is provided to the switch 1612, and the switch 1612 outputs the accumulated output 1024 or the delayed accumulator output 1654 based on the counter input 852. Fig.16 As shown, switch 1612 outputs a delay accumulator output 1654 based on the counter input 852 satisfying a condition not equal to zero. The output 1652 of switch 1612 is provided to unit delay 1614. Unit delay 1614 holds the output 1652 for a period corresponding to one or more samples to generate the delay accumulator output 1654. The delay accumulator output 1654 is provided to switch 1612 and RMVA logic 812.

[0175] When the counter input 852 is equal to zero, the value of the accumulated output 1024 is reset to zero, as shown in the reference Fig.11As explained above. When the counter input 852 is not equal to zero, the output logic 1026 stores the delayed accumulator output 1654 value until the accumulated output 1024 is received again by the delay unit 1614 (i.e., when the counter input 852 is equal to 0). The unit delay 1614 (e.g., a register or a shadow register) holds the value of the delayed accumulator output 1654 for one cycle, i.e., until a new accumulated output 1024 is received at the beginning of the next resolver stimulus signal cycle (i.e., when the counter input 852 is equal to 0). The value of the delayed accumulator output 1654 corresponds to the previous final accumulator value of the accumulated output 1024 before the accumulated output 1024 is reset to zero. Because the RMVA logic 812 captures the value of the delayed accumulator output 1654, which is held by the switch 1612 and the delay unit 1614 (i.e., sampled by the RMVA logic 812 one sample after the counter input 852 is zero), the RMVA logic 812 receives the previous final accumulator value of the accumulator output 1024 before the accumulator output 1024 is reset to zero.

[0176] The RMVA logic 812 determines the intermediate value of the last n delay accumulator outputs 1654 and outputs the intermediate value of the last n delay accumulator outputs 1654 as the demodulated output 362 in response to the Boolean input value 1628 indicating true. Figure 8 The RMVA logic 812 uses the same Fig.16 The same number n as the RMVA logic 812. In other embodiments, Figure 8 The RMVA logic 812 uses the same Fig.16 The RMVA logic 812 determines the median demodulated output 1656 based on the last three delayed accumulator outputs 1654 in a particular embodiment.

[0177] Fig.17 1700 is a diagram showing an example of an accumulator output of a demodulation circuit. An accumulator (e.g., Fig.10 The accumulator logic 1014 and the output logic 1026 can generate multiple intermediate values ​​and output values. Fig.17 As shown, the accumulator generates an accumulator signal 1522 (by accumulating the value corresponding to the output 1156 of the third switch 1120), generates a demodulated output signal 1524 (corresponding to the accumulated output 1024), and generates a demodulated sinusoidal output 362 (corresponding to the median or median demodulated output 1656 of the demodulated output signal 1524), as shown in reference Figure 10-16 The demodulated output signal 1524 and the demodulated sinusoidal output 362 include sign information (ie, positive or negative).

[0178] Fig.181 is a logic diagram 1800 showing an example of logic 1802 for combining the resolver outputs of the dual speed resolver 312. The logic 1802 is configured to combine the outputs from each resolver 342, 344 of the dual speed resolver 312 to determine an initial position or an absolute initial position in a first domain and determine a subsequent position based solely on the fine resolver. Determining a subsequent position (e.g., a position change from the initial position) based solely on the fine resolver increases the accuracy of the dual speed resolver beyond determining a subsequent position based on the output of the coarse resolver. The operation of the logic 1802 may be performed by Figure 5 The angle combination circuit 542 is executed. The logic 1802 receives the angle estimate 364 in the second domain based on the fine position signal from the fine resolver 344, Fig.18 1818. The second domain angle estimate 1812 is received from the fine resolver 344 in a second domain (e.g., a 16x speed domain) associated with the fine resolver 344. The logic 1802 differentiates the second domain angle estimate 1812 to determine a change in position (speed) in the second domain. For example, the previous position value 1814 is subtracted from the current position value 1816 of the second domain angle estimate 1812 to generate a change in position value 1818. The change in position value 1818 may be converted to a 32-bit signed integer and delayed to account for a processing pipeline or flow of the circuitry used to execute the logic 1802. The change in position value 1818 is right shifted 4 bits (divided by 16) to convert the change in position value 1818 into the first domain to generate a converted change in position value 1820 (e.g., Figure 3 The transformed fine position signal of the fine resolver 344 is represented by the transformed position change value 1820 . The transformed position change value 1820 represents the position change determined by the fine resolver 344 with respect to the first domain.

[0179] The logic 1802 receives an estimated initial position 1822 determined based on the coarse position signal of the coarse resolver 342. The estimated initial position 1822 corresponds to a first or initial angle estimate of the angle estimate 364 of the coarse resolver 342. The estimated initial position 1822 represents an initial position determined by the coarse resolver 342 and is located in a first domain. A switch 1826 (e.g., an initialization switch) is configured to output the estimated initial position 1822 when a Boolean input 1824 (init_rslv) indicates true (i.e., the dual speed resolver 312 is in initialization mode). The switch 1826 is configured to output position feedback (e.g., a previously determined position, such as the delayed combined estimated angle 1844) when a Boolean input 1824 (init_rslv) indicates false (i.e., the dual speed resolver 312 is not in initialization mode).

[0180] The converted position change value 1820 and the estimated initial position 1822 are combined by a combiner 1830 (eg, an adder or other arithmetic circuit) to generate a combined estimated angle 1832 (eg, an estimated position of the motor). The combined estimated angle 1832 includes or corresponds to Figure 3 In some embodiments, combiner 1830 also receives drift correction value 1828 and is configured to generate combined estimated angle 1832 further based on drift correction value 1828. In such embodiments, combined estimated angle 1832 is delayed (e.g., by zero-order hold) to generate delayed combined estimated angle 1844. Delayed combined estimated angle 1844 is provided to Figure 5 The drift correction circuit 544 is used to generate the drift correction value 1828. The generation of the drift correction value 1828 is referenced Fig.19 For the first or initial combined estimated angle 1832 (ie, initial position), the drift correction value 1828 is zero because the drift correction circuit 544 has not yet received the combined estimated angle 1832 and started providing the drift correction value 1828 .

[0181] The combined estimated angle 1832 is provided as an output of the logic 1802. In some embodiments, the logic 1802 generates one or more additional outputs based on the combined estimated angle 1832. For example, the combined estimated angle 1832 is combined with a rotor offset 1852 for commutation of the rotor. For illustration, the rotor offset 1852 for commutation of the motor 124 accounts for misalignment between the solver and the rotor magnets of the motor 124. Additionally or alternatively, the combined estimated angle 1832 is combined with a rotor offset 1862 (e.g., a rotor servo offset) for servo control of the rotor. For illustration, the rotor offset 1862 for servo control of the motor 124 accounts for misalignment of the universal joint (e.g., Figure 1 The offset of one of the gimbals 122 of the rotor 1852 relative to the horizon pointing upward or opposite to gravity. In a particular embodiment, the rotor offsets 1852, 1862 are constant values ​​and are input by the user.

[0182] These rotor offsets 1852, 1862 are often referred to as taring the resolver outputs. Taring the resolver outputs helps improve accuracy, and precision taring is often required in conventional dual resolvers. However, taring has a reducing effect (reduced improvement), and less precise taring may be used when reducing noise due to the time coordination of the excitation signal and the current drive switching, when adding jitter to the excitation signal, or both, as described with reference to FIGS. 22-28. The tared outputs 1856, 1866 may be provided to other components to adjust the commutation and servo control of the rotor. For example, the servo offset output 1866 may be provided to Figure 2The feedback control system 232 is used for initialization of the inertial measurement unit 102, as shown in FIG. Fig.32 As another example, the balancing outputs 1856, 1866 may indicate an estimated position of the motor 124. For illustration, when the combined estimated angle 1832 indicates Figure 3 The combined estimated angle 1832 may be adjusted to indicate the position of the motor 124 when the position of the dual speed resolver 312 is determined. The combined estimated angle 1832 is adjusted / tare to indicate the estimated position of the motor or its components (e.g., Figure 3 Additionally or alternatively, the tared outputs 1856 , 1866 may be used to determine an estimated RPM 368 of the motor 124 .

[0183] Independent of the subsequent coarse resolver 342 position input, the logic 1802 generates a subsequent position output (an output after determining the initial position or after the initialization process). For illustration, when the Boolean input 1824 indicates that the initialization process is complete (e.g., when the Boolean input 1824 is equal to zero), the switch 1826 "filters out" the subsequent coarse resolver 342 position input (i.e., the estimated initial position 1822) and provides the previously calculated angle (delayed combined estimated angle 1844). In other words, the logic 1802 determines subsequent changes in position based solely on the subsequent fine resolver 344 output of the fine resolver 344.

[0184] Fig.19 1 is a logic diagram 1900 showing an example of logic 1902 of the drift corrector of the dual speed resolver 312. The operation of the logic 1902 may be performed by Figure 5 The drift correction circuit 544 of the embodiment is executed. The logic 1902 is configured to generate a drift correction value 1828 based on the delayed combined estimated angle 1844, the second domain angle estimate 1812 and the 180 degree bias value 1918.

[0185] The logic 1902 receives the angle estimate 364 of the fine resolver 344 of the dual speed resolver 312 as the second domain angle estimate 1812. The logic 1902 also receives the delayed combined estimated angle 1844 (e.g., by Fig.18 The delayed combined estimated angle 1844 is in a first domain (e.g., 1x speed domain) associated with the motor 124 and the coarse resolver 342. The logic 1902 converts the delayed combined estimated angle 1844 to a second domain (e.g., 16x speed domain) associated with the fine resolver 344 of the dual speed resolver 312. Fig. 9 As shown, the delayed combined estimated angle 1844 is left shifted by 4 bits (multiplied by 16) to generate a converted estimated angle 1914 (eg, a transformed initial position output).

[0186] The converted estimated angle 1914 and the 180 degree bias value 1918 are subtracted from the second domain angle estimate 1812 to generate an error value 1920. Fig. 9 In the illustrated embodiment, the logic 1902 uses 32-bit integers, and the 180 degree offset value 1918 corresponds to the value 2^31-1 (or 2^(number of bits-1)-1). The 180 degree offset value 1918 provides protection from noise and integer mathematical errors that may cause incorrect alignment of the resolvers 342, 344 during initialization. Such noise and integer mathematical errors may be caused by the differentiation of the second domain angle estimate 1812.

[0187] The error value 1920 may be converted to a signed integer, such as a 32-bit signed integer. The proportional gain 1922 and the integral gain 1924 are applied to the error value 1920 by the proportional gain circuit and the integral gain circuit. In some implementations, the proportional gain 1922 and the integral gain 1924 are generated based on the error value 1920. Fig.19 As shown, proportional gain 1922 is generated by right shifting error value 1920 by 15 bits (divided by 32768), and integral gain 1924 is generated by switch 1926. Switch 1926 outputs integral gain 1924 having a value of 1 or -1 based on comparing error value 1920 to a comparison condition greater than or equal to zero.

[0188] The comparison gain 1922 and the integral gain 1924 are combined (added) by a combiner 1928 to generate a drift correction value 1828. The drift correction value 1828 may be stored, provided to the logic 1802, or both. For example, the drift correction value 1828 is provided to a combiner 1830 of the logic 1802 to determine a next combined estimated angle 1832, such as a reference angle. Fig.18 The next combined estimated angle 1832 adjusts or corrects the subsequent combined estimated angle 1832 (the combined estimated angle 1832 of the subsequent position) to account for the lower precision of the coarse resolver output used when generating the combined estimated angle 1832 for the initial position. Thus, the logic 1902 can correct or reduce the precision of the coarse resolver output used in the dual speed resolver (e.g. Figure 3 The error that occurs when solvers of different speeds are combined in the dual-speed solver 312).

[0189] Fig. 20 Schematic diagram 2000 is included showing an estimated angle 2002 of the resolver system 204 and an actual angle 2004 of the motor. The estimated angle 2002 may include or correspond to Figure 3 Estimated location 366 or Fig.18 Alternatively, estimated angle 2002 may include or correspond to adjusted (balanced) estimated position 366 (e.g., Fig.18 1856, 1858) or Fig.18 1832. Schematic diagram 2000 shows estimated angles 2002 output by resolver system 204 during and after an initialization process or mode.

[0190] exist Fig. 20 At a first time T1, the solver system 204 is activated and begins an initialization mode or process. During the initialization mode or process, the solver system 204 generates an initialization calculation based on the coarse solver output. Fig. 20 At the second time T2, an initial position output 2012 of the estimated angle 2002 is generated. Fig. 20 After the second time T2, the solver system 204 begins to correct the estimated angle 2002 using the drift correction circuit 544. Fig. 20 At the third time T3, the drift correction circuit 544 has adjusted for the initial error of the coarse resolver 342 and is locked to the position of the fixed motor. After the third time T3, the resolver system 204 generates a subsequent position output 2014 of the estimated angle 2002. Fig. 20 At the fourth time T4, the motor starts to move. Fig. 20 At the fifth time T5, the motor stops moving.

[0191] Fig.21 Included is a schematic diagram 2100 depicting Fig. 20 2100 better illustrates the delay and accuracy of the solver system 204. Schematic diagram 2100 depicts a small error at a third time T3 after the drift correction circuit 544 has been adjusted for the initial error of the coarse solver 342 and locked to the position of the fixed motor. Fig. 20 As described above, at the fourth time T4, the motor starts to move. However, as shown in the reference Fig.12 and Fig.13 The demodulation processing delay described above does not allow the resolver system 204 to detect the movement and output an angle estimate corresponding to the movement until Fig.21 After the fifth time T5, the resolver system 204 begins tracking the movement of the motor occurring at the fourth time T4. The schematic diagram 2100 shows an accuracy of 0.01 arc seconds.

[0192] Fig.22A is a diagram 2202 showing an angle determined based on a resolver output using an excitation signal without dithering (eg, excitation signal 452 of FIG. 4 ). Fig.22A The motor is depicted activated at about 0.02 seconds and deactivated at about 0.0375 seconds. Fig.22A, the estimated angle 2002 of the drive shaft of the motor tracks the actual angle 2004 of the drive shaft with an accuracy of approximately 1.23 arc seconds. The motor is reactivated and resumes movement at approximately 0.06 seconds, and the resolver system 204 continues to track the motor.

[0193] Fig. 22B 2204 is a diagram showing an ADC output 2252 generated based on a resolver output generated by an excitation signal without jitter. The ADC output 2252 is substantially symmetrical and uniform, and the ADC output 2252 is latched to a single bit for a relatively long period of time. Latching to a single bit for a relatively long period of time prevents oversampling to improve accuracy because it causes the accumulated value to be non-zero and / or unchanged.

[0194] Fig.23 is a diagram showing an excitation signal containing jitter (such as Figure 3 Schematic diagram 2300 of an example of a jitter excitation signal 352). Fig.23 In the example, the jitter excitation signal 352 still repeats like a normal sine wave, but the amplitude of the jitter excitation signal 352 has local variations. For example, the amplitude of the jitter excitation 352 has sinusoidal fluctuations (e.g., first harmonics) during the sine wave of the basic excitation signal 452. To illustrate, the amplitude sometimes increases during the transition from peak to valley, and sometimes decreases during the transition from valley to peak. Fig.23 As shown, the excitation signal 452 is dithered based on the high-order even harmonics of the excitation signal 452 to generate the dithered excitation signal 352. Therefore, the dithered excitation signal 352 includes a "mini sine wave" deviation relative to the excitation signal 452. Because high-order even harmonics (e.g., 16th harmonics) are used, the dithering does not affect or change the average amplitude of the sine wave because the basic excitation signal 452 and the even harmonics have the same phase and because the harmonic signal has the same function as the basic excitation signal 452. Therefore, the dithering does not introduce noise that causes additional errors and reduced accuracy.

[0195] Fig.24 2400 is a diagram showing an ADC output 2402 generated based on a resolver output generated by a dithered excitation signal. Fig. 22B Compared to the ADC output 2252 generated based on the excitation signal without dithering, the ADC output 2402 generated based on the dithered excitation signal has greater variability, and the ADC output 2402 does not lock to the same value for long or too long. Therefore, the accumulated output 1024 can fluctuate and be zero. Therefore, the estimated angle 2002 can fluctuate from overestimating and underestimating the actual angle 2004, such as Fig.25 shown.

[0196] Fig.25 It is shown based on Fig.23 Schematic diagram 2500 of the dither excitation signal 352 generated by the resolver output based on the angle determined. Fig.25 , the estimated angle 2002 of the drive shaft of the motor tracks the actual angle 2004 of the drive shaft. The dithering excitation signal 352 causes the estimated angle 2002 to switch between overestimating and underestimating the actual angle 2004 of the drive shaft. Thus, by averaging the estimated angle 2002 (e.g., averaging over 1 second intervals), the dithering excitation signal 352 enables the resolver system 204 to provide an accuracy of 0.01 arc seconds. Fig.22A Compared with the accuracy of 2002's estimated angles, the accuracy of 0.01 arc seconds represents an increase in accuracy of multiple orders of magnitude.

[0197] Fig.26 26 is a logic diagram 2600 illustrating an example of logic 2602 for excitation signal generation. The logic 2602 is configured to generate a signal to be provided to an active sensor (e.g., Figure 3 For example, the logic 2602 outputs the digital differential output to the DAC 310, which converts the digital differential output into an excitation signal for the rotating primary coil 422 provided to the resolvers 342, 344. Figure 2 The excitation signal generation system 202 (eg, excitation signal generation circuitry) performs the operations of the logic 2602 .

[0198] Logic 2602 enables generation of different types of excitation signals, including Figure 3 The jitter excitation signal 352 of FIG. 4 or the excitation signal 452 of FIG. 4. The logic 2602 includes one or more logic chains configured to generate an excitation signal. Fig.26 As shown, logic 2602 includes three logic chains 2612-2616. Each logic chain 2612-2616 is used to generate a portion of the excitation signal. In other embodiments, logic 2602 may include additional logic chains or fewer logic chains. Fig.26 In the example shown, logic 2602 includes logic chains 2612-2616, two of which (logic chains 2612 and 2614) are active.

[0199] The first logic chain 2612 is configured to generate a first order harmonic (ie, the fundamental excitation signal 452). The second logic chain 2614 is configured to generate a jitter. Fig.26As shown, the second logic chain 2614 is configured to generate high-order even harmonics of the basic excitation signal. An example of a high-order even harmonic is the 16th harmonic. Other high-order even harmonics may be used, depending on the sampling rate of the ADC and DAC, the frequency of the hardware, or a combination thereof. For example, other embodiments may utilize the 8th harmonic, the 10th harmonic, the 12th harmonic, the 18th harmonic, the 20th harmonic, the 24th harmonic, the 32nd harmonic, the 64th harmonic, etc., or a combination thereof. The third logic chain 2616 is configured to generate low-order odd harmonics of the basic excitation signal. As shown Fig.26 As shown, the third logic chain 2616 is configured to generate the third harmonic of the basic excitation signal 452. Adding one or more low-order odd harmonics tends to "square" the excitation signal. Other low-order odd harmonics can be used alone or in combination with the third harmonic to square the excitation signal. Squaring the excitation signal can increase the signal-to-noise ratio of the sensor output.

[0200] During operation, the first logic chain 2612 generates the basic excitation signal 452. Fig.26 As shown, the first logic chain 2612 generates the basic excitation signal 452 as a differential signal (including a positive signal component and a negative signal component). The first logic chain 2612 receives two inputs: a sine function at input 2652 and an amplitude setting of the sine function at input 2654. In some embodiments, the first logic chain 2612 reduces the number of bits of the sine function, the amplitude setting, or both. Additionally or alternatively, the first logic chain 2612 reduces the number of bits of the sine function, the amplitude setting, or both by adding a user-defined value (e.g., Fig.26 The first logic chain 2612 multiplies the sine function by the shifted amplitude setting to generate an intermediary sine wave.

[0201] The first logic chain 2612 generates a differential output (eg, a positive output and a negative output) based on the intermediate sine wave. For example, the first logic chain 2612 includes a conversion logic 2622 configured to generate a differential output based on generating positive and negative values ​​for each value of the intermediate sine wave.

[0202] In some embodiments, the conversion logic 2622 is further configured to convert the positive output and the negative output to unsigned values ​​and further reduce the number of bits of the positive output and the negative output for Figure 3 When the positive output and the negative output have more bits than the number of bits that the DAC 310 is configured to process, reducing the number of bits of the positive output and the negative output does not reduce the accuracy of the inertial measurement unit 102. In addition, the first conversion logic 2622 adjusts the positive output and the negative output based on the addition of the intermediate voltage offset value 2630. Fig.26, the intermediate voltage offset value 2630 is 2^11-1, and DAC 310 is a 12-bit DAC.

[0203] The first logic chain 2612 provides the positive and negative outputs of the first logic chain 2612 to the combiners 2624, 2626. The positive and negative outputs of the first logic chain 2612 correspond to the fundamental excitation signal 452 (or the first harmonic of the dithered excitation signal 352).

[0204] The second logic chain 2614 generates jitter to be added to (combined with) the excitation signal generated by the first logic chain 2612. The second logic chain 2614 receives two inputs: the higher order even harmonics of the sine function at input 2662 and the amplitude setting of the higher order even harmonics of the sine function at input 2664. In some embodiments, the second logic chain 2614 reduces the number of bits of the higher order even harmonics of the sine function, the amplitude setting of the higher order even harmonics, or both. Additionally or alternatively, the ... Fig.26 The second logic chain 2614 multiplies the higher order even harmonics of the sine function by the shifted amplitude setting to generate a higher order even harmonic signal 2666 (ie, an example of dithering of the dithered excitation signal 352).

[0205] The second logic chain 2614 generates a differential output (e.g., a positive output and a negative output) based on the high-order even harmonic signal 2666. For example, the second logic chain 2614 includes a conversion logic 2622 configured to generate a differential output based on generating a positive value and a negative value for each value of the high-order even harmonic signal 2666.

[0206] The second logic chain 2612 (or conversion logic 2622 ) may convert the positive and negative outputs to unsigned values ​​and may further reduce the number of bits of the positive and negative outputs similar to the first logic chain 2602 for processing by the DAC 310 .

[0207] The operation of the third logic chain 2606 is similar to the operation of the second logic chain 2614. In a particular embodiment, the amplitude of the third logic chain 2602 is set to zero, that is, the logic 2602 does not use the third harmonic to generate the excitation signal.

[0208] The combiners 2624, 2626 combine the outputs of the logic chains 2612-2616. For example, the combiner 2624 adds the positive outputs of the first logic chain 2612 and the second logic chain 2614 to generate a positive combined output. The combiner 2624 adds the negative outputs of the first logic chain 2612 and the second logic chain 2614 to generate a negative combined output. The logic 2602 provides the positive combined output and the negative combined output to the DAC 310 via the output terminals 2642, 2644. The DAC 310 converts these combined outputs into the dithering excitation signal 352. In other embodiments, the combiners 2624, 2626 can subtract the output of the third logic chain 2616.

[0209] In some implementations, logic 2602 includes logic for initializing a process. Fig.26 As shown, logic 2602 includes switches 2632, 2634, Boolean input 2636 ( Fig.26 The intermediate voltage is marked as frozen) and the intermediate voltage is initialized to 2638. Fig.26 In the example shown, the DAC 310 is a 12-bit DAC and the intermediate voltage value is half of the 12-bit value (2^11-1). The switches 2632, 2634 are configured to switch between the combined excitation signal output of the output combiners 2624, 2626 or the intermediate voltage initialization value 2638 based on the Boolean input 2636. Fig.26 As shown, logic 2602 is not operating in an initialization mode, as indicated by the positions of switches 2632 , 2634 .

[0210] In some embodiments, a table storing numerical values ​​(e.g., a lookup table) is used to generate the sine function input. In a particular embodiment, the lookup table for the sine function input is shared, that is, one sine lookup table generates the sine function input for the three logic chains 2612-2616. In addition, as further described herein, the sine lookup table can be shared with other components and logic of the inertial measurement unit 102. For example, the sine lookup table can be shared with other components and logic through round-robin scheduling. In other embodiments, the sine function input is calculated using a series of arithmetic logic operations (e.g., addition and shift operations) or Taylor expansion.

[0211] Fig. 27 27 is a circuit diagram 2700 showing an example of a resolver driver circuit 2702. The resolver driver circuit 2702 generates a differential excitation signal (eg, Figure 3 4) and sends the differential excitation signal to the resolver via terminals 2712 and 2714. The resolver driver circuit 2702 may include or correspond to Figure 2The excitation signal generating system 202. In some embodiments, the differential excitation signal is time-coordinated with the current drive switching of the motor.

[0212] The resolver driver circuit 2702 includes a low precision ADC 2704 and a high precision ADC 2706. As an example, the low precision ADC 2704 may be a 10-bit or 12-bit ADC, and the high precision ADC 2706 is a 16-bit ADC. In other embodiments, other sized ADCs may be used. The low precision ADC 2704 and the high precision ADC 2706 are configured to dither the excitation signal (or the dithered excitation signal 352) with respect to the excitation signal. Figure 2 and Figure 3 The PWM 242, ADC 318, 320 and demodulation system 222 are time coordinated.

[0213] The low precision ADC 2704 is configured to receive the resolver output and generate a differential excitation signal. The low precision ADC 2704 provides the differential excitation signal to the resolver. For example, the low precision ADC 2704 provides the differential signal to the Figure 3 The low precision ADC 2704 is also configured to generate a serial peripheral interface (SPI) excitation signal 2742 and send the SPI excitation signal 2742 to a component of the inertial measurement unit 102, such as its FPGA.

[0214] The high precision ADC 2706 is configured to receive the resolver output and generate an SPI feedback signal 2744. The SPI feedback signal 2744 is provided to components of the inertial measurement unit 102, such as its FPGA. The SPI excitation and feedback signals 2742, 2744 enable time coordination between components of the inertial measurement unit 102. The SPI excitation and feedback signals 2742, 2744 can be generated based on the resolver feedback. For example, the SPI excitation signal 2742 is generated based on positive sine and cosine feedback (and independent of negative sine and cosine feedback), and the SPI feedback signal 2744 is generated based on differential sine and cosine feedback.

[0215] During operation, the resolver driver circuit 2702 receives differential sine feedback from a particular resolver (e.g., one of the resolvers 342, 344) of the dual speed resolver 312 at terminals 2722 and 2724. The resolver driver circuit 2702 receives differential cosine feedback from the particular resolver at terminals 2732 and 2734. The differential sine and cosine feedback are used to generate a differential resolver excitation signal and a feedback signal. Because the differential excitation signal and the SPI excitation signal 2742 are generated based on the resolver feedback, the DAC 310, the dual speed resolver 312, the differential voltage sensors 314, 316, or a combination thereof can be time coordinated. Because the SPI feedback signal 2744 is generated based on the resolver feedback and indicates the timing of the resolver system 204 (e.g., the timing of the input and output), the demodulation system 222, the dual resolver combination system 224, the feedback control system 232, the PWM 242, or a combination thereof can be time-coordinated with each other, and these components are time-coordinated by the SPI excitation signal 2742. For illustration, the SPI excitation and feedback signals 2742, 2744 indicate data and clock data (e.g., when the data is sampled), thereby achieving synchronization between the components. Additionally or alternatively, the PWM 242 can achieve time coordination with the above components through counter or clock synchronization, as described in reference Figure 33-35 described.

[0216] Fig.28 28 is a circuit diagram 2800 showing an example of a motor driver circuit 2802. The motor driver circuit 2802 is coupled to a power source and a motor, such as Figure 1 and Figure 2 power source 252 and motor 124. Fig.28 The motor driver circuit 2802 shown in corresponds to an inverter for a three-phase motor, such as Figure 1 In this embodiment, the power supply 252 provides DC power to the motor driver circuit 2802. The motor driver circuit 2802 converts the DC power into an AC signal and provides the AC signal to the motor, for example, providing the AC power signal 380 to the motor 124, as shown in FIG. Figure 3 In other embodiments, motor 124 may have more than three phases or less than three phases. For an inertial measurement unit 102 including a gimbal device 114 having multiple gimbals 122 , inverter 112 may have a motor driver circuit 2802 for each motor 124 driving a corresponding gimbal 122 .

[0217] The motor driver circuit 2802 includes six transistors 2822-2826, 2832-2836 arranged in three half bridges. In other embodiments, the six transistors 2822-2826, 2832-2836 can be arranged in a full bridge. The six transistors 2822-2826, 2832-2836 are configured to control the power delivery to a specific motor 124. The first, second and third transistors 2822-2826 correspond to upper transistors, and the fourth, fifth and sixth transistors 2832-2836 correspond to low transistors. The first and fourth transistors 2822, 2832 correspond to the first phase (first lane) of the motor. The second and fifth transistors 2824, 2834 correspond to the second phase (second lane) of the motor, and the third and sixth transistors 2826, 2836 correspond to the third phase (third lane) of the motor. In some embodiments, the six transistors 2822-2826, 2832-2836 include or correspond to N-channel MOSFETs. The six transistors 2822-2826, 2832-2836 may include or correspond to Figure 3 Transistor 336.

[0218] In some embodiments, the motor driver circuit 2802 includes one or more high bandwidth current sensors 2812 configured to determine the current of the motor driver circuit 2802. Fig.28 As shown, the motor driver circuit 2802 includes two high-bandwidth current sensors 2812. In other embodiments, the motor driver circuit 2802 includes more than two high-bandwidth current sensors 2812 or less than two high-bandwidth current sensors 2812. Fig.28 In the particular example shown, the high bandwidth current sensor 2812 includes or corresponds to a Hall effect current sensor. The high bandwidth current sensor 2812 is configured to perform a continuous built-in test of the current of the motor driver circuit 2802.

[0219] In some implementations, the motor driver circuit 2802 includes one or more voltage sensors 2814 configured to determine the voltage of the motor driver circuit 2802. Fig.28 As shown, the motor driver circuit 2802 includes three voltage sensors 2814, each of which is coupled to an output terminal (e.g., source) of an upper transistor 2822-2826. Fig.28 As shown, voltage sensor 2814 is configured to determine the voltage at the output of upper transistors 2822-2826, which may correspond to the voltage provided to the motor. Fig.28Also shown is a schematic diagram of a first transistor 2822 of the upper transistors 2822-2826. The schematic diagram shows three terminals 2862-2866. Transistor 2822 includes a first terminal 2862 (eg, drain), a second terminal 2864 (eg, gate), and a third terminal 2866 (eg, source).

[0220] The motor driver circuit 2802 includes a gate driver 2842 to drive the gates (second terminals 2864) of the six transistors. The gate driver 2842 is configured to generate an activation signal and provide the activation signal to the gates (second terminals 2864) of the six transistors 2822-2826, 2832-2836. For example, the gate driver 2842 generates high and low logic signals in response to the PWM pulse signal, and provides the high and low logic signals to the gates (second terminals 2864) of the six transistors 2822-2826, 2832-2836, which controls the three-phase power delivery to the motor.

[0221] The motor driver circuit 2802 can include a bootstrap power supply line 2844 for the upper transistors 2822-2826. For example, when the upper transistors 2822-2826 include N-channel MOSFETs, the bootstrap power supply line 2844 is used to drive the upper transistors 2822-2826.

[0222] The motor driver circuit 2802 is coupled to the output terminal (e.g., via output terminal 2852) between the upper transistors 2822-2826 and the lower transistors 2832-2836. Figure 1 The motor 124. Fig.28 As shown, third terminals 2866 (eg, sources) of upper transistors 2822-2826 and first terminals 2862 (eg, drains) of lower transistors 2832-2836 are coupled to the motor.

[0223] In some embodiments, the motor driver circuit 2802 is controlled by an FPGA and time-coordinated with the solver stimulus. Figure 2 The PWM 242 control, as referenced Figure 32-35 Additionally or alternatively, the motor driver circuit 2802 is time coordinated with the resolver sensing. Time coordination with the resolver excitation and sensing reduces noise and errors in the resolver output and improves the accuracy of determining the drive shaft of the motor. For example, time coordination reduces electromagnetic interference caused by motor driver switching.

[0224] Fig.2929 is a schematic diagram 2900 showing an example of a cascade feedback logic 2902 for velocity feedback and position feedback. The cascade feedback logic 2902 includes an outer loop 2912 and an inner loop 2914. The outer loop 2912 and the inner loop 2914 refer to feedback loops corresponding to position and velocity feedback 2924, 2936 generated as a result of a current command 2940. The current command may include or correspond to Figure 3 The current command 372.

[0225] The outer loop 2912 corresponds to a position feedback loop and is configured to generate a rate command 2930 based on the received position command 2922. The position command 2922 and the position feedback 2924 are used to generate an intermediate signal (e.g., an error signal). A control gain is applied to the intermediate signal to generate the rate command 2930. The rate command 2930 indicates a rate, such as a rate of change of position. The rate command 2930 (generated by the cascade feedback logic 2902) may indicate a speed similar to the speed command 2932 (received from the flight computer), but the rate command 2930 may have different units than the speed command 2932. For example, the units of the rate command 2930 may be radians per second, while the units of the speed command 2932 may be RPM.

[0226] The inner loop 2914 is configured to limit the rate command 2930 based on the speed command 2932 (e.g., RPM command) to generate a limited rate command 2934. Speed ​​feedback 2936 (e.g., RPM feedback) is applied to the limited rate command. The limited rate command 2934 and a second control gain (e.g., RPM gain 2938 (Krpm)) are applied to generate a current command 2940. The inner loop 2914 outputs the current command 2940, and for example, Figure 3 The current tracker 330 converts the current command 2940 into a duty cycle value for the PWM 242 .

[0227] During operation, the outer ring 2912 is Figure 2 The flight computer 254 receives the position command 2922 and receives the position feedback 2924 from the resolver system 204. The outer loop 2912 generates an error signal based on subtracting the position feedback 2924 from the position command 2922. A control gain is applied to the error signal to generate a rate command 2930. For example, the error signal is multiplied by a proportional gain 2926, and the error signal (or its integral) is multiplied by an integral gain 2928. The outer loop 2912 provides the rate command 2930 to the inner loop 2914.

[0228] Inner loop 2914 rate limits rate command 2930 based on speed command 2932. For example, when speed command 2932 indicates a lower RPM than rate command 2930, rate command 2930 is reduced. To illustrate, when the RPM indicated by speed command 2932 corresponds to a position change value that is smaller (slower) than the position change value of rate command 2930, inner loop 2914 reduces the position change value of rate command 2930 to the position change value of speed command 2932. Inner loop 2914 subtracts the position change value from limited rate command 2934 from the position change value of speed command 2932. Figure 2 The resolver system 204 receives the speed feedback 2936 to generate a second error signal. A current command 2940 is generated based on applying a second control gain to the second error signal. For example, the second error signal is multiplied by the RPM gain 2938. The inner loop 2914 is directed to Figure 1 The inverter 112 provides a representation Figure 1 The current command 2940 of the torque of the motor 124 is used to control the inverter 112 based on the current command 2940. Figure 1 The inner loop 2914 of the cascade feedback logic 2902 may be difficult to implement, especially for low damping systems, such as those used for positioning Figure 1 The motor 124 of the universal joint 122 .

[0229] Fig.30 is a logic diagram 3000 showing an example of logic 3002 for combined speed and position feedback control. Fig.29 Compared to schematic 2900 of FIG. 29, logic 3002 includes a single feedback loop for combining position and velocity feedback. Unlike schematic 2900, logic 3002 uses velocity feedback 2936 for damping rather than as a separate feedback loop. Additionally, logic 3002 generates a rate limited position command 3034 (e.g., a combined velocity and position command) before applying feedback. Fig.29 Compared to the cascade feedback logic 2902, the logic 3002 is for low damping motors (e.g., for positioning Figure 1 The motor 124 of the universal joint 122 provides improved control and lower complexity.

[0230] During operation, logic 3002 is Figure 2 The flight computer 254 receives the position command 2922 and the speed command 2932. The logic 3002 rate limits the position command 2922 based on the speed command 2932 to generate a rate limited position command 3034. For example, when the position change relative to the previous position indicated by the speed command 2932 (converted to a position value indicating a maximum position change relative to the previous position) is less than a second position change relative to the previous position indicated by the position value of the position command 2922, the position value of the position command 2922 is decreased.

[0231] The rate limited position command 3034 is generated before the error signal 3012 is generated (or the control gain is applied). The logic 3002 generates the error signal 3012 by subtracting the position feedback 2924 from the rate limited position command 3034. For example, the position value of the rate limited position command 3034 is adjusted based on the position value of the position feedback 2924 to generate a position error.

[0232] The logic 3002 applies the control gain to the error signal 3012. For example, the logic 3002 multiplies the error signal 3012 by the proportional gain 2926 and multiplies the error signal 3012 by the integral gain 2928. The logic 3002 generates the adjusted error signal 3014 based on the sum of the two products of the error signal 3012 and the gains 2926, 2928. In a particular embodiment, the first product corresponds to the derivative of the error signal 3012 multiplied by the proportional gain 2926.

[0233] Additionally, the logic 3002 may dampen the adjusted error signal 3014 based on the speed feedback 2936. The logic 3002 multiplies the speed feedback 2936 by the RPM gain 2938 (e.g., a damping factor) to generate an RPM damping value 3016. The logic 3002 subtracts the RPM damping value 3016 from the adjusted error signal 3014 to dampen the adjusted error signal 3014. For example, damping the adjusted error signal 3014 will generate a damped error signal. The logic 3002 generates the current command 2940 based on the damped error signal. For example, the logic 3002 integrates the damped error signal to generate the current command 2940. Fig.29 Compared to the cascaded feedback logic 2902, logic 3002 provides improved control and stability for a low damping motor with less complexity (eg, without multiple or nested control loops).

[0234] Fig.31 and Fig.32 is a logic diagram showing an example of logic for combined speed and position feedback including multiple operating modes. Fig.31 and Fig.32 The diagrams shown have been simplified for clarity. For example, Fig.31 Some of the logic boxes in the schematic diagram are blank and about Fig.32 In addition, some conversions, shifts, holds, and constant values ​​are omitted in the description for clarity. Fig.31 and Fig.32In the figure, the conversion logic box is represented by the letter "C" to represent the bit conversion, "si" represents the signed / unsigned conversion, the shift logic box is represented by a three-character string including the letter "S", the direction (i.e., "L" or "R") and the number of bits, the absolute value logic box is represented by "abs", and the hold or delay unit is represented by "1 / z".

[0235] refer to Fig.31 , which shows a logic diagram 3100 of an example of logic 3102 for combined speed and position feedback control including a direct speed command mode. Fig.30 Compared to the logic 3002 of FIG. 3 , the logic 3102 is configured to operate in a direct speed mode or in a position and speed mode. By utilizing the direct speed mode and the position and speed mode, the logic 3102 can control the motor 124 by adjusting the torque or speed of the motor 124. The logic 3102 includes direct speed command mode logic 3112, position command logic 3114, speed command logic 3116, rate limiter logic 3118, error generation logic 3120, combined proportional gain logic 3122, combined integral gain logic 3124, and output logic 3126.

[0236] The direct speed command mode logic 3112 is configured to generate a derived position command 3132 based on the speed command 2932. The derived position command 3132 indicates an incremental change in position relative to a previous position. The direct speed mode may include or correspond to a direct RPM command mode. The direct RPM command mode includes or corresponds to the flight computer 254 only Figure 3 After switching from the first mode (position and speed mode) to the second mode (direct speed mode), the direct speed command mode logic 3112 is configured to output the speed command 2932 (RPM command) in the command 370 of FIG. Figure 2 The resolver system 204 determines the position of the motor (e.g., the estimated position 366) instead of deriving the position command 3132. By outputting the estimated position 366 after switching modes, the direct speed command mode logic 3112 achieves smooth operation of the motor (e.g., reduces or eliminates jitter from switching modes). The operation of the direct speed command mode logic 3112 can be performed by the direct speed circuit. As an example, the direct speed circuit includes one or more combiners, multipliers, delay elements, switches, etc. to perform the operation of the direct speed command mode logic 3112, such as Fig.31 shown.

[0237] Position command logic 3114 is configured, for example, to Figure 2The flight computer 254 receives the position command 2922 and outputs the position command 2922 to the rate limiter logic 3118 when in the first mode. The position command logic 3114 is configured to output the derived position command 3132 when in the second mode. For example, the position command logic 3114 includes a switch 3134 that is configured to provide the derived position command 3132 to the rate limiter logic 3118 based on a Boolean input indicating that the logic 3102 is operating in the second mode. Therefore, when operating in the second mode, the output logic 3126 generates the current command 2940 based on the speed command 2932 and independently of the position command 2922.

[0238] The speed command logic 3116 is configured to receive the speed command 2932 and provide the speed command 2932 to the rate limiter logic 3118. In some embodiments, the speed command logic 3116 is configured to convert the speed command 2932 to an unsigned integer and convert the value of the speed command 2932 to an absolute value. Additionally or alternatively, the speed command 2932 can be adjusted for the resolver. For example, the speed command 2932 can be adjusted by multiplying the speed command 2932 by a constant value to account for the difference between the RPM of the motor and the resolver speed.

[0239] The rate limiter logic 3118 is configured to generate a rate limited position command 3034 based on the position command 2922 and the speed command 2932 when in the first mode. The rate limiter logic 3118 is configured to generate a rate limited position command 3034 based on the speed command 2932 when in the second mode. In some embodiments, the rate limiter logic 3118 is also configured to operate in an initialization mode, as described in reference to Fig.32 described.

[0240] The error generation logic 3120 is configured based on Figure 2 The rate-limited position command 3034 and the position feedback 2924 of the resolver system 204 generate an error signal 3012 (representing a position error). For example, the error generation logic 3120 generates the error signal 3012 by subtracting the position feedback 2924 from the rate-limited position command 3034. The operation of the error generation logic 3120 can be performed by an error signal generation circuit. As an example, the error signal generation circuit includes a combiner, such as Fig.31 shown.

[0241] The combined proportional gain logic 3122 is configured to apply the proportional gain 2926 to the error signal 3012. The combined proportional gain logic 3122 is configured to output the product of the error signal 3012 and the proportional gain 2926 to the output logic 3126. In a particular embodiment, the proportional gain 2926 is multiplied by the derivative of the error signal 3012 to produce the product. The combined integral gain logic 3124 is configured to apply the integral gain 2928 to the error signal 3012. The combined integral gain logic 3124 is configured to output the product of the error signal 3012 and the integral gain 2928 to the output logic 3126.

[0242] The output logic 3126 is configured to generate a current command 2940 based on the proportional gain 2926 and the integral gain 2928. For example, the output logic 3126 is configured to add the two products to generate an adjusted error signal 3014. The output logic 3126 is configured to generate the current command 2940 based on the adjusted error signal 3014. For example, the output logic 3126 is configured to integrate the adjusted error signal 3014 to generate the current command 2940. In a particular embodiment, the integrated adjusted error signal 3014 can be limited based on a maximum current value and a minimum current value to generate the current command 2940. The output logic 3126 outputs the current command 2940 via the output terminal 3130.

[0243] In some embodiments, the logic 3102 also includes damping logic 3128. The damping logic 3128 generates a damping value 3016 that is applied to the adjusted error signal 3014 to generate a damping error signal 3138. In such embodiments, the damping error signal 3138 is integrated to generate the current command 2940. In addition, the logic 3102 may include a switch (not shown) to control the damping mode, i.e., when damping is applied or not applied. The operation of the damping logic 312 may be performed by a damping circuit. As an example, the damping circuit includes one or more combiners, multipliers, delay elements, switches, etc. to perform the operation of the damping logic 3128, such as Fig.31 shown.

[0244] refer to Fig.32 , which shows a logic diagram 3200 of an example of logic 3202 for combined speed and position feedback control including an initialization mode. The logic 3202 includes Fig.31 The logic 3202 is similar to the logic 3102 of FIG. 1 and additionally includes initialization logic 3204. The initialization logic 3204 includes tracking logic 3212 and initial condition (ic) logic 3214.

[0245] Initialization logic 3204 is configured to receive and generate initialization inputs. For example, tracking logic 3212 is configured to receive position tracking enable input 3222 and RPM tracking enable input 3224. Tracking logic 3212 generates tracking input 3226 as output based on position tracking enable input 3222 or RPM tracking enable input 3224 indicating true (or tracking enabled).

[0246] IC logic 3214 is configured to generate IC input 3232 as an output based on position tracking enable input 3222 , RPM tracking enable input 3224 , initialization filter input 3228 , servo offset output 1866 , and RPM pulse tracking enable input 3230 .

[0247] Logic 3202 includes additional switches 3242-3248 as compared to logic 3102. Switches 3422-3428 are configured to input an initialization value (e.g., 0 or null value) in response to one or more of initialization inputs 3222-3232. For example, first switch 3242 receives initialization filter input 3228 and outputs the position of the motor determined by the resolver, or outputs position command 2922 based on initialization filter input 3228. To illustrate, when in initialization mode, the estimated position 366 of the motor is provided to rate limiter logic 3118, and after initialization mode, the position command 2922 is provided to rate limiter logic 3118.

[0248] Additionally, rate limiter logic 3118 is further configured to receive Figure 2 The resolver system 204 determines the present or current position of the motor (e.g., Figure 3 The rate limiter logic 3118 is configured to output the current position of the motor as a rate limited position command 3034 in response to the IC enable input indicating true. In a particular embodiment, the IC enable input is generated based on the IC input 3232 and the shutdown input 3236. For example, an OR logic gate generates the IC enable input based on the IC input 3232 and the shutdown input 3236. For illustration, when the IC input 3232 or the shutdown input 3236 indicates true, the IC enable input indicates true, and the rate limiter logic 3118 outputs the current position of the motor determined by the resolver (e.g., the estimated position 366) as the rate limited position command 3034.

[0249] The second switch 3244 receives the tracking input 3226 and outputs a zero value or an adjusted error signal 3014 (or a damped error signal 3138) based on the tracking input 3226. The third switch 3246 receives the freeze input 3234 and outputs a zero value or an adjusted error signal 3014 (or a damped error signal 3138) based on the freeze input 3234. Thus, if the tracking input 3226 or the freeze input 3234 is true, the third switch 3246 outputs zero instead of the adjusted error signal 3014 (or the damped error signal 3138).

[0250] The fourth switch 3248 receives a Boolean output generated based on the ic input 3232 and the shutdown input 3236. Based on the Boolean output, the fourth switch 3248 outputs a zero value or a current command. Fig.32 In the example shown, this Boolean output is output by an OR logic gate, so if either the ic input 3232 or the shutdown input 3236 is true, the switch 3248 outputs a zero. To illustrate, the logic 3202 outputs a current command 2940 indicating zero current during initialization and shutdown modes.

[0251] In other embodiments, equivalent logic may be used. For example, the second and third switches 3244 and 3246 may be replaced by a single switch and logic gate, similar to the fourth switch 3248 and the corresponding OR logic gate.

[0252] Fig.33 3300 is a schematic diagram showing an example of PWM operation with an adjustable comparison standard. Figure 2 The PWM 242 receives a set point signal including a comparison value and at least one comparison criterion. The at least one comparison criterion includes a Boolean condition. For example, the Boolean condition includes or corresponds to a greater than condition, a less than condition, a greater than or equal to condition, or a less than or equal to condition. In other embodiments, the comparison value and the at least one comparison criterion are received in separate signals. The PWM 242 is configured to control power delivery to a controlled component. The controlled component may include a light emitting diode, a duty cycle controller, a clock signal generator, a buck converter, a servo, a stepper motor, a single-phase motor, or a multi-phase motor.

[0253] exist Fig.33 In the embodiment, the counter 3302 (e.g., an up-down counter) is configured to count up from zero to a specific number and then count down from the specific number to zero. Fig.33 As shown, the counter 3302 counts up to 8192, and the counter signal 3304 generated by the counter 3302 is depicted by the dashed line. The PWM 242 includes a comparator for comparing the counter value of the counter signal 3304 with a comparison value 3322 (CMP) indicated by the set point signal. In some embodiments, the counter 3302 and the Figure 8 The synchronization of counter 842 and 3302 enables the current drive switching of the motor to be synchronized with the Figure 2 The excitation signal of the solver system 204 is synchronized (eg, offset) and enables masking of data affected by current drive switching.

[0254] Fig.33 The operation of the PWM 242 for five different set point signals 3312-3320 is depicted. The first set point signal 3312 includes a comparison value 3322 and two comparison criteria 3324, 3326. The PWM 242 determines the comparison value 3322 and the two comparison criteria 3324, 3326 by processing the set point signals 3312-3320. For example, the PWM 242 right-shifts the first set point signal 3312 to obtain the comparison value 3322. The PWM 242 uses the two least significant bits (LSBs) of the first set point signal 3312 to determine the two comparison criteria 3324, 3326. Figure 1 As shown, the first set point signal 3312 has a value of 16384. Right shifting the value 16384 of the first set point signal 3314 generates a value of 4096 for the comparison value 3322. In binary, the two LSBs of 16384 are "00". The PWM 242 determines that the two-bit value "00" corresponds to a first comparison criterion 3324 greater than and a second comparison criterion 3326 greater than. The PWM 242 can determine that the two-bit value corresponds to or indicates the two comparison criteria 3324, 3326 by processing the two-bit value with logic or by performing a table lookup.

[0255] In response to the comparison value 3322 satisfying the comparison criteria 3324, 3326 relative to the value of the counter 3302, the PWM 242 provides a high signal to the gate of the transistor (or causes a high signal to be provided). Providing a high signal to the transistor activates the transistor. Fig.33 As shown, when the comparison value 3322 having a value of 4096 is greater than the value of the counter 3302 (eg, when the counter value decreases to be lower than the comparison value 3322 having a value of 4096), the PWM 242 activates the transistor. Fig.33 , for the first set point signal 3312 , the transistor is activated at a counter value of 4095. Activating the transistor will generate a pulse edge of a pulse of the PWM signal based on the first set point signal 3312 .

[0256] In response to the comparison value 3322 not satisfying the comparison criteria 3324, 3326 relative to the value of the counter 3302, the PWM 242 provides a low signal to the gate of the transistor (or causes a low signal to be provided). Providing a low signal to the transistor disables the transistor. When the comparison value 3322 of 4096 is less than the value of the counter 3302 (e.g., when the counter value increases to be higher than the comparison value 3322 of 4096), the PWM 242 disables the transistor. Fig.33 , for the first set point signal 3312, the transistor is disabled at a counter value of 4096, which means that the transistor is turned on when the counter value is 4095. The on-time of the transistor (and the pulse width of the pulse of the PWM signal) is given by Fig.33 33 and 34. The cross-hatched triangle area in FIG. 33 is shown and corresponds to the time period when the comparison value 3322 is greater than the value of the counter 3302 for the first set point signal 3312. The transistor conduction time of the first set point signal 3312 is 8190 counts, i.e., the counts corresponding to the counter value going from 4095 to 0 and back from 0 to 4095.

[0257] PWM 242 receives second set point signal 3314. Second set point signal 3314 has a value of 16385. Right shifting the value 16385 of second set point signal 3314 generates a value of 4096 for comparison value 3322. In binary, the two LSBs of 16385 are "01". PWM 242 determines that the two-bit value "01" corresponds to a first comparison criterion 3324 of greater than or equal to and a second comparison criterion 3326 of greater than. Fig.33 As shown, when the comparison value 3322 having a value of 4096 is equal to the value of the counter 3302, that is, when the counter value is 4096, the PWM 242 activates the transistor. Activating the transistor will generate a pulse edge of the second pulse of the PWM signal based on the second set point signal 3314. When the comparison value 3322 having a value of 4096 is equal to (no longer greater than) the value of the counter 3302, the PWM 242 deactivates the transistor. Fig.33 , PWM 242 disables the transistor at a counter value of 4096. Disabling the transistor generates a second pulse edge of a second pulse of the PWM signal based on the second set point signal 3314. The on-time of the transistor (and the pulse width of the pulse of the PWM signal) is determined by Fig.33 33. The on-time of the second set point signal 3314 is one count higher (i.e., 1 in 8192) than the on-time of the first set point signal 3312. For illustration, the second set point signal 3314 indicates that the transistor is on for 8191 counts, i.e., counts corresponding to the counter values ​​of 4096 to 0 and 0 to 4095.

[0258] In conventional PWM, the comparison criteria is constant (e.g., only greater than or only greater than or equal to). Therefore, to increase the pulse width of the pulse, the comparison value is changed (similar to the comparison value changing from 4096 to 4097 between the first and fifth set point signals 3312, 3320). Changing the comparison value 3322 increases the on-time or pulse width by two counts. For example, increasing the comparison value 3322 from 4096 to 4097 (with a constant comparison criteria of greater than) increases the on-time count by 2, i.e., from 8190 counts for 4096 to 8192 counts for 4097. To illustrate, for a comparison value 3322 of 4097, the transistor on-time starts from 4097 to 0 and returns from 0 to 4097. Thus, the PWM 242 has reduced granularity and finer precision and control of the motor 124.

[0259] PWM 242 receives a third set point signal 3316. The third set point signal 3316 has a value of 16386. The value 16385 of the second set point signal 3314 is right shifted to generate a value of 4096 for comparison value 3322. In binary, the two LSBs of 16386 are "10". PWM 242 determines that the two-bit value "10" corresponds to the first comparison criterion 3324 greater than or equal to and the second comparison criterion 3326 greater than. The third set point signal 3316 operates identically to the second set point signal 3314 to generate a third pulse of the PWM signal based on the third set point signal 3316. In a multi-channel embodiment, for example, reference Fig.34 As described above, the third set point signal 3316 can increase power delivery to the controlled component while increasing the adjustable comparison standard of the second channel by 1 count.

[0260] PWM 242 receives fourth set point signal 3318. Fourth set point signal 3318 has a value of 16387. In binary, the two LSBs of 16387 are "11". PWM 242 determines that the two-bit value "11" corresponds to first comparison criterion 3324 of greater than or equal to and second comparison criterion 3326 of greater than or equal to. Fig.33As shown, when the comparison value 3322 having a value of 4096 is equal to the value of the counter 3302, i.e., when the counter value is 4096, the PWM 242 activates the transistor. The activated transistor will generate a pulse edge of the fourth pulse of the PWM signal based on the fourth set point signal 3318. When the comparison value 3322 having a value of 4096 is less than (no longer equal to or greater than) the value of the counter 3302, i.e., when the counter value is 4097, the PWM 242 deactivates the transistor, which means that the transistor is turned on when the counter value is 4096. The deactivated transistor will generate a second pulse edge of the fourth pulse of the PWM signal based on the fourth set point signal 3318. The on time of the fourth set point signal 3318 is one count higher (i.e., 1 in 8192) than the on time of the second set point signal 3314. To illustrate, the second set point signal 3314 indicates that the transistor is on for 8191 counts, while the fourth set point signal 3318 indicates that the transistor is on for 8192 counts, ie, counts corresponding to counter values ​​of 4096 to 0 and 0 to 4096.

[0261] PWM 242 receives fifth set point signal 3320. Fifth set point signal 3320 has a value of 16388. In binary, shifting 16388 right by 2 bits gives a value of 4097 for comparison value 3322. The two LSBs of 16388 are "00". PWM 242 determines that the two bit values ​​"00" correspond to a first comparison criterion 3324 of greater than and a second comparison criterion 3326 of greater than. Fifth set point signal 3320 operates with a different comparison value 3322 and different comparison criteria 3324, 3326 than fourth set point signal 3318, but produces the same number of on-time counts as fourth set point signal 3318. In other embodiments, each of the two LSBs may correspond to a specific comparison rule or condition. For example, a bit with a value of 0 may indicate a greater than condition, and a bit with a value of 1 may indicate a greater than or equal to condition.

[0262] like Fig.33 As shown, the on-time for adjusting the comparison criteria is increased by 0.01250 microseconds, rather than 0.0250 microseconds for adjusting the comparison value. Thus, PWM 242 has reduced granularity and increased precision and control by adjusting the comparison criteria 3324, 3326. Fig.33 In the example shown, PWM 242 has a frequency of 40 MHz. The frequency of resolver system 204 (2441.2 Hz) is equal to the frequency of PWM 242 divided by two times the period of PWM 242 (8192).

[0263] In other embodiments, a single adjustable comparison standard may be used and may be indicated by 1 LSB of the set point signal. In such an embodiment, the PWM 242 still has a granularity of 1 counter value or 0.01250 microseconds for each 1 value adjustment of the set point signal. As an example, in response to the value of the first set point signal 3312 increasing by 1, the PWM 242 will operate similarly to the second set point signal 3314. In response to the value of the first set point signal 3312 increasing by 2, the PWM 242 will operate similarly to the fifth set point signal 3320 (rather than the third set point signal 3316). Therefore, the set point signal with a single adjustable comparison standard is shifted right by one position compared to shifting the set point signal right by two positions for two adjustable comparison standards. In addition, the set point signal with one adjustable comparison standard will have a value range from 0 to 16384, compared to the set point signal with two adjustable comparison standards having a value range from 0 to 32768. This embodiment can be implemented without using multi-channel control, for example, LEDs, single-phase motors, etc.

[0264] like Fig.33 As shown, the set point signals 3312-3320 indicate changes to the illustrated operation of the PWM 242 each cycle. During operation of the controlled component, the PWM 242 may receive the set point signal each cycle, and the set point signal may or may not indicate a change in the duty cycle of the controlled component relative to the previous set point signal of the previous cycle. Alternatively, the PWM 242 may receive a set point signal indicating a different duty cycle in response to a change in the duty cycle value, and may maintain the current set point signal (i.e., the comparison value 3322 and its comparison criteria 3324, 3326) until a new set point signal is received.

[0265] Fig.34 3400 is a schematic diagram showing an example of two-channel PWM operation with an adjustable comparison standard. Schematic diagram 3400 shows the operation of the A channel and the B channel. In a specific embodiment, the A channel corresponds to the upper transistor of the first phase and the B channel corresponds to the lower transistor of the second phase. For example, the upper transistor corresponds to Fig.28 of 2822, while the lower transistor corresponds to Fig.28 of 2834.

[0266] The operation of channel A is similar to that of Fig.33 The PWM operation described in the following table is shown in Figure 1. The operation of channel B is similar to channel A, but inverted. When the specific comparison value 3422 (CMPB) meets the requirements of Fig.33 When the value of the B channel of the counter 3302 meets the comparison criteria 3424, 3426 (eg, less than or less than or equal to), the B channel is low (eg, connected to ground).

[0267] When the A channel is high and the B channel is low, a voltage difference is generated across the controlled component (e.g., a motor), and current is provided to the controlled component. The A channel is high and the B channel is low by closing or activating the upper transistor 2822 and the lower transistor 2834. Activating transistors 2822 and 2834 allows current to flow from the battery (or other power source), through the upper transistor 2822 to the motor 124, across the motor 124 to the lower transistor 2834, and to ground through the lower transistor 2834. Fig.33 Compared to the pulses of the PWM 242 described above, the pulses of the PWM 24 for the A channel and the B channel are generated by the combination of the set point signals for each channel. In other words, each set point signal for a particular channel generates pulse edges of two different pulses (rather than Fig.33 The two pulse edges of a single pulse in Fig.33 In , the pulses provided to the controlled component (e.g., a motor) correspond to the cross-hatched triangles. Fig.34 In , the pulses supplied to the controlled component (e.g., a motor) correspond to the dashed rectangles. Fig.34 In the illustrated embodiment, each of the set point signals 3312-3320 generates a first pulse edge for a first pulse and a second pulse edge for a second pulse, and the corresponding set point signal 3412-3420 generates a second pulse edge for a first pulse and a first pulse edge for a second pulse.

[0268] The B channel receives the first set point signal 3412. The first set point signal 3412 has a value of 16384. Shifting the value 16384 of the first set point signal 3412 right by two bits (i.e., dividing by 4) indicates that the comparison value 3422 (CMPB) of the B channel is 4096. The two LSBs of 16384 are "00", and for the B channel, the two LSBs indicate a first comparison criterion 3424 of less than or equal to and a second comparison criterion 3426 of less than or equal to. The B channel is low, and the comparison value 3422 is less than or equal to the value of the counter 3302, as shown in FIG. Fig.34 The horizontal hatching in the figure shows the

[0269] In response to the comparison value 3422 not satisfying the comparison criteria 3424, 3426 relative to the value of the counter 3302, the PWM 242 provides a low signal (or causes a low signal to be provided) to the gate of the lower transistor 2834. Providing a low signal to the lower transistor 2834 disables the lower transistor 2834. When the comparison value 3422 having a value of 4096 is less than or equal to the value of the counter 3302 (e.g., when the counter value decreases to a value of 4096 below the comparison value 3322), the PWM 242 disables the lower transistor 2834. Fig.34, for the first set point signal 3412, the lower transistor 2834 is deactivated at the counter value 4095, which means that the lower transistor 2834 is turned on when the counter value is 4096. Activating the upper transistor 2822 will generate a first pulse edge of a first pulse of the PWM signal based on the first set point signal 3312, 3412, and deactivating the lower transistor 2834 will generate a second pulse edge of the first pulse of the PWM signal based on the first set point signal 3312, 3412.

[0270] The conduction time of the lower transistor 2834 is determined by Fig.34 3420 corresponds to the off time of the lower transistor 2834, and the set point signal 3312-3320 corresponds to the on time of the upper transistor 2822.

[0271] In response to the comparison value 3422 satisfying the comparison criteria 3424, 3426 relative to the value of the counter 3302, the PWM 242 provides a high signal to the gate of the lower transistor 2834 (or causes the high signal to be satisfied). The high signal of the lower transistor 2834 will activate the lower transistor 2834. Fig.34 As shown, when the comparison value 3422 having a value of 4096 is less than or equal to the value of the counter 3302 (eg, when the counter value reaches the comparison value 3422 having a value of 4096), the PWM 242 activates the lower transistor 2834. Fig.34 , for the first set point signal 3412, the lower transistor 2834 is activated at the counter value 4096. Activating the lower transistor 2834 will generate a first pulse edge of the second pulse of the PWM signal based on the first set point signal 3312, 3412, and deactivating the upper transistor 2822 will generate a second pulse edge of the second pulse of the PWM signal based on the first set point signal 3312, 3412.

[0272] The first and second pulses of the PWM signal indicate the motor on time and correspond to the overlap of the on time of the A channel and the B channel (cross-hatched triangles). The first and second pulses are indicated by Fig.34 The dashed rectangle in the figure indicates Fig.34As shown, the first motor on time associated with the first pulse of the first set point signal 3312, 3412 is 25ns, and the second motor on time associated with the second pulse of the first set point signal 3312, 3412 is 25ns. Therefore, the total motor on time associated with the first set point signal 3312, 3412 of the A channel and the B channel is 50 nanoseconds.

[0273] The B channel receives the second set point signal 3414 having a value of 16383. Shifting the value 16383 of the second set point signal 3414 right by two bits (i.e., divided by 4) indicates that the comparison value 3422 is 4095. The two LSBs of 16383 are "11", and for the B channel, the two LSBs indicate a first comparison criterion 3424 of less than and a second comparison criterion 3426 of less than. Because the comparison criteria 3424, 3426 change and the comparison value 3422 changes, the time that the B channel is off does not change. However, because one of the comparison criteria of the A channel (i.e., the first comparison criterion 3324) changes in the corresponding second set point signal 3314, the total motor on time (duty cycle) of the second set point signals 3314, 3414 increases by 25ns relative to the previous total motor channel time of 50ns for the first set point signals 3312, 3412. As Fig.34 As shown, for a total motor on time of 75 ns, the first motor on time associated with the first pulse of the second set point signal 3314, 3414 is 50 ns, and the second motor on time associated with the second pulse of the first set point signal 3314, 3414 is 25 ns.

[0274] The B channel receives the third set point signal 3416 having a value of 16382. Shifting the value 16382 of the third set point signal 3416 right by two bits (i.e., dividing by 4) indicates that the comparison value 3322 is 4095. The two LSBs of 16382 are "10", and for the B channel, the two LSBs indicate a first comparison criterion 3424 of less than and a second comparison criterion 3426 of less than or equal to. As shown in reference Fig.33 As explained, the A channel does not change the comparison criteria 3324, 3326 or the comparison value 3322 from the second set point signal 3312. Because the second comparison criteria 3426 of the second set point signal 3416 is changed on the B channel, the time that the B channel is off increases, and the on time (duty cycle) of the motor 124 increases by 25 ns relative to the previous total motor on time of 75 ns for the second set point signals 3314, 3414. Fig.34 As shown, for a total motor on time of 100 ns, the first and second motor on times of the third set point signals 3316, 3416 are 50 ns.

[0275] The B channel receives the fourth set point signal 3418 having a value of 16381. Shifting the value 16381 of the fourth set point signal 3418 right by two bits (i.e., divided by 4) indicates a comparison value of 4095. The two LSBs of 16381 are "01," and for the B channel, the two LSBs indicate a first comparison criterion 3424 of less than and a second comparison criterion 3426 of less than or equal to. Because the comparison criteria 3424, 3426 change and the comparison value 3422 changes, the time that the B channel is low does not change. However, because one of the comparison criteria of the A channel (i.e., the second comparison criterion 3326) changes in the corresponding fourth set point signal 3318, the on-time (duty cycle) of the motor 124 is increased by 25ns relative to the previous total motor on-time of 100ns for the third set point signals 3316, 3416. As Fig.34 As shown, for a total motor on time of 125 ns, the first motor on time associated with the first pulse of the fourth set point signal 3318, 3418 is 75 ns, and the second motor on time associated with the second pulse of the fourth set point signal 3318, 3418 is 50 ns.

[0276] The B channel receives the fifth set point signal 3420 having a value of 16381. Shifting the value 16380 of the fifth set point signal 3420 right two bits (i.e., divided by 4) indicates that the comparison value 3422 is 4095. The two LSBs of 16380 are "00," and for the B channel, the two LSBs indicate a first comparison criterion 3424 of less than or equal to and a second comparison criterion 3426 of less than or equal to. Because the first comparison criterion 3424 changes on the B channel, the time that the B channel is low increases, and the motor 124 on time (duty cycle) increases by 25 ns relative to the previous total motor on time of 125 ns for the fourth set point signal 3318, 3418. As shown in FIG. Fig.34 As shown, for a total motor on time of 150 ns, the first motor on time associated with the first pulse of the fifth set point signal 3320, 3420 is 75 ns, and the second motor on time associated with the second pulse of the fifth set point signal 3320, 3420 is 75 ns.

[0277] like Fig.34As shown, PWM 242 receives multiple set point signals, each for one channel. For example, channel A receives a second set point signal 3314 indicating a value of 16385, and channel B receives a second set point signal 3414 indicating a value of 16383. In other embodiments, PWM 242 receives a single set point signal indicating a duty cycle value 374 and at least one comparison standard. PWM 242 calculates comparison values ​​3322, 3422 for each channel based on the duty cycle value 374. For example, PWM 242 calculates comparison values ​​3322, 3422 for each channel using the following equations: CMPA = DutyCycle * CTRPRD * 4 and CMPB = (1-DutyCycle) * CTRPRD * 4, where CTRPRD is the maximum counter value (8192).

[0278] In some embodiments, PWM 242 is configured to control two transistors per channel. In a particular embodiment, PWM 242 is configured to provide deadband control, i.e., PWM 242 delays activation of a particular transistor of a channel to prevent both transistors of the channel from being activated simultaneously. For example, PWM 242 delays activation of the upper transistor of a particular channel to allow the lower transistor of the particular channel to be deactivated. This delay is referred to as dead time or dead tick. PWM 242 is further configured to activate the transistor based on a dead tick setting or a determined number of dead ticks, as described in reference to FIG. Fig.35 described.

[0279] Fig.35 35 is a logic diagram 3500 showing an example of PWM logic 3502 with adjustable comparison criteria and dead band control. The PWM logic 3502 is configured to control Figure 3 transistor 336 (e.g., transistors 2822-2826 and 2832-2836) and to Figure 1 The motor 124 provides power. Fig.35 , PWM logic 3502 controls a three-phase motor having phases or channels A, B, and C. PWM logic 3502 is configured to determine when to activate transistor 336 based on a comparison value and at least one comparison criterion, such as reference Fig.33 and Fig.34 In Fig.35 , PWM logic 3502 is configured to determine when to activate transistor 336 further based on dead time input 3512 and drive enable input 3514. For example, PWM logic 3502 can adjust the on timing of the channels to provide a dead band so that the upper transistor and the lower transistor of a particular channel are not turned on at the same time.

[0280] The PWM logic 3502 includes a comparison logic block 3504 for each channel. Each comparison logic block 3504 is configured to generate two outputs: a high active output 3506 and a low active output 3508 based further on a dead time input 3512 and a drive enable input 3514. The high active output 3506 and the low active output 3508 include Boolean outputs, such as true or false indicated by a logical 0 or 1. Fig.33 and Fig.34 The high activation output 3506 and the low activation output 3508 may include or correspond to deadband activation outputs or adjusted activation outputs compared to the on-time determined in the . Providing deadband control may reduce the total on-time indicated by a particular set point signal, but deadband control does not increase or decrease the granularity of on-time control or the accuracy of the set point signal indicating an adjustable comparison standard.

[0281] The dead time input 3512 (DT) is configured to adjust the turn-on timing of the transistor 336. The value of the dead time input 3512 is based on the number of dead_ticks determined according to the current command, the user setting, or both. For example, the user can enter a constant value for the number of dead ticks. As another example, the number of dead ticks can be determined based on the current command 2940, the voltage of the power supply, or both. In addition, the dead ticks can be positive or negative, and can be with respect to either transistor, i.e., turning on the upper transistor or the lower transistor earlier or later.

[0282] The drive enable input 3514 (DE) is configured to enable a particular channel or phase to be operated or controlled by the PWM 242. The drive enable input 3514 is a Boolean input or Boolean value. Fig.35 As shown, the drive enable input 3514 is determined based on the channel drive enable input 3516 (e.g., [DEA]) and the shutdown input 3518 ([notSD]). Each of these inputs 3516, 3518 may include a Boolean value. The channel drive enable input 3516 is configured to control the specific channel or phase of the motor to be activated or controlled. The shutdown input 3518 is configured to turn off all transistors 336 to disable the motor 124. Fig.35 As shown, the drive enable input 3514 is generated as the output of an AND logic gate that receives a channel drive enable input 3516 and a shutdown input 3518. To illustrate, when the channel drive enable input 3516 and the shutdown input 3518 indicate true or logic high, the drive enable input 3514 indicates true or high and the particular channel is enabled to be controlled by the PWM logic 3502.

[0283] The PWM logic 3502 includes gate drivers 3522, 3524 configured to generate gate high and low outputs 3532, 3534 based on the high active output 3506 and the low active output 3508 from each channel. The gate drivers 3522, 3524 may include or correspond to Figure 3 The gate driver 334. The gate high and low outputs 3532, 3534 comprise Boolean outputs, such as true or false indicated by a logical 0 or 1.

[0284] During operation, each comparison logic block 3504 generates an on-time of a corresponding channel based on the counter 3302, the comparison value 3322, and one or more comparison criteria (e.g., comparison criteria 3324, 3326), such as reference Fig.33 and Fig.34 The comparison logic block 3504 adjusts the on-time of a particular channel based on the dead time input 3512. For example, for each dead clock of the dead time input 3512 value, the comparison logic block 3504 reduces the on-time of the A channel being high (e.g., AH) by 2 points or counts. To illustrate, the upper transistor 2822 of the A channel is higher than Fig.33 and Fig.34 The situation determined in the above example delays the on-time of the A channel by one count (one dead clock) and turns off by one count (one dead clock) in advance, so that the upper transistor is not turned on at the same time as the lower transistor 2832 of the A channel. Alternatively, the comparison logic block 3504 reduces the on-time of the A channel being low (e.g., AL) by 2 dead clocks or counts.

[0285] The gate drivers 3522, 3524 generate a gate high output 3532 and a gate low output 3534 based on the high active output 3506 and the low active output 3508 of each channel. The gate high output 3532 and the gate low output 3534 indicate which upper transistor and lower transistor are turned on or active. Fig.35 As shown, gate drivers 3522, 3524 activate one upper transistor (high transistor) and one lower transistor at a time. As an illustrative example, gate drivers 3522, 3524 provide gate high output 3532 and gate low output 3534 to a circuit that generates a logic high signal and a low signal (e.g., a high voltage and a low voltage) for activating and deactivating transistor 336.

[0286] Fig.36 A method 3600 for determining rotational position using a dual resolver is shown. The method 3600 may be performed by Figure 1 Solver 126, Figure 2 The solver system 204, the demodulation system 222, the dual solver combination system 224, Figure 3 The dual speed solver 312, the coarse solver 342, the fine solver 344, Figure 5The output circuit 532, the angle combination circuit 542, the drift correction circuit 544 or a combination thereof is performed.

[0287] The method 3600 includes receiving a coarse position signal from a coarse resolver and a fine position signal from a fine resolver at 3602. The coarse position signal indicates a coarse position of a drive shaft of a motor, and the fine position signal indicates a fine position of a drive shaft of the motor. The coarse resolver may include or correspond to Figure 3 342. The rough position signal may include or correspond to Figure 3 The differential voltage output 354, the differential voltage signal 356, the ADC output 358, Fig.13 sine and cosine values ​​1312, 1314, or a combination thereof, and the fine position signal may include or correspond to Figure 3 The differential voltage output 354, the differential voltage signal 356, the ADC output 358, Fig.12 ADC output signal 1212 or a combination thereof.

[0288] Fig.36 The method 3600 also includes generating an initial position output indicating an initial position of the drive shaft based on the coarse position signal at 3604. The initial position output may include or correspond to Fig. 20 The initial position output 2012, and the initial position of the drive shaft may include or correspond to Fig. 20 The actual angle 2004. In some implementations, the initial position output corresponds to the output of the initialization mode of the dual speed resolver 312.

[0289] Fig.36 The method 3600 also includes generating a subsequent position output indicating a subsequent position of the drive shaft based on the fine position signal at 3606. The subsequent position output may include or correspond to Fig. 20 The subsequent position output 2014, and the subsequent position of the drive shaft may include or correspond to Fig. 20 The actual angle 2004. In some embodiments, the subsequent position output corresponds to the output of the dual speed resolver 312 in a normal operating mode (ie, non-initialization mode).

[0290] In some embodiments, the coarse position signal and the fine position signal are generated based on an excitation signal received by the resolver. In a particular embodiment, the excitation signal includes or corresponds to a dithering excitation signal, such as Figure 3 and Fig.23 Additionally or alternatively, the excitation signal (or the dithered excitation signal 352) is time-coordinated with the direct current switching of the motor. For example, the excitation signal deviates from the current driven switching of the motor 124, as shown in FIG. Figure 2 and Figure 3For purposes of illustration, the excitation signal 452 is synchronized with a current drive switching signal associated with the motor 124 such that a peak amplitude of the excitation signal 452 is offset from the current drive switching signal.

[0291] In some embodiments, a subsequent position output is generated based on the initial position output and the fine position signal, wherein the subsequent position output is generated independently of the subsequent coarse position signal, as shown in FIG. Fig.18 and Fig.19 described.

[0292] In some embodiments, generating the initial position output includes determining a starting position of the drive shaft based on the coarse position signal, and providing the starting position as the initial position output based on the initialization mode input, such as reference Fig.18 and Fig.19 For example, the logic 1802 generates the combined estimated position 1832 based on the estimated initial position 1822 (indicating a starting position determined based on the solver output 354 of the coarse solver 342) provided from the switch 1826 in response to the Boolean input 1824 (init_rslv) indicating true.

[0293] In some embodiments, generating a subsequent position output includes differentiating the fine position signal and converting the differential fine position signal into a first domain associated with the coarse position signal. Generating a subsequent position output also includes generating an estimated subsequent position based on the initial position output, the differential fine position signal, and the drift correction value, and includes outputting a subsequent position based on the estimated subsequent position, such as a reference Fig.18 For example, the logic 1802 performs a difference on the second domain angle estimate 1812 (the angle estimate 364 in the second domain based on the fine position signal from the fine resolver 344) by subtracting the previous position value 1814 from the current position value 1816 of the second domain angle estimate 1812 to generate a change in position value 1818. The logic 1802 converts the change in position value 1818 into a converted change in position value 1820 and provides the converted change in position value 1820 to the combiner 1830. The combiner 1830 generates a subsequent combined estimated position 1832 based on the converted change in position value 1820, a delayed combined estimated position 1844 (e.g., an initial position output or an initial combined estimated position 1832), and a drift correction value 1828.

[0294] In some embodiments, generating the drift correction value includes converting the initial position output to a second domain associated with the fine position signal, and generating an error value based on the converted initial position output, the fine position signal, and the 180 degree bias offset value. Generating the drift correction value also includes determining the drift correction value based on the error value, the proportional gain, and the integral gain, as shown in reference Fig.19For example, the logic 1902 converts the delayed combined estimated position 1844 from the 1x speed domain to the 16x speed domain and subtracts the converted estimated angle 1914 and the 180 degree bias offset 1918 from the second domain angle estimate 1812 to generate an error value 1920. The logic 1902 generates a drift correction value 1828 based on the error value 1920, the proportional gain 1922, and the integral gain 1924. In a particular embodiment, the error value 1920 is right-shifted to apply the proportional gain 1922, and the integral gain 1924 corresponds to 1 or -1 based on the error value 1920.

[0295] In some implementations, the initial position output and the plurality of subsequent position outputs (including the subsequent position outputs) are generated based on contiguous math. For example, the solver system 204 generates the position outputs based on a continuous function where input parameters are varied one at a time.

[0296] In some embodiments, multiple subsequent position outputs including the subsequent position output are generated independently of mode switching or counter jumping. For example, the resolver system 204 generates multiple subsequent position outputs corresponding to the output of a full rotation (0 to 360 degrees) of the motor without switching modes or resetting counters. The resolver system 204 does not need to have a separate mode for each half or quadrant of the motor and switch between modes as the motor rotates from 0 degrees to 360 degrees.

[0297] In some embodiments, method 3600 further includes transforming a fine position signal from the fine resolver from the second domain to a first domain associated with the coarse resolver, and further generating a subsequent position output based on the transformed fine position signal. For example, second domain angle estimate 1812 is differentiated to produce a change in position value 1818; the change in position value 1818 is transformed from the second domain to the first domain by right shifting the change in position value 1818 by 4 bits to generate a transformed change in position value 1820 (the transformed fine position signal), as shown in reference Fig.18 described.

[0298] In some embodiments, method 3600 further includes transforming the initial position output into a second domain associated with the fine solver, and further generating a subsequent position output based on the transformed initial position output. For example, the delayed combined estimated position 1844 is transformed from the first domain to the second domain by shifting the delayed combined estimated position 1844 left by 4 bits to generate the transformed estimated angle 1914 (the transformed initial position output), as shown in reference Fig.19 described.

[0299] Fig.37 A method 3700 of pulse width modulation is shown. The method 3700 may be performed by Figure 1 Inverter 112, Figure 2 PWM 242, Fig.35 The method 3700 includes receiving a comparison value and a comparison criterion at 3702. The comparison value may include or correspond to Fig.33 The comparison value is 3322 or Fig.34 The comparison value 3422, and the comparison criteria may include or correspond to Fig.33 In some embodiments, the comparison value and the comparison criterion are included in the set point signal, such as Fig.33 and Fig.34 Set point signals 3312-3320 and 3412-3420.

[0300] Fig.37 The method 3700 also includes comparing the comparison value to the counter value based on the comparison criteria at 3704. The counter value may include or correspond to Fig.33 counter value or counter signal. Fig.33 Counter 3302) receives the counter value.

[0301] Fig.37 The method 3700 also includes, at 3706, sending a control signal to the gate of the first transistor to generate a pulse edge of a pulse of the pulse width modulated signal in response to the comparison value satisfying the comparison criterion relative to the counter value. The control signal may include or correspond to Fig.35 The gate of the first transistor may include or correspond to one of the high and low activation outputs 3506, 3508 or the gate high and low outputs 3532, 3534. Figure 3 The transistor 336 or Fig.28 The pulse edge of the pulse width modulated signal 378 may include or correspond to the gate of any one of the transistors 2822-2826 or 2832-2836. Figure 3 The first edge or the second edge of the pulse width modulated signal 378.

[0302] In some embodiments, Fig.37 The method 3700 includes receiving a set point signal indicating a comparison value, a comparison criterion, and a second comparison criterion, and comparing the comparison value to a second counter value based on the second comparison criterion. The method 3700 also includes sending a second control signal to a gate of the first transistor to generate a second pulse edge of a pulse of the pulse width modulated signal in response to the comparison value satisfying the second comparison criterion relative to the second counter value, as described in reference Fig.33 and Fig.34For example, the PWM 242 receives the first set point signal 3312 and generates a second pulse edge of the first pulse based on comparing the comparison value 3322 with the value of the counter 3302 based on the second comparison criterion 3326 .

[0303] In some embodiments, Fig.37 The method 3700 includes determining a comparison value based on one or more first bits of a set point signal, and determining a comparison criterion and a second comparison criterion based on one or more second bits of a set point signal, such as a reference Fig.33 and Fig.34 For example, the PWM 242 receives the first set point signal 3312 and generates a comparison value 3322 by right-shifting the value of the first set point signal 3312 indicated by the first set point signal 3312 (e.g., indicated by all bits of the first set point signal), and generates a comparison value by determining the value of the LSB of the first set point signal 3312 and retrieving comparison criteria 3324, 3326 based on the value of the LSB.

[0304] In some embodiments, determining the comparison value includes right shifting the set point signal by one or more bits, such as reference Fig.33 and Fig.34 In some embodiments, the one or more second bits of the set point signal correspond to the one or more least significant bits of the set point signal, as shown in FIG. Fig.33 and Fig.34 In some embodiments, Fig.37 Method 3700 includes selecting a comparison criterion from a table based on one or more least significant bits of a set point signal, such as a reference Fig.33 and Fig.34 described.

[0305] In some embodiments, Fig.37 The method 3700 includes receiving a second set point signal indicating a second comparison value and a second comparison criterion, and comparing the second comparison value to a second counter value based on the second comparison criterion. The method 3700 also includes sending a second control signal to a gate of a second transistor to generate a pulse edge of a second pulse of the pulse width modulated signal in response to the second comparison value satisfying the second comparison criterion relative to the second counter value, as described in reference to Fig.33 and Fig.34 For example, the PWM 242 receives the second set point signal 3314 and generates a first pulse edge of the second pulse based on comparing the comparison value 3322 with the value of the counter 3302 based on the first comparison criterion 3324 of the second set point signal 3314 .

[0306] In some embodiments, Fig.37The method 3700 includes receiving a second set point signal indicating a second comparison value and a second comparison criterion, and comparing the second comparison value to a second counter value based on the second comparison criterion. The method 3700 also includes sending a second control signal to a gate of a second transistor to generate a second pulse edge of a pulse of a pulse width modulated signal in response to the second comparison value satisfying the second comparison criterion relative to the second counter value, as described in reference to Fig.33 and 34 For example, the PWM 242 receives the first set point signal 3312 and generates a second pulse edge of the first pulse based on comparing the comparison value 3422 with the value of the counter 3302 based on the second comparison criterion 3426 .

[0307] Fig.38 A method 3800 for feedback control is shown. The method 3800 may be performed by Figure 2 control system 205, feedback control system 232, Fig.30 Logic 3002, Fig.31 Logic 3102, Fig.32 The method 3800 includes receiving a position command of a controlled component and a velocity command of a controlled component at 3802. The controlled component may include or correspond to Figure 1 The position command may include or correspond to the motor 124, the drive shaft of the motor 124, the universal joint 122, the sensor 128, or a combination thereof. Figure 29-32 The position command 2922. The speed command may include or correspond to Figure 29-32 The speed command 2932. In some implementations, the position command indicates the angle of the motor, while the speed command indicates the RPM of the motor.

[0308] Fig.38 The method 3800 also includes generating a rate-limited position command based on the speed command and the position command at 3804. The rate-limited position command may include or correspond to Figure 30-32 Rate limit location command 3034. In some embodiments, Fig.38 The method 3800 includes converting the current command into a duty cycle value and controlling the motor based on the duty cycle value, as shown in FIG. Figure 3 and Figure 33-35 described.

[0309] Fig.38 The method 3800 includes receiving position feedback indicating the position of the controlled component at 3806. The position feedback may include or correspond to Figure 29-32 In some embodiments, the position feedback is generated based on the solver output. For example, the position feedback can be implemented by Fig.36 The solver of method 3600, by implementing Fig.39 The demodulation circuit of method 3900 or both are generated.

[0310] Fig.38 The method 3800 also includes applying a control gain to the error signal to generate an adjusted error signal at 3808. The error signal is based on the position feedback and the rate limited position command. The control gain may include or correspond to Figure 29-32 The proportional gain 2926, the integral gain 2928, or both. The error signal may include or correspond to the error signal 3012, and the adjusted error signal may include or correspond to Figure 30-32 The adjusted error signal 3014.

[0311] Fig.38 The method 3800 also includes outputting a current command based on the adjusted error signal at 3810. The current command may include or correspond to Figure 29-32 In some embodiments, the current command is used to control the motor and indicate the torque of the motor, such as reference Figure 3 For example, the current command 2940 is provided to the current tracker 330, and the current tracker 330 generates the duty cycle value 374 based on the current command 2940, as shown in FIG. Figure 3 PWM 242 receives a set point signal indicating a duty cycle value 374 of a duty cycle setting 376 and provides an AC power signal 380 to motor 120 based on the set point signal.

[0312] In some embodiments, generating a rate-limited position command based on the speed command and the position command includes generating a threshold (e.g., a threshold value) based on the speed command and reducing the value of the position command to the value of the speed command to generate the limited position command, as described in reference to Figure 30-32 described.

[0313] In some embodiments, Fig.38 Method 3800 includes generating an error signal based on position feedback and a rate-limited position command. In some such embodiments, generating the error signal includes subtracting a position indicated by the position feedback signal from a position indicated by the rate-limited position command, such as a reference signal. Figure 30-32 described.

[0314] In some embodiments, applying the control gain to the error signal to generate an adjusted error signal includes applying a proportional gain to the error signal and applying an integral gain to the error signal. Additionally or alternatively, applying the control gain to the error signal to generate an adjusted error signal includes multiplying the error signal by the proportional gain to generate a first product, multiplying an integral of the error signal by the integral gain to generate a second product, and adding the first product and the second product to generate the adjusted error signal, as described in reference to Figure 30-32described.

[0315] In some embodiments, Fig.38 Method 3800 includes based on speed feedback (e.g. Figure 29-32 In some such embodiments, based on the damping error signal (e.g., Fig.31 The damping error signal 3138) generates a current command, and generating the damping error signal includes applying a second control gain to the adjusted error signal, such as the reference Figure 30-32 described.

[0316] In certain embodiments, applying the second control gain to the adjusted error signal includes differentiating the speed feedback to generate a differentiated speed feedback, multiplying the differentiated speed feedback by the second control gain to generate a damping value, and subtracting the damping value from the adjusted error signal, wherein subtracting the damping value from the adjusted error signal generates a damped error signal, and wherein the current command is generated based on the damped error signal, as described with reference to Figure 30-32 For example, the speed feedback 2936 is differentiated and multiplied by the rpm gain 2938 to generate the damping value 3016. The damping value 3016 is subtracted from the adjusted error signal 3014 to generate the damping error signal 3138; and the damping error signal 3138 is limited by the minimum and maximum values, and the limited damping error signal 3138 is integrated to generate the current command 2940, as shown in FIG. Figure 30-32 described.

[0317] Fig.39 3900 is shown to decode the output of the solver. The method 3900 can be performed by the solver system 204, the demodulation system 222, the dual solver combination system 224, Figure 5 The demodulation circuits 514, 524 are configured to perform Figure 7-11 , Fig.14 , Fig.16 , Fig.18 and Fig.19 The method 3900 includes receiving a plurality of ADC outputs from an analog-to-digital converter (ADC) at 3902. The plurality of ADC outputs are generated based on the resolver outputs. The ADC may include or correspond to Figure 3 The solver may include or correspond to one of the ADCs 318, 320. Figure 1 Solver 126, Figure 3 The ADC output may include or correspond to a dual speed resolver 312, a coarse resolver 342, a fine resolver 344, or a combination thereof. Figure 3 ADC output 358 or regulated voltage value 360.

[0318] Fig.39 The method 3900 also includes rectifying the plurality of ADC outputs based on a square wave at 3904. In some embodiments, the square wave includes a square wave with amplitudes of 1 and -1. The square wave can switch between amplitudes based on a counter value, such as a toggle input 1022 determined based on the counter input 852, as shown in reference Figure 10-12 described.

[0319] Fig.39 The method 3900 includes determining a demodulated amplitude value corresponding to the resolver output based on the rectified plurality of ADC outputs at 3906. The demodulated amplitude value may include or correspond to Figure 3 The demodulated amplitude value 362. In some embodiments, the demodulated amplitude value can be generated by recursive median filtering, as shown in FIG. Fig. 9 and Fig.16 described.

[0320] Fig.39 The method 3900 also includes generating a position output based on the demodulated amplitude value at 3908. The position output may include or correspond to Figure 3 An angle estimate 364 or a position estimate 366 is provided. In some embodiments, the position output indicates the position (angle) of the drive shaft of the motor 124, such as the reference Figure 3 In some embodiments, the demodulated amplitude value includes sign information (eg, is a signed integer), and the angle estimate 364, the position estimate 366, or both are calculated based on the function atan2. Additionally or alternatively, the position output may be generated based on a shared sine table circuit.

[0321] In some embodiments, generating a demodulated amplitude value includes generating an accumulated value based on the rectified multiple ADC outputs, calculating a median of the last n accumulated values, and outputting the median as a specific demodulated amplitude value in the demodulated amplitude value, as shown in FIG. Fig.16 described.

[0322] In some embodiments, rectifying the plurality of ADC outputs comprises multiplying the plurality of ADC outputs based on a square wave. In a particular embodiment, the square wave has an amplitude of 1 for counter values ​​below a particular counter value (e.g., a median counter value) and an amplitude of -1 for counter values ​​above the particular counter value, as shown in FIG. Figure 10-12 described.

[0323] In some embodiments, multiplying the plurality of ADC outputs based on the square wave includes changing the sign of a specific ADC output among the plurality of ADC outputs to generate an inverted ADC output, selecting the specific ADC output or the inverted ADC output based on the flip input, and outputting the selected ADC output as a specific rectified ADC output, as shown in FIG. Fig.11 described.

[0324] In some embodiments, Fig.39 The method 3900 includes masking a subset of ADC outputs aligned with current drive switching of a motor associated with a resolver to generate a filtered set of ADC outputs. The method 3900 also includes determining a demodulated amplitude value based on the filtered set of ADC outputs in the data window 1514, as shown in reference Fig.14 and Fig.15 described.

[0325] In some embodiments, the masked set of ADC outputs includes ADC outputs occurring near the peak amplitude of the first harmonic of the excitation signal associated with the solver, as shown in FIG. Fig.14 and Fig.15 In addition, each of the demodulated amplitude values ​​corresponds to a period of the first harmonic of the excitation signal, as shown in reference Figure 14-16 described.

[0326] In some embodiments, Fig.39 Method 3900 includes recursively filtering a plurality of ADC outputs to generate a median ADC output, as shown in reference Figure 8 and Fig. 9 In this embodiment, rectifying the plurality of ADC outputs includes rectifying a median ADC output.

[0327] In some implementations, the resolver receives a dithered excitation signal having zero mean dither and generates a resolver output based on the dithered excitation signal. In such implementations, the ADC oversamples the resolver output to generate the ADC output.

[0328] Fig.40 A method 4000 for generating an excitation signal for a sensor device is shown. The method 4000 may be performed by Figure 2 The excitation signal generating system 202, the jitter generator 212, the coordination system 214, Fig.26 Logic 2602, Fig. 27 The method 4000 includes generating, at 4002, higher-order even harmonics of a fundamental excitation signal. The higher-order even harmonics may include or correspond to Fig.26 The basic excitation signal may include or correspond to Fig.23 The basic excitation signal 452 is .

[0329] Fig.40 The method 4000 also includes generating a dithered excitation signal based on the combined higher-order even harmonics and the fundamental excitation signal at 4004. The dithered excitation signal may include or correspond to Figure 3 and Fig.23The jitter excitation signal 352 is provided.

[0330] Fig.40 The method 4000 also includes outputting the jitter excitation signal to the sensor device at 4006. In some embodiments, the sensor device includes a resolver. In a particular embodiment, the resolver includes a dual resolver or a dual speed resolver, such as Figure 3 In other embodiments, the sensor device may include or correspond to a synchronous active transducer (e.g., a linear variable differential transformer) or other active sensor. In addition, the sensor may be included in Figure 1 In the inertial measurement unit 102.

[0331] In some implementations, the dithered excitation signal includes or corresponds to a digital signal and includes digital samples. In such implementations, a DAC (eg, DAC 310) converts the dithered excitation signal to an analog signal and provides the dithered excitation signal to the sensor device.

[0332] In some embodiments, the base excitation signal corresponds to a sine wave signal, and the jitter excitation signal has a zero mean deviation from the sine wave signal. For example, the 16th order harmonic signal includes 16 sine waves for each sine wave of the base excitation signal. Therefore, the combined signal of the higher-order even harmonics and the base excitation signal generates the jitter excitation signal 352, wherein during each sine wave of the base excitation signal 452, the average amplitude of the jitter excitation signal 352 does not deviate from the average amplitude of the base excitation signal 452, as shown in FIG. Fig.23 shown.

[0333] In some embodiments, method 4000 further includes generating a basic excitation signal. Figure 2 The excitation signal generator system 202 generates the basic excitation signal 452 and provides the basic excitation signal 452 to the combiners 2624, 2626, as shown in FIG. Fig.26 In certain embodiments, the excitation signal is generated based on a sine function and an amplitude setting. For example, the excitation signal generation system 202 (e.g., its first logic chain 2612) generates the basic excitation signal 452 by retrieving a value from a sine lookup table and multiplying the value by the amplitude setting. In some such embodiments, the lookup table is shared with one or more other components, and the lookup table is accessed based on Round-Robin scheduling.

[0334] In some embodiments, the method 4000 further includes generating a high-order even harmonic based on the 16th harmonic of the sine function and the second amplitude setting. For example, the second logic chain 2614 of the excitation signal generation system 202 generates a high-order even harmonic signal 2666 based on the harmonic of the sine function and the amplitude setting, and provides the high-order even harmonic signal 2666 to the combiners 2624, 2666, as shown in FIG. Fig.26 described.

[0335] In some embodiments, the method 4000 further comprises generating a low-order odd harmonic signal and combining the low-order odd harmonics, the high-order even harmonics and the fundamental excitation signal to generate a dithered excitation signal. In other embodiments, the combiner is configured to combine the high-order even harmonics and the fundamental excitation signal to generate a dithered excitation signal.

[0336] In some embodiments, method 4000 further includes time-coordinating the dithering excitation signal with the current switching of the motor. In a particular embodiment, time-coordinating the dithering excitation signal with the current switching of the motor includes offsetting the current switching from the peaks and valleys of the base excitation signal, as shown in FIG. Fig. 27 , Fig.28 and Figure 33-35 Additionally or alternatively, time-coordinating the dithering excitation signal with the current switching of the motor includes performing an even number of current switching during the waveform of the base excitation signal, as described in reference to Fig.33 In certain embodiments, the number of current switching events that occur during the waveform is the same as the number of current switch activations and current switch deactivations.

[0337] In some embodiments, method 4000 further includes time-coordinating the dithering excitation signal with the current switching of the motor. In a particular embodiment, time-coordinating the dithering excitation signal with the current switching of the motor includes offsetting the current switching from the peaks and valleys of the base excitation signal, as shown in FIG. Fig.33 Additionally or alternatively, the dithering excitation signal is synchronized with a sampling rate of the output of the solver.

[0338] In some embodiments, the motor is coupled to the sensor and the dithering excitation signal is offset from the current drive switching of the motor. In some such embodiments, the method 4000 further includes time-coordinating a first clock for generating the dithering excitation signal and a second clock configured to control the PWM of the motor so that the current drive switching of the motor is offset from the dithering excitation signal. For example, Figure 8 The counter 842 and Fig.33 The 3302 can be synchronized.

[0339] In some embodiments, the ADC is coupled to the resolver. In some such embodiments, the method 4000 further includes receiving, by the ADC, an output signal from the resolver and oversampling the output signal. In certain embodiments, the first clock is synchronized with a second clock of the ADC. In other embodiments, the ADC is based on the first clock (e.g., Figure 8 The counter 842) oversamples the output signal.

[0340] refer to Fig.41 , which is a block diagram 4100 of an illustrative embodiment of an aircraft 4102. Fig.41 As shown, vehicle 4102 (e.g., a spacecraft, satellite, or space station) includes frame 4118, interior 4122, and multiple systems 4120. System 4120 may include one or more of propulsion system 4124, electrical system 4126, environmental system 4128, hydraulic system 4130, and inertial measurement unit 102. In other embodiments, compared to Fig.41 As shown in system 4120 , aircraft 4102 may include additional systems or fewer systems.

[0341] Inertial measurement unit 102 includes Figure 1 The inverter 112 and the universal joint device 114. The inverter 112 may include Figure 2 PWM 242, Figure 3 The current tracker 330, the gate driver 334, the transistor 336, Fig.28 The inverter 112 may include circuitry and firmware configured to perform Fig.33 The operations described in Fig.34 The operations described in Fig.35 operation of the PWM logic 3502, or a combination thereof.

[0342] The gimbal device 114 may include Figure 1 The universal joint 122, the motor 124, the resolver 126, the sensor 128, Figure 2 The excitation signal generating system 202, the solver system 204, the control system 206, the demodulation system 222, the feedback control system 232, Figure 3 DAC 310, dual speed resolver 312, differential voltage sensors 314, 316, ADC 318, 320, voltage regulation circuits 322, 324, angle estimation circuit 326, Figure 5 The demodulation circuits 514, 524, the angle calculation circuits 516, 526, the angle combination circuit 542, and the drift correction circuit 544, or a combination thereof.

[0343] Additionally or alternatively, the gimbal device 114 may include circuitry and firmware configured to perform Figure 6 Logic 602, Figure 7 Logic 702, Figure 8 Logic 802, Fig. 9 RMVA logic 812, Fig.10 Demodulation logic 826, Fig.11 The accumulator logic 1014, Fig.11 Logic 1102, Fig.14 Mask logic 1018, Fig.16 The output logic is 1026, Fig.18 Logic 1802, Fig.19 Logic 1902, Fig.26 Logic 2602, Fig.30 Logic 3002, Fig.31 Logic 3102, Fig.32 The inertial measurement unit 102 may be included within the aircraft 4102 or coupled to an external surface of the aircraft 4102.

[0344] The inertial measurement unit 102 is configured to enable inertial navigation of the aircraft 4102, as described above with reference to Figure 1-40 As described. For example, the inertial measurement unit 102 (e.g., one or more components thereof) is configured to perform one or more operations of one or more of the methods 3600-4000. As another example, the inertial measurement unit 102 is configured to execute computer-executable instructions (e.g., a program of one or more instructions) stored in a memory. These instructions, when executed, cause the inertial measurement unit 102 to perform one or more operations of one or more of the methods 3600-4000. For example, the processor receives a coarse position signal from a coarse solver and a fine position signal from a fine solver, generates an initial position output based on the coarse position signal, and generates a subsequent position output based on the fine position signal, as shown in reference Fig.36 described.

[0345] The description of the examples described herein is intended to provide a general understanding of the structure of various embodiments. These descriptions are not intended to be used as a complete description of all elements and features of the devices and systems utilizing the structures or methods described herein. After reading this disclosure, many other embodiments are apparent to those skilled in the art. Other embodiments can be derived from this disclosure using this disclosure so that structural and logical replacements and changes can be made without departing from the scope of this disclosure. For example, method operations can be performed in an order different from that shown in the figure, or one or more method operations can be omitted. Therefore, this disclosure and the accompanying drawings should be considered illustrative rather than restrictive.

[0346] In addition, although specific examples have been illustrated and described herein, it should be appreciated that any subsequent arrangement designed to achieve the same or similar results may replace the specific embodiments shown. This disclosure is intended to cover any and all subsequent adaptations or variations of the various embodiments. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art after reading this specification.

[0347] The abstract of the present disclosure is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, various features may be combined together or described in a single embodiment for the purpose of simplifying the present disclosure. The above examples illustrate but do not limit the present disclosure. It should also be understood that various modifications and variations may be made according to the principles of the present disclosure. As reflected in the appended claims, the subject matter claimed may involve less than all the features of any disclosed example. Therefore, the scope of the present disclosure is defined by the appended claims and their equivalents.

[0348] Furthermore, the present disclosure includes embodiments according to the following clauses:

[0349] Clause 1. A pulse width modulation control circuit (242, 3502), comprising:

[0350] a first transistor (336, 2822) comprising a first terminal (2862) coupled to the power source (252) and a second terminal (2866) coupled to the first input (2852) of the controlled component (124); and

[0351] A signal generator (334, 2842, 3522, 3524) coupled to the gate (2864) of the first transistor, the signal generator being configured to:

[0352] Receive (3702) comparison value (3322,3422) and comparison criteria (3324,3326,3424,3426);

[0353] comparing (3704) the comparison value with a counter value (3304) based on the comparison criteria; and

[0354] In response to the comparison value satisfying the comparison criterion relative to the counter value, a control signal (3532, 3534) is sent (3706) to the gate of the first transistor to generate a pulse edge of a pulse of a pulse width modulated signal (380).

[0355] Item 2. The pulse width modulation control circuit as described in Item 1 further includes a second transistor (336, 2824), the second transistor including a first terminal (2862) coupled to the power supply, a second terminal (2866) coupled to the second input terminal (2852) of the controlled component, and a gate (2864) coupled to the signal generator.

[0356] Clause 3. The pulse width modulation control circuit as described in Clause 1 also includes a third transistor (336, 2826), wherein the third transistor includes a first terminal (2862) coupled to the power supply, a second terminal (2866) coupled to the third input terminal (2852) of the controlled component, and a gate (2864) coupled to the signal generator.

[0357] Clause 4. The pulse width modulation control circuit as described in Clause 1 also includes a fourth transistor (336, 2832), the fourth transistor including a first terminal (2862) coupled to the power supply via the first transistor, coupled to the controlled component, and including a second terminal (2864) coupled to ground, and coupled to a gate (2864) of the signal generator.

[0358] Item 5. A pulse width modulation control circuit as described in Item 1, wherein the comparison value and the comparison criterion are included in a set point signal (3312-3320, 3412-3420), and wherein the comparison criterion includes a greater than condition, a greater than or equal to condition, a less than condition, or a less than or equal to condition.

[0359] Clause 6. The pulse width modulation control circuit of Clause 5, wherein the signal generator is further configured to determine the comparison value based on a shift operation of the set point signal.

[0360] Clause 7. The pulse width modulation control circuit of Clause 5, the signal generator further configured to determine the comparison criterion based on one or more bits of the set point signal.

[0361] Clause 8. The pulse width modulation control circuit of Clause 1, the signal generator comprising a comparator configured to compare the counter value with the comparison value based on the comparison criterion.

[0362] Clause 9. The pulse width modulation control circuit of clause 1, wherein the controlled component comprises a light emitting diode, a duty cycle controller, a clock signal generator, a buck converter, a servo, a stepper motor, a single-phase motor, or a multi-phase motor.

[0363] Clause 10. A pulse width modulation method (3700), the method comprising:

[0364] Receive (3702) comparison value and comparison criteria (3324,3326,3424,3426);

[0365] comparing (3704) the comparison value to the counter value (3304) based on the comparison criteria; and

[0366] In response to the comparison value satisfying the comparison criterion relative to the counter value, a control signal (378, 3532, 3534) is sent (3706) to the gate (2864) of the first transistor (336, 2822-2826, 2832-2836) to generate a pulse edge of a pulse of the pulse width modulated signal (380).

[0367] Clause 11. The method of clause 10, further comprising:

[0368] receiving a set point signal (3312-3320, 3412-3420) indicative of the comparison value, the comparison criterion, and a second comparison criterion (3326, 3426);

[0369] comparing the comparison value with a second counter value (3304) based on the second comparison criterion; and

[0370] In response to the comparison value satisfying the second comparison criterion relative to the second counter value, a second control signal (378) is sent to the gate of the first transistor to generate a second pulse edge of the pulse of the pulse width modulated signal.

[0371] Clause 12. The method according to clause 11, further comprising:

[0372] determining the comparison value based on one or more first bits of the set point signal; and

[0373] The comparison criterion and the second comparison criterion are determined based on one or more second bits of the setpoint signal.

[0374] Clause 13. The method of Clause 12, wherein determining the comparison value comprises right shifting the setpoint signal by one or more bits.

[0375] Clause 14. The method of Clause 12, wherein the one or more second bits of the set point signal correspond to one or more least significant bits of the set point signal.

[0376] Clause 15. The method of Clause 14, further comprising selecting the comparison criterion from a table based on the one or more least significant bits of the setpoint signal.

[0377] Clause 16. The method of clause 10, further comprising:

[0378] receiving a second set point signal (3312-3320, 3412-3420) indicative of a second comparison value (3322, 3422) and a second comparison criterion (3324, 3424);

[0379] comparing the second comparison value with a second counter value (3304) based on the second comparison criterion; and

[0380] In response to the second comparison value satisfying the second comparison criterion relative to the second counter value, a second control signal (378) is sent to the gate (2864) of the second transistor (336, 2822-2826, 2832-2836) to generate a pulse edge of a second pulse of the pulse width modulated signal.

[0381] Clause 17. A system (102), comprising:

[0382] a motor (124); and

[0383] a pulse width modulation control circuit (242, 3502) coupled to the motor and configured to output a pulse width modulation signal (380) to the motor, the pulse width modulation control circuit comprising:

[0384] a first transistor including a first terminal coupled to a power source and a second terminal coupled to a first input of the motor; and

[0385] a signal generator comprising a first node coupled to a gate of the first transistor, the signal generator being configured to:

[0386] receiving a set point signal indicative of a comparison value and a comparison standard;

[0387] comparing the comparison value with a counter value based on the comparison criterion; and

[0388] In response to the comparison value satisfying the comparison criterion relative to the counter value, a control signal is sent to the gate of the first transistor to generate a pulse edge of a pulse of the pulse width modulated signal.

[0389] Clause 18. The system of Clause 17, further comprising: an up-down counter (3302) configured to generate the counter value.

[0390] Clause 19. A system as described in Clause 17, wherein the motor comprises a three-phase motor (124), wherein the first input terminal corresponds to a first phase of the three-phase motor, and wherein the pulse edge of the pulse width modulated signal is configured to cause activation of the first phase of the three-phase motor.

[0391] Clause 20. The system of Clause 17, wherein the motor and the pulse width modulation control circuit are included in a gimbaled inertial measurement unit (102).

Claims

1. A pulse width modulation control circuit (242, 3502), comprising: a first transistor including a first terminal (2862) coupled to a power source (252) and a second terminal (2866) coupled to a first input (2852) of a controlled component (124); and A signal generator (334, 2842, 3522, 3524) coupled to the gate (2864) of the first transistor, the signal generator being configured to: Receive (3702) comparison value (3322,3422) and comparison criteria; comparing the comparison value with a counter value based on the comparison criteria (3704); and In response to the comparison value satisfying the comparison criterion relative to the counter value, sending (3706) a control signal (3532, 3534) to the gate of the first transistor to generate a pulse edge of a pulse of a pulse width modulated signal (380), wherein the comparison value and the comparison criterion are included in a set point signal, and wherein the comparison criterion is adjustable and includes a greater than condition, a greater than or equal to condition, a less than condition, or a less than or equal to condition, wherein the signal generator is further configured to determine the comparison value based on a shift operation of the set point signal, and to determine the comparison criterion based on one or more bits of the set point signal.

2. The pulse width modulation control circuit of claim 1 , further comprising a second transistor comprising a first terminal (2862) coupled to the power supply, a second terminal (2866) coupled to the second input terminal (2852) of the controlled component, and a gate (2864) coupled to the signal generator.

3. The pulse width modulation control circuit of claim 1 , further comprising a third transistor comprising a first terminal (2862) coupled to the power supply, a second terminal (2866) coupled to the third input terminal (2852) of the controlled component, and a gate (2864) coupled to the signal generator.

4. The pulse width modulation control circuit of claim 1 , further comprising a fourth transistor, the fourth transistor comprising a first terminal (2862) coupled to the power supply via the first transistor, coupled to the controlled component and comprising a second terminal (2866) coupled to ground, and coupled to a gate (2864) of the signal generator. 5 . The PWM control circuit of claim 1 , the signal generator comprising a comparator configured to compare the counter value with the comparison value based on the comparison criterion.

6. The pulse width modulation control circuit of claim 1, wherein the controlled component comprises a light emitting diode, a duty cycle controller, a clock signal generator, a buck converter, a servo, a stepper motor, a single-phase motor, or a multi-phase motor.

7. A method (3700) of performing pulse width modulation by using a pulse width modulation control circuit (242, 3502) according to any one of the preceding claims, the method comprising: Receive (3702) a comparison value and a comparison criterion; comparing the comparison value with a counter value based on the comparison criteria (3704); and In response to the comparison value satisfying the comparison criterion relative to the counter value, sending (3706) a control signal (378, 3532, 3534) to the gate (2864) of the first transistor to generate a pulse edge of a pulse of the pulse width modulated signal (380), Wherein the comparison value and the comparison criterion are included in a set point signal, and wherein the comparison criterion is adjustable and includes a greater than condition, a greater than or equal to condition, a less than condition, or a less than or equal to condition.

8. The method according to claim 7, further comprising: receiving a set point signal indicative of the comparison value, the comparison criterion, and a second comparison criterion; comparing the comparison value with a second counter value based on the second comparison criterion; and In response to the comparison value satisfying the second comparison criterion relative to the second counter value, a second control signal (378) is sent to the gate of the first transistor to generate a second pulse edge of the pulse of the pulse width modulated signal.

9. The method according to claim 8, further comprising: determining the comparison value based on one or more first bits of the set point signal; and The comparison criterion and the second comparison criterion are determined based on one or more second bits of the setpoint signal.

10. The method of claim 9, wherein determining the comparison value comprises right shifting the setpoint signal by one or more bits.

11. The method of claim 9, wherein the one or more second bits of the set point signal correspond to one or more least significant bits of the set point signal.

12. The method of claim 11, further comprising selecting the comparison criterion from a table based on the one or more least significant bits of the setpoint signal.

13. The method according to claim 7, further comprising: receiving a second set point signal indicative of a second comparison value (3322, 3422) and a second comparison criterion; comparing the second comparison value with a second counter value based on the second comparison criterion; and In response to the second comparison value satisfying the second comparison criterion relative to the second counter value, a second control signal (378) is sent to the gate (2864) of the second transistor to generate a pulse edge of a second pulse of the pulse width modulated signal.

14. A system for pulse width modulation, comprising: Motor (124); and The pulse width modulation control circuit (242, 3502) according to any one of claims 1-6, wherein the pulse width modulation control circuit (242, 3502) is coupled to the motor as the controlled component.

15. The system of claim 14, further comprising: An up-down counter (3302) is configured to generate the counter value.

16. The system of claim 14, wherein the motor comprises a three-phase motor (124), wherein the first input corresponds to a first phase of the three-phase motor, and wherein the pulse edges of the pulse width modulated signal are configured to cause activation of the first phase of the three-phase motor.

17. The system of claim 14, wherein the motor and the pulse width modulation control circuit are included in a gimbaled inertial measurement unit (102).

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