Accessing Graph Metadata

Abstract

The present application relates to accessing primitive data. A method for generating identifiers (IDs) for primitives and optionally for vertices during tessellation is described herein. The ID comprises a binary sequence of bits representing the tessellation steps taken during the tessellation process, thus encoding the manner in which the tessellation is performed. Such an ID can then be used to generate a random primitive or vertex, and thus recalculate vertex data for that primitive or vertex.

Description

Technical Field

[0001] The present application relates to, but is not limited to, accessing metadata. background

[0002] Tessellation is a technique used in computer graphics that breaks a set of surfaces representing objects in a scene into many smaller and simpler pieces, called primitives, which are typically triangles, that are more suitable for rendering. The resulting tessellated surface is typically an approximation of the original surface, but the accuracy of this approximation can be improved by increasing the number of primitives generated, which in turn typically results in smaller primitives. The number of tessellation / sub-divisions is typically determined by the level of detail (LOD). Therefore, where a higher level of detail is required (for example, because objects are closer to the viewer and / or the objects have a more complex shape), an increased number of primitives is typically used. However, using a larger number of triangles increases the amount of processing required to render the scene.

[0003] Tessellation of triangle primitives is typically performed on patches that are square or triangular in shape (i.e., quads or triangles), and the patches may be curved to fit the surface of the object they represent (and thus may be referred to as "surface patches") and / or have displacement mappings applied. However, rather than performing the tessellation on curved patches, the tessellation is performed in the domain of the patches (e.g., as if the patches were planar, rather than defined by, for example, polynomial equations), which domain may be defined in terms of (u,v) parameters (also known as UV parameters), and is referred to as "parameter space" or "UV space". This means that the tessellation process is independent of any curvature present in the final surface.

[0004] Due to the increase in the number of primitives generated, the ability of the graphics processing system to process primitives becomes more important. A known way to improve the efficiency of a graphics processing system is to render images in a tile-based manner. In this way, the rendering space in which the primitives are rendered is divided into a plurality of tiles, which can then be rendered independently of each other. A tile-based graphics system includes a tiling unit that tiles the primitives, i.e., for a primitive, determines in which tile of the rendering space the primitive is located. Then, when the rendering unit renders the tile, information indicating which primitives should be used to render the tile can be given.

[0005] The embodiments described below are provided by way of example only and are not limiting of implementations that address any or all disadvantages of known graphics processing systems.

[0006] Overview

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0008] This article describes a method for generating identifiers (IDs) for primitives and optionally for vertices during tessellation. The IDs include a binary sequence of bits that represent the tessellation steps taken during the tessellation process, thus encoding the manner in which the tessellation is performed. Such IDs can then be used to generate random primitives or vertices and thus recalculate vertex data for that primitive or vertex.

[0009] A first aspect provides a method for performing surface tessellation in a computer graphics system, the method comprising: subdividing an initial patch into a plurality of primitives using a plurality of subdivision steps; and generating a primitive ID for each primitive, wherein the primitive ID encodes data on how the primitive was generated by the plurality of subdivision steps.

[0010] The data on how to generate primitives by subdividing the initial patch may include a sequence of bits describing a plurality of subdivision steps taken during tessellation to generate the primitives. Each bit in the sequence of bits may indicate which branch to take in a corresponding subdivision step during tessellation to generate the primitives.

[0011] The ID of the primitive may include a sequence of bits that specifies a recursive sequence to be employed during the tessellation process.The ID of the primitive may also include a variable length trailer portion, and wherein the ID of the primitive includes a fixed number of bits.

[0012] Subdividing an initial patch into a plurality of primitives using a plurality of subdivision steps may include: analyzing the initial patch to determine whether to subdivide the patch; in response to determining that the patch will not be subdivided, outputting the patch as a triangle primitive; in response to determining that the patch will be subdivided, dividing the initial patch into two or more sub-patches; selecting each sub-patch formed by the subdivision of the initial patch in turn, and repeating the method with the selected sub-patch replacing the initial patch; and wherein generating an ID for each primitive may include: in response to dividing the initial patch into two or more sub-patches, assigning an ID to the sub-patch that matches an ID of a patch that has been subdivided; and in response to selecting a patch formed by the subdivision of the initial patch, updating the ID of each patch formed by the subdivision of the initial patch according to the selection.

[0013] The initial patch may be formed by subdividing a triangular, quadrilateral or polygonal domain, and the patch ID also includes a header portion including one or more bits indicating which of a plurality of initial patches formed by triangular or quadrilateral domains the primitive is in.

[0014] Updating the ID of each patch formed by the tessellation of the initial patch according to the selection may comprise, for each ID: adding one or more new bits to a sequence of bits specifying a recursive sequence employed during the tessellation process, the value of the new bits depending on the selection.

[0015] The initial patch may be a triangle patch, and selecting each sub-patch formed by the subdivision of the initial patch in turn and repeating the method with the selected sub-patch in place of the initial patch may include: selecting each of the sub-patch formed by the subdivision of the initial patch in turn based on the value of one or more flags, and repeating the method with the selected sub-patch in place of the initial patch; and wherein repeating the method with the selected sub-patch in place of the initial patch includes: analyzing the selected sub-patch to determine whether to further subdivide the selected sub-patch; in response to determining that the selected sub-patch will not be subdivided, outputting the selected sub-patch as a triangle primitive; in response to determining that the selected sub-patch will be further subdivided, dividing the selected sub-patch into two or more sub-patch; and selecting each sub-patch formed by the subdivision of the selected sub-patch in turn based on the value of one or more flags, and repeating the method with the selected sub-patch.

[0016] Dividing the initial slice into two or more sub-slices may include dividing the initial slice into a left sub-slice and a right sub-slice.

[0017] In the method, an initial slice may have a sorting flag, subdivided into two slices, a left slice and a right slice, and selecting each of the left slice and the right slice formed by the subdivision of the initial slice in turn based on the value of one or more flags may include: selecting each of the left slice and the right slice formed by the subdivision of the initial slice in turn based on the value of the sorting flag of the initial slice.

[0018] In the method, subdividing to form two slices, a left slice and a right slice, and sequentially selecting each of the left slice and the right slice formed by the subdivision of the initial slice based on the value of one or more flags may include: sequentially selecting each of the left slice and the right slice formed by the subdivision of the initial slice based on the value of the sorting flag.

[0019] The method may further include: for each increase or decrease of the subdivision level, inverting the value of the sort flag once.

[0020] The initial slice may include two or three vertices, and dividing the initial slice into two or more sub-slices may include: adding a new vertex (M); assigning the ID of the subdivided initial slice to the new vertex; forming a left sub-slice including the new vertex and one or two vertices of the initial slice; and forming a right sub-slice including the new vertex and one or two vertices of the initial slice.

[0021] The method may also include: receiving, in a tessellation unit, an ID and a surface patch reference of a previously tessellated primitive; accessing data from the surface patch associated with the primitive, the data including tessellation factors and topology data; selecting an initial patch based on the primitive ID, and at least partially tessellating the initial patch using one or more tessellation stages, wherein at each stage of the tessellation, determining whether to perform tessellation and which of any newly formed sub-patches to be further tessellated is based on a sequence of one or more bits in the primitive's ID.

[0022] The method may also include: receiving an ID of a primitive in a tessellation unit; truncating the ID of the primitive at multiple different locations to generate an ID for each vertex in the primitive; for a subset of vertices in the primitive, truncating the vertex ID of the vertex at multiple different locations to generate an ID of a parent vertex; using the vertex ID to calculate UV coordinates for each vertex in the primitive and for the parent vertex of the subset of vertices in the primitive; and generating vertex data for each vertex in the primitive based on the calculated UV coordinates using a domain shader.

[0023] A second aspect provides a method for performing tessellation in a computer graphics system, the method comprising: receiving in a tessellation unit an ID and a patch reference of a previously tessellated primitive; accessing data from the patch associated with the primitive, the data comprising tessellation factors and topology data; selecting an initial patch based on the primitive ID, and at least partially tessellating the initial patch using one or more tessellation stages, wherein at each stage of the tessellation, determining whether to perform tessellation and which of any newly formed sub-patches to be further tessellated is determined based on a sequence of one or more bits in the primitive's ID.

[0024] The method may also include selecting an input patch based on data from a surface patch associated with the primitive, and subdividing the input patch into one or more initial patches.

[0025] The primitive's or tile's ID may include a sequence of bits that specifies a recursive sequence to employ during the tessellation process. Each bit in the sequence of bits may indicate whether to process a left or right sub-tile formed by a tessellation operation in the tessellation process.

[0026] The method may further include accessing from memory an ID of a previously tessellated primitive.

[0027] In the method, at least partially tessellating an initial patch generated by tessellation of an input patch may result in regenerating a previously tessellated primitive.

[0028] The method may also include: outputting domain vertices for the previously tessellated primitive. The domain vertices may be output to a domain shader. In the case where the previously tessellated primitive is a triangle primitive, three domain vertices are output. In the case where the previously tessellated primitive is an isoline primitive, two domain vertices are output.

[0029] A third aspect provides a method for performing surface tessellation in a computer graphics system, the method comprising: receiving an ID of a primitive in a surface tessellation unit; truncating the ID of the primitive at multiple different positions to generate an ID for each vertex in the primitive; for a subset of vertices in the primitive, truncating the vertex ID of the vertex at multiple different positions to generate an ID for a parent vertex; using the vertex ID to calculate UV coordinates for each vertex in the primitive and for the parent vertex of the subset of vertices in the primitive; and using a domain shader to generate vertex data for each vertex in the primitive based on the calculated UV coordinates.

[0030] The ID of a primitive may include a sequence of bits that describes the subdivision sequence used to generate the primitive.

[0031] The ID of the primitive may include a sequence of bits that specifies a recursive sequence employed during the tessellation process. The recursive sequence may define a subdivision hierarchy, and truncating the ID of the primitive at a plurality of different locations to generate an ID for each vertex in the primitive may include: performing a first truncation according to a first function that steps one step back up the subdivision hierarchy to generate a first vertex ID; performing two further truncations according to a second function to generate a second vertex ID and a third vertex ID, wherein the second function steps two steps back up the subdivision hierarchy to generate the second vertex ID, and steps S steps back up the subdivision hierarchy to generate the third vertex ID, wherein the value of S is determined by the ID of the primitive. Each vertex may have an associated displacement factor, and the subset may include only those vertices in the primitive whose displacement factors are not equal to a maximum of the displacement factors.

[0032] The recursive sequence may define a subdivision hierarchy, and for a subset of vertices in a primitive, truncating the vertex ID of the vertex at multiple different locations to generate an ID of a parent vertex may include: for a subset of vertices in the primitive, performing two truncations according to a second function to generate a first parent vertex ID and a second parent vertex ID, wherein the second function steps back the subdivision hierarchy two steps to generate the first parent vertex ID, and steps back S steps to generate the second parent vertex ID, wherein the value of S is determined by the vertex ID.

[0033] The recursive sequence may define a subdivision hierarchy, and using the vertex ID to calculate UV coordinates for each vertex in the primitive and for a parent vertex of a subset of the vertices in the primitive may include: for each vertex in the primitive: using a third function to calculate the vertex UV coordinate for the vertex according to the vertex ID; and for the subset of vertices in the primitive: using the third function to calculate the vertex UV coordinate for the parent vertex of the vertex according to the vertex ID of the parent vertex. The third function may include: generating a fixed complex value; forming a sequence of scaled versions of the complex value for each bit of the vertex ID; summing all scaled versions in the sequence; and performing a scale and translate operation to generate a vertex UV corresponding to the vertex ID.

[0034] A fourth aspect provides a tessellation unit configured to perform tessellation in a computer graphics system, the tessellation unit comprising hardware logic arranged to: subdivide an initial patch into a plurality of primitives using a plurality of tessellation steps; and generate a primitive ID for each primitive, wherein the primitive ID encodes data on how the primitive was generated through the plurality of tessellation steps.

[0035] The hardware logic arranged to split the initial slice into two or more sub-slices may include hardware logic arranged to split the initial slice into a left sub-slice and a right sub-slice.

[0036] In various examples, an initial slice has a sorting flag, subdivided into two slices, a left slice and a right slice, and hardware logic arranged to sequentially select each of the left slice and the right slice formed by the subdivision of the initial slice based on the value of one or more flags includes hardware logic arranged to perform the following operations: sequentially select each of the left slice and the right slice formed by the subdivision of the initial slice based on the value of the sorting flag of the initial slice.

[0037] The subdivision may form two slices, a left slice and a right slice, and the hardware logic arranged to select, in turn, each of the left and right slices formed by the subdivision of the initial slice based on the value of one or more flags may include hardware logic arranged to select, in turn, each of the left and right slices formed by the subdivision of the initial slice based on the value of a sorting flag.

[0038] The tessellation unit may further comprise hardware logic arranged to invert the value of the sorting flag once for each increase or decrease in the tessellation level.

[0039] In various examples, the initial slice includes two or three vertices, and the hardware logic arranged to divide the initial slice into two or more sub-slices may include hardware logic arranged to perform the following operations: add a new vertex (M); assign the new vertex an ID of the initial slice that has been subdivided; form a left sub-slice including the new vertex and one or two vertices of the initial slice; and form a right sub-slice including the new vertex and one or two vertices of the initial slice.

[0040] A fifth aspect provides a computer graphics system comprising: a first tessellation unit as described herein; and a second tessellation unit comprising hardware logic, the hardware logic being arranged to: receive an ID and a patch reference of a previously tessellated primitive in the tessellation unit; access data from the patch associated with the primitive, the data comprising tessellation factors and topology data; select an input patch based on the data from the patch associated with the primitive, and tessellate the input patch into one or more initial patches; select the initial patch based on the primitive ID, and at least partially tessellate the initial patch using one or more tessellation stages, wherein at each stage of the tessellation, whether to perform tessellation and which of any newly formed sub-patterns are to be further tessellated is determined based on a sequence of one or more bits in the primitive's ID.

[0041] The tessellation unit may further comprise hardware logic arranged to: output domain vertices for previously tessellated primitives. The domain vertices may be output to a domain shader.

[0042] The tessellation unit may further comprise hardware logic arranged to access from the memory the IDs of previously tessellated primitives.

[0043] A sixth aspect provides a computer graphics system, comprising: a first tessellation unit as described herein; a second tessellation unit comprising hardware logic, the hardware logic being arranged to: receive an ID of a primitive in the tessellation unit; truncate the ID of the primitive at multiple different locations to generate an ID for each vertex in the primitive; for a subset of vertices in the primitive, truncate the vertex ID of the vertex at multiple different locations to generate an ID for a parent vertex; and use the vertex ID to calculate UV coordinates for each vertex in the primitive and for the parent vertex of the subset of vertices in the primitive; and a domain shader comprising hardware logic, the hardware logic being arranged to generate vertex data for each vertex in the primitive based on the calculated UV coordinates.

[0044] The ID of a primitive may include a sequence of bits that specify the recursive sequence to employ during the tessellation process.

[0045] In various examples, each vertex has an associated displacement factor, and the subset includes only those vertices in the primitive whose displacement factors are not equal to the maximum of the displacement factors.

[0046] In various examples where the ID of the primitive includes a sequence of bits that specifies a recursive sequence employed during the tessellation process, the recursive sequence may define a tessellation hierarchy, and hardware logic in the tessellation unit arranged to use the vertex ID to calculate UV coordinates for each vertex in the primitive and for a parent vertex of a subset of the vertices in the primitive may include hardware logic arranged to perform the following operations: for each vertex in the primitive: calculate the vertex UV coordinate for the vertex from the vertex ID using a third function; and for the subset of vertices in the primitive: calculate the vertex UV coordinate for the parent vertex of the vertex from the vertex ID of the parent vertex using a third function. The third function may include: generating a fixed complex value; forming a sequence of scaled versions of the complex value for each bit of the vertex ID; summing all scaled versions in the sequence; and performing a scale and translate operation to generate a vertex UV corresponding to the vertex ID.

[0047] A seventh aspect provides a tessellation unit configured to perform tessellation in a computer graphics system, the tessellation unit comprising hardware logic arranged to: receive an ID and a patch reference of a previously tessellated primitive in the tessellation unit; access data from the patch associated with the primitive, the data comprising tessellation factors and topology data; select an initial patch based on the primitive ID, and at least partially tessellate the initial patch using one or more tessellation stages, wherein at each stage of the tessellation, a determination is made as to whether to perform tessellation and which of any newly formed sub-patterns are to be further tessellated based on a sequence of one or more bits in the primitive's ID.

[0048] An eighth aspect provides a computer graphics system, comprising: a tessellation unit, which includes hardware logic, which is arranged to: receive an ID of a primitive in the tessellation unit; truncate the ID of the primitive at multiple different positions to generate an ID for each vertex in the primitive; for a subset of vertices in the primitive, truncate the vertex ID of the vertex at multiple different positions to generate an ID for the parent vertex; and use the vertex ID to calculate UV coordinates for each vertex in the primitive and for the parent vertex of the subset of vertices in the primitive; and a domain shader including hardware logic, which is arranged to generate vertex data for each vertex in the primitive based on the calculated UV coordinates.

[0049] A hardware tessellator or other hardware configured to perform any of the methods described herein may be embodied in hardware on an integrated circuit, such as a separate single primitive tessellator (or a graphics pipeline including the hardware). A method of manufacturing a tessellation unit configured to perform one of the sorting methods described herein at an integrated circuit manufacturing system may be provided. An integrated circuit definition data set may be provided that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a hardware tessellator or other hardware (such as a separate single primitive tessellator) configured to perform any of the methods described herein. A non-transitory computer-readable storage medium may be provided having stored thereon a computer-readable description of an integrated circuit that, when processed, causes a layout processing system to generate a circuit layout description for use in an integrated circuit manufacturing system to manufacture a hardware tessellator or other hardware (such as a separate single primitive tessellator) configured to perform any of the methods described herein.

[0050] An integrated circuit manufacturing system can be provided, comprising: a non-temporary computer-readable storage medium having stored thereon a computer-readable integrated circuit description describing a hardware tessellator or other hardware (e.g., a separate single primitive tessellator) configured to perform any of the methods described herein; a layout processing system configured to process the integrated circuit description to generate a circuit layout description of an integrated circuit embodying the hardware tessellator or other hardware (e.g., a separate single primitive tessellator) configured to perform any of the methods described herein; and an integrated circuit generation system configured to manufacture the hardware tessellator or other hardware (e.g., a separate single primitive tessellator) configured to perform any of the methods described herein based on the circuit layout description.

[0051] Computer program code for performing the methods described herein may be provided.A non-transitory computer readable storage medium having computer readable instructions stored thereon may be provided, which when executed at a computer system causes the computer system to perform the methods described herein.

[0052] As will be apparent to the skilled person, the above features may be combined as appropriate and with any aspects of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Examples will now be described in detail with reference to the accompanying drawings, in which:

[0054] Figure 1A is a schematic diagram of a known GPU pipeline;

[0055] Figure 1B is a schematic diagram of the improved GPU pipeline;

[0056] Figure 2A-2E A schematic diagram illustrating tessellation of a triangular input patch is shown;

[0057] Figure 3A is a flow chart illustrating a first example tessellation method;

[0058] Figure 3B It is shown Figure 3A A flowchart of a variation of the first example tessellation method is shown;

[0059] Figure 3C It shows the application Figure 3A A schematic diagram of an example sequence of a tessellation method;

[0060] Figure 4A is a flow chart illustrating a second example tessellation method in which primitives are generated according to "improved sorting";

[0061] Figure 4B It is shown Figure 4A A flowchart of a variation of the second example tessellation method is shown;

[0062] Figure 5A and Figure 5B is a schematic diagram showing the structure of an example primitive ID;

[0063] Figure 6 is a flowchart of an example method for generating IDs for primitives;

[0064] Figure 7 , Fig. 8A and Figure 8B is a flowchart of an example method for generating vertex data based on a primitive ID;

[0065] Fig. 9A , Fig. 9B and Fig. 9C It is shown that when used with known tessellation schemes, Fig. 8A and Figure 8B three graphical representations of parts of the method;

[0066] Fig. 10A and Fig. 10B Shows Fig. 8A and Figure 8B A graphical representation of parts of the method;

[0067] Fig.11 is a schematic diagram of a computing-based device configured to implement the methods described herein for generating and / or using primitive and / or vertex IDs;

[0068] Fig.12A computer system is shown in which a hardware tessellator or other hardware (e.g., a separate single primitive tessellator) configured to perform any of the methods described herein is implemented;

[0069] Fig.13 An integrated circuit manufacturing system is shown for producing an integrated circuit embodying a hardware tessellator or other hardware (e.g., a separate single primitive tessellator) configured to perform any of the methods described herein;

[0070] Fig.14A and Fig. 14B is a schematic diagram illustrating the preprocessing stage of the tessellation method described herein;

[0071] Fig.15 is the definition Fig. 8A A table of the second function γ is shown.

[0072] The accompanying drawings illustrate different examples. The skilled person will recognize that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the figures represent an example of boundaries. In some examples, it may be that an element may be designed as multiple elements, or multiple elements may be designed as one element. Where appropriate, common reference numerals are used to indicate similar features throughout the accompanying drawings. Detailed Description

[0073] The following description is presented by way of example to enable those skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0074] The embodiments will now be described by way of example only.

[0075] As described above, tessellation involves selectively subdividing patches, typically square or triangular in shape, into smaller triangular patches. A determination as to whether a patch should be tessellated is typically made based on one or more tessellation factors (TFs), for example by comparing one or more TFs to each other and / or to a threshold. In some examples, edge tessellation factors are used, where each edge of a patch has an edge tessellation factor, and the edge tessellation factor defines how many times a particular edge (and thus the patch of which the particular edge is a part) should be tessellated. In other examples (e.g., in the methods described in GB2533443 and GB2533444), vertex tessellation factors are used, where each vertex (or corner) of a patch has a vertex tessellation factor.

[0076] The term "surface patch" is used herein to refer to a typically finite N-dimensional surface (or an N-dimensional curve segment in the case of an isoline) that is the result of applying a parametric mapping function to a bounded 2D domain, the surface patch being a quadrilateral, triangle, or other polygon (or a 1D line segment in the case of an isoline). The resulting surface or isoline can be considered to be N-dimensional because it may include not only 3 (or 4) dimensions for Cartesian (or uniform) space positioning, but also other parameters, such as texture coordinates. As described above, the surface patches may be curved to fit the surface of the object they represent and / or displacement mapping may be applied. However, tessellation (i.e., subdivision of the patch) is not performed in "world space" (i.e., it is not performed on a curved surface patch), but rather in domain space (which may also be referred to as parameterized space or parameter space or UV space), where any position in the domain can be described by two coordinates (u, v) that are considered to be domain space coordinates, which means that the tessellation process is independent of any curvature present in the final surface.

[0077] The term "patch" is used herein to refer to an ordered set of two, three, four or more vertices (for contours, triangles, quadrilaterals or polygons, respectively) that define a domain. Thus, the term "domain" refers to the two-dimensional space defined by the vertices of a patch. The term "input patch" is used to refer to a patch selected by a tessellation unit based on an input topology, and the input patch also refers to an ordered set of vertices. In an example where a tessellation unit performs a preprocessing stage, the preprocessing stage tessellates the input patch, after which the tessellation algorithm is repeatedly applied to the patch formed by the preprocessing stage, the patch formed in the preprocessing stage is referred to herein as an "initial patch". The patch formed by the tessellation of the initial patch is referred to herein as a "sub-patch". The term "primitive" is used herein to refer to a patch (e.g., an initial patch or a sub-patch) output by a tessellation unit, because it does not require further tessellation, and although each primitive corresponds to a patch (i.e., an initial patch or a sub-patch), it may be in a different form from a patch (e.g., a primitive may include an index instead of an ordered set of vertices). Although the input patch, initial patch, and sub-patch are typically triangles, and the examples below show triangles, in other examples the input patch, initial patch, and / or sub-patch may be contour lines or any form of polygon.

[0078] Described in GB2533443 and Fig.14A and Fig. 14B An example of a preprocessing stage to generate an initial patch is shown in . The preprocessing stage is used to ensure that the tessellation is independent of orientation. Fig.14A As shown, if the input patch is a triangle patch 1402, the pre-processing stage outputs one triangle patch 1402 (which is the same as the input triangle patch and does not require tessellation) or three triangle patches 1408-1410. Fig. 14B As shown, if the input patch is a quadrilateral patch 1404, the pre-processing stage outputs four triangular patches 1412-1415. Similar techniques can also be applied to the input polygonal patch to subdivide it into multiple initial triangular patches.

[0079] The term "vertex" is often used to describe a position plus other attributes, where these attributes differ depending on the context. For example, input control points and output vertices from a domain shader include a 3D position plus other parameters such as normals, tangents, textures, etc. (and may be referred to as "world space vertices"), whereas vertices within a tessellator (i.e., those vertices used as elements of a patch within a tessellation method) include domain space coordinates and a vertex tessellation factor (and may be referred to as "tessellator vertices"). Thus, these vertices within the tessellator are distinct from the input control points or final N-dimensional vertices that form the final triangles.

[0080] Figure 1A 1 shows a schematic diagram of an example graphics processing unit (GPU) pipeline 100 that can be implemented in hardware within a GPU and that uses a tile-based rendering approach. Figure 1A As shown, pipeline 100 includes a geometry processing phase 101A and a rasterization phase 101B. Geometry processing phase 101A includes a tessellation unit 104 and a vertex shader 102 responsible for performing per-vertex calculations. Vertex shader 102 is unaware of mesh topology and performs per-vertex operations such that it only has information about the current vertex being processed. There may be one or more optional hull shaders between vertex shader 102 and tessellation unit (or tessellator) 104 that are not in the Figure 1A The geometry processing stage 101A also includes a geometry-specific domain shader (DS) 103, a tiling unit 106, and may also include other elements, such as a memory 105 and / or Figure 1A Other elements not shown.

[0081] Unlike vertex shaders, the hardware tessellation unit 104 (and any optional hull shader) operates per-patch rather than per-vertex. The tessellation unit 104 outputs primitives, and in a system that uses vertex indices, the output primitives take the form of a buffer of three vertex indices and vertex data (e.g., one UV coordinate for each vertex, and in various examples, other parameters such as a displacement factor and optionally a parent UV coordinate). Where indices are not used, the output primitives take the form of three domain vertices, where a domain vertex may include only UV coordinates, or may include UV coordinates plus other parameters (e.g., weights, such as a displacement factor and optionally a parent UV coordinate). The data output by the tessellation unit 104 may be stored in a memory 105.

[0082] The geometry-specific domain shader 103 in the geometry processing stage 101A generates the projected positions of the corners of the primitives. The tiling unit 106 reads the data generated by the tessellator 104 from the memory 105 and uses the data together with the projected positions generated by the geometry-specific domain shader 103 to generate per-tile display lists. The display lists are then output to the parameter memory 107. For a particular tile, each per-tile display list identifies those primitives that are at least partially within that tile. These display lists may be generated by the tiling unit 106 using a tiling algorithm. Subsequent elements within the GPU pipeline (e.g., the rasterization stage 101B) may then read the data from the parameter memory 107.

[0083] although Figure 1A The use of a geometry-specific domain shader 103 is shown to calculate the projected position of the new primitive in screen space (referred to as "screen coordinates"), but in other examples, a global shader (similar to domain shader 108) may be used or alternative dedicated hardware may be used to perform these calculations of the screen coordinates of the primitives. In other examples that do not include a geometry-specific domain shader 103, hardware may be provided that is arranged to estimate the screen coordinates of the new primitive.

[0084] The domain shader 108, which is part of the rasterization stage 101B, acts as a second vertex shader for the vertices generated by the tessellator 104 and is executed once pervertex per primitive per tile, however a cache can be used to enable reuse of shaded vertices. The domain shader is provided with a domain space position (u, v) and is given all the slice information (e.g., from the vertex shader) and outputs a complete vertex structure. The domain shader constructs new vertices using the slice control points and domain space coordinates and applies any displacement mapping (e.g., by sampling a height map encoded in a texture). Domain shading (in the domain shader 108) can be left in the GPU pipeline 100 as late as possible because it greatly expands the space required to store each vertex. After the domain shader 108 has been run for each generated vertex per slice, the data for each tile is further processed in the rasterizer 109 and some or all primitives are rendered.

[0085] In order for the vertex data to be available for rendering (e.g., for the domain shader 108 and the rasterizer 109), the vertex data generated by the tessellator 104 may be stored according to a tiled storage scheme. In a first example scheme, the vertex data may be stored in a list of primitives for each group (or tile) generated by the tiling unit 106, for example, where the primitives are output in the form of triplets of vertex UVs, and in another example scheme, the vertex data may be stored together and the list of primitives may include a reference to the data. Optionally, the vertex data (e.g., the contents of the buffer of vertex UVs in the memory 105) may be discarded (e.g., after the tiling unit 106), and only the primitive identifiers may be retained in the display list (and stored in the parameter memory 107). When the vertex data is needed (e.g., by the domain shader 108), the tessellation process may be rerun, and the data for those primitives that are not needed (e.g., for a particular display list) may be discarded or not generated at all. Storing vertex data (e.g., UV coordinates and, in some examples, additional vertex attributes) in display lists (and therefore in parameter memory 107) uses a lot of storage and bandwidth (e.g., between the GPU and system memory), so discarding the vertex data and then regenerating it saves storage and bandwidth; however, regenerating the vertex data by re-running tessellation on all primitives is inefficient.

[0086] A method of generating IDs for primitives output from a tessellation unit (alternatively, which may be referred to as a tessellator) is described herein, wherein these primitive IDs encode information about how the primitives were generated, rather than simply indicating the order in which the primitives were output from the tessellation unit. A tessellation unit (or tessellator) that implements the method is also described. Using the primitive IDs described herein, vertex data can be discarded and not stored in a display list (thereby saving storage and bandwidth) rather than re-running the tessellation, and the primitive IDs can be used to generate vertex data, such as in the tessellation unit or in separate dedicated hardware logic. Also described herein are methods of generating vertex data for primitives using their primitive IDs, and hardware that implements these methods, including methods that do not involve re-running a tessellation unit that performs a complete tessellation or performs tessellation for a single primitive.

[0087] The methods described herein may be implemented in hardware, for example in Figure 1B The improved GPU pipeline 101 is shown. Figure 1B As shown, the pipeline 101 includes a geometry processing stage 111A and a rasterization stage 111B. The geometry processing stage 111A includes a vertex shader 102 responsible for performing per-vertex calculations. Figure 1A As described above, the vertex shader 102 is unaware of the mesh topology, but only the current vertex that has been fed into it. The geometry processing stage 111A also includes an All Primitives Tessellator 112, a memory 115, a geometry-specific domain shader (DS) 113, and a tiling unit 116. There may be one or more optional hull shaders (not in the hull shader) between the vertex shader 102 and the All Primitives Tessellator 112. Figure 1B ).

[0088] Unlike the vertex shader 102, all primitive tessellators 112 (and any optional hull shaders) operate on a per-patch basis rather than a per-vertex basis.

[0089] The all-primitive tessellator 112 is configured to perform an initial full tessellation and generate primitives and their IDs and vertex data. In various examples, the all-primitive tessellator 112 outputs a list of primitives (e.g., in the form of a UV buffer and an index buffer using indices, or in the form of a primitive buffer of UV triplets if indices are not used). The all-primitive tessellator 112 also generates an ID buffer (matching the primitive order), and the primitive list and ID buffer may be stored in the memory 115.

[0090] The geometry-specific domain shader 113 in the improved GPU pipeline 101 generates the projected positions (i.e., screen coordinates) of the corners of the primitives. The tiling unit 116 then uses the projected positions (as generated by the geometry-specific domain shader 113) to determine which primitives are at least partially located in each tile and generates corresponding per-tile display lists. The primitive IDs or references to these IDs (depending on the tile storage scheme used) are stored in the corresponding display lists (e.g., in the parameter memory 117, i.e., the list of primitives that are partially visible in each tile), rather than in UV coordinates which can then be discarded. Primitive IDs are more compact than three UV coordinates, so this saves memory usage and bandwidth (so the size of the parameter memory 117 can be smaller than 100). Figure 1A The corresponding parameter memory 107 in the illustrated GPU pipeline 100 is much smaller, and such an arrangement would use less power.) References to patch control points (including tessellation factors) are also stored (eg, in parameter memory 117).

[0091] Despite the above description and Figure 1B The use of a geometry-specific domain shader 113 is shown to calculate the projected position of the new primitive in screen space (referred to as "screen coordinates"), but in other examples, a global shader (similar to the domain shader 108) may be used or alternative dedicated hardware may be used to perform these calculations of the screen coordinates of the primitives. In other examples that do not include a geometry-specific domain shader 113, hardware may be provided that is arranged to estimate the screen coordinates of the new primitive.

[0092] When a tile is to be rasterized (in the rasterization stage 111B), each primitive ID in the display list for the tile is transformed into a triplet of UV coordinates (which may be abbreviated as "UV triplet") using a single primitive tessellator 114. The single primitive tessellator 114 is configured to generate vertex data based on the input primitive ID, and although this is shown as part of the rasterization stage 111B (because this is where it is located in the data flow), it may be physically close to or integrated with all the primitive tessellators 112, for example so that logic can be reused between all the primitive tessellators 112 and the single primitive tessellator 114. The two tessellators 112, 114 are physically co-located or integrated together, and the two tessellators may be collectively referred to as an improved tessellating unit.

[0093] The domain shader 118 in the rasterization stage 111B acts as a second vertex shader for vertices generated by a single primitive tessellator 114 and is executed once per vertex per primitive per tile, although a cache can be used to enable reuse of shaded vertices. The domain shader 118 is provided with a domain space position (u, v) and is given all the fragment information and outputs a complete vertex structure. The domain shader constructs new vertices using the fragment control points and domain space coordinates and applies any displacement mapping (e.g., by sampling a height map encoded in a texture). Domain shading (in the domain shader 118) can be kept as late as possible in the GPU pipeline 101 because it greatly expands the vertex size (e.g., in terms of the number of bits of data per vertex). In the case where the domain shader 118 and the geometry-specific domain shader 113 are implemented separately, the size of the domain shader 118 can be larger than the geometry-specific domain shader 113 because it can also be configured to process other sideband data in addition to geometry data.

[0094] After the domain shader 118 has been run for each vertex generated by the individual primitive tessellators 114, the data for each tile is further processed in the rasterizer 119 and some or all of the primitives are rendered.

[0095] As described above, the method of generating primitive IDs and the method of generating vertex data based on the primitive IDs of primitives (e.g., a single primitive) described herein can be implemented in all primitive tessellators 112 and a single primitive tessellator 114, respectively, or in an improved tessellating unit that combines the functions of the two tessellators 112, 114.

[0096] Figure 1B The GPU pipeline 101 is shown as an example only, and the improved tessellation method described herein can be used in any GPU architecture. It will also be appreciated that all primitive tessellation devices 112 and / or a single primitive tessellation device 114 can be used in a GPU pipeline that includes other shaders in addition to the vertex shader 102, the optional shell shader, and the domain shader 118, or other shaders in place of the vertex shader 102, the optional shell shader, and the domain shader 118.

[0097] All primitive tessellators 112 and a single primitive tessellator 114 may be implemented in hardware. Alternatively, the methods described herein may be implemented in software (or a combination of software and hardware) and are described below with reference to Fig.11 Example computing-based devices that may be configured to implement the above-described tessellation methods are described.

[0098] Although not described above, vertex data may be stored in memory (e.g., in Figure 1A 105 and / or parameter memory 107, and in Figure 1B memory 115 and / or parameter memory 117) is compressed.

[0099] If you can refer to Figure 2A-2E and Figure 3A As described, the tessellation method may be recursive. Figure 2A An example triangle initial patch 202 is shown, and Figure 3A is a flow chart showing a method for tessellation. Figure 2A-2E In the example shown, the initial patch is a triangle patch, but in other examples, the initial patch can be a contour or a polygon with any number of edges. As mentioned above, a triangle patch is an ordered set of three vertices that define a domain, and in the examples described herein, this ordered set of vertices is written as (T, L, R), where T, L, and R refer to the top, left, and right vertices, respectively (e.g. Figure 2A In the methods described herein, a reference to a slice or sub-slice refers to an ordered set of vertices (ie, data representing the slice).

[0100] The tessellation of the initial patch 202 begins with an evaluation being made to determine whether tessellation of the initial patch 202 is required (block 302). This determination (in block 302) may be made using any suitable tessellation method (e.g., any tessellation method involving binary tessellation), and two examples of using vertex tessellation factors are described in GB2533443 and GB2533444 (although the method is applicable to quadrilateral patches rather than triangular patches). Alternatively, other tessellation methods may be used.

[0101] If it is determined that the initial slice does not need to be subdivided ("No" in block 302), the initial slice is output as a primitive (block 304). However, if it is determined that the initial slice needs to be subdivided ("Yes" in block 302), a left sub-slice 204L and a right sub-slice 204R are formed (block 306). This subdivision of the initial slice 202 may include adding intermediate vertices (indicated as M) on the edges between the left vertex and the right vertex (e.g., Figure 2B ), and in various examples, an intermediate vertex may be added at an intermediate point between the left vertex and the right vertex. The two patches 204L, 204R formed (in block 306) are both triangle patches and include an ordered set of three vertices: (M, R, T) and (M, T, L), and they may be referred to as the right sub-patch 204R and the left sub-patch 204L, respectively. As described above, although in Figure 2A-2E In the example shown, the initial patch is a triangular patch, but in other examples the initial patch may be a contour line or a polygon with any number of sides.

[0102] At the next stage of tessellation, use Figure 3A The method selects each of the sub-patches in turn to be further tessellated (block 308), such that Figure 3A Only when the first selected sub-patch of the initial sub-patch has been tessellated so that no further tessellation is required, the second of the sub-patch formed by the tessellation of the initial patch is selected (in block 308) and input to Figure 3A For example, if the right sub-slice 204R (from Figure 2B ) (in block 308), input to Figure 3A In the method of , and then further subdivided (in block 306), there are two sub-slices 206R and 206L (such as Figure 2C ), which in turn are selected (in block 308) to be input to Figure 3A If it is determined that the first of these (e.g., 206L) does not need to be subdivided ("No" in block 302), the next of these (e.g., 206R) is input to Figure 3A Once the sub-tile has been completely tessellated (to the desired degree), the method returns to the top level of the recursion, and the second of the sub-tiles formed from the initial tile (e.g., 204L) is input to Figure 3A , and the method is recursively applied to any sub-tiles formed from the sub-tile (e.g., sub-tiles 208L and 208R). The method continues until all sub-tiles formed from the initial tile have been evaluated and it has been determined that they do not need to be subdivided (“No” in block 302). The sub-tiles (and the initial tile if there is no subdivision) once output can be referred to as primitives because they do not require any further subdivision.

[0103] use Figure 3A In this approach, the tessellation method is recursively applied to each subdivision level of the initial patch before evaluating another branch of the subdivision tree, where one branch of the subdivision tree is fully subdivided, such as Figure 3C As shown, each branch represents a sub-slice, and the number on each branch indicates that the sub-slice is input to Figure 3A The sub-tiles that are output as primitives (in block 304) have Figure 3C Their sequence numbers are shown in bold.

[0104] Also like Figure 3C As shown, the order in which primitives are output by the tessellation unit (in block 304) depends on the order in which the sub-tiles are selected for evaluation (in block 308). Different criteria may be used to select a tile at each tessellation, or branching, point (in block 308), and Figure 4AAn example tessellation method is shown that alternates the order in which sub-tiles are processed within the tessellation unit for each tessellation level by specifically encoding the tile selection for each tessellation tile, and thus, adjacent primitives in the sorting are guaranteed to be adjacent primitives in UV space, sharing two vertices. This sorting of output primitives may be referred to as "improved sorting".

[0105] Figure 4A The illustrated method initially takes as input an initial patch, which may be, for example, a triangle patch 202, and performs an evaluation to determine whether tessellation of the initial patch 202 is required (block 302). This determination may be made using any suitable tessellation method (e.g., any tessellation method involving binary tessellation), and two examples of using vertex tessellation factors are described in GB2533443 and GB2533444.

[0106] If it is determined that the initial slice does not need to be subdivided ("No" in block 302), the initial slice is output as an image (block 304). However, if it is determined that the initial slice needs to be subdivided ("Yes" in block 302), left and right subslices are formed (block 306). This subdivision of the initial slice 202 may include adding intermediate vertices (indicated as M) on the edges between the left vertex and the right vertex (e.g. Figure 2B ), and in various examples, intermediate vertices may be added at intermediate points between the left and right vertices. The two sub-sheets 204L, 204R formed in the example shown (in block 306) are both triangle sheets and include an ordered set of three vertices: (M, R, T) and (M, T, L), but in other examples, they may be contour lines or have more than three edges, and they may be referred to as right sub-sheet 204R and left sub-sheet 204L, respectively.

[0107] One of the newly formed sub-slices (i.e., the left sub-slice 204L or the right sub-slice 204R formed in block 306) is then selected (in block 408) to be processed by inputting the selected sub-slice back into the Figure 4A The order of selection of the left or right sub-slice (in block 408) is based on the value of one or more flags, and two different examples of the use of flags are described below. In this way, before evaluating another branch of the subdivision tree (e.g., with Figure 3C but in which the order of selection at each branch point is determined by one or more flags), Figure 4A The method is recursively applied to each subdivision level of the initial patch, where one branch of the subdivision tree is completely subdivided.

[0108] In a first example, there is a flag (e.g., a single bit flag) for each tile (e.g., for each initial tile and for each sub-tile subsequently formed by tessellation). The per-tile flag determines whether the left sub-tile or the right sub-tile is selected first and is input back to the tessellation table when the tile is tessellated (i.e., when the initial tile is tessellated (in block 306)). Figure 4A In the method (in block 408), the flag associated with the initial patch determines the order of selections made in subsequent steps (in block 408). In such an example, this makes the triangle patch an ordered set of three vertices and a flag, for example, (T, L, R, F) or (T, L, R, ), where F and Represents two different flag values ​​(e.g., off and on, 1 and 0).

[0109] If the flag of the initial slice 202 (which was subdivided in block 306 as a result of the evaluation in block 302) has the first value of the flag (e.g., F), then the right sub-slice is selected first and is input back to Figure 4A In the method (in block 408), and only when it is not possible to further subdivide the right sub-slice, the left sub-slice is input back to Figure 4A However, if the flag of the initial slice 202 has another value (e.g. ), the left sub-piece is selected first and is input back to Figure 4A In the method (in block 408), and only when it is not possible to further subdivide the left sub-slice, the right sub-slice is input back to Figure 4A In such an example, when two child slices are generated by subdividing a parent slice (in block 306, where the parent slice may be an initial slice or a child slice formed from the initial slice), the values ​​of the flags for the two newly formed child slices are set to have opposite values ​​to those of the parent slice. Thus, if the initial slice is (T, L, R, F), the two child slices formed (in block 306) are (M, T, L, F). ) and (M, R, T, ). Similarly, if the initial slice is (T, L, R, ), the two sub-tiles formed (in block 306) are (M, T, LF) and (M, R, T, F).

[0110] In a second example, a single flag can be used in the tessellator, which switches state each time the recursion level decreases or increases by one. In this second example, if the single flag has a first value (e.g., F), the right sub-tile is selected first and input back to Figure 4A In the method (in block 408), and only when it is not possible to further subdivide the right sub-slice, the left sub-slice is input back to Figure 4AHowever, if a single flag has another value (e.g. ), first select the left sub-slice and input it back Figure 4A In the method (in block 408), and only when it is not possible to further subdivide the left sub-slice, the right sub-slice is input back to Figure 4A In this example, the exchange of flag values ​​may be performed, for example, after deciding to perform subdivision (eg, in response to “yes” in block 302 ) or after forming two sub-tiles (in block 306 ).

[0111] As described above, one of the two newly formed sub-slices 204R, 204L has been selected (in block 408), and the selected sub-slice is input back to Figure 4A and is tessellated until no further tessellation is possible, and this is a recursive process. The newly formed sub-piece (e.g., piece 204R) selected becomes Figure 4A The method of FIG. 204 is input to the sub-tile method, and determines whether the sub-tile should be subdivided (in block 302). If subdivision is not required ("No" in block 302), the selected newly formed sub-tile is output as a primitive (block 304), and the unselected newly formed sub-tile (e.g., tile 204L) is input to the Figure 4A method.

[0112] However, if the selected sub-tile (e.g., 204R) requires subdivision ("yes" in block 302), then left and right sub-tiles (206L, 206R) are formed from the selected sub-tile (block 306). Because the flags at this recursion level have been swapped (either as a result of the flags in sub-tile 204R being opposite to the flags in the initial tile 202, or because a single flag is swapped as part of the method of generating sub-tiles 204R, 204L), instead of first selecting the right sub-tile 206R (as was the case at the immediately previous recursion level that resulted in the selection of sub-tile 204R), the left sub-tile 206L is first selected (in block 408). If the selected sub-tile 206L does not require any subdivision, it is output as a primitive (in block 304), and the unselected sub-tile 206R is selected and evaluated (in block 302). Only when the tessellation of both sub-tiles 206L, 206R is complete, the unselected sub-tile 204L is input from the top layer of the tessellation to Figure 4A and is considered for segmentation (in block 302).

[0113] The output primitives (from block 304) take the form of three indices in a system that uses vertex indices, and take the form of three domain vertices in a system that does not use indices, and as detailed above, where the domain vertices may include only UV coordinates or may include UV coordinates plus other parameters (e.g., weights (such as displacement factors) and optionally parent UV coordinates).

[0114] like Figure 2D As shown, if the unselected sub-tile 204L requires subdivision ("yes" in block 302), two new sub-tiles 208L, 208R are formed. When selecting between sub-tiles 208L and 208R, the flag used to make the selection (in block 408) has the same value as when selecting between sub-tiles 206L and 206R, because both subdivisions occur at the same recursive / tessellation level, the left sub-tile 208L is selected first. If the selected sub-tile 208L does not require any subdivision, it is output (in block 304), and the unselected sub-tile 208R is selected and evaluated (in block 302).

[0115] If you use Figure 4A According to the method shown in the figure, using the specific encoding of the flag bit for sub-slice selection as described above, the initial slice 202 is subdivided into four sub-slices 206L, 206R, 208L, 208R, the sub-slices are generated, and the primitives are output in the following order: 206L, 206R, 208L, 208R, and Figure 2E This order is shown (with the output primitives labeled 0-3 in order).

[0116] Figure 5A and Figure 5B Schematic diagram showing two example primitive IDs 500, 501 generated using the method described herein. Figure 5A and Figure 5B As shown, primitive IDs 500, 501 include a sequence 502 of r bits, which specify the primitive IDs to be used in the tessellation process (e.g. Figure 3A or Figure 4A Each bit in sequence 502 indicates the recursive sequence used during any selection operation (e.g., Figure 3A Block 308 or Figure 4A 408 in block 408), whether the patch from which the primitive is formed is first selected for tessellation (e.g., indicated by 0) or not selected (e.g., indicated by 1). Thus, each bit indicates whether the patch from which the primitive is formed is the first to be tessellated or the second to be tessellated, and this can also be described by a branching algorithm, where the sequence of bits 502 indicates whether the first branch is taken (i.e., the patch is first selected for tessellation in block 408) or the second branch is taken (i.e., the patch is selected for tessellation a second time in block 408).

[0117] In addition to the sequence 502 of r bits that specify the recursive sequence employed during the tessellation process, the primitive IDs 500, 501 may include one or more additional bits or sequences of bits. Figure 5A The first example 500 shown includes a header portion 504 and a trailer portion 506, but in other examples, the primitive ID may include only one of the header portion 504 and the trailer portion 506, or may include neither the header portion 504 nor the trailer portion 506, and / or may include other portions. Figure 5B The second example 501 in FIG. 5 , which is shown as including only the tail portion, may include the header portion or may not include the tail portion.

[0118] In a tessellation method, in which an input triangle, quadrilateral or polygonal patch is tessellated in a preprocessing step prior to tessellation (e.g., such that the input triangle, quadrilateral or polygonal patch is divided into a plurality of initial patches, each of which is then input to Figure 3A or Figure 4A In a tessellation method of the invention, the primitive ID 500 may include a header portion 504, the header portion 504 including one or more bits (e.g., 2 bits) indicating the primitive in (e.g., Fig.14A and 14B Which of those initial patches (as shown and formed from the input triangle / quad / polygon patches as described above) is used.

[0119] In various examples, the primitive ID may include a tail portion 506 that is used to provide a fixed length primitive ID 500, 501. Without such a tail portion 506, the length of the primitive ID 500, 501 would depend on the length of the recursive sequence (i.e., the value of r), and this could lead to ambiguity if the IDs were concatenated (e.g., because the encodings are not prefix-free, where the term "prefix-free" refers to the fact that there are encoding pairs c, d where c is a prefix of d, and thus the parser cannot determine whether they have reached the end of encoding c or in the middle of encoding d). By including a variable length tail portion 506, the length of the primitive ID is fixed regardless of the value of r, and the tail portion may include a predefined bit sequence (e.g., such as Figure 5A and Figure 5B As shown in the example in , a single 1 is followed by zero or more 0s), which enables the tail portion 506 to be identified and distinguished from the sequence of bits 502 that specifies the recursive sequence employed.

[0120] like Figure 6 As shown, in order to generate a primitive ID, each time a sub-slice is formed ("Yes" in block 602, for example, Figure 3A or Figure 4A ), it inherits the primitive ID of its parent tile (block 604), and each time a child tile selection occurs ("yes" in block 606, e.g. Figure 3A Block 308 or Figure 4A 408), another set of bits (e.g., one or more bits) is appended to the sequence 502 of bits specifying the recursive sequence employed (block 608). This addition of new bits to the sequence 502 (in block 608) may result in the removal of one or more bits from the tail portion 506 (if provided), or alternatively, in the case where the tail portion 506 is provided, the bits may be added to the sequence 502 in the manner specified in the recursive sequence employed. Figure 6 After the recursive sequence 502 is generated by the method, the tail portion 506 is added.

[0121] Although Figure 6 The method is similar to the surface subdivision method (such as Figure 3A and Figure 4A ) are shown separately, but it will be appreciated that the two methods may be implemented together, such that the initial generation of primitive IDs for newly formed sub-tiles matching their parent tile IDs (in block 604) may be implemented as part of the process for subdividing the initial tile or sub-tiles (e.g., in Figure 3A or Figure 4A ), and the update of the ID may be implemented as part of the sub-slice selection operation (e.g., in Figure 3A In block 308 or in Figure 4A 408 of FIG. 10 ).

[0122] like Figure 5A As shown, for quadrilateral or triangular domains (i.e., for primitives formed from input triangles or quadrilateral patches that are subdivided into multiple initial patches), the size of the ID can be fixed at 2T+2 bits by using a variable length tail portion 506, where T is a predefined fixed value (non-zero) and, in various examples, can be greater than or equal to the maximum tessellation factor (e.g., maximum vertex TF) that can be used for tessellation (i.e., so that the codebook has enough elements to encode all possible primitives). It will be appreciated that in the event that the header portion 504 is omitted or is not equal to 2 bits in length, this will change the size of the ID, for example to 2T+h bits, where h is the number of bits in the optional header portion 504 (which, as described above, can encode the initial domain subdivision), or more generally to h+bR+1 bits, where b is the number of bits added at each recursion level, and R is the maximum number of recursion levels (and in the examples described herein, h=2, b=1 and R=2T-1).

[0123] In the example where T is equal to the maximum TF, the length of the primitive ID is minimal (and the codebook can be minimal), so this provides an efficient implementation, as shown in the following table:

[0124]

[0125] In the examples described herein, the maximum TF and all tessellation factors are considered to be logarithms to base 2.

[0126] As described above, for a triangle, quadrilateral, or polygon domain, where the input patch is pre-processed to subdivide it into 3, 4, or more initial patches prior to tessellation, the primitive ID 500 may include a header portion 504 that identifies which of those initial patches the primitive is in. For a contour domain or other situations where the input patch is not pre-processed, the primitive ID may have a value such as Figure 5B . This example ID 501 omits the header portion 504. In such an example and for contour domains (where the tessellation level is half of that of a quadrilateral or triangle domain), the size of the ID can be fixed at T+1 bits by using a variable length tail portion 506, as described above, where T is a predefined fixed value (non-zero) and, in various examples, can be greater than or equal to the maximum tessellation factor (e.g., maximum vertex TF) that can be used for tessellation. Again, it can be shown that in the example where T is equal to the maximum TF, the length of the primitive ID is minimized, so this provides an efficient implementation, as shown in the following table:

[0127] domain Maximum number of primitives inequality least bit Unused encoding Contour lines <![CDATA[2 T+1 -1]]> <![CDATA[2 T <2 T+1 -1<2 T+1 ]]> T+1 0...0

[0128] When primitive IDs are output in the same order as their associated primitives were generated by the recursive algorithm of the tessellator, and where bit 0 corresponds to the first sub-tile processed and bit 1 corresponds to the second sub-tile processed, the primitive IDs are output in lexicographical order. Thus, finding where in the buffer a primitive with a particular ID is or is present in the buffer can be performed efficiently. This is also the case if more than 1 bit is appended to the sequence at each tessellation step, as long as the order in which the sub-tiles are selected matches the lexicographically ordered appended bits. Furthermore, the differences between adjacent IDs are typically small, and this can be used to efficiently compress blocks of IDs in memory.

[0129] Although the method of generating IDs is described above in conjunction with the surface tessellation method using binary tessellation (e.g., Figure 3A and Figure 4A ), but the method described herein can also be used when a slice is subdivided into more than two sub-slices (for example, into four sub-slices or X sub-slices, where X can generally be a power of 2). Figure 3B Shown as Figure 3A Another tessellation method which is a variation of the method shown (as described above), and Figure 4B Shown as Figure 4A Another tessellation method that is a variation of the method shown (described above).

[0130] exist Figure 3B In the method shown, if subdivision is required ("yes" in block 302), the initial patch or a sub-patch in a subsequent recursive level is subdivided into two or more sub-patches (block 306', e.g., subdivided into X sub-patches). Each of the sub-patches is then selected in turn (in block 308) to be fed as input into the method (i.e., fed into block 302), and the method is repeated until all sub-patches formed (in block 306') have been selected and tessellated until no further subdivisions are required.

[0131] exist Figure 4B In the illustrated method, if subdivision is required ("yes" in block 302), the initial slice or a sub-slice in a subsequent recursive level is subdivided into two or more sub-slices (block 306', e.g., subdivided into X sub-slices). Each of the sub-slices is then selected in turn, where the order of selection is based on the value of one or more flags (block 408), which are fed to Figure 4B and is tessellated until there are no further subdivisions.

[0132] The order in which the sub-tiles are selected (in block 408) is based on the values ​​of more than one flag. More generally, the values ​​of the one or more flags can be considered to encode the order in which the sub-tiles are tessellated from the input tile (in block 306'), and each sub-tile can be tessellated in turn (by selecting the sub-tile as the input tile). Figure 4B ) until there are no further subdivisions based on the ordering encoded by the values ​​of one or more flags.

[0133] As above reference Figure 4A As described, each initial slice (and sub-slice once formed) may have associated flags, and the values ​​of these flags may be used when selecting a sub-slice (in block 408). In examples where each sub-slice does not have an associated flag (as in the second flag example described above), and where the input slice is subdivided into X sub-slices, one or more flags may include a small stack of integers (with one entry for each recursive level) storing the number of sub-slices formed at each subdivision level, such as a value for a particular subdivision level X, where the value may be different for different levels.

[0134] If a new subdivision of a slice (e.g., an initial slice or a subslice) into X subslices occurs, the value X is pushed onto the stack. Each time no subdivision occurs, the topmost value on the stack is decremented by 1. If the value of the topmost short end on the stack reaches zero, it is popped from the stack. The subdivision level is then given by the number of elements in the stack, and the order of subslice selection (in block 408) can be determined as a function of this level.

[0135] In an alternative, if a new subdivision of the slice into X sub-slices occurs, the value X-1 is pushed onto the stack. Each time a slice / sub-slice subdivision does not occur and a primitive is output, the topmost value on the stack is decremented by 1, unless the value is 0, in which case it is popped from the stack. If when a value is popped from the stack, the next value is also 0, it is also popped from the stack. When the stack is empty, the process terminates. The subdivision level is then derived from the number of elements in the stack, and the order of sub-slice selection (in block 408) can be determined as a function of this level. This alternative has only X possible values ​​per entry, rather than X+1 as in the previous scheme, which means that each entry can be encoded with fewer bits.

[0136] use Figure 3B or Figure 4B , and where X is a power of 2, from Figure 2A-2E Two or more subdivision levels of the method may, for example, be performed in one subdivision step (eg, in one slice before the next slice selection occurs).

[0137] In the case where the tessellation method subdivides the initial patch or sub-patch into more than two sub-patches (e.g., Figure 3B and Figure 4B The same principle can be used to generate primitive IDs, where a new bit is added to the bit sequence each time a sub-tile selection occurs (e.g., Figure 6 For example, when subdividing into a power of 2 number of sub-tiles (e.g., 8 sub-tiles), a plurality of bits (e.g., 3 bits) are added to the end of the primitive ID each time a subdivision occurs, wherein the added bits indicate the position of the sub-tile in the processing order (e.g., 3 bits indicate whether the sub-tile is processed first, second, ..., or eighth). Figure 6 The method can be used for any tessellation method involving recursive subdivision of patches, regardless of the number of branches at any level. The number of branches does not have to be a power of 2, but when binary encoding is used, the process is most efficient for powers of 2.

[0138] In the example where no tessellation occurs, i.e., the initial patch is not tessellated and only a single primitive is output, any unused primitive ID can be assigned to that primitive (e.g., any primitive ID that begins with 11). By using special primitive IDs in this way, a primitive can always be identified as a special case, and its vertex IDs can also be generated as special cases based on the primitive ID (e.g., 000...0, 010...0, and 100...0).

[0139] The methods described herein may also be used for other tessellation methods that do not use recursive tessellation, for example, where the tessellation method is iterative rather than recursive, such as in DirectX and OpenGL (as described on pages 313-321 of the OpenGL specification, https: / / www.khronos.org / registry / OpenGL / specs / es / 3.2 / es_spec_3.2.pdf). In such examples, the sequence of r bits 502 does not specify the recursive sequence employed during the tessellation process, but still encodes the sequence of subdivisions employed during the tessellation process. For example, if the tessellation method first divides a quadrilateral domain into rows and then into columns, and then subdivides each quadrilateral sub-piece formed by the row-column division into two triangles (e.g., top left and bottom right), then for a particular triangle primitive, the sequence of r bits 502 may encode the row it is in, the column it is in, and whether it is a top left primitive or a bottom right primitive. The header portion may additionally indicate whether the primitive is an edge primitive (i.e., at the edge of a quadrilateral domain) or an internal primitive (i.e., not at the edge of a quadrilateral domain). Edge primitives may be encoded by ID as an ordered list, or one portion of the encoding may be used to indicate which edge of the domain the edge primitive is adjacent to, and another portion of the encoding may be used to indicate its position along that edge.

[0140] By using a primitive ID comprising an r-bit sequence 502 that specifies a sequence of tessellations (e.g., a recursive sequence employed) during the tessellation process (as described above), the primitive ID can be used to efficiently generate vertex data (e.g., UVs) for the primitive without completely re-tessellizing the entire input or initial patch, thereby eliminating the need to store all domain vertex data as well as the primitive ID, thereby saving memory.

[0141] In various examples, the ID may be input to a method that performs tessellation, such as Figure 3A , Figure 3B , Figure 4A or Figure 4B ) of the surface subdivision unit (as shown in Figure 1BAs shown, the vertex data for the primitives may be generated according to the primitive ID in a simplified version of a single primitive tessellator 114, but as shown in FIG. Figure 7 As shown, the decision about each subdivision branch (for example, in Figure 3A and Figure 3B In block 308, Figure 4A and Figure 4B The vertex data for a primitive may be generated in a similar manner based on the primitive ID, where the tessellation method used is not recursive, but an iterative process (as described above).

[0142] In such an example, the method (such as Figure 7 ) includes: receiving an ID and a patch reference of a primitive in a tessellation unit (block 701), wherein the primitive has been previously tessellated (e.g., as described above). The patch reference may identify data associated with the patch, such as patch control points, tessellation factors, and domain topology. The patch reference may be stored for each primitive (e.g., associated with or stored with the primitive ID), or a single patch reference may be stored for multiple primitives formed from the same patch (e.g., all primitives from the same patch within the same tile) to save space. The method also includes: accessing data from the patch associated with the primitive using the received patch reference (block 702), selecting an input patch using the domain topology for the patch associated with the primitive (block 703), performing any necessary preprocessing on the input patch to produce one or more initial patches (block 704), and selecting an initial patch (from those formed in block 704) based on the primitive ID (block 705). The header portion 504 (e.g., Figure 5A The method then includes tessellizing the selected initial patch (block 706), wherein at each stage of the tessellation, based on a sequence of one or more bits in the primitive ID, it is determined whether to perform tessellation and which of any newly formed sub-patches to further tessellate. Figure 7 The vertex data output by the method (block 708) includes a plurality of domain vertices (e.g., two, three, or more domain vertices), where, as described above, each domain vertex may include only UV coordinates, or may include UV coordinates plus other parameters (e.g., a displacement factor and, optionally, a parent UV coordinate).

[0143] However, in other examples, an iterative process (regardless of whether the tessellation process used to generate the primitive ID is iterative or recursive) may be used to generate vertex data for the primitive based on the primitive ID, and Fig. 8A and Figure 8BTwo examples are shown in Figure 2. Fig. 8A and Figure 8B The method shown and Figure 1B The method is implemented in the illustrated rasterization stage 111B. Part of the illustrated method may be implemented within a dedicated single primitive tessellator 114 (e.g., the functions π, γ, z, and similarly z' followed by ρ may be implemented in hardware logic within the dedicated single primitive tessellator 114), and the final part of the method may be implemented within the domain shader 118 (e.g., as in Fig. 8A and Figure 8B DS, DS (and mixtures) marked in.

[0144] described above and using Figure 6 The primitive IDs generated by the method can also be used to provide vertex IDs for each domain vertex. In the subdivision algorithm, each subdivided initial slice (e.g., (T, L, R)) creates a new vertex M (e.g., Figure 2B ), and similarly, each subdivided sub-tile (e.g., (T,L,R)) creates a new vertex M. The ID of the primitive given by (T,L,R) can also be assigned to vertex M. When the primitive ID encodes the sequence of branches that reach the primitive, it also encodes the sequence of branches that reach vertex M. Since subdivision does not occur on the smallest primitive, each vertex ID requires one less bit than the primitive ID, so a single bit can be saved (i.e., 2T+1 bits for quad / triangle domains and T bits for contour domains). For example, these vertex IDs may be used to randomly regenerate a single vertex in a manner similar to the way that vertex data for a primitive is generated using the primitive ID, e.g., by inputting the vertex ID to a tessellation unit (e.g., to a single primitive tessellator 114), and following the same branching sequence through the tessellator as was originally followed when generating the vertex; however, the method for generating a primitive according to its primitive ID is modified by performing a final tessellation on the generated primitive between its left and right vertices (to generate vertex M), and this is the desired vertex. In examples where more than one new vertex is generated by tessellation of an initial patch or sub-patch, the ID of the newly added vertex M is then given by appending one or more bits to the end of the primitive ID given by the patch that was tessellated to generate vertex M.

[0145] This method of encoding vertices as vertex IDs does not include domain vertices that were not generated by subdivision of the initial slice or subslice, e.g. Fig.14A and Fig. 14B, and the corner vertices and intermediate vertices 1416, 1418 shown in FIG. However, because the codes 000...0, 010...0, 100...0, 110...0 are not used for the 2D domain, and 000...0 is not used for the contour domain, these codes can be assigned to the corner vertices and the leftmost vertex in a clockwise manner, respectively (e.g., assigned to UV coordinates (0, 0), (1, 0), (1, 1), and (0, 1)). This will reserve the intermediate vertices for the 2D domain and the right vertex in the contour domain. For the quadrilateral domain and the contour domain, an additional bit is required to assign the new code. In various examples, codes given by a single 1 followed by (2T+1 or T) 0s can be used, indicated by 1000...0 and 10...0, respectively. For the triangle domain, the code 110...0 can be used for the intermediate vertices. These codes make the IDs of the intermediate vertices for the 2D domain and the IDs of the right vertices for the contour domain the last vertices when the vertex IDs are arranged in lexicographic order. In general, unused codes can be assigned to the input slices by preprocessing (e.g. Fig.14A and Fig. 14B vertices generated by the subdivision of the initial slice or subslice (as shown) instead of by the subdivision of the initial slice or subslice. These small number of vertex / ID pairs can be treated as special cases when assigning IDs or regenerating domain vertices based on IDs. Including these special vertices, one extra bit is required to store each possible encoding for the quad domain and contour domain (i.e., 2T+2 bits for the quad domain and T+1 bits for the contour domain), so every encoding except the middle vertex of the quad domain and the right vertex of the contour domain is preceded by a 0.

[0146] Vertex IDs generated in the above manner are usually not unique. Fig.14A and Fig. 14B The quadrilateral / triangular domain shown and Figure 2A-2E The tessellation of the initial patch and sub-patch is shown. Some vertex IDs are not unique: any non-border, non-intermediate vertex is generated twice by the tessellator because the tessellated edge is shared by two triangle patches, so there are two possible branching sequences to reach it, so these vertices have two different vertex IDs; however, any ID can be used to generate the vertex data. Vertices with two IDs can be divided into two types, vertices that are inside the initial triangle patch and vertices that are on the diagonal between the two initial triangle patches.

[0147] Fig. 8A A flow chart of a first example method for generating vertex data for a primitive according to the primitive ID of the primitive is shown. Fig. 8AAs shown, the method of generating vertex data for a primitive based on its primitive ID also takes as input up to three displacement factors (DF), one for each vertex of a triangle patch, where these DFs can be stored, for example, together with the primitive ID. Fig. 8A The input of 3 DFs is shown, but in various examples, less than 3 DFs may be input, and the DF of any vertex that does not receive a DF may be set equal to 1. The use of displacement factors is described in UK Patent Application No. 1509762.9 filed on June 5, 2015, and published under publication number GB2539042. As described in the patent application, a displacement factor is a parameter that is used with the domain space (UV) coordinates of a vertex in a primitive to generate one or more world space vertex parameters (e.g., position, normal, and tangent) for each vertex of the primitive. The displacement factor of a vertex may be calculated using the vertex TF of one or more vertices (e.g., a parent vertex). The displacement factors may be defined so that they have values ​​between 0 and 1 (i.e., they have values ​​in [0, 1]), and the value of the displacement factor for a vertex varies depending on the "age" of the vertex. To avoid visual artifacts (e.g., popping), the displacement factor used for a vertex is zero when the vertex is first introduced (e.g., at a particular level of detail), the displacement factor increases (as the level of detail increases), and is one before the vertex becomes a parent vertex (as the level of detail increases further). More generally, the displacement factor can use any range of values, where the value of the displacement factor varies depending on the age of the vertex, with one extreme value when the vertex is added and another extreme value before the vertex becomes a parent vertex.

[0148] like Fig. 8A As shown, vertex data is generated based on the primitive ID and three DFs by first generating the IDs of three vertices (top, right, and left) based on the primitive ID using a first function π (described below, arrow 802). A second function γ (described below, arrow 804) is used to generate two parent vertex IDs of the vertex, and then a third function z (described below, arrow 806) is used to map the vertex ID to the vertex UV. The vertex is then submitted (arrow 808) to a domain shader (e.g., Figure 1B Domain shader 118 shown), and for a triangle domain, as Fig. 9C As shown and described below, this involves using the function For a vertex, if its DF is less than 1, the function γ is applied, and the resulting vertex is then shaded and blended in the domain shader (e.g., where the blending step can be an interpolation between two values ​​(the average of the child and the parent) with the weight given by the DF). Any vertex with a DF of 1 can skip the use of the function γ and can be shaded without blending.

[0149] Figure 8B FIG. 4 is a flow chart showing a second example method for generating vertex data for a primitive according to the primitive ID of the primitive. Figure 8B As shown, the method for generating vertex data for a primitive based on its primitive ID also uses up to three displacement factors (DF) as input, including one DF for each vertex of the input slice, DF not equal to 1, wherein these DFs can be stored, for example, together with the primitive ID. As mentioned above, the use of displacement factors is described in the British patent application publication No. GB2539042.

[0150] like Figure 8B As shown, vertex data is generated based on a primitive ID and up to three DFs by first generating UVs for three vertices (top, right, and left) based on the primitive ID using a first function z' (described below, arrow 812). Then, a second function p (described below, arrow 814) is used to generate the two parent vertex UVs for any associated vertices. The vertices are then Fig. 8A The first method is shown in the same manner as the first method and is submitted (arrow 808) to the domain shader (e.g., Figure 1B Domain shader 118 shown) (similarly for a triangle domain, such as Fig. 9C As shown and described below, this involves using the function As above, if DF < 1, the function ρ is used, and the resulting vertex is shaded and blended in the domain shader (e.g., where the blending step can be an interpolation between two values ​​(the average of the child and the parent) with the weight given by DF), and any vertex with DF 1 can skip the use of ρ and can be shaded without blending.

[0151] It will be recognized that although Fig. 8A and Figure 8B The methods are shown for triangle primitives, but they can also be used for contour domains (e.g., where only two vertices are generated, and therefore only two input DFs are required). Fig. 8A Three DFs are shown in FIG. 1 , but as a space optimization, less than three DFs may be stored. In the example, only two DFs are stored per primitive (eg, Figure 8BAs shown), since one of the vertices (e.g., the left or right vertex) is the parent of the top vertex, the displacement factor is 1. Which vertex has DF=1 can be determined based on the vertex ID or by storing a flag bit (e.g., by looking at the number of trailing zeros: if the top vertex T has a body of T bits, then one of the L and R vertices will have a body of T-1 bits. The parent of T is the other vertex, namely the vertex that does not have a body of T-1 bits). Similarly, for the contour domain, only a single DF can be stored, e.g., for the vertex with the smallest number of trailing zeros in its vertex ID, since this will be the child vertex.

[0152] Fig. 8A and Figure 8B The size of each data structure is shown, where T refers to the maximum TF (as above). The values ​​shown are related to quadrilateral domains. For triangular domains (regardless of whether using Fig. 8A The method is still Figure 8B ), requiring two extra bits for each vertex UV. For the contour domain, only T bits are needed for the vertex ID (as described above), and only half as many bits are needed for the vertex UV.

[0153] Can be used Fig. 8A and Figure 8B Instead of any method Figure 7 By using Figure 8B Instead of Fig. 8A The approach has fewer stages and the computation is moved out of the ID space faster, which may be beneficial in some applications, while Fig. 8A In the approach of , the calculations are performed in ID space and subsequently moved to UV space, and this can lead to a more compact solution (e.g., 1 bit per vertex). The choice between methods may be implementation specific, for example, because it may depend on which other processes in the system require UVs and when they are needed.

[0154] exist Fig. 8A and Figure 8B In the following description of the functions used in the method, a tessellation method that results in improved primitive ordering is assumed (such as Figure 4A and Figure 4B ) is used to generate primitive IDs. If another tessellation method is used, Fig. 8A and Figure 8B The methods of still apply, and at a high level, the functions operate in the same or similar manner (eg, the first function and the second function still truncate the primitive ID), however, the exact form of the functions will be different.

[0155] exist Fig. 8AIn the method, a first function π is used to generate IDs of three vertices (top, right, and left) from a primitive ID, and the first function involves truncating the primitive ID at three different locations. The first function π consists of two functions: γ', which is an ordered version of the second function γ applied to the primitive ID (as described below, and which includes truncations of vertex IDs at two different locations) and τ (which involves a single truncation of the primitive ID). The ordered version of γ is used because a primitive contains an ordered set of three vertices, so the first function π needs to generate the top, right, and left vertex IDs in the correct order to avoid generating primitives with incorrect orientations. When truncating a primitive ID, truncating n bits from the ID (or a portion thereof) is equivalent to stepping back the subdivision hierarchy by n steps.

[0156] Back to reference Figure 2A and Figure 2B , M has a vertex ID equal to the primitive ID of the primitive 202 it subdivides, so the left and right vertices (L and R) are the parents of M. This can be determined using a function γ', which steps back the subdivision hierarchy two steps to produce the first parent vertex, and steps back another number S steps (S>2) to produce the second parent vertex. The value of S is determined by the primitive ID (which is equivalent to the vertex ID of M). The function is described in the table below. The function τ generates a vertex ID corresponding to the top vertex (T) of the primitive based on the primitive ID. If a previous subdivision occurred, the top vertex (T) is the value of M from the previous subdivision, so its ID can be determined by truncation of the primitive ID. A special case is if the number of subdivision steps r is 0, in which case the primitive is the initial slice and the ID of its top vertex is 1000...0. If r>0, the primitive ID is truncated by 1 bit, for example, the last bit in the sequence 502 of r bits is removed from the sequence (for example, when using Figure 5A In the case of a tail portion 506 of the form shown, the bits before the last 1 in the ID) and the additional bits (if provided) are included in the tail portion 506. If using Figure 5A The tail portion 506 of the form shown thus includes setting the bit before the last 1 in the ID to 1 and replacing the last 1 in the ID with 0.

[0157] exist Fig. 8A In the method, the second function γ is used to generate the two parent vertex IDs of the vertex, and as Fig. 8AAs shown, it is implemented as part of the first function π (in its ordered version), and then at most three times (e.g., once for each of the top, right, and left vertices generated using the first function). As described above, this second function backs up the subdivision hierarchy two steps to produce the first parent vertex ID, and backs up the hierarchy another number S steps (S>2) to produce the second parent vertex ID, where the value of S is determined by the vertex ID of the current vertex. Assuming that for vertices with DF=1, no blending is performed (as described above), no parent vertex is required, so the second function γ can be omitted for such vertices (e.g., Fig. 8A Thus, this second function γ (and its ordered version γ′) includes truncation of primitive IDs at two different positions for all vertices except for special cases (e.g., those involving intermediate vertices or corner vertices), and can be expressed as Fig.15 The definitions set out in the table shown (where rows 1-6 refer to special cases) are defined using the following notation:

[0158] 1000...0 middle vertex

[0159] a0a10...0 Angle vertex

[0160] 10...0 Vertex ID tail

[0161] 0...0 zero or more zeros

[0162] 1...1 zero or more 1s

[0163] 0...1 empty string or 01...1

[0164] 1...0 empty string or 10...0

[0165] For example, a0a1011...110...0 and the parent ID a0a10...110...0 represent any of the following mappings of child IDs to parent IDs:

[0166] a0a10110...0→a0a110...0

[0167] a0a101110...0→a0a1010...0

[0168] a0a1011110...0→a0a10110...0

[0169] a0a10111110...0→a0a101110...0

[0170] Fig.15 The table also has the values ​​a′0, a′1, s, R, L, T, P + , P- , P r-1 as well as Its definition is as follows:

[0171] ·2a′0+a′1≡2a0+a1+1(mod 4);

[0172] s is the element ID, where a i The bits correspond to the header portion 504, b i The bits correspond to the sequence of r bits indicating the recursive sequence 502, and the bits 10...0 correspond to the tail portion 506;

[0173] R, L, and T refer to the right, left, and top vertices of the initial slice of vertex M in its domain, which are represented by a i Position decision (such as Figure 2A , Fig. 9A and Fig. 9B ), which means that R and L are the corner vertices of the domain, and T is the middle vertex of the domain;

[0174] ·P + and P - Yes Fig. 9A The two parent vertices shown. + and P - corresponding to the left and right vertices of the triangle patch 901 subdivided by adding the vertex M; and

[0175] ·P r-1 is the parent vertex produced by going two steps back in the subdivision hierarchy;

[0176] · is the parent vertex produced by walking back S steps in the subdivision hierarchy, where the value of S is encoded in the vertex ID.

[0177] Although the codomain of γ consists of unordered pairs, the cases with different orders are separated in the table above to highlight (P _ ,P + ) can be equal to (P p* ,P r-1 )or , so we can define an ordered version of γ γ'. This ordered version of γ γ' can be used to define the first function π (as described above).

[0178] In the example, if T=3 (so 2T+1=7), then for the vertex with ID 1000101 (=69), this gives:

[0179] r=4,r-1=3,b r-1 =0

[0180] p * =2, b p* =i

[0181] So the parent vertex ID is as follows:

[0182] (P - , P +}={P p* , P r-1}={1001000,1000100}={72,68}

[0183] exist Fig. 8A In the method, the third function z is used to map the vertex ID to the vertex UV, and as Fig. 8A As shown, it is executed multiple times, for example, when two DFs are stored, it can be up to seven times: once for each vertex ID generated using the second function (two sets of three vertices, one child vertex plus two parent vertices), and once for vertices with DF=1 (and no parent vertex generated for them). However, at most five unique vertex IDs are generated, so fewer runs of function z can be achieved by reusing the results. The third function z generates the vertex UV from the vertex ID by starting with a fixed complex value, forming a sequence of (complex) scaled versions of this value for each bit of the ID, and then adding all of these values. A final scaling and translation is performed to generate the vertex UV.

[0184] For a quadrilateral domain and a code consisting of 2T+1 bits s=a0a1b0...b r-1 10...0 gives the non-corner, non-intermediate vertex ID. The complex form of the result of the third function (and the UV coordinate M of the vertex) is:

[0185]

[0186]

[0187] z j is defined as the jth term of z and is given by:

[0188]

[0189] like Fig. 9A As shown, for a code a0a1b0...b with 2T+2 bits r-1 10...0 gives the primitive ID, and the UV coordinates of its vertices T, R, and L are given by the following formula:

[0190] (T, R, L) = (Mz r-1 , M-iz r-1 ,M+iz r-1 )

[0191] In the expression given above:

[0192] 2 T-1 is a global scaling that ensures that the coordinates are Gaussian integers

[0193] (1+i) is to about 2 T-1 Global translation of the center coordinates of (1+i)

[0194] is the rotation of the initial triangle patch (-i, 1, i or -1) encoded in a0 and a1

[0195] is the relative position of the jth new vertex with respect to the (j-1)th vertex, where j=-1 gives the vertex of the subdivided initial triangle patch, and j=0,1,...r-1 gives the vertex of the subdivided triangle patch by b j The vertex of the determined sub-piece. The magnitude of the relative position of the new vertex relative to the previous vertex is scaled The relative directions are:

[0196]

[0197] like Fig. 9B As shown, position b k Choose to multiply by μ or Thereby reversing the direction and rotating 2π / 8 clockwise or counterclockwise.

[0198] For a triangular domain, vertices can be generated in the same way as for a quadrilateral domain, and then the coordinates can be transformed back into the triangular domain by using a transformation function. An example transformation function is the function

[0199]

[0200]

[0201] Wherein, A, B, C and A', B', C' are three triangular regions in the triangular domain 902 and the quadrilateral domain 903 respectively, (u, v) are UV coordinates (wherein, z(s) = M = u + iv), and Fig. 9C The transformation is graphically shown in . In other examples, different transformation functions may be used.

[0202] For the contour domain and the encoding s=b0...b by T bits r-1 10...0 gives the vertex ID, where b r =1,b r+1 =…=b T-1= 0, the coordinates of its vertex M are considered as binary expansion and are given by:

[0203]

[0204] For a code b0...b consisting of up to T bits r-1 10...0 gives the primitive ID, whose vertices L and R are given by:

[0205] (L, R) = (M-2 T-1-r , M+2 T-1-r )

[0206] exist Figure 8B In the method, the first function z' is used to generate the UVs of the three vertices (top, right and left) of the primitive according to the primitive ID of the primitive. This function is the above Fig. 8A A modified version of the third function z (arrow 806) in the method of . As described above, function z generates a vertex UV from a vertex ID by starting with a fixed complex value, forming a sequence of (complex) scaled versions of that value for each bit of the ID, and then adding all of these values. Figure 8B In the method, a modified version of the function z' generates three UVs based on a single primitive ID, and therefore includes an additional stage where the three vertex UVs are generated by translation of a single UV. This can be seen in Fig. 9A The primitive ID corresponds to the ID of the middle vertex M, so the vertex UV for M has been generated and can be removed by canceling the last step of the tessellation (translation -z r-1 ) to get the UV of the top vertex, and then you can get the UV of the top vertex by adding z r-1 Rotate i and -i respectively to get the UV of the left and right vertices by translation.

[0207] The function z or its modified version z' can be generated recursively. The expression for z is described in detail in equations (1)-(3) above. T-1 ·w(b0...b r-1 10...0) to calculate z(s), and then calculate:

[0208]

[0209] For 2 T-1 ·w(b0...b r-1 The recursive expression for (n)2 = n(mod 2) is as follows:

[0210] S -1 =w -1 =2 T-1

[0211]

[0212] S j =S j-1 +w j

[0213] 2 T-1 ·w(b o ...b r-1 10...0)=S r-1

[0214] By multiplying by 2 T-1 , ensuring that all w j and S j All in the collection {-2 T-1 ,...,0,...,2 T-1} 2 In the example above, we can use the Gaussian integers. b =2(b+1)2-1) to derive the recursive expression:

[0215]

[0216] Fig. 10A An example iterative implementation of the above recursive expression is shown. A single output 1001 is required for the original function z, and three outputs 1002 are required for the modified version of the function z'.

[0217] exist Figure 8B In the method, the second function ρ is used to generate the two parent vertex UVs of the vertex, and is executed for each vertex with DF < 1. The following table shows the equations that define the mapping of this function for a quadrilateral domain. They are generated based on the following characteristics. First, after generating one of the parent UVs, the child UVs are generated in exactly two steps of subdivision. Second, the child vertex bisects an edge in one of four different directions, as can be seen in Fig. 10B Description: If it is horizontal (in Fig. 10B ), only the u coordinate changes; if it is vertical (in Fig. 10B ), only the v coordinate changes; if it is the lower right diagonal (in Fig. 10B ), the u and v coordinates vary with the same magnitude and sign; if the diagonal line is in the upper right (shown by horizontal shading 1008 in Fig. 10B The u and v coordinates vary with the same magnitude but different signs, as shown in FIG. 1010 with vertical shading 1010. Finally, the magnitude of each difference in the u or v coordinate is equal to the floor of the hierarchy of UVs raised to powers of two.

[0218] Also available in Figure 8BThe second function, p, is used in contexts other than those shown. For example, since it provides a way to generate two parent UVs from a child UV, it can be used to reduce the size of the output vertices from the tessellator (and therefore the size of any caches used to store them), since these output vertices might otherwise contain a child UV, two or three parent UVs, and a DF. Using this second function, parent UVs can be omitted.

[0219] Although Fig. 8A The generation of vertex UVs from primitive IDs is shown, but the vertex IDs can alternatively be generated from UVs (without re-running the tessellator), and the function z is shown in the table below -1 The function can also be used to generate a primitive ID based on its UV without re-running the tessellator (e.g. after the tiling stage), and this can be used to save bandwidth, for example, since the UV coordinates have already been generated, these can be sent to the tile unit without the primitive ID, thus reducing the data transferred between the tessellator and the tile unit, and the primitive ID can be regenerated afterwards after tiling.

[0220] The following table also includes the function γ -1 , which generates a child vertex ID based on two parent vertex IDs, and this function can be used to determine the ID of a child vertex of a given parent vertex based on its own ID, so that it can be determined when the last child vertex of the parent vertex has been processed, so that the parent vertex can be removed from the cache. This improves the efficiency of the cache because vertices can only be stored in the cache when they are needed.

[0221] The following table shows a summary of the vertex ID functions for a quad domain:

[0222]

[0223]

[0224]

[0225]

[0226]

[0227]

[0228]

[0229]

[0230]

[0231]

[0232] In the above table, the ~ symbol is used as follows: given a function f from set A to set B, we can define an equivalence relation on A, denoted ~, such that a is equivalent to a' (a~a') if and only if f(a)=f(a'). This is an equivalence relation because a~a; a~a' implies a'~a; and a~a', a'~a" implies a~a. Next, A can be partitioned into a set of subsets {U}, such that for any u in U, v is in A, then v~u if and only if v is in U. The set of subsets {U} is denoted A / ~, and for any u in U, it gives the inheritance function f / ~ from A / ~ to B given by f / ~(U)=f(u). Furthermore, the function is one-to-one and is therefore invertible on its image.

[0233] For the triangle domain, the role of encoding 1000...0 is swapped with 110...0 for the intermediate vertex ID. 110...0 has three parent IDs 000..0, 010..0, and 100..0, and corresponds to the vertex with parent coordinates (0,0), (3·2 T ,0) and (0,3·2 T )’s vertex coordinates (2 T-1 ,2 T-1 ). (2) Any functions in the domains are pre-composed separately or To pre-map the triangle domain UV into the quad domain UV (for example, Fig. 9C ). (2) Any functions in the domain are post-composed. or To map the quadrilateral domain UV to the triangle domain UV. Fig.15 For other cases shown in the table, there is also an alternative congruence 2a′0+a′1≡2a0+a1+1 (mod 3) of the TR or TL boundary vertices.

[0234] The table below shows a summary of the vertex ID functions for the contour domain. Since the vertex ID of a U coordinate is just its binary expansion, and since U coordinates are usually stored in binary form, they can be considered equivalent. One notable part of the table below is the parent calculation, which is given by adding and subtracting the largest power of 2 that divides the U coordinate (where the equivalent expression for the vertex ID involves truncating the encoding to two different lengths).

[0235]

[0236]

[0237]

[0238]

[0239]

[0240]

[0241]

[0242] As mentioned above, Fig. 8A The three functions used in the method are relative to the tessellation method that leads to improved primitive sorting (such as Figure 4A If another surface subdivision method is used, Fig. 8A The methods of still apply, and at a high level, the functions operate in the same or similar ways, but the functions themselves are different. For example, if you do not use the improved sort, you can add each odd number b x to give the modified ID of each vertex. Then, by combining this complement, we can find Fig. 8A For example, to find the parent ID, the method may include: complement each odd number b x , truncate the ID to p * or r-1, and then add each odd number b in the truncated code x .

[0243] Using the above method for primitive ID and vertex ID generation, an ID is a string of bits including a portion of r bits, each of which indicates one of two possible branches in the tessellator (e.g., a selected or unselected patch), so the ID encodes the tessellator branch. The tessellation unit can use these IDs to regenerate complete vertices and / or complete primitives (as described above). As described above, vertex and primitive IDs on the boundary of a domain take a different form than vertex and primitive IDs on the interior of the domain, so it is possible to determine whether a vertex / primitive is on the boundary or in the interior based solely on the ID.

[0244] As described above, the vertex ID encodes the UV coordinates, as it can be used to generate a single UV coordinate, and the primitive ID can be used to generate three UV coordinates for a quad / triangle domain or two UV coordinates for a contour domain. As described above, the primitive ID encodes its vertex ID, and as described above, these can be determined by truncation of the ID. When the primitives output in sequence by the tessellator have sequential primitive IDs when sorted in lexicographic order (indicated as ID order), the ID also encodes the order. For a given vertex, the IDs of its parent vertices are usually nearby in the ID order, and since nearby IDs are also very similar, this allows the ID blocks to be well compressed when stored in memory. In addition, as described above, the IDs can be compact, that is, they can have a form that includes the minimum number of bits required to represent all primitives and vertices (e.g., where T equals the maximum TF).

[0245] Instead of storing UVs, IDs can be used to regenerate other tessellator vertex attributes using a single primitive tessellator. In contrast, if only UVs are stored, they do not encode the order and cannot be used to regenerate other tessellator vertex attributes (such as the displacement factor).

[0246] The method described in this article is applicable to all input domains of tessellation: quadrilaterals, triangles, contours, and general polygons.

[0247] As described below, there are many applications for primitive IDs and vertex IDs, some of which have been described above. Example applications include:

[0248] • Vertex generation for domain shaders / blenders - Random vertices or primitive IDs can be fed into a single primitive tessellator to generate one or three / two vertices with attributes (such as UV and DF) respectively.

[0249] Generate UV coordinates - Hardware units can be used to generate UV coordinates for random vertex IDs, or generate triple / two UV coordinates for random primitive IDs.

[0250] Searching Tesseler Output Primitives - When the tesseler outputs primitives in the order given by their lexicographically ordered IDs, they are ready to be sorted for searching.

[0251] Addressing Cache - Vertices or primitives can be cached and addressed by their respective IDs. The ID order ensures good cache coherence, especially when searching for recently used parent vertices, since they are close in ID ordering and therefore more likely to belong in the cache.

[0252] • Searching for a parent vertex - a vertex ID can be used to generate a parent vertex ID, which in turn can be used to search for the parent vertex in the vertex cache.

[0253] Searching for primitive vertices - Primitive IDs can be used to generate their three / two vertex IDs, which in turn can be used to search for their vertices in the vertex cache.

[0254] The above methods for generating and using primitive IDs and vertex IDs are described in conjunction with a graphics processing system using tile-based deferred rendering (TBDR). However, these methods can also be used in a graphics processing system that uses techniques to reduce the amount of data stored in a parameter memory (e.g., Figure 1A and Figure 1B The amount of storage in the parameter memory 107, 117 shown. One such technique is described in UK patent application publication No. GB2458488. Typically, for each particular tile, the display list includes an indication of which transformed primitives are required to render the particular tile (where a transformed primitive is a primitive that is transformed into screen space). The transformed primitives are stored in the parameter memory together with the display list. By using untransformed primitives, the need to store transformed primitives in the parameter memory is avoided, and instead each display list includes an indication of the untransformed primitives required to render the particular tile. In the rasterization stage, the primitives are retransformed using the untransformed primitive data stored in the graphics memory, which requires additional processing (compared to reading the transformed primitive data from the parameter memory), but has the benefit of reducing the amount of data stored in the parameter memory. Where this technique is used in conjunction with the method described herein, the display list includes a list of IDs generated as described above, and at least one reference to the slice for all primitives in the tile generated from that slice. In such an example, a single primitive tessellator 114 (in Figure 1B ) will be a stage in the chain of primitive generation stages. This has the effect of reducing processing in the rasterization stage, as the primitive ID simplifies the tessellation process by encoding the tessellation sequence to follow.

[0255] The hardware tessellation unit 112 (such as Figure 1B The method described herein may be implemented in software (as shown) or in a separate single primitive tessellator 114. Alternatively, the method may be implemented in software (or a combination of software and hardware). Fig.11 Various components of an exemplary computing-based device 1100 are shown, which may be implemented in any form of computing and / or electronic device, and which may be configured to implement the methods described above.

[0256] The computing-based device 1100 includes one or more processors 1102, which can be a microprocessor, a controller, or a processor for processing computer executable instructions to control the operation of the device so as to perform the primitive and optional vertex sorting methods described herein. In some examples, such as in the case of a system using an on-chip architecture, the processor 1102 may include one or more fixed function blocks (also referred to as accelerators) that implement a portion of the sorting method in hardware (rather than software or firmware). Platform software including an operating system 1104 or any other suitable platform software can be provided at the computing-based device to enable application software 1106 to be executed on the device, and the application software may include a tessellation module 1108, which is configured to implement one or more methods described herein.

[0257] Computer executable instructions can be provided using any computer-readable medium accessible to computing-based device 1100. Computer-readable media may include, for example, computer storage media (such as memory 1110) and communication media. Computer storage media (i.e., non-temporary machine-readable media) such as memory 1110 include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical memory, cassettes, tapes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information accessed by a computing device. In contrast, communication media may embody computer-readable instructions, data structures, program modules or other data in modulated data signals (such as carrier waves) or other transmission mechanisms. As defined herein, computer storage media do not include communication media. Although computer storage media (i.e., non-transitory machine-readable media such as memory 1110) are shown within computing-based device 1100, it will be appreciated that the memory may be remotely distributed or located and accessed via a network or other communications link (e.g., using communications interface 1112).

[0258] The computing-based device 1100 may also include an input / output controller arranged to output display information to a display device that may be separate from or integrated with the computing-based device 1100. The display information may provide a graphical user interface. The input / output controller may also be arranged to receive and process input from one or more devices, such as a user input device (e.g., a mouse or keyboard). In an embodiment, if the display device is a touch-sensitive display device, it may also serve as a user input device. The input / output controller may also output data to devices other than the display device, such as a locally connected printing device.

[0259] Fig.12 A computer system is shown in which the GPU pipeline 101 described above (including the hardware tessellator 112) can be implemented. The computer system includes a CPU 1202, a GPU 1204, a memory 1206, and other devices 1214 such as a display 1216, a speaker 1218, and a camera 1220. Figure 1B The improved GPU pipeline 101 shown forms part of a GPU 1204. The components of the computer system may communicate with each other via a communication bus 1222.

[0260] The hardware tessellator 112 (or other hardware configured to perform any of the methods described herein, such as a separate single primitive tessellator 114) may be embodied in hardware on an integrated circuit. The tessellator unit 112 described herein may be configured to perform any of the methods described herein. Generally, any of the functions, methods, techniques, or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuits), or any combination thereof. The terms "module", "function", "component", "element", "unit", "block", and "logic" may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, a module, function, component, element, unit, block, or logic represents a program code that performs a specific task when executed on a processor. The algorithms and methods described herein may be performed by one or more processors that execute a code that causes the processor(s) to perform the algorithm / method. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disks, flash memory, hard disk storage, and other memory devices that can use magnetic, optical, or other technologies to store instructions or other data and can be accessed by a machine.

[0261] As used herein, the terms computer program code and computer readable instructions refer to any type of executable code for a processor, including code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, bytecode, code that defines an integrated circuit (such as a hardware description language or netlist), and code expressed in programming language code such as C, Java, or OpenCL. Executable code can be, for example, any type of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, executed in a virtual machine or other software environment, causes a processor of a computer system that supports the executable code to perform the tasks specified by the code.

[0262] Processor, computer or computer system can be any type of equipment, machine or special circuit or their collection or part with processing power so that it can execute instruction.Processor can be any type of general processor or special processor, such as CPU, GPU, system on chip, state machine, media processor, application specific integrated circuit (ASIC), programmable logic array, field programmable gate array (FPGA), physical processing unit (PPU), radio processing unit (RPU), digital signal processor (DSP), general processor (for example, general GPU), microprocessor, any processing unit designed to accelerate task outside CPU etc.Computer or computer system can include one or more processors.Those skilled in the art will recognize that such processing power is incorporated into many different equipments, and therefore term "computer" includes set-top box, media player, digital radio, PC, server, mobile phone, personal digital assistant and many other equipments.

[0263] It is also intended to encompass software that defines the configuration of hardware as described herein, such as HDL (Hardware Description Language) software, such as for designing integrated circuits, or for configuring a programmable chip to perform a desired function. That is, a computer-readable storage medium may be provided having computer-readable program code encoded thereon in the form of an integrated circuit definition data set, which when processed in an integrated circuit manufacturing system configures the system to manufacture a tessellation unit configured to perform any of the methods described herein, or to manufacture a tessellation unit comprising any of the apparatus described herein. The integrated circuit definition data set may, for example, be an integrated circuit description.

[0264] The integrated circuit definition data set may be in the form of computer code, for example, as a netlist, code for configuring a programmable chip, as a hardware description language defining the integrated circuit at any level (including as register transfer level (RTL) code), as a high-level circuit representation such as Verilog or VHDL, and as a low-level circuit representation such as OASIS (RTM) and GDSII. The higher-level representation (such as RTL) that logically defines the integrated circuit may be processed at a computer system that is configured to generate a manufacturing definition of the integrated circuit in the context of a software environment, including definitions of circuit elements and rules for combining such elements, so as to generate a manufacturing definition of the integrated circuit so defined by the representation. As is typically the case where software is executed at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required in order for a computer system configured to generate a manufacturing definition of an integrated circuit to execute code that defines the integrated circuit, thereby generating a manufacturing definition of the integrated circuit.

[0265] Now refer to Fig.13 An example of processing an integrated circuit definition data set at an integrated circuit manufacturing system to configure the system to manufacture a tessellation unit is described.

[0266] Fig.13 An example of an integrated circuit (IC) manufacturing system 1302 is shown, which includes a layout processing system 1304 and an integrated circuit generation system 1306. The IC manufacturing system 1302 is configured to receive an IC definition data set (e.g., defining a hardware tessellator or other hardware configured to perform any of the methods described herein, such as a separate single primitive tessellator), process the IC definition data set, and generate an IC (e.g., which embodies a hardware tessellator or other hardware configured to perform any of the methods described herein, such as a separate single primitive tessellator) based on the IC definition data set. The processing of the IC definition data set configures the IC manufacturing system 1302 to manufacture hardware embodying a hardware tessellator or other hardware configured to perform any of the methods described herein (e.g., a separate single primitive tessellator).

[0267] The layout processing system 1304 is configured to receive an IC definition data set and process it to determine a circuit layout. Methods for determining a circuit layout based on an IC definition data set are known in the art and may, for example, involve synthesizing RTL code to determine a gate-level representation of a circuit to be generated, for example, in terms of logic components (e.g., NAND, NOR, AND, OR, MUX, and flip-flop components). The circuit layout may be determined based on the gate-level representation of the circuit by determining location information of the logic components. This may be done automatically or with the aid of user intervention to optimize the circuit layout. When the layout processing system 1304 has determined the circuit layout, it may output a circuit layout definition to the IC generation system 1306. For example, the circuit layout definition may be a circuit layout description.

[0268] As is known in the art, IC generation system 1306 generates ICs according to the circuit layout definition. For example, IC generation system 1306 may implement a semiconductor device manufacturing process to generate an IC, which may involve a multi-step sequence of photolithography and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask that may be used in a photolithography process to generate an IC according to the circuit definition. Alternatively, the circuit layout definition provided to IC generation system 1306 may be in the form of a computer readable code that the IC generation system 1306 may use to form an appropriate mask for use in generating the IC.

[0269] The different processes performed by the IC manufacturing system 1302 can all be implemented at one location, such as by one party. Alternatively, the IC manufacturing system 1302 can be a distributed system so that some of the processes can be performed at different locations and can be performed by different parties. For example, some of the following stages can be performed at different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition data set to form a gate-level representation of a circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) forming a mask based on the circuit layout; and (iv) manufacturing the integrated circuit using the mask.

[0270] In other examples, processing of an integrated circuit definition data set at an integrated circuit manufacturing system may configure the system to manufacture a tessellation unit configured to perform a sorting method as described herein without processing the IC definition data set to determine a circuit layout. For example, an integrated circuit definition data set may define a configuration of a reconfigurable processor (e.g., an FPGA), and processing of the data set may configure the IC manufacturing system to generate a reconfigurable processor having the defined configuration (e.g., by loading the configuration data into the FPGA).

[0271] In some embodiments, the integrated circuit manufacturing definition data set, when processed in the integrated circuit manufacturing system, can cause the integrated circuit manufacturing system to generate the device as described herein. Fig.13 Configuration by an integrated circuit manufacturing definition data set in the manner described may enable the manufacture of a device as described herein.

[0272] In some examples, the integrated circuit definition data set may include software that runs on or in combination with hardware defined at the data set. Fig.13 In the example shown, the IC generation system may also be configured by the integrated circuit definition data set to load firmware onto the integrated circuit when manufacturing the integrated circuit according to the program code defined at the integrated circuit definition data set, or to otherwise provide program code to the integrated circuit for use with the integrated circuit.

[0273] Those skilled in the art will recognize that storage devices for storing program instructions can be distributed in a network. For example, a remote computer can store examples of processes described as software. A local or terminal computer can access the remote computer and download a portion or all of the software to run the program. Alternatively, a local computer can download fragments of the software on demand, or execute some software instructions at a local terminal and execute some software instructions at a remote computer (or computer network). Those skilled in the art will also recognize that all or part of the software instructions can be executed by a dedicated circuit (e.g., DSP, programmable logic array, etc.) by utilizing conventional techniques known to those skilled in the art.

[0274] The methods described herein may be performed by a computer configured with software in a machine-readable form stored on a tangible storage medium, such as in the form of a computer program including computer-readable program code for configuring a computer to perform the components of the method, or in the form of a computer program including computer program code suitable for performing all the steps of any method described herein when the program is run on a computer, and wherein the computer program may be embodied on a computer-readable storage medium. Examples of tangible (or non-transitory) storage media include disks, thumb drives, memory cards, etc., and do not include propagating signals. The software may be suitable for execution on a parallel processor or a serial processor, so that the method steps may be executed in any appropriate order or simultaneously.

[0275] The hardware components described herein may be generated by a non-transitory computer-readable storage medium having computer-readable program code encoded thereon.

[0276] The memory storing the machine executable data used in implementing the disclosed aspects may be a non-transitory medium. The non-transitory medium may be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memories, such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic memory technologies, flash memory, phase change memory, resistive RAM.

[0277] A specific reference to "logic" refers to a structure that performs one or more functions. Examples of logic include circuits that are arranged to perform these functions (one / more functions). For example, such circuits may include transistors and / or other hardware elements available in the manufacturing process. As an example, such transistors and / or other elements may be used to form circuits or structures that implement and / or contain memory (e.g., registers, flip-flops, or latches), logic operators (e.g., Boolean operations), mathematical operators (e.g., adders, multipliers, or shifters) and interconnections. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other abstract levels. Such elements may be interconnected in a specific arrangement. Logic may include fixed-function circuits, and the circuits may be programmed to perform one or more functions; such programming may be provided by firmware or software updates or control mechanisms. Logic identified as performing a function may also include logic that implements constituent functions or subprocesses. In an example, hardware logic has circuits that implement fixed-function operations, or multiple operations, state machines, or processes.

[0278] As will be apparent to the skilled artisan, any range or device value given herein may be expanded or altered without losing the effect sought.

[0279] It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.

[0280] Any reference to "an" item refers to one or more of those items. The term "comprising" is used herein to mean including the identified method blocks or elements, but such blocks or elements do not comprise an exclusive list, and an apparatus may contain additional blocks or elements, and a method may contain additional operations or elements. Furthermore, blocks, elements, and operations themselves are not implicitly closed.

[0281] The steps of the method described herein can be performed in any appropriate order or performed simultaneously when appropriate. The arrows between the frames in the accompanying drawings illustrate an example order of method steps, but are not intended to exclude the parallel execution of other orders or multiple steps. In addition, each block can be deleted from any method without departing from the spirit and scope of the subject matter described herein. The aspect of any example described above can be combined with any aspect of other examples described to form other examples without losing the effect sought. The elements of the accompanying drawings are shown as being connected by arrows, and it will be appreciated that these arrows only illustrate an example communication flow (comprising data and control messages) between the elements. The flow between the elements can be in either direction or in two directions.

[0282] The applicant hereby independently discloses each individual feature described herein and any combination of two or more such features, to the extent that such feature or combination can be implemented as a whole based on this specification in accordance with the common general knowledge of a person skilled in the art, regardless of whether such feature or combination of features solves any problem disclosed herein. In view of the above description, it will be apparent to a person skilled in the art that various modifications may be made within the scope of the invention.

[0283] When compared with known implementations, the implementation of the concepts set forth in this application in devices, apparatuses, modules and / or systems (and methods implemented herein) can cause performance improvements. Performance improvements can include one or more of increased computing performance, reduced latency, increased throughput and / or reduced power consumption. During the manufacture of such devices, devices, modules and systems (e.g., in integrated circuits), performance improvements can be compromised with physical implementations to improve manufacturing methods. For example, performance improvements can be weighed for layout area to match the performance of known implementations, but using less silicon. This can be accomplished, for example, by reusing functional blocks in a serialized manner or sharing functional blocks between elements of devices, devices, modules and / or systems. On the contrary, the concepts set forth in this application that produce improvements (such as reduced silicon area) in the physical implementation of devices, devices, modules and systems can be weighed for improved performance. This can be accomplished, for example, by manufacturing multiple instances of modules within a predetermined area budget.

Claims

1. A tessellation unit, the tessellation unit being configured to perform tessellation in a computer graphics system, the tessellation unit comprising hardware logic, the hardware logic being arranged to: subdividing the initial patch into a plurality of primitives using a plurality of subdivision steps; and Generate a primitive identifier ID for each primitive, where: The primitive identifier ID encodes data on how the primitive is generated by the multiple subdivision steps and enables subsequent generation of vertex data for the vertices of the primitive, wherein the data on how the primitive is generated by subdividing the initial patch includes a sequence of bits describing the multiple subdivision steps taken during surface tessellation to generate the primitive, wherein each bit in the sequence of bits indicates which branch is taken at a corresponding subdivision step during surface tessellation to generate the primitive, one branch representing a sub-patch formed by the subdivision of the initial patch, and wherein the sequence of bits specifies a recursive sequence adopted during the surface tessellation process.

2. The tessellation unit according to claim 1, wherein: The primitive's ID also includes a variable length trailer portion, and wherein the primitive's ID includes a fixed number of bits.

3. The tessellation unit according to claim 1, wherein: The hardware logic arranged to subdivide the initial patch into a plurality of primitives using a plurality of subdivision steps comprises hardware logic arranged to: analyzing an initial slice to determine whether to subdivide the slice; In response to determining that the patch is not to be tessellated, outputting the patch as a triangle primitive; In response to determining that the tile is to be subdivided, dividing the initial tile into two or more sub-tiles; Selecting in turn each sub-slice formed by subdividing the initial slice, and repeating the operation with the selected sub-slice replacing the initial slice; And wherein the hardware logic arranged to generate an ID for each primitive comprises hardware logic arranged to perform the following operations: In response to dividing the initial tile into two or more sub-tiles, assigning to the sub-tiles an ID at least part of which is inherited from an ID of a tile that has been subdivided; and In response to selecting a tile formed by the subdivision of the initial tile, an ID of each tile formed by the subdivision of the initial tile is updated according to the selection.

4. The tessellation unit according to claim 3, wherein: The initial patch is formed by subdividing a triangle domain, a quadrilateral domain or a polygonal domain, and the ID of the patch also includes a header part, which includes one or more bits indicating which of multiple initial patches formed by the triangle domain or quadrilateral domain the primitive is in.

5. The tessellation unit according to claim 3, wherein: The hardware logic arranged to update the ID of each tile formed by the subdivision of the initial tile according to the selection comprises hardware logic arranged to perform the following operations for each ID: One or more new bits are added to the sequence of bits specifying a recursive sequence employed during the tessellation process, the values ​​of the new bits being dependent on the selection.

6. The tessellation unit according to claim 3, wherein: The initial patch is a triangle patch, and the hardware logic arranged to sequentially select each sub-patch formed by subdivision of the initial patch and repeat the operation with the selected sub-patch in place of the initial patch comprises hardware logic arranged to: sequentially selecting each of the sub-slices formed by subdivision of the initial slice based on the value of one or more flags, and repeating the operation with the selected sub-slice replacing the initial slice; And wherein the hardware logic arranged to repeat the operation with the selected sub-slice replacing the initial slice comprises hardware logic arranged to perform the following operations: analyzing the selected sub-slice to determine whether to further subdivide the selected sub-slice; In response to determining that the selected sub-tile is not to be tessellated, outputting the selected sub-tile as a triangle primitive; In response to determining that the selected sub-slice is to be further subdivided, dividing the selected sub-slice into two or more sub-slices; and Each sub-tile formed by the subdivision of the selected sub-tile is selected in turn based on the value of one or more flags, and the operation is repeated with the selected sub-tile.

7. The tessellation unit according to claim 6, wherein: Subdividing into two slices, a left slice and a right slice, and hardware logic arranged to sequentially select each of the sub-slices formed by the subdivision of the initial slice based on the value of one or more flags comprises hardware logic arranged to perform the following operations: Each of the left and right slices formed by the subdivision of the initial slice is selected in turn based on the value of the sort flag.

8. The tessellation unit of claim 7 , further comprising hardware logic arranged to: For each increase or decrease in the subdivision level, the value of the sorting flag is inverted once.

9. A tessellation unit configured to perform tessellation in a computer graphics system, the tessellation unit comprising hardware logic arranged to: In a tessellation unit, receiving an identifier ID of a previously tessellated primitive and a patch reference, wherein the patch reference identifies data associated with the patch and is associated with the primitive, the primitive being formed from the patch; Accessing data associated with the surface patch, the data including tessellation factors and topological data; Selecting an initial slice based on the primitive's ID, and The initial patch is at least partially tessellated using one or more tessellation stages, wherein: at each stage of tessellation, determining whether to perform tessellation and which of any newly formed sub-tiles to further tessellate based on a sequence of bits in the ID of the primitive, wherein the sequence of bits describes a number of tessellation steps taken during tessellation to generate the primitive, and wherein each bit in the sequence of bits indicates which branch to take at a corresponding tessellation step during tessellation to generate the primitive, one branch representing one sub-tile formed from tessellation of the initial tile, and wherein the sequence of bits (502) specifies a recursive sequence taken during the tessellation process in which newly formed sub-tiles are formed from tessellation of the initial tile, and Output vertex data for the vertices of the primitive.

10. The tessellation unit according to claim 9, wherein: The tessellation unit further comprises hardware logic arranged to: An input patch is selected based on data from the surface patch and subdivided into one or more initial patches.

11. The tessellation unit according to claim 10, wherein: The primitive's or tile's ID comprises a sequence of bits that specifies the recursive sequence to be employed during the tessellation process.

12. The tessellation unit according to claim 10, wherein: Each bit in the sequence of bits indicates whether to process a left sub-tile or a right sub-tile formed by a tessellation operation in the tessellation process.

13. The tessellation unit according to claim 9, wherein: At least partially tessellating an initial patch generated by tessellation of an input patch results in regenerating the previously tessellated primitives.

14. The tessellation unit of claim 9, further comprising hardware logic arranged to: Output the domain vertices for the previously tessellated primitive.

15. A computer graphics system comprising: A tessellation unit, the tessellation unit comprising hardware logic arranged to: Receiving an identifier ID of a primitive in a tessellation unit; Truncating the ID of the primitive at a plurality of different positions to generate the IDs of the vertices in the primitive; For a subset of vertices in the primitive, truncating the ID of each vertex at a plurality of different locations to generate an ID of a parent vertex in a subdivision hierarchy; as well as using vertex IDs to calculate UV coordinates of the parent vertex for each vertex in the primitive and for the subset of vertices in the primitive; as well as A domain shader includes hardware logic arranged to generate vertex data for each vertex in the primitive based on the calculated UV coordinates.

16. The computer graphics system of claim 15, wherein: The ID of the primitive comprises a sequence of bits that describes the subdivision sequence used to generate the primitive.

17. The computer graphics system of claim 15, wherein: The ID of the primitive comprises a sequence of bits specifying a recursive sequence to be employed during a tessellation process, and wherein the recursive sequence defines the tessellation hierarchy, and wherein hardware logic in the tessellation unit arranged to truncate the ID of the primitive at a plurality of different locations to generate IDs of vertices in the primitive comprises hardware logic arranged to: performing a first truncation according to a first function that steps the subdivision hierarchy back one step to generate a first vertex ID; Further truncation is performed twice according to a second function to generate a second vertex ID and a third vertex ID, wherein the second function steps back the subdivision hierarchy two steps to generate the second vertex ID and steps back the subdivision hierarchy S steps to generate the third vertex ID, wherein the value of S is determined by the ID of the primitive.

18. The computer graphics system of claim 15, wherein: The ID of the primitive comprises a sequence of bits specifying a recursive sequence to be employed during a tessellation process, and wherein the recursive sequence defines a tessellation hierarchy and for the subset of vertices in the primitive, hardware logic in the tessellation unit arranged to truncate the vertex IDs of the vertices at a plurality of different locations to generate IDs of parent vertices comprises hardware logic arranged to: For the subset of vertices in the primitive, truncation is performed twice according to a second function to generate a first parent vertex ID and a second parent vertex ID, wherein the second function steps back the subdivision hierarchy by two steps to generate the first parent vertex ID, and steps back the subdivision hierarchy by S steps to generate the second parent vertex ID, wherein the value of S is determined by the vertex ID.

Images