Gate layer arranged partially into the trench

Abstract

A gate layer is disclosed that is disposed partially into a trench. According to some examples, a system includes a substrate layer (65) having an outer surface (100). The system includes a plurality of trenches (90, 92, 94, 96) extending into the substrate layer from the outer surface. The system then includes a plurality of active regions (102, 104, 106), where each active region is positioned between a different pair of consecutive trenches of the plurality of trenches. The system also includes a dielectric layer (88) disposed in each trench of the plurality of trenches and on each active region of the plurality of active regions. The system then includes a gate layer (20) disposed on the dielectric layer and extending at least partially into each trench of the plurality of trenches.

Description

BACKGROUND

[0001] A non-volatile memory (NVM) bitcell is an electronic component configured to store information. An electrical state (e.g., threshold voltage) of the bitcell can be used to define a logic level, such as a logic low (meaning a digital low or 0) or a logic high (meaning a digital high or 1). This defined logic level can sometimes be referred to as the information (or bit) stored in the bitcell. SUMMARY

[0002] According to at least one example, a system includes a substrate layer having an outer surface. The system includes a plurality of trenches extending into the substrate layer from the outer surface. The system also includes a plurality of active regions, where each active region is positioned between a different pair of consecutive trenches of the plurality of trenches. The system then includes a dielectric layer disposed in each trench of the plurality of trenches and on each active region of the plurality of active regions. The system also includes a gate layer disposed on the dielectric layer and extending at least partially into each trench of the plurality of trenches.

[0003] According to at least one other example, a method includes obtaining a wafer including a plurality of floating gate layers; measuring a thickness of the plurality of floating gate layers; using the measured floating gate layer thickness and a target value to calculate a floating gate thickness variation value; and increasing an oxide etch time of the wafer based on the floating gate thickness variation value.

[0004] According to at least yet another other example, a method includes obtaining a substrate layer having an outer surface and including a plurality of shallow trench isolation structures extending into the substrate layer from a first surface above the outer surface, where a first dielectric layer interfaces the outer surface, and where a plurality of floating gate layers are positioned on the first dielectric layer; measuring a thickness of each floating gate layer of the plurality of floating gate layers; using the measured thickness of the plurality of floating gate layers and a target value to calculate a floating gate thickness variation value; and etching the plurality of shallow trench isolation structures based on the floating gate thickness variation value. BRIEF DESCRIPTION OF DRAWINGS

[0005] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0006] FIG. 1(a) depicts an illustrative layout of a split-gate flash bitcell memory array, according to various examples.

[0007] FIG. 1(b) depicts one side view cross-section of a pair of illustrative bitcells, according to various examples.

[0008] FIG. 1(c) depicts another side view cross-section of a pair of illustrative bitcells, according to various examples.

[0009] Figure 2(a) depicts an illustrative floating gate feed forward system, in accordance with various examples.

[0010] Figure 2(b) depicts an illustrative method of compensating for floating gate thickness variations of a semiconductor wafer, in accordance with various examples.

[0011] Figure 2(c) depicts an illustrative graph showing data points for read current of a flash memory array including a wrap-round over an active region and without a wrap-round, in accordance with various examples.

[0012] Figures 3(a)-3(i) Manufacturing steps for fabricating a bit cell are illustrated, in accordance with various examples.

[0013] Figures 4(a)-4(i) Manufacturing steps for adjusting a wrap-around region over an active region are illustrated, in accordance with various examples. DETAILED DESCRIPTION

[0014] Flash memory is a non-volatile storage medium that can store information in an array of bit cells. This stored information (or "bits") can be electrically erased, programmed, and read. In some cases, floating gate transistor bit cell arrays can be used in flash memory. Floating gate transistor bit cells are similar to standard metal oxide field effect transistors (MOSFETs), except that floating gate transistor bit cells include multiple gates, e.g., a control gate and a floating gate. As described above, the electrical state of a bit cell can be used to define a logic level, which can further be referred to as a bit stored in the bit cell. For example, when an electron is trapped in its floating gate, the threshold voltage of a floating gate transistor bit cell can increase, and this different (new) threshold voltage (relative to the base (or old) threshold voltage) can be interpreted as a logic low. In other words, the electrical state exhibited when an electron is trapped in a floating gate transistor bit cell can be referred to as a digital low or "0" being stored as a bit in the bit cell. On the other hand, the electrical state when an electron is depleted in the floating gate can be referred to as a digital high or "1" being stored in the bit cell.

[0015] In some cases, floating gate transistor bit cells utilize a split gate structure to store bits. Such bit cells are often referred to as split gate flash bit cells, which include more than one transistor. For example, a split gate flash memory cell has a portion of the floating gate underneath the control gate, such that the channel of the memory cell transistor is controlled by both the word line gate as well as the floating gate. This causes the split gate flash memory cell to act as two transistors working in series, equivalent to 1.5T per cell when the source or drain is shared by two flash bit cells. Likewise, in some configurations, a split gate flash bit cell can have a 2T (two transistor) configuration. The combination of one or more of these gates can be configured to program, erase, and read the split gate bit cell.

[0016] As described above, the floating gate in a split-gate flash memory bit cell can store charge (e.g., electrons), and the resulting electrical state of the split-gate flash memory bit cell (similar to a floating gate transistor bit cell) can be assigned a digital value (0 or 1). For example, applying a positive voltage potential to the control gate can trap electrons in the floating gate. This condition can change the electrical state of the split-gate flash memory bit cell (e.g., an increased threshold voltage), and this change can represent a logic low or digital "0" state. Conversely, the absence of electrons in the floating gate can also change the electrical state of the bit cell, and this condition (e.g., a decreased threshold voltage) can represent a high logic level or digital "1" state.

[0017] The electrical state of a split-gate flash memory bit cell can be read. This is typically done by reading the current between the bit line and the source line of the bit cell. This read current is related to the thickness of the floating gate. In the case of an electron-depleted (i.e., digital 1 state) floating gate, the read current for this "1" state (referred to herein as an IR1 read current) can vary substantially due to floating gate thickness variations. It is also observed that the thicker the floating gate (relative to a target thickness), the lower the read current (and vice versa). From a manufacturing perspective, the floating gate thickness is dependent on the chemical mechanical polishing (CMP) process and / or subsequent etch-back process. CMP and etch-back process variations result in floating gate thickness variations from wafer to wafer, thus introducing wafer-to-wafer IR1 read current variations.

[0018] Conventionally, a source / drain pocket implant is used to compensate for this variation. However, the pocket implant is not desirable because it impacts the programming efficiency of the split-gate flash memory bit cell. Thus, a different technique to mitigate the wafer-to-wafer IR1 read current variation problem is desired.

[0019] Accordingly, at least some examples disclosed herein are directed to systems and methods for compensating for the above-mentioned IR1 read current variation. In particular, the present disclosure describes using a feedforward process that compensates for wafer-to-wafer IR1 current variation. As mentioned above, this wafer-to-wafer IR1 current variation occurs due to floating gate thickness variation compared to a target thickness (e.g., 45 nanometers). It is observed that an increase in the surround area of the word line gate above the active area can increase the IR1 read current. The present disclosure describes a floating gate thickness feedforward method that includes feeding forward a thickness variation value to compensate for the IR1 read current variation, particularly by increasing the active area surround area of the word line gate layer. The floating gate feedforward method of at least some examples includes increasing the surround area of the word line gate layer by increasing the etch time of the isolation region. In some examples, increasing the etch time can occur in one or more fabrication steps. In other words, one or more etch steps can contribute to increasing the surround area of the word line gate layer above the active area. The thickness variation value can be considered when performing one or more of these etch steps that contribute to increasing the surround area. In some examples, the isolation region that is etched to increase the surround area can include a shallow trench isolation (STI) structure.

[0020] Referring now to FIG. 1(a), a portion of an illustrative layout 10 of a split-gate flash memory bitcell array is shown in accordance with various examples. The layout of the split-gate flash memory array depicted by FIG. 1 includes erase gates. However, the present disclosure is not limited to split-gate flash memory bitcell arrays that include erase gates. The following explanation is valid for split-gate flash memory arrays that include word line gates and floating gates.

[0021] Layout 10 is used, at least in part, as a layout (blueprint) for fabricating a bitcell array that is implemented with a CMOS logic array (not explicitly depicted). In some examples, layout 10 can be used to fabricate a bitcell array that is implemented as a standalone memory device (e.g., implemented on its own semiconductor die, enclosed within its own chip package, etc.). Other versions can be implemented with other devices (e.g., on a die that includes other devices, enclosed within a chip package that includes other devices, etc.).

[0022] Layout 10 depicts at least some of the layers that form a split-gate flash memory bitcell array. Layout 10 includes bitline (BL) layers 22-23 and source line (SL) layers 34. Layout 10 also includes wordline (WL) gate layers 12, 20, erase gate (EG) layer 16, and control gate (CG) layers 14, 18. Layout 10 also depicts regions labeled with numerals 36, 38, 40, 42 in which shallow trench isolation structures (not explicitly shown) can be positioned. Figure 1(a) also illustrates a coordinate system 1 in which the X and Y axes of coordinate system 1 each lie in the page of the drawing, and the Z axis is out of the page (outward). Coordinate system 1 is shown in other figures so that the relative orientation of various examples is readily determined. For example, from the perspective of layout 10, one or more bitcells are positioned on a line 50 aligned with the Y axis, but, from a manufacturing perspective, a side view of a cross-section of one or more bitcells can be observed in the Y-Z plane along line 50. Likewise, from the perspective of layout 10, one or more shallow trench isolation structures are presented along a line 60 aligned with the X axis, and, from a manufacturing perspective, a side view of a cross-section of an STI region can be observed in the X-Z plane along line 60. In some examples, the region between two STI regions is referred to as an active region.

[0023] Referring now to Figure 1(b), a side view cross-section of an illustrative pair of bitcells 70, 80 can be observed in the Y-Z plane along line 50. Other bitcells can be observed in the Y-Z plane along other lines presented on the Y axis. For example, a pair of bitcells can be formed along bitline layers 22, 23, and other pairs of bitcells can be formed along bitlines 26, 27.

[0024] Bitcells 70 and 80 are generally similar in structure. Bitcell 70 includes bitline layer 24 disposed in substrate 65. Bitcell 70 also includes wordline gate layer 12, control gate layer 14, floating gate layer 15, and erase layer 16 (which is also shared by bitcell 80). Bitcell 70 also includes dielectric layers 66, 67, and 69. These dielectric layers are fabricated to provide isolation between wordline gate layer 12, control gate 14, floating gate 15, erase gate layer 16, and substrate 65. The WL transistor in bitcell 70 includes WL gate layer 12 (similar to the gate of a MOSFET), bitline layer 24 (similar to the drain of a MOSFET), and source line layer 34 (similar to the source of a MOSFET). Bitcell 70 also includes an implant layer 9 disposed beneath wordline gate layer in substrate 65. In some examples, implant layer 9 is also used to change the threshold voltage of the WL transistor.

[0025] Similar to bit cell 70, bit cell 80 includes bit line 25, source line layer 34, erase gate 16, floating gate 19, and control gate 18. Bit cell 80 also includes dielectric layers 66, 67, and 69, which isolate erase gate 16, control gate 18, floating gate 19, and word line gate layer 20 from one another. Bit cell 80 also forms a WL transistor, which includes word line gate layer 20 (similar to a MOSFET's gate), bit line layer 25 (similar to a MOSFET's drain), and source line layer 34 (similar to a MOSFET's source). In some examples, substrate 65 also includes silicon. In one such example, dielectric layer 66 can include silicon dioxide and dielectric layers 67, 69 can include silicon nitride. Bit cell 80 also includes implant layer 8 disposed below word line gate layer 20 in substrate 65. Similar to bit cell 70, implant layer 8 can be used to change the threshold voltage of the aforementioned WL transistor.

[0026] Bit cells 70, 80 can also include contact layers 2, 4, 5, 6, 7, which contact bit line layer 25, bit line layer 24, word line gate layer 12, erase gate layer 16, and word line gate layer 20, respectively. Both bit cells 70 and 80 share punch through stop layer 11 disposed in substrate 65. Punch through stop layer 11 can be used to reduce punch through leakage between bit line layer 24 and source line layer 34. The present disclosure describes split gate flash memory bit cells that include four gate layers (word line gate layer, control gate layer, erase gate layer, and floating gate layer). The principles discussed herein can be applicable to bit cells that include any number of gates (or gate layers).

[0027] As described above, one or more shallow trench isolation regions can be presented along line 60, which is aligned with the X-axis (Figure 1(a)). Figure 1(c) depicts a portion 101 of Figure 1(a) along line 60, which is a side cross-section of the STI regions viewed along line 60 in the X-Z plane. Figure 1(c) depicts regions 36, 38, 40, 42 (Figure 1(b)), in which shallow trench isolation structures 90, 92, 94, 96 are positioned. Figure 1(c) also depicts substrate 65, which has an outer surface 100. Portion 101 includes shallow trench isolation structures 90, 92, 94, and 96, which extend from outer surface 100 into substrate 65. Portion 101 also includes active regions that exist between two adjacent trenches. For example, active region 102 exists between shallow trench isolation structures 90 and 92. Likewise, active region 104 exists between shallow trench isolation structures 92 and 94. Shallow trench isolation structures 90, 92, 94, and 96 include dielectric layer 88, which extends from each shallow trench isolation structure to an adjacent shallow trench isolation structure over an active region between the two shallow trench isolation structures, such that a portion of dielectric layer 88 is positioned on the active region and serves as a gate oxide layer for word line gate layer 20.

[0028] Figure 1(c) also depicts a WL gate layer 20 positioned on the substrate 65 such that the WL gate layer 20 partially extends into each of the shallow trench isolation structures 90, 92, 94, and 96 and contacts the dielectric layer disposed in the shallow trench isolation structures 90, 92, 94, and 96 above the active regions 102, 104, and 106. The substrate layer 65 includes implanted layers in each of the active regions 102, 104, and 106. For example, the substrate 65 under the active region 102 includes implanted layers 89 and 91. Likewise, the substrate 65 under the active region 104 includes implanted layers 93 and 95, and the substrate 65 under the active region 106 includes implanted layers 97 and 98. In some examples, the implanted layers 89, 93, 97 (similar to the implanted layers 8, 9 in Figure 1(b)) can be formed in the substrate 65 by implanting boron, and the implanted layers 91, 95, 98 can be punch-through prevention implanted layers (similar to the punch-through prevention implanted layers in Figure 1(b)) and can be formed in the substrate 65 by implanting boron. In some examples, the substrate 65 can be silicon. In such examples, the dielectric layer 88 disposed in each of the shallow trench isolation structures can include silicon dioxide, and in such examples, the WL gate layer 20 can be polysilicon.

[0029] Referring now to a read operation of the bit cell 80, information (or bits) stored in a bit cell, such as the bit cell 80, can be read by reading the current between the bit line 25 and the source line 34. Based on the electron density in the floating gate 19, the bit cell 80 can be programmed in a "0" state or erased in a "1" state. As described above, the erased bit cell read current IR1 depends on the thickness of the floating gate 19, and the higher the floating gate thickness (relative to a target thickness), the lower the IR1 read current (and vice versa). For example, assuming a desired thickness of 45 nanometers and the floating gate 19 has a floating gate thickness of 50 nanometers, the floating gate 19 will exhibit a lower IR1 read current due to its higher than desired floating gate thickness. To compensate for this variation in the IR1 read current, the word line wrap around region of the corresponding word line gate layer 20 above the active region 102 is increased.

[0030] From FIG. 1(a) and FIG. 1(b), it can be inferred that the shallow trench isolation structure 92 (in region 38) is positioned behind the bit cell 80 (i.e., into the drawing toward the X-axis in coordinate system 1). To compensate for the thickness variation of the floating gate 19, the surrounding area of the corresponding word line gate layer near the active region can increase. For example, assume that the thickness of the floating gate 19 is higher than the target (threshold) thickness. In this case, the word line gate layer 20 will have a higher surround in the active region 102 to compensate for the higher thickness of the floating gate 19. Thus, to compensate for this variation, a higher surrounding area of the word line gate 20 over its corresponding active region 102 is desired. The higher surrounding area of the word line gate layer 20 over the active region 102 can be obtained by increasing the etch time of the fabrication of the shallow trench isolation structure 92. For simplicity, the above explanation is directed to a single bit cell, such as bit cell 80. The foregoing explanation can be applied to compensate for wafer-to-wafer variation of the IR1 read current. For example, assume that the desired thickness is 45 nanometers and the floating gates arranged in a first wafer ("Wafer A") have a median floating gate thickness of 50 nanometers, and the floating gates arranged in a second wafer ("Wafer B") have a median floating gate thickness of 55 nanometers. Wafer A and Wafer B will exhibit lower IR1 read currents due to their higher than desired floating gate thickness, and also exhibit different IR1 read currents relative to each other. To compensate for this wafer-to-wafer variation of the IR1 read current, the word line surround area over the active region is to be increased.

[0031] Referring now to FIG. 2(a), an illustrative floating gate feedforward system 201 can dynamically vary the etch time of a shallow trench isolation structure based on a thickness variation value of a floating gate layer present on a wafer. The floating gate feedforward system 201 can be installed in a manufacturing processing facility that manufactures bitcells. The floating gate feedforward system 201 can include a central processing unit (CPU) 202 coupled to a storage device 203 (e.g., random access memory (RAM), read only memory (ROM)) that can include any suitable type of non-transitory computer-readable medium that stores machine-executable instructions, such as instructions 207. The CPU 202, in executing the instructions 207, performs some or all of the actions attributed herein to the floating gate feedforward system 201. In some examples, the CPU 202 can be coupled to an etch station 204 that controls the oxide etch time of a wafer based on a thickness variation of a floating gate layer detected using a scatterometer 205 or other suitable measurement device. For example, based on a floating gate thickness measurement received from the scatterometer 205, the CPU 202 can determine a variation in the floating gate thickness and can control the etch station 204 to increase or decrease the time that a wafer is held in an etch tank accordingly. The more time a wafer is in the etch tank, the more oxide will be etched, and vice versa. Controlling the etch time in this manner affects the aforementioned surround region above the active region, thereby compensating for the non-uniform floating gate layer thickness.

[0032] In some examples, the CPU 202 includes a cognitive computing system having a neural synapse hardware architecture and machine-executable instructions to facilitate machine learning and probabilistic algorithms. The CPU 202 can be a monolithic CPU 202 (e.g., a single device), or it can include distributed CPUs 202 located in multiple independent locations. The CPU 202 can include multiple different subsystems, including computer subsystems and non-computer subsystems (e.g., hardware that performs actions with tangible objects). The CPU 202 can perform its functions in a fully autonomous manner, or it can perform its functions in a semi-autonomous manner (e.g., with human assistance).

[0033] Referring now to FIG. 2(b), an illustrative method 200 can be performed to compensate for floating gate thickness variations in a semiconductor wafer and / or between one or more semiconductor wafers. Briefly, in some examples, a first floating gate thickness variation in a single wafer is determined, for example, using measurements from a scatterometer 205 (FIG. 2(a)). Next, the floating gate thickness variation information determined using measurements from the scatterometer 205 is used to adjust the surround region of the wordline gate layer above the active region of all bitcells present in the wafer (e.g., by increasing or decreasing the etch time of a shallow trench isolation structure).

[0034] Accordingly, Figure 2(b) depicts an illustrative floating gate feed forward method 200. The method 200 is now described in conjunction with Figures 3(a)-3(i) and Figures 4(a)-4(i) together. The method 200 is described in conjunction with Figures 3(a)-3(i) and Figures 4(a)-4(i) a floating gate feed forward method for a plurality of bit cells present on a wafer. However, for simplicity, Figures 3(a)-3(i) and Figures 4(a)-4(i) depict fabrication steps for a bit cell 80 (Figure 2(b)).

[0035] The method 200 can be performed after performing a chemical mechanical polishing (CMP) process and / or an etch back process (not explicitly shown). The CMP and etch back processes self-align the floating gate layer 19 with the top of the shallow trench isolation structures 90, 92, as depicted in Figure 4(a). After the aforementioned self-alignment process, a wafer is obtained that includes a plurality of floating gate layers (step 206). The wafer can also include a plurality of shallow trench isolation structures, and thus a plurality of floating gate layers that are self-aligned with the shallow trench isolation structures. The thickness of one or more floating gate layers, such as the floating gate layer 19; Figure 4(a), can be measured (step 210). In some examples, the thickness measurement can be performed using a scatterometer 205. In other examples, a different instrument can be used. As described above, the scatterometer 205 can be coupled to the CPU 202, which is configured to instruct the scatterometer 205 to measure the thickness of the floating gate layer.

[0036] In some examples, the thickness can be measured at different locations of the wafer, which can be further used to derive a mean value (or other value, such as median) of the thickness. For example, the scatterometer 205 can calculate the thickness of the floating gate at 21 different locations of the wafer. The thickness information from these 21 different locations can be used to determine a mean value of the thickness. The method 200 can further use this calculated mean value and derive a thickness variation value by comparing the mean value and a predefined target value (step 220). This step 220 can also be performed in the CPU 202, which is connected to the scatterometer 205. In other examples, a separate CPU can be present in the scatterometer 205, which can calculate the thickness variation with respect to the predefined target value. The method 200 can then feed forward the thickness variation value to the CPU 202 (step 230), which can control the etching time of the shallow trench isolation structure. For example, assume that the CPU 202 (after receiving the scatterometer data) compares the mean value of the scatterometer data with the target value and concludes that the mean thickness is higher than the target value. Based on this determination, the CPU 202 can instruct the etching station 204 to increase the oxide etching time (e.g., the etching time of the shallow trench isolation structure), which can help to increase the surrounding area of the word line gate layer above the active region (step 240). Referring briefly to FIG. 4(g), which depicts the etched shallow trench isolation structures 90, 92. The longer the etching time, the deeper the hollow well inside the shallow trench isolation structures 90, 92. After the aforementioned etching step, the word line gate layer 20 can be deposited such that portions of the word line gate layer 20 are disposed inside the shallow trench isolation structures 90, 92. The portions of the word line gate layer 20 disposed in the shallow trench isolation structures 90, 92 increase the surrounding area of the word line 20 above the active region 102, which can compensate for the variation (e.g., increase) in the floating gate layer 19.

[0037] FIG. 2(c) depicts an illustrative graph showing data points of the flash memory array read current including a surround above a plurality of active regions (data points 251). The graph 250 also shows flash memory array read current data points including a surround above a plurality of active regions (data points 252). The data points of bit cells without a surround above the active region show a median read current at ~35.5 uA (data points 251), and the data points of bit cells including a surround above the active region show a median read current at ~37.5 (data points 252), thus depicting an increase in read current of 2 uA.

[0038] Figures 3(a)-3(i) and Figures 4(a)-4(i) manufacturing steps that can be used to fabricate bit cells (e.g., bit cells 80) and compensate for floating gate layer (e.g., floating gate 19) thickness variations by increasing the surrounding area of a corresponding word line gate layer (e.g., word line gate layer 20) above a respective active region (e.g., region 102).Figures 3(a)-3(i) Illustrative steps that can be observed in the Y-Z plane (along line 50; Fig. 1(a)) are illustrated, and Figures 4(a)-4(i) Illustrative steps that can be observed in the X-Z plane (along line 60; Fig. 1(a)) are depicted. For simplicity, in Figures 3(a)-3(i) and Figures 4(a)-4(i) only one bit cell and its corresponding floating gate layer, word line gate layer, and active region are depicted in Figs. 3(a) and 4(a). However, as noted above, the above illustrations can apply to multiple floating gate layers, multiple bit cells, and multiple their corresponding word lines and active regions.

[0039] In some examples, the substrate 65 can comprise silicon. In one such example, the dielectric layer 66 can be silicon dioxide and the floating gate layer 19 can comprise polysilicon.

[0040] As noted above, after the self-alignment process, the thickness of the floating gate layer can be higher or lower than the target thickness c, and Figs. 3(a) and 4(a) depict one such floating gate layer 19. Fig. 3(a) also depicts the substrate 65, the dielectric layer 66. Fig. 4(a) also depicts the substrate 65, the dielectric layer 66 (or 88), the shallow trench isolation structures 90, 92, and the floating gate 19, which is aligned along line 35 with the tops of the shallow trench isolation structures 90, 92. In other words, the shallow trench isolation structures 90, 92 extend into the substrate 65 from line 35.

[0041] Fig. 4(b) depicts a recess that can be constructed in the shallow trench isolation structures 90, 92 based at least in part on the above-described calculated thickness variation value. On the other hand, Fig. 3(b) depicts a structure that is generally similar to Fig. 3(a). This can be because the etching step performed to construct the recess (depicted in Fig. 4(a)) has no effect on the Y-Z plane.

[0042] Figs. 3(c) and 4(c) depict subsequent steps in the fabrication process after etching the shallow trench isolation structures 90, 92. Figs. 3(c) and 4(c) depict the formation of a cell punch through implant layer 11 from the perspective of both the X-Z plane and the Y-Z plane, respectively. Figs. 3(c) and 4(c) also depict an additional dielectric layer (66, 67) deposited over the floating gate layer 19. Figs. 3(c) and 4(c) further depict the deposition of a control gate layer 18 and a dielectric layer 69 over the control gate layer 18. In some examples, the dielectric layers 67, 69 can comprise silicon nitride, and the dielectric layer 66 can comprise silicon dioxide. In some examples, the foregoing deposition steps can be performed by chemical vapor deposition.

[0043] Figure 3(d) further depicts the partial formation of the bit cell stack. Figure 3(d) depicts the patterned control gate layer 18 and the dielectric layers 66, 67, 69 positioned above the control gate layer 18. Figure 4(d) depicts a similar structure as depicted in Figure 4(b).

[0044] Figures 3(e) and 4(e) depict the patterned floating gate layer 19. In some examples, at this stage of the manufacturing process, another implant layer 8 can be formed in the substrate 65. This implant can be carried out by using ion implantation techniques (or any other related techniques). The implant layer 8 is depicted in Figures 3(e) and 4(e). Figure 4(e) depicts the shallow trench isolation layer structure 90, 92 being partially etched (as a result of the etching performed in Figure 4(b)).

[0045] Figures 3(f) and 4(f) depict (in both Figures 3(f) and 4(f)) the additional dielectric layer 68 (sometimes referred to as a gap oxide layer) formed above the dielectric layer 66. Figure 3(f) also depicts the source line layer 34, which can be formed using ion implantation. In some examples, both the dielectric layers 66 and 68 can comprise silicon dioxide, and thus can be referred to as a single dielectric layer 66. As mentioned above, the shallow trench isolation structure 90, 92 can be etched at different locations in the manufacturing chain. For simplicity, it is assumed that the shallow trench isolation structure 90, 92 is not etched in Figure 4(b). In this scenario, the shallow trench isolation structure 90, 92 can be etched in Figure 4(f) using a thickness variation value in order to increase the surrounding area above the active areas 36, 38 as depicted in Figure 4(g). Figure 4(g) depicts the recesses structured in the shallow trench isolation areas 90, 92 based in part on the aforementioned thickness variation value. Figure 3(g) depicts a similar structure as Figure 3(f), but with the dielectric layer 66 having a reduced thickness. Figures 3(h) and 4(h) depict the additional polysilicon layer 39. The polysilicon layer 39 can be deposited using chemical vapor deposition techniques. Figure 4(h) depicts the polysilicon layer 39 arranged in part in the interior as depicted in Figure 4(g). Figures 3(i) and 4(i) depict the patterned polysilicon layer 39. After patterning, the polysilicon layer 39 can be transformed into the word line gate layer 20 and the erase gate layer 16. Figure 4(i) depicts a similar structure as Figure 3(g), but with the patterned polysilicon layer 39 referred to as the word line gate layer 20. This word line gate layer 20 arranged in part in the shallow trench isolation structure 36, 38 increases the surrounding of the word line gate layer 20 above the active areas 102, which further compensates for the read current variation due to the thickness variation of the floating gate layer 19.

[0046] In the foregoing discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "couples" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection can be through a direct connection or through an indirect connection via other devices and connections.

[0047] The above discussion is meant to be illustrative of the principles and various examples of the application. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be construed to include all such variations and modifications.

Claims

1. A semiconductor device comprising: Silicon substrate; a plurality of trenches extending from a surface of the silicon substrate into the silicon substrate; a plurality of active regions in the silicon substrate, each active region positioned between a different pair of consecutive trenches in the plurality of trenches; a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active areas; as well as A gate layer is disposed on the dielectric layer and extends at least partially into each of the plurality of trenches. 2 . The semiconductor device according to claim 1 , wherein each of the plurality of active regions comprises at least one implantation layer. 3 . The semiconductor device of claim 1 , wherein portions of the dielectric layer in the plurality of trenches form a plurality of shallow trench isolation regions. 4 . The semiconductor device of claim 1 , wherein a portion of the dielectric layer on the active region forms a gate oxide of the gate layer. 5 . The semiconductor device of claim 1 , wherein the gate layer comprises polysilicon, and the dielectric layer comprises silicon dioxide. The semiconductor device according to claim 1 , wherein each of the plurality of active regions comprises an anti-punch-through layer.

7. The semiconductor device according to claim 1, wherein the silicon substrate includes a plurality of memory cells. 8 . The semiconductor device according to claim 1 , wherein the gate layer corresponds to a word line gate layer of a split-gate flash memory cell.

9. The semiconductor device according to claim 8, further comprising: The floating gate of the split-gate flash memory cell is arranged above the silicon substrate and adjacent to the word line gate layer.

10. The semiconductor device according to claim 9, further comprising: An erase gate of the split-gate flash memory cell partially overlaps the floating gate.

11. The semiconductor device according to claim 10, further comprising: The control gate of the split-gate flash memory cell is disposed above the floating gate and between the word line gate layer and the erase gate. 12 . The semiconductor device of claim 11 , wherein the word line gate layer, the floating gate, the erase gate, and the control gate comprise polysilicon.

13. A semiconductor die comprising: A memory array, each memory cell in the memory array comprising: a first trench and a second trench extending into the silicon substrate; an active region in the silicon substrate, the active region being positioned between the first trench and the second trench; a dielectric layer disposed in each of the first trench and the second trench and on the active area; a word line gate layer disposed on the dielectric layer and extending at least partially into each of the first trench and the second trench; a floating gate layer over the active area; a control gate layer over the floating gate layer; and An erase gate layer is on a side of the control gate layer opposite the word line gate layer. The semiconductor die of claim 13 , wherein the active region comprises at least one implant layer. 15 . The semiconductor die of claim 13 , wherein portions of the dielectric layer in the first and second trenches form shallow trench isolation regions. 16 . The semiconductor die of claim 13 , wherein the portion of the dielectric layer over the active region forms a gate dielectric layer of the word line gate layer.

17. The semiconductor die of claim 13, wherein the floating gate layer comprises polysilicon and the dielectric layer comprises silicon dioxide.

18. The semiconductor die of claim 13, wherein the active region comprises an anti-punch-through layer.

19. The semiconductor die of claim 13, wherein the memory cell is a split-gate flash memory cell.

20. The semiconductor die of claim 13, wherein the word line gate layer, the floating gate layer, the erase gate layer, and the control gate layer comprise polysilicon.

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