Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a substrate and a monolithic package. The substrate has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening extending between the first surface and the second surface and respectively exposing the plurality of side surfaces. The monolithic package includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate, and a third portion disposed within the first opening and the second opening.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method for manufacturing the same. The present disclosure relates to a semiconductor device package including a double-sided molding structure and a method for manufacturing the same. Background Art

[0002] In order to reduce the area or footprint of a semiconductor device package, electronic components may be mounted to the upper and lower surfaces of a substrate. In order to protect the electronic components mounted on the substrate, a double-sided molding technique may be used to form a package body on each of the upper and lower surfaces of the substrate. Such double-sided molding techniques may include two separate or individual molding operations (e.g., forming a first package body to cover the upper surface, and then forming a second package body to cover the lower surface), which may increase the time and cost of manufacturing the semiconductor device package. Summary of the invention

[0003] In one aspect, according to some embodiments, a semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening extending between the first surface and the second surface and respectively exposing the plurality of side surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate, and a third portion disposed within the first opening and the second opening.

[0004] On the other hand, according to some embodiments, a semiconductor device package includes a substrate, an encapsulant, and a conductive pillar. The substrate has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface and the second surface of the substrate. The encapsulant defines an opening. The conductive pillar is disposed in the opening. A portion of the encapsulant is disposed between the conductive pillar and the substrate.

[0005] On the other hand, according to some embodiments, a method for manufacturing a semiconductor device package includes: (a) providing a substrate strip comprising a plurality of singulation lines and a plurality of substrate units disposed between the singulation lines, wherein each of the substrate units has a first surface and a second surface opposite to the first surface, and defines at least two openings adjacent to the singulation lines and penetrating the corresponding substrate units; and (b) causing an encapsulant to flow from the first surface of the substrate unit through the openings to the second surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that various features may not be drawn to scale and that the sizes of features depicted in the drawings may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0008] Figure 1B A bottom view of a semiconductor device package according to some embodiments of the present invention is illustrated.

[0009] Figure 1C A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 1D An enlarged view of a portion of a semiconductor device package according to some embodiments of the present invention is illustrated.

[0011] Figure 2 A bottom view of a semiconductor device package according to some embodiments of the present disclosure is illustrated.

[0012] Figure 3A A bottom view of a semiconductor device package according to some embodiments of the present disclosure is illustrated.

[0013] Figure 3B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0014] Figure 3C A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0015] Figure 4 A bottom view of a semiconductor device package according to some embodiments of the present disclosure is illustrated.

[0016] Figure 5A A bottom view of a semiconductor device package according to some embodiments of the present disclosure is illustrated.

[0017] Figure 5B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0018] Figure 6 A bottom view of a semiconductor device package according to some embodiments of the present disclosure is illustrated.

[0019] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G and Figure 7HA method of manufacturing a semiconductor device package according to some embodiments of the present disclosure is described.

[0020] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F A method of manufacturing a semiconductor device package according to some embodiments of the present disclosure is described.

[0021] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements.The present invention will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0022] Figure 1A Cross-sectional views illustrating some embodiments of a semiconductor device package 1 according to a first aspect of the present invention. The semiconductor device package 1 comprises a substrate 10; electronic components 11a, 11b, 11c; a package body 12 and a conductive layer 13.

[0023] The substrate 10 may be, for example, a printed circuit board (PCB), for example, a paper-based copper foil laminate, a composite copper foil laminate, a polymer-impregnated glass fiber copper foil laminate, or a combination of two or more thereof. The substrate 10 may include an interconnect structure, such as a redistribution layer (RDL). The substrate 10 has a top surface 101 (also referred to as a "first surface") and a bottom surface 102 (also referred to as a "second surface") opposite to the top surface 101. The substrate 10 defines through holes (or openings) 10h1 and 10h2 that penetrate the substrate 10. In some embodiments, the through holes 10h1 and 10h2 of the substrate 10 are adjacent to the edge of the substrate 10. In some embodiments, the through holes 10h1 and 10h2 are gaps between the substrate 10 and the conductive layer 13.

[0024] One or more electrical contacts 10b are disposed on the bottom surface 102 of the substrate 10 and can be electrically connected to the top surface 101 of the substrate 10 through an interconnect structure. In some embodiments, the electrical contacts 10b are controlled collapse chip connection (C4) bumps, solder bumps, one or more land grid arrays (LGA), or a combination of two or more thereof. A portion of each of the one or more electrical contacts 10b is exposed from the package body 12 to provide electrical connection between the semiconductor device package 1 and other circuits or conductive pads. In some embodiments, the electrical contacts 10b are copper pillars.

[0025] Electronic components 11a and 11b are disposed on the top surface 101 of the substrate 10. The electronic component 11a may be an active component, such as an integrated circuit (IC) chip or die. The electronic component 11b may be a passive component, such as a capacitor, a resistor, or an inductor. The electronic components 11a and 11b may be electrically connected to one or more of another electronic component and / or the substrate 10 (e.g., to an interconnect layer), and the electrical connection may be achieved by means of flip chip or wire bonding techniques.

[0026] The electronic component 11c is disposed on the bottom surface 102 of the substrate 10. The electronic component 11c may be an active component (e.g., an IC chip or die) or a passive component (e.g., a capacitor, a resistor, or an inductor). The electronic component 11c may be electrically connected to the substrate 10 (e.g., to an interconnect layer), and the electrical connection may be achieved by means of flip chip or wire bonding technology. The electronic component 11c may be electrically connected to the electronic components 11a and 11b through the interconnect layer within the substrate 10.

[0027] The package body 12 includes portions 12a, 12b, and 12c, and covers or encapsulates the substrate 10; the electronic components 11a, 11b, 11c, and a portion of the electrical contact 10b. The portion 12a of the package body 12 is disposed on the top surface 101 of the substrate 10, and may extend laterally beyond the substrate 10, and covers the electronic components 11a and 11b. The portion 12b of the package body 12 is disposed on the bottom surface 102 of the substrate 10, and may extend laterally beyond the substrate 10, and covers a portion of the electronic component 11c and the electrical contact 10b. The portion 12c of the package body 12 is disposed in the through holes 10h1 and 10h2 of the substrate 10. In some embodiments, the portions 12a, 12b, and 12c of the package body 12 are formed in a single process and may be integrally formed. For example, the package body 12 is a single structure including a molding compound (or encapsulant). For example, during a process for forming the package body 12, the through holes 10h1 and 10h2 of the substrate 10 allow the molding compound to flow from the top surface 101 to the bottom surface 102, or from the bottom surface 102 to the top surface 101, to form the package body 12 in a single process. In some embodiments, the package body 12 includes an epoxy resin with a filler, a molding compound (such as an epoxy molding compound or other molding compounds), a polyimide, a phenolic compound or material, a material with silicone dispersed therein, or a combination thereof.

[0028] The conductive layer 13 is disposed on at least a portion of the outer surface of the package body 12 and covers the package body 12. For example, the conductive layer 13 is disposed on the top surface 121 of the package body 12 and a portion of the side surface 122 of the package body 12. The conductive layer 13 is electrically connected to a ground element (not shown) of the substrate 10. In some embodiments, the conductive layer 13 is a conformal shielding layer. In some embodiments, the conductive layer 13 is a conductive film and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, alloy or other combination thereof. The conductive layer 13 may include a single conductive layer or a plurality of conductive layers.

[0029] Figure 1B A bottom view of a semiconductor device package 1 according to some embodiments of the present disclosure is illustrated. Figure 1A A cross-sectional view of a semiconductor device package 1 is taken across Figure 1B The line A-A' in is intercepted. Figure 1B As shown in FIG. 1 , the through holes 10h1 and 10h2 are adjacent to the respective side surfaces of the substrate 10, and each of the through holes 10h1 and 10h2 is located in the middle or near the middle of the respective corresponding edge of the substrate 10 (e.g., spaced apart from the end of the corresponding edge by a distance in the range of about 40% to about 60% of the total length of the corresponding edge). The semiconductor device package 1 further includes a conductive pillar 14 disposed at a corner of the semiconductor device package 1. The conductive pillar 14 may include metal, alloy, or other conductive materials.

[0030] Figure 1C Illustration of a diagram taken across line BB' according to some embodiments of the present disclosure Figure 1B FIG. 1 is a cross-sectional view of a semiconductor device package 1 in FIG. Figure 1C As shown in FIG, the conductive pillar 14 is disposed on the bottom surface 102 of the substrate 10 and is partially covered by the second portion 12b of the package body 12. For example, the side surface of the conductive pillar 14 is exposed from the package body 12. The portion of the conductive pillar 14 exposed from the package body 12 contacts the conductive layer 13.

[0031] Figure 1D Description of some embodiments of the present disclosure Figure 1C FIG. 1 is an enlarged view of a portion of the semiconductor device package 1 surrounded by a dotted square A. Figure 1DAs shown in , the conductive pillar 14 is separated from the bottom surface 102 of the substrate 10 by the second portion 12b of the package body 12. For example, a portion of the second portion 12b of the package body 12 is disposed between the conductive pillar 14 and the bottom surface 102 of the substrate 10. For example, there is a gap between the conductive pillar 14 and the bottom surface 102 of the substrate 10. For example, the conductive pillar 14 is spaced apart from the bottom surface 102 of the substrate 10. For example, the conductive pillar 14 is electrically insulated from the substrate 10.

[0032] In the comparative semiconductor device package omitting the conductive pillar, the heat generated inside the semiconductor device package is dissipated to the outside through the molding compound. However, compared with conductive materials (such as metals), the thermal conductivity of the molding compound is relatively low, and thus the heat dissipation performance of the comparative semiconductor device package is poor. Figure 1C and Figure 1D In the embodiment of the present invention, the conductive pillar 14 can provide a heat dissipation path for the semiconductor device package 1. For example, the heat generated by the electronic components 11a, 11b and 11c or any other electronic components in the semiconductor device package 1 can be dissipated to the outside of the semiconductor device package 1 through the conductive pillar 14, which will improve the heat dissipation performance of the semiconductor device package 1. In addition, since the conductive layer 13 is in contact with the package body 12 (which may include the portions 12a, 12b and 12c), the substrate 10 and the side surfaces of the conductive pillar 14, the conductive layer 13 can further improve the heat dissipation performance of the semiconductor device package 1.

[0033] Figure 2 A bottom view of a semiconductor device package 2 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 2 is similar to Figure 1B , except that in the semiconductor device package 2, the through holes 10h1, 10h2 are disposed at the corners of the semiconductor device package 2, and each of the conductive pillars 14 is disposed in the middle or near the middle of the respective corresponding edge of the substrate 10 (e.g., spaced apart from the end of the corresponding edge by a distance in the range of about 40% to about 60% of the total length of the corresponding edge). In some embodiments, the cross-sectional view of the semiconductor device package 2 taken along the line A-A' is similar to Figure 1A In some embodiments, a cross-sectional view of the semiconductor device package 2 taken along line BB' is similar to Figure 1C 2 is a cross-sectional view of a semiconductor device package 1 shown in FIG.

[0034] Figure 3A A bottom view of a semiconductor device package 3 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 3 is similar to Figure 1BThe semiconductor device package 1 in FIG. 1 is different in that the semiconductor device package 3 further includes a frame plate 30 disposed along the electrical contacts 10 b. For example, the frame plate 30 and the electrical contacts 10 b are arranged along the bottom surface 102 of the substrate 10 or near the periphery of the bottom surface 102.

[0035] Figure 3B A diagram illustrating a diagram taken along line A-A' according to some embodiments of the present disclosure Figure 3A 10b). The frame board 30 is disposed on the electrical contact 10b. The frame board 30 may include at least one through hole penetrating the frame board 30 to provide an electrical connection for the electrical contact 10b (not shown). In some embodiments, the bottom surface 302 of the frame board 30 is exposed from the package body 12. The frame board 30 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0036] Figure 3C Illustration of a diagram taken along line B-B' according to some embodiments of the present disclosure Figure 3A 2 is a cross-sectional view of a semiconductor device package 3 in FIG. Figure 3C The semiconductor device package 3 is similar to Figure 1C The semiconductor device package 3 is different from the semiconductor device 1 in that it further includes a frame plate 30 disposed on the electrical contacts 10b.

[0037] Figure 4 A bottom view of a semiconductor device package 4 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 4 is similar to Figure 3A , except that in the semiconductor device package 4, the through holes 10h1, 10h2 are disposed at the corners of the semiconductor device package 4, and each of the conductive pillars 14 is disposed in the middle or near the middle of the respective corresponding edge of the substrate 10 (e.g., spaced apart from the end of the corresponding edge by a distance in the range of about 40% to about 60% of the total length of the corresponding edge). In some embodiments, the cross-sectional view of the semiconductor device package 4 taken along the line A-A' is similar to Figure 3B In some embodiments, a cross-sectional view of a semiconductor device package 4 taken along line BB' is similar to Figure 3C 2 is a cross-sectional view of a semiconductor device package 3 shown in FIG.

[0038] Figure 5A A bottom view of a semiconductor device package 5 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 5 is similar to Figure 3A The semiconductor device package 3A in FIG. 5 is different in that the frame plate 50 of the semiconductor device package 5 further extends to the second portion 12b of the package body 12. Figure 5B As shown, it illustrates the view taken along line A-A' Figure 5A , the frame plate 50 extends under the through holes 10h1 and 10h2. For example, the side surface 503 of the frame plate 50 is substantially coplanar with the side surface 123 of the package body 12. In some embodiments, the cross-sectional view of the semiconductor device package 5 taken along the line BB' is similar to Figure 3C 1. The frame plate 50 may define an opening or recess that accommodates the conductive pillars 14. There may be a corresponding gap between the frame plate 50 and each of the conductive pillars 14.

[0039] Figure 6 A bottom view of a semiconductor device package 6 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 6 is similar to Figure 5A , except that in the semiconductor device package 6, the through holes 10h1, 10h2 are disposed at the corners of the semiconductor device package 6, and each of the conductive pillars 14 is disposed in the middle or near the middle of the respective corresponding edge of the substrate 10 (e.g., spaced apart from the end of the corresponding edge by a distance in the range of about 40% to about 60% of the total length of the corresponding edge). In some embodiments, the cross-sectional view of the semiconductor device package 6 taken along the line A-A' is similar to Figure 5B In some embodiments, a cross-sectional view of a semiconductor device package 6 taken along line BB' is similar to Figure 3C 1. The frame plate 50 may define an opening or recess that accommodates the conductive pillars 14. There may be a corresponding gap between the frame plate 50 and each of the conductive pillars 14.

[0040] According to some embodiments of the method of manufacturing a semiconductor device package of the present disclosure, Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G and Figure 7H are cross-sectional views of semiconductor structures at various stages of fabrication. The figures have been simplified to more clearly present aspects of the disclosure.

[0041] refer to Fig. 7A, a carrier strip (or carrier panel) including a carrier (or substrate) 70 is provided. The carrier strip defines a plurality of openings (or through holes) 70h penetrating the carrier strip. Electronic components 11a and 11b are disposed on a surface 701 of the carrier strip, and electronic component 11c is disposed on a surface 702 of the carrier strip opposite to surface 701. In some embodiments, electronic components 11a, 11b, and 11c are disposed on the carrier strip by surface mounting technology, wire bonding technology, or flip chip technology. Electrical contacts 10b are disposed on the surface 702 of the carrier strip. In some embodiments, electrical contacts 10b are solder bumps or copper pillars.

[0042] refer to Figure 7B , the carrier strip is disposed in the molding cavity 78. The molding cavity 78 includes a first mold sleeve 78a and a second mold sleeve 78b corresponding to the first mold sleeve 78a. In some embodiments, the edge of the carrier strip is sandwiched by the first mold sleeve 78a and the second mold sleeve 78b to fix the carrier strip during the molding process. In some embodiments, the first mold sleeve 78a includes one or more protruding structures 78c (e.g., dummy runners) in contact with the surface 702 of the carrier strip. A molding material 79 is injected or applied to the second mold sleeve 78b. The molding material 79 may include an epoxy resin including a filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0043] refer to Figure 7C , the plate 78b1 of the second mold set 78b moves toward the first mold set 78a to promote the molding material 79 to flow from the surface 701 of the carrier strip through the opening 70h to the surface 702 of the carrier strip. Then, the molding material 79 is cured or hardened by providing heat to the molding material 79 to form an encapsulant 79' covering the electronic components 11a, 11b, 11c and the electrical contacts 10b. For example, the encapsulant 79' is formed by a compression molding technique.

[0044] refer to Fig.7D ,Will Figure 7C The structure in the mold cavity 78 is removed. A grinding process is performed on the surface 791 of the encapsulant 79' to expose a portion of the electrical contact 10b. Figure 7C After the structures in are removed from the molding cavity 78, the one or more openings 79h corresponding to the one or more protruding structures 78c expose one or more portions of the surface 702 of the carrier strip that are in contact with the one or more protruding structures 78c.

[0045] refer to Fig. 7E , the opening 79h is filled with a conductive material to form a conductive column 74. Then, singulation can be performed to separate individual semiconductor device packages, such as Figure 7FThat is, singulation is performed through the encapsulant 79' and the carrier strip containing the carrier 70. For example, singulation is performed by using a dicing saw, a laser or other suitable cutting technology.

[0046] In some embodiments, Figure 7G , which illustrates that carrier strips from surface 702 may be singulated along lines A-A' and BB' which may be singulation lines. Figure 7G , the portion of the carrier strip enclosed by the dotted square is the portion in which one or more protruding structures 78c of the molding cavity 78 are disposed. Figure 7H , which illustrates that carrier strips from surface 702 may be singulated along lines A-A' and BB' which may be singulation lines. Figure 7H , the portion of the carrier strip enclosed by the dotted square is the portion in which the one or more protruding structures 78c of the molding cavity 78 are disposed.

[0047] like Figure 7F As shown in FIG. 1 , a conductive layer 73 is formed to cover surfaces 792 and 793 of the encapsulant 79′, a side surface 703 of the carrier 70, and a portion of a side surface of the conductive pillar 74. In some embodiments, the conductive layer 73 is formed, for example, by sputtering or other suitable techniques. In some embodiments, Figure 7F The semiconductor device package in Figure 1A A semiconductor device package 1 is provided.

[0048] According to some embodiments of the method of manufacturing a semiconductor device package of the present disclosure, Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F are cross-sectional views of semiconductor structures at various stages of fabrication. The figures have been simplified to more clearly present aspects of the disclosure.

[0049] refer to Fig. 8A, a carrier strip (or carrier panel) including a carrier (or substrate) 70 is provided. The carrier strip defines a plurality of openings (or through holes) 70h penetrating the carrier strip. Electronic components 11a and 11b are disposed on a surface 701 of the carrier strip, and electronic component 11c is disposed on a surface 702 of the carrier strip opposite to the surface 701. In some embodiments, the electronic components 11a, 11b, and 11c are disposed on the carrier strip by surface mounting technology, wire bonding technology, or flip chip technology. The electrical contact 10b is disposed on the surface 702 of the carrier strip. In some embodiments, the electrical contact 10b is a solder bump or a copper pillar. A frame plate 80 attached to an adhesive layer 80h is disposed on the electrical contact 10b. In some embodiments, the adhesive layer 80h comprises a thermal tape.

[0050] refer to Figure 8B , the carrier strip is disposed in the molding chamber 78. The molding chamber 78 includes a first mold sleeve 78a and a second mold sleeve 78b corresponding to the first mold sleeve 78a. In some embodiments, the edge of the carrier strip is sandwiched by the first mold sleeve 78a and the second mold sleeve 78b to fix the carrier strip during the molding process. In some embodiments, the first mold sleeve 78a includes one or more protruding structures 78c (e.g., dummy runners) that contact the surface 702 of the carrier strip.

[0051] The molding material 79 is injected or applied to the second mold sleeve 78b. The molding material 79 may include epoxy resin including fillers, molding compounds (such as epoxy molding compounds or other molding compounds), polyimide, phenolic compounds or materials, materials including silicone dispersed therein, or combinations thereof.

[0052] refer to Figure 8C , the plate 78b1 of the second mold set 78b moves toward the first mold set 78a to promote the molding material 79 to flow from the surface 701 of the carrier strip through the opening 70h to the surface 702 of the carrier strip. Then, the molding material 79 is cured or hardened by providing heat to the molding material 79 to form an encapsulant 79' covering the electronic components 11a, 11b, 11c; the electrical contacts 10b and the frame plate 80. For example, the encapsulant 79' is formed by a compression molding technique.

[0053] refer to Fig.8D ,Will Figure 8C The structure in is removed from the molding cavity 78, and the adhesive layer 80h is removed from the frame plate 80. Figure 8C After the structures in are removed from the molding cavity 78, the one or more openings 79h corresponding to the one or more protruding structures 78c expose one or more portions of the surface 702 of the carrier strip that are in contact with the one or more protruding structures 78c.

[0054] refer to Fig. 8E, the opening 79h is filled with a conductive material to form a conductive column 74. Then, singulation can be performed to separate individual semiconductor device packages, such as Fig.8F That is, singulation is performed through the encapsulant 79' and the carrier strip containing the carrier 70. For example, singulation is performed by using a dicing saw, a laser or other suitable cutting technology.

[0055] Next, a conductive layer 73 is formed to cover the surfaces 792 and 793 of the encapsulant 79', the side surface 703 of the carrier 70, and a portion of the side surface of the conductive pillar 74. In some embodiments, the conductive layer 73 is formed, for example, by sputtering or other suitable techniques. In some embodiments, Fig.8F The semiconductor device package in Figure 3B Semiconductor device package 3.

[0056] according to FIG. 7A to FIG. 7H as well as Fig. 8A , Fig.8F In the embodiment of the present invention, by forming the opening 70h to penetrate the carrier strip, the molding material 79 can flow from one surface of the carrier strip to the opposite surface of the carrier strip, and thus a double-sided molding operation can be achieved in a single molding process, which will reduce the time and cost of manufacturing the semiconductor device package. In addition, the formation of the conductive pillar 74 can provide a heat dissipation path for the semiconductor device package, which will improve the heat dissipation performance of the semiconductor device package.

[0057] As used herein, the terms "substantially," "largely," "approximately," and "about" may be used to describe and take into account small variations. When used in conjunction with an event or circumstance, the terms may refer to situations where the event or circumstance clearly occurs as well as situations where the event or circumstance is very close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered "substantially" or "approximately" the same if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%). For example, "substantially" parallel may refer to an angular variation range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" vertical may refer to an angular variation range of less than or equal to ±10° relative to 90° (e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°).

[0058] If the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the two surfaces are considered to be coplanar or substantially coplanar. If the difference between the highest point and the lowest point of the surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the surface is considered to be planar or substantially planar.

[0059] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens / meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m (e.g. at least 10 5 S / m or at least 10 6S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0060] As used herein, the singular terms "a", "an", and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intervening components are located between the former component and the latter component.

[0061] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made without departing from the true spirit and scope of the present invention as defined by the appended claims, and equivalent components may be substituted in the embodiments. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction and the actual device in the present invention. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A semiconductor device package, comprising: A substrate (10) having a first surface (101) and a second surface (102) opposite to the first surface, wherein the substrate defines a first opening (10h1) extending between the first surface and the second surface of the substrate; an encapsulant (12) covering the first surface and the second surface of the substrate, wherein the encapsulant has a first portion (12c) disposed in the first opening; a frame plate (30) disposed on the second surface of the substrate, wherein the frame plate defines a second opening; as well as a conductive column (14) disposed in the second opening, The encapsulant has a second portion disposed between the conductive pillar and the substrate.

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