System and method for generating Gaussian random numbers using hardware acceleration

Abstract

Described herein is hardware acceleration of random number generation for machine learning and deep learning applications. An apparatus (700) includes a uniform random number generator (URNG) circuit (710) for generating uniform random numbers, and an adder circuit (750) coupled to the URNG circuit (710). The adder circuit hardware (750) accelerates the generation of Gaussian random numbers for use in machine learning.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via general purpose graphics processing units. In particular, embodiments relate to systems and methods for generating Gaussian random numbers with hardware acceleration. Background Art

[0002] Current parallel graphics data processing involves the development of systems and methods for performing specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling these processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempts to process as much graphics data as possible in parallel in different parts of the graphics pipeline. Parallel graphics processors with a single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously as frequently as possible to improve processing efficiency. A general overview of the software and hardware for a SIMT architecture can be found in Shane Cook, CUDA Programming Chapter 3, pages 37-51 (2013).

[0004] For random number generation, Box-muller, cumulative density function (CDF) inversion, transformation, rejection, and recursive methods are commonly used. CDF inversion methods simply invert the CDF to generate random numbers from the desired distribution. Transformation methods involve directly transforming uniform random numbers into a Gaussian distribution. The third category, rejection, again starts with uniform random numbers and transformations, but has an additional step of conditionally rejecting certain transformed values. Recursive (the final category) utilizes linear combinations of previously generated Gaussian numbers to generate new outputs. The Box-muller method is time-consuming and slow to generate Gaussian random numbers. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Thus, in order that the manner in which the above-described features of the present invention may be understood in detail, a more particular description of the embodiments briefly summarized above may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope.

[0006] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0007] Figure 2A-2D shows a parallel processor assembly according to an embodiment;

[0008] Figure 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0009] Figures 4A-4F An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0010] Figure 5 shows a graphics processing pipeline according to an embodiment;

[0011] Figure 6 A method 600 for generating Gaussian random numbers using hardware acceleration is shown according to an embodiment.

[0012] Figure 7 A block diagram of a system for generating Gaussian random numbers using hardware acceleration is shown, according to one embodiment.

[0013] Figure 8 A timing diagram for generating Gaussian random numbers according to one embodiment is shown.

[0014] Figure 9 A machine learning software stack is shown, according to an embodiment.

[0015] Figure 10 A highly parallel general purpose graphics processing unit is shown in accordance with an embodiment.

[0016] Figure 11 A multi-GPU computing system is shown in accordance with an embodiment.

[0017] Figures 12A-12B The layers of an exemplary deep neural network are shown.

[0018] Figure 13 An exemplary recurrent neural network is shown.

[0019] Figure 14 Demonstrates the training and deployment of a deep neural network.

[0020] Figure 15 is a block diagram illustrating distributed learning.

[0021] Figure 16 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is shown;

[0022] Figure 17 is a block diagram of a processing system 1700 according to an embodiment;

[0023] Figure 18is a block diagram of an embodiment of a processor 1800 having one or more processor cores 1802A-1802N, an integrated memory controller 1814, and an integrated graphics processor 1808;

[0024] Figure 19 is a block diagram of a graphics processor 1800 , which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores;

[0025] Figure 20 is a block diagram of a graphics processing engine 2010 of a graphics processor according to some embodiments;

[0026] Figure 21 is a block diagram of another embodiment of a graphics processor 2100;

[0027] Figure 22 shows thread execution logic 2200, which comprises an array of processing elements employed in some embodiments of a GPE;

[0028] Figure 23 is a block diagram illustrating a graphics processor instruction format 2300 according to some embodiments;

[0029] Figure 24 is a block diagram of another embodiment of a graphics processor 2400;

[0030] Figure 25A is a block diagram illustrating a graphics processor command format 2500 according to some embodiments;

[0031] Figure 25B is a block diagram illustrating a graphics processor command sequence 2510 according to an embodiment;

[0032] Figure 26 illustrates an exemplary graphics software architecture for data processing system 2600 according to some embodiments;

[0033] Figure 27 is a block diagram illustrating an IP core development system 2700 that may be used to manufacture integrated circuits to perform operations according to an embodiment; and

[0034] Figures 28-30 An exemplary integrated circuit and associated graphics processor are shown that may be fabricated using one or more IP cores in accordance with various embodiments described herein.

[0035] Other logic and circuitry may be included in addition to that shown, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores. DETAILED DESCRIPTION

[0036] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign jobs to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0037] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the current embodiments.

[0038] System Overview

[0039] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104 communicating via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset component or may be integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which may enable computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may implement a display controller, which may be included in one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0040] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0041] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform and various other devices that may be added via one or more accessory devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radios.

[0042] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. The use of the I / O hub 107 may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI Express) or any other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect) or interconnect protocols known in the art. Figure 1 The communication paths that interconnect the various components in a system.

[0043] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while maintaining the basic computing architecture described in more detail herein. In yet another embodiment, components of computing system 100 may be integrated onto a single integrated circuit along with one or more other system elements. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, components of computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0044] It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112, may be modified as desired. For example, in some embodiments, system memory 104 is connected to processor 102 directly rather than through a bridge, while other devices communicate with system memory 104 via memory hub 105 and processor 102. In other optional topologies, parallel processors 112 are connected to I / O hub 107 or directly to one of one or more processors 102 rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple sockets, which may be coupled to two or more instances of parallel processors 112.

[0045] Some of the specific components described herein are optional and may not be included in all implementations of computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be specific to the Figure 1 Components shown may use different terminology for similar components. For example, in some architectures memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0046] Figure 2A 1 shows a parallel processor 200 according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the parallel processor 200 shown is Figure 1 Variations of the one or more parallel processors 112 are shown.

[0047] In one embodiment, parallel processor 200 includes parallel processing unit (PPU) 202. PPU includes I / O unit 204, which enables communication with other devices, including other instances of PPU 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 connects to other devices via the use of a hub or switch interface (e.g., memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within PPU 202, I / O unit 204 is connected to host interface 206 and memory crossbar switch 216, where host interface 206 receives commands related to performing processing operations, and memory crossbar switch 216 receives commands related to performing memory operations.

[0048] When host interface 206 receives command buffers via I / O unit 204, it can direct job operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other job items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before tasks are distributed to processing clusters within the processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and job distribution operations at both coarse and fine granularity, enabling fast preemption and context switching of threads executing on processing array 212. In one embodiment, host software can request workloads for scheduling on processing array 212 via one of multiple graphics processing doorbells. The workloads can then be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

[0049] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or job allocation algorithms to allocate jobs to clusters 214A-214N of processing cluster array 212, which may vary depending on the workload generated for each type of program or computation. Scheduling may be dynamically manipulated by scheduler 210 or may be partially facilitated by compiler logic during the compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0050] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0051] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0052] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 214A-214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0053] During operation, processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands specifying the processing tasks from front end 208. For graphics processing operations, a processing task may include an index of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data), as well as state parameters and commands specifying how the data is to be processed (e.g., what program to execute). Scheduler 210 may be configured to retrieve an index corresponding to a task, or may receive an index from front end 208. Front end 208 may be configured to ensure that processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0054] Each of the one or more instances of parallel processing units 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion (e.g., memory cells) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding second memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0055] In various embodiments, memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of memory units 224A-224N may vary and may be selected from a variety of conventional designs. Render targets (e.g., frame buffers or texture maps) may be stored in memory units 224A-224N, allowing partitioning units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, it may be advantageous to utilize a unified memory design that combines system memory with local cache memory, eliminating local instances of parallel processor memory 222.

[0056] In one embodiment, any of the clusters 214A-214N in the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. Memory crossbar 216 can be configured to route the output of each cluster 214A-214N to any of the partition units 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with a memory interface 218 via the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has connections to memory interface 218 for communication with I / O unit 204, as well as connections to local instances of parallel processor memory 222, enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0057] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems including one or more instances of row processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0058] Figure 2B is a block diagram of the division unit 220 according to an embodiment. In one embodiment, the division unit 220 is Figure 2A 20N。 As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225 and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 is connected to the memory unit (e.g., Figure 2A One of the memory units 224A-224N (e.g., within parallel processor memory 222)) is engaged.

[0059] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stencil printing, z-testing, blending, etc.). ROP 226 then outputs the processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a plurality of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0060] In some embodiments, ROP 226 is included in each processing cluster (e.g. Figure 2AIn such an embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar switch 216. The processed graphics data can be displayed on a display device (e.g., Figure 1 10B), is routed for further processing by the processor 102, or is routed for further processing by the processor 102. Figure 2A One of the processing entities within the parallel processor 200 is processed.

[0061] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is Figure 2A 214N。Processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of usually synchronized threads using a common instruction unit, and the common instruction unit is configured to issue instructions to a group of processing engines in each of the processing clusters. Different from the SIMD execution system (wherein all processing engines generally execute the same instruction), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing system represents a functional subset of the SIMT processing system.

[0062] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. Figure 2A The scheduler 210 receives instructions and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 is shown as an illustrative instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager 232 may facilitate the distribution of the processed data by specifying the destination of the processed data distributed via the data crossbar 240.

[0063] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., an arithmetic logic unit with adder circuitry, a load-store unit, etc.). The function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In one embodiment, the same function-unit hardware may be used to perform different operations, and any combination of function units may be present.

[0064] Instructions sent to processing cluster 214 constitute threads. A group of threads executing on this set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which that thread group is processing. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed during consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0065] In one embodiment, the graphics multiprocessor 234 includes internal cache memory to perform load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and use cache memory (e.g., L1 cache 248) within the processing cluster 214. Each graphics multiprocessor 234 also has access to partition units (e.g., L1 cache 248) that are shared among all processing clusters 214. Figure 2A The L2 cache within the partition units 220A-220N of the graphics multiprocessor 234 can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 248.

[0066] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 may reside in Figure 2AThe MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tiles in a moment) and optionally a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or a cache or L1 cache that may be present within the graphics multiprocessor 234 or processing cluster 214. The physical address is processed to distribute surface data access locations to allow efficient requests to be interleaved among the partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0067] In graphics and compute applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A pre-ROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234, direct the data to the ROP unit, which may be used in conjunction with the partitioning units described herein (e.g., Figure 2A The pre-ROP 242 unit may perform optimization for color mixing, organize pixel color data, and perform address translation.

[0068] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, pre-ROP 242, etc.) may be included within a processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing clusters 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0069] Figure 2DA graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0070] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. Instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0071] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 234. Register file 258 provides temporary storage of operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to graphics multiprocessor 234. In one embodiment, register file 258 is divided between each functional unit such that each functional unit is allocated a dedicated portion of register file 258. In one embodiment, register file 258 is divided between the different warps executed by graphics multiprocessor 234.

[0072] Each of the GPGPU cores 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions for the graphics multiprocessor 234. According to embodiments of the present design, the ALU may include an adder circuit (e.g., system 700, adder circuit 750). Depending on the embodiment, the GPGPU cores 262 may be architecturally similar or architecturally distinct. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core 262 includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or implement variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed- or special-function logic.

[0073] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions of the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0074] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 234 to the register file 258 and shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 are very low latency. Shared memory 270 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. In addition to automatically caching data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0075] Figure 3A-Figure 3B Additional graphics multiprocessors are shown according to an embodiment. Graphics multiprocessors 325, 350 are shown as Figure 2C The illustrated graphics multiprocessors 320, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0076] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes information about Figure 2D The graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0077] Various components can communicate via interconnect fabric 327. In one embodiment, interconnect fabric 327 includes one or more crossbar switches to facilitate communication between the various components of graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate, high-speed network fabric layer on which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B can each communicate with shared memory 346 via interconnect fabric 327. Interconnect fabric 327 can arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth distribution between components.

[0078] Figure 3B FIG2 shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A As shown. Execution resources 356A-356D can work in conjunction with texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D can share multiple instances of instruction cache 354 and shared memory 362 as well as texture and / or data cache memories 358A-358B. Various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0079] Those skilled in the art will understand that Figure 1 、 Figure 2A-2D and Figure 3A-3B The architecture described in the present invention is illustrative and not restrictive with respect to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units such as Figure 2A The parallel processing unit 202 and one or more graphics processors or special purpose processing units may be used without departing from the scope of the embodiments described herein.

[0080] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In another embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can distribute jobs to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0081] Technologies for GPU to host processor interconnect

[0082] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 429, 440, 442, and 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 429, 440, 442, and 443 are implemented to support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0083] Furthermore, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444 and 449, which may be implemented using the same or different protocols / links as used for high-speed links 429, 440, 442, and 443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocols / links may be used (e.g., via a common interconnect fabric) to implement the multi-core processors 405-406. Figure 4A All communications between the various system components are shown. However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0084] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0085] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed throughout the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0086] Figure 4B 4 shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated with the processor 407 on the same package or chip.

[0087] The processor 407 shown includes a plurality of cores 460A-460D, each having a translation-bypass buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, recorder buffer, etc.), which are not shown to avoid obscuring the basic principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by several groups of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 - 402 .

[0088] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 via inter-core communication over a coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0089] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, allowing graphics acceleration module 446 to participate in cache coherence protocols as a core's peer. In particular, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0090] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines, media processing engines (e.g., video encoders / decoders), samplers, and BLI engines within a GPU (e.g., a graphics execution unit). In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be separate GPUs integrated into a common package, line card, or chip.

[0091] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, data stored in the cache 438 and graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and system memory 441. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates related to modifications / accesses of cache lines on processor caches 462A-462D, 456 to cache 438 and receiving updates from cache 438).

[0092] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is restored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, context management circuitry 448 may store current register values to a designated area in memory (e.g., identified by a context pointer). It may then restore the register values upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0093] In one implementation, virtual / effective addresses from the graphics processing engine 431 are translated by the MMU 439 into real / physical addresses in the system memory 441. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407 or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0094] Thus, the accelerator integrated circuit acts as a bridge to the system for graphics acceleration module 446 and provides address translation and system memory cache services. Additionally, accelerator integrated circuit 436 may provide virtualization facilities to the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0095] Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped to the real address space visible to host processor 407, any host processor can directly use effective address values to manipulate these resources. In one embodiment, one function of accelerator integrated circuit 436 is the physical separation of graphics processing engines 431-432, N so that they appear to the system as independent units.

[0096] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0097] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memories 433-434, M is data that is most frequently used by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, N) within the cores' caches 462A-462D, 456 and system memory 441.

[0098] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via a high-speed link 440 via an interface 437 and an interface 435 (which again may utilize any form of bus or interface protocol). The accelerator integrated circuit 436 may perform operations related to the graphics processing engine 431-432, N. Figure 4B The same operation as described, but possibly at higher throughput, assuming it is in close proximity to the coherency bus 464 and caches 462A-462D, 426.

[0099] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0100] In one embodiment of a dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can send other application requests to virtualized graphics processing engines 431-432, N provided within a VM / partition.

[0101] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. This shared model requires a hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0102] For the shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 441 and is addressable using the effective address to real address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (that is, calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0103] Figure 4DAn exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specific portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 441 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process element 483 contains the process state of the corresponding application 480. The job descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a queue of jobs. In the latter case, the WD 484 is a pointer to the job request queue in the application's address space 482.

[0104] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or a subset of processes in the system. Embodiments of the present invention include infrastructure for establishing process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0105] In one implementation, a dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process when the graphics acceleration module 446 is allocated.

[0106] In operation, a WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of a job completed by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 may be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448, as shown. For example, one embodiment of the MMU 439 includes fragment / page walk circuitry for accessing fragment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 may process interrupt events 492 received from the graphics acceleration module 446. When executing graphics operations, effective addresses 493 generated by the graphics processing engines 431-432, N are converted into real addresses by the MMU 439.

[0107] In one embodiment, the same set of registers 445 is repeated for each graphics processing engine 431-432, N, and / or graphics acceleration module 446 and can be initialized by the hypervisor or operating system. Each of these repeated registers can be included in the accelerator integration slice 490. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0108] Table 1 - Registers initialized by the hypervisor

[0109]

[0110]

[0111] Example registers that may be initialized by the operating system are shown in Table 2.

[0112] Table 2 - Registers initialized by the operating system

[0113] 1 Process and thread identification 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual address (VA) storage segment table pointer 5 Permission blocking 6 Job Descriptor

[0114] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information that the graphics processing engine 431-432, N needs to complete its job, or it may be a pointer to a memory location in a command queue where the application has established jobs to be completed.

[0115] Figure 4E 496 , which virtualizes the graphics acceleration module engine of the operating system 495 .

[0116] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics pointer sharing.

[0117] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization through the hypervisor 496, the graphics acceleration module 446 may adhere to the following requirements: 1) Application job requests must be autonomous (that is, state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) Application job requests are guaranteed by the graphics acceleration module 446 to complete within a specified amount of time, including any translation errors, or the graphics acceleration module 446 provides the ability to preempt the processing of jobs. 3) The graphics acceleration module 446 must be guaranteed fairness between processes when operating in a direct sharing programming model.

[0118] In one embodiment, for a shared model, application 480 requires a graphics acceleration module 446 type, a job descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can describe the job to be completed by the graphics acceleration module 446 in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application setting the AMR. If the accelerator integrated circuit 436 and graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current privilege mask overlay register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the address space 482 of the application for the graphics acceleration module 446 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. The context save / restore area may be fixed system memory.

[0119] When the system call is received, the operating system 495 can verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0120] Table 3 - OS to Hypervisor Call Parameters

[0121]

[0122]

[0123] When the hypervisor call is received, the hypervisor 496 verifies that the operating system 495 has been registered and granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 in a linked list of process elements of the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0124] Table 4 - Process element information

[0125] 1 Job Descriptor (WD) 2 The value of the Authority Mask Register (AMR) (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table obtained from hypervisor call parameters 9 Status register (SR) value 10 Logical Partition ID (LPID) 11 Real Address (RA) hypervisor accelerator utilizing record pointers 12 Storage Descriptor Register (SDR)

[0126] In one embodiment, the hypervisor initializes the plurality of registers 445 of the accelerator integrated slice 490 .

[0127] like Figure 4F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space, which is used to access physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0128] In one embodiment, bias / coherency management circuitry 494A-494E within one or more of MMUs 439A-439E ensures cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413 and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. Figure 4F Multiple instances of bias / coherence management circuits 494A- 494E are shown in , but the bias / coherence circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0129] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without the typical performance drawbacks associated with full system cache coherence. The ability to access GPU-attached memory 420-423 as system memory without the heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to create operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. In the case of heavy streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand creation, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0130] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423 with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0131] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed before the actual access to the GPU memory, resulting in the following operations. First, local requests from the GPUs 410-413 to find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPUs to find their pages in the host bias are forwarded to the processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from the processor 405 to find their requested pages in the host processor bias complete requests like normal memory reads. Alternatively, requests to pages in the GPU bias can be forwarded to the GPUs 410-413. If the GPU is not currently using the page, it can then transfer the page to the host processor bias.

[0132] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, by a purely hardware-based mechanism.

[0133] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, which directs it to change the bias state, and for some transitions, performs a cache flush operation in the host. The cache flush operation is required for the transition from the host processor 405 to the GPU bias, but not for the reverse transition.

[0134] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are pages that are needed by the GPU but not host processor 405, and vice versa.

[0135] Graphics processing pipeline

[0136] Figure 5 5. A graphics processing pipeline 500 is shown according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem (e.g., Figure 2A In one embodiment, the parallel processor 200 is Figure 1 Various parallel processing systems can be implemented via parallel processing units (e.g. Figure 2A The graphics processing pipeline 500 is implemented using one or more instances of the parallel processing unit 202 of FIG. For example, a shader unit (e.g., Figure 2D The graphics multiprocessor 234 of the graphics multiprocessor 234 may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operations unit 526 may also be performed by processors in processing clusters such as Figure 2C Other processing engines within the processing cluster 214) and corresponding partitioning units (e.g. Figure 2AThe graphics processing pipeline 500 may also be implemented using one or more dedicated processing units. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., as in a memory interface 528) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 can be Figure 2A An instance of the memory interface 218.

[0137] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, which illuminate and transform the vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0138] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0139] The tessellation control processing unit 508 processes the input vertices into control points for a geometry patch. The control points are transformed from an input representation of the patch (e.g., the basis of the patch) into a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are sent to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0140] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform the graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0141] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for use in processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0142] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use in processing the fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0143] Raster operations unit 526 is a graphics processing unit that performs raster operations (including but not limited to stenciling, z-testing, blending, etc.) and outputs pixel data as processed graphics data to be stored in graphics memory (e.g., as in Figure 2A The parallel processor memory 222 in the and / or as in Figure 1Raster operations unit 526 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0144] System and method for generating Gaussian random numbers using hardware acceleration

[0145] Embodiments of this design provide hardware acceleration for random number generation for machine learning and deep learning applications. In one example, Gaussian random number generation is important for Bayesian-based machine learning methods. Gaussian random numbers can be generated using a Gaussian random number generator algorithm (e.g., summing uniform random numbers according to the central limit theorem). Compared to traditional methods for generating Gaussian random numbers, the process is accelerated using an adder circuit. The adder circuit can be customized for generating Gaussian random numbers.

[0146] Figure 6 A method 600 for generating Gaussian random numbers using hardware acceleration according to one embodiment is shown. The method 600 can be performed by processing logic, which can include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof. In one example, at least one of an adder circuit, an arithmetic logic unit, a processor, a graphics multiprocessor, a GPGPU core, a computing cluster, and any hardware component discussed herein performs the operations of the method 600. The processes of the method 600 are shown in linear order and in parallel for the sake of brevity and clarity of description; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in a different order.

[0147] Method 600 begins at operation 602 by generating a uniform random number for use in a Gaussian random number using a uniform random number generator (URNG) circuit. The uniform random number may be sent to any adder (e.g., adder-1 in operations 604 and 622, adder-2 in operation 606, adder-N in operations 608 and 624, etc.) of an adder circuit of a hardware component (e.g., a processor, a graphics multiprocessor, a GPGPU core, a computing cluster). At operation 604, adder-1 adds (sums) two uniform random numbers (e.g., a first and a second uniform random number from the URNG circuit) to generate a first output of adder-1. At operation 606, adder-2 adds (sums) another uniform random number (e.g., a third uniform random number from the URNG circuit) to the first output to generate a first output of adder-2. Subsequent adders (e.g., Adder-3 through Adder-N-1) then continue adding additional uniform random numbers to the output from the previous adder until reaching operation 608. Adder-N adds (sums) another uniform random number (e.g., the N+1 uniform random number from the URNG circuit) to the first output of Adder-N-1 at operation 608 to generate a first Gaussian random number, which is sent to another location or stored in memory at operation 610. N can be any integer value.

[0148] At operation 622, after adder-1 completes operation 604, adder-1 can add two other uniform random numbers (for example, different uniform random numbers) to generate the second output of adder-1. Subsequent adders (for example, adder-2 to adder-N-1) then continue to add additional uniform random numbers to the output from the previous adder until reaching operation 624. At operation 624, adder N adds (sums) another uniform random number to the second output of the second output adder-N-1 to generate a second Gaussian random number, which is sent to another location or stored in a memory at operation 626. In one example, then adder-1 to adder-N continues to add uniform random numbers to generate additional Gaussian random numbers. At operation 690, the mth Gaussian random number is sent to another location or stored in a memory. In one example, method 600 is carried out according to the central limit theorem.

[0149] Figure 7A block diagram of a system for generating Gaussian random numbers using hardware acceleration according to one embodiment is shown. System 700 can be implemented using processing logic, which can include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof. In one example, adder circuit 750 can be implemented using at least one of: an arithmetic logic unit, a processor, a graphics multiprocessor, a GPGPU core, a computing cluster, and any hardware component discussed herein. Method 600 can be implemented using the following components: a uniform random number generator (URNG) circuit 710 for generating uniform random numbers and an adder circuit 750 for generating Gaussian random numbers. The uniform random number can be sent to any adder (e.g., adder-720, adder-721, ..., adder-N, etc.) of adder circuit 750 of a hardware component (e.g., a processor, a graphics multiprocessor, a GPGPU core, a computing cluster, etc.) using communications 711-713.

[0150] In one example, adder-1 adds two uniform random numbers (e.g., the first and second uniform random numbers from the URNG circuit 710) to generate a first output of adder-720. Adder-721 adds another uniform random number (e.g., the third uniform random number from the URNG circuit) to the first output to generate a first output of adder-721. Subsequent adders (e.g., adder-3 to adder-N-1) then continue to add another uniform random number to the output of the previous adder. Adder-N adds another uniform random number (e.g., the N+1 uniform random numbers from the URNG circuit 710) to the first output of adder-N-1 to generate a first Gaussian random number, which can be sent to another location or stored in a memory.

[0151] After adder-720 finishes generating the first output, adder-720 can add two more uniform random numbers (e.g., different uniform random numbers) to generate the second output of adder-721. Subsequent adders (e.g., adder-2 to adder-N-1) then continue to add another uniform random number to the output from the previous adder. Adder-N adds another uniform random number to the second output of adder-N-1 to generate a second Gaussian random number, which is sent to another location or stored in a memory. Adders-720 to adder-N then continue to add uniform random numbers to generate additional Gaussian random numbers. Figure 7 The adders in the addition of uniform random numbers can be configured in any way to generate Gaussian random numbers. Any type of adder can be used for Figure 7 The adder in .

[0152] Figure 81 shows a timing diagram for generating a Gaussian random number according to one embodiment. The timing diagram 800 includes a vertical Gaussian random number axis 812 and a horizontal time axis 810 in milliseconds. The timeline 830 represents a first time period for generating a first Gaussian random number G1. The first time period includes T A1 , T of adder-2 A2 ,..., adder-N T AN A series of delays for adding uniform random numbers to generate the first Gaussian random number G1. Timeline 840 represents the second time period, which includes T of adder-1. A1 , T of adder-2 A2 ,..., adder-N T AN A series of delays for adding uniform random numbers to generate the second Gaussian random number G2. Timeline 850 represents a third time period, which includes T of adder-1. A1 , T of adder-2 A2 ,..., adder-N T AN A series of delays are used to add uniform random numbers to generate a third Gaussian random number G3. The first, second and third time periods are approximately equal.

[0153] In one example, a first Gaussian number is generated at a first time, where the first time is equal to the adder delay of a plurality of adders -N multiplied together. A second Gaussian number is generated at a second time, where the second time is equal to the adder delay of a plurality of adders N+1 multiplied together. An mth Gaussian random number is generated at an mth time, where the mth time is equal to the adder delay of a plurality of adders N+m-1 multiplied together.

[0154] Gaussian random numbers can be generated for machine learning applications. Specifically, a hardware-accelerated method for generating a large number of Gaussian random numbers can be used for Bayesian-based machine learning applications, which may require a large number of Gaussian random numbers to be generated in a short period of time.

[0155] Machine Learning Overview

[0156] Machine learning algorithms are algorithms that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0157] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as a non-periodic curve in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. The nodes of the network are fully connected to the nodes in adjacent layers via edges, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "forward fed") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer in the network based on coefficients ("weights") associated with each edge connecting the layers. The output from the neural network algorithm can take a variety of forms, depending on the specific model represented by the algorithm being executed.

[0158] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting the weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize that error as the error signal propagates backward through the layers of the network. The network is considered "trained" when the error for each output generated based on an instance of the training data set is minimized.

[0159] The accuracy of a machine learning algorithm can be significantly affected by the quality of the dataset used to train the algorithm. The training process can be computationally intensive and can require a significant amount of time on a conventional general-purpose processor. Consequently, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally amenable to parallel implementation. In particular, many machine learning algorithms and software applications are well-suited to utilizing the parallel processing hardware found within general-purpose graphics processing devices.

[0160] Figure 9is a generalized diagram of a machine learning software stack 900. A machine learning application 902 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 902 can include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. The machine learning application 902 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, automated navigation, speech synthesis, medical imaging, or language translation.

[0161] Hardware acceleration of the machine learning application 902 can be achieved via the machine learning framework 904. The machine learning framework 904 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 904, the developer of the machine learning algorithm would need to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when a new parallel processor is developed. Alternatively, the machine learning application can be configured to use the primitives provided by the machine learning framework 904 to perform the necessary calculations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 904 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms (e.g., matrix and vector operations).

[0162] The machine learning framework 904 can process input data received from the machine learning application 902 and generate appropriate input to the computation framework 906. The computation framework 906 can abstract the basic instructions provided to the GPGPU driver 908 to enable the machine learning framework 904 to take advantage of hardware acceleration via the GPGPU hardware 910 without requiring the machine learning framework 904 to have detailed knowledge of the architecture of the GPGPU hardware 910. Furthermore, the computation framework 906 can implement hardware acceleration for the machine learning framework 904 across various types and generations of GPGPU hardware 910.

[0163] GPGPU machine learning acceleration

[0164] Figure 10 A highly parallel general-purpose graphics processing unit 1000 is shown in accordance with an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 1000 can be configured to be particularly efficient at processing the type of computational workload associated with training deep neural networks. Furthermore, the GPGPU 1000 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster to increase the speed of training, in particular, deep neural networks.

[0165] GPGPU 1000 includes a host interface 1002 for connecting to a host processor. In one embodiment, host interface 1002 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 1000 receives commands from the host processor and uses a global scheduler 1004 to distribute execution threads associated with those commands to a set of compute clusters 1006A-1006H. Compute clusters 1006A-1006H share a cache memory 1008. Cache memory 1008 can serve as a higher-level cache than the cache memory within compute clusters 1006A-1006H.

[0166] GPGPU 1000 includes memory 1014A-1014B coupled to a computing cluster 1006A-1006H via a set of memory controllers 1012A-1012B. In various embodiments, memory 1014A-1014B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, Figure 2A The memory cells 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0167] In one embodiment, each computing cluster 1006A-1006H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessors of the compute cluster may include various types of integer and floating-point logic units to perform computational operations with a range of precision suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating-point units in each of the compute clusters 1006A-1006H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0168] Multiple instances of GPGPU 1000 can be configured to operate as a compute cluster. The communication mechanisms used by the compute cluster for synchronization and data exchange vary across various embodiments. In one embodiment, multiple instances of GPGPU 1000 communicate via a host interface 1002. In one embodiment, GPGPU 1000 includes an I / O hub 1009 that couples GPGPU 1000 to a GPU link 1010, which enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 1010 is coupled to a dedicated GPU-to-GPU bridge that facilitates communication and synchronization between multiple instances of GPGPU 1000. In one embodiment, GPU link 1010 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1000 are located in separate data processing systems and communicate via network devices accessible through host interface 1002. In one embodiment, GPU link 1010 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1002 .

[0169] While the illustrated configuration of GPGPU 1000 can be configured to train neural networks, one embodiment provides an alternative configuration of GPGPU 1000 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 1000 includes fewer of compute clusters 1006A-1006H relative to the training configuration. Additionally, the memory technology associated with memories 1014A-1014B can differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 1000 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0170] Figure 11 A multi-GPU computing system 1100 is shown according to an embodiment. The multi-GPU computing system 1100 may include a processor 1102 coupled to a plurality of GPGPUs 1106A-D via a host interface switch 1104. In one embodiment, the host interface switch 1104 is a PCI Express switch device that couples the processor 1102 to a PCI Express bus, through which the processor 1102 can communicate with the set of GPGPUs 1106A-D. Each of the plurality of GPGPUs 1106A-1106D may be a Figure 10GPGPU 1000. GPGPUs 1106A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 1116. The high-speed GPU-to-GPU links may be connected via dedicated GPU links (e.g., Figure 10 1106D). A P2P GPU link 1116 enables direct communication between each of the GPGPUs 1106A-1106D without requiring communication over a host interface bus to which the processor 1102 is connected. In the event that GPU-to-GPU traffic is directed to the P2P GPU link, the host interface bus remains available for access to system memory or for communication with other instances of the multi-GPU computing system 1100, for example, via one or more network devices. While in the illustrated embodiment, the GPGPUs 1106A-1106D are connected to the processor 1102 via the host interface switch 1104, in one embodiment, the processor 1102 includes direct support for the P2P GPU link 1116 and can connect directly to the GPGPUs 1106A-1106D.

[0171] Machine Learning Neural Network Implementation

[0172] The computing architecture provided by the embodiments described herein can be configured to perform a type of parallel processing particularly well-suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions that have curvilinear relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as described above.

[0173] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network designed to process data with a known grid-like topology (e.g., image data). Consequently, CNNs are commonly used in computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. Calculations for a CNN involve applying the mathematical operation of convolution to each filter to produce the output of that filter. Convolution is a specialized type of mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function used for convolution can be referred to as the input, while the second function can be referred to as the convolution kernel. The output can be referred to as a feature map. For example, the input to a convolutional layer can be a multidimensional array of data defining the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted by the training process used for the neural network.

[0174] A recurrent neural network (RNN) is a series of feedforward neural networks that include feedback connections between layers. RNNs model sequential data by sharing reference data among different parts of the neural network. The architecture of an RNN includes loops. Loops represent the influence of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN serves as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature of language data.

[0175] The figures described below present exemplary feedforward, CNN, and RNN networks and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and not limiting of any particular embodiment described herein, and that the concepts shown can be generally applied to deep neural networks and machine learning techniques in general.

[0176] The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning that uses deep neural networks. The deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers, unlike shallow neural networks that only include a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the network's additional hidden layers enable multi-step pattern recognition, which results in reduced output errors compared to shallow machine learning techniques.

[0177] The deep neural networks used in deep learning generally include a front-end network to perform feature recognition coupled to a back-end network representing a mathematical model that can perform operations (such as object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without the need for hand-crafted feature engineering performed on the model. Alternatively, deep neural networks can learn features based on statistical structures or associations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to the specific task to be performed, and different models will be used to perform different tasks.

[0178] Once a neural network is constructed, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backward propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the expected output, and an error value is calculated for each neuron in the output layer. The error value is then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then use an algorithm (such as a stochastic gradient descent algorithm) to learn from those errors to update the weights of the neural network.

[0179] Figures 12A-12B An exemplary convolutional neural network is shown. Figure 12A The various layers within a CNN are shown. Figure 12A As shown, an exemplary CNN for modeling image processing may receive an input 1202 describing the red, green, and blue (RGB) components of an input image. The input 1202 may be processed by a plurality of convolutional layers (e.g., convolutional layer 1204, convolutional layer 1206). The outputs from the plurality of convolutional layers may optionally be processed by a set of fully connected layers 1208. The neurons in a fully connected layer have full connections to all activations in the previous layer, as described above for a feedforward network. The outputs from the fully connected layer 1208 may be used to generate output results according to the network. Activations within the fully connected layer 1208 may be calculated using matrix multiplication rather than convolution. Not all CNN implementations utilize a fully connected layer 1208. For example, in some implementations, the convolutional layer 1206 may generate outputs for the CNN.

[0180] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1208. Traditional neural network layers are fully connected so that each output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the domain is input (rather than the corresponding state value of each node in the domain) to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs the convolution operation, and its output is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process larger images.

[0181] Figure 12B 1 shows exemplary computational stages within a convolutional layer of a CNN. The input to a convolutional layer 1212 of the CNN can be processed in three stages of a convolutional layer 1214. These three stages can include a convolutional stage 1216, a detector stage 1218, and a pooling stage 1220. The convolutional layer 1214 can then output data to a subsequent convolutional layer. The last convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN.

[0182] The convolution stage 1216 performs several convolutions in parallel to produce a set of linear activations. The convolution stage 1216 may include an affine transformation, which is any transformation that can be defined as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 1216 defines a set of linear activations that are processed by the subsequent stages of the convolution layer 1214.

[0183] The linear activations may be processed by the detector stage 1218. In the detector stage 1218, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinearity of the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) so that the activation is thresholded at zero.

[0184] Pooling stage 1220 uses a pooling function that replaces the output of convolutional layer 1206 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations of the input do not change the pooled output. Invariance to local translations may be useful in situations where the presence of features in the input data is more important than the exact location of the features. Various types of pooling functions can be used during pooling stage 1220, including maximum pooling, average pooling, and standard pooling. In addition, some CNN implementations do not include a pooling stage. Alternatively, such an implementation replaces an additional convolution stage with an increased stride relative to the previous convolution stage.

[0185] The output from the convolutional layer 1214 may then be processed by the next layer 1222. The next layer 1222 may be an additional convolutional layer or one of the fully connected layers 1208. For example, Figure 12A The first convolutional layer 1204 may output to the second convolutional layer 1206 , and the second convolutional layer may output to the first layer of the fully connected layer 1208 .

[0186] Figure 13 An exemplary recurrent neural network 1300 is shown. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be constructed in various ways using various functions. The use of RNNs is often based on mathematical models that predict the future based on previous sequences of inputs. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous sequence of words. The illustrated RNN 1300 can be described as having an input layer 1302 that receives an input vector, a hidden layer 1304 for implementing a recursive function, a feedback mechanism 1305 for implementing a "memory" of previous states, and an output layer 1306 for outputting a result. RNN 1300 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1305. For a given time step, the state of the hidden layer 1304 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1304. The second input (x2) can be processed by the hidden layer 1304 using the state information determined during the processing of the initial input (x1). A given state can be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. Function f is typically nonlinear, such as the hyperbolic tangent function (Tanh) or a variation of the corrector function f(x) = max(0, x). However, the specific mathematical function used in hidden layer 1304 may vary depending on the specific implementation details of RNN 1300.

[0187] In addition to the basic CNN and RNN networks described, variations on those networks may also be possible. An example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary to process longer language sequences. A variant on CNN is the convolutional deep belief network, which has a similar structure to a CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of random variables. Greedy unsupervised learning can be used to train the DBN layer by layer. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial set of weights for the neural network.

[0188] Figure 14 The training and deployment of a deep neural network is shown. Once a given network is constructed for a task, the neural network is trained using a training dataset 1402. Various training frameworks 1404 have been developed to enable hardware acceleration of the training process. For example, Figure 9 The machine learning framework 904 can be configured as a training framework 904. The training framework 904 can hook into the untrained neural network 1406 and use the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1408.

[0189] To start the training process, initial weights can be chosen randomly or by pre-training using a deep belief network. A training cycle is then performed in a supervised or unsupervised manner.

[0190] Supervised learning is a learning method in which training is performed as an intermediate operation, such as when the training dataset 1402 includes inputs paired with expected outputs for those inputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then propagated back through the system. The training framework 1404 can be adjusted to control the weights of the untrained neural network 1406. The training framework 1404 can provide tools to monitor how well the untrained neural network 1406 is converging on a model that is suitable for generating the correct answer based on the known input data. The training process occurs repeatedly as the network's weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1408. The trained neural network 1408 can then be deployed to implement any number of machine learning operations.

[0191] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1402 will include input data without any associated output data. The untrained neural network 1406 can learn the groups within the unlabeled inputs and can determine how the individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1408 that can perform operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input data set that deviate from the normal pattern of the data.

[0192] Variations on supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1402 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1408 to adapt to new data 1412 without forgetting the instructions instilled into the network during initial training.

[0193] Whether supervised or unsupervised, the training process for a particular deep neural network may be too computationally intensive for a single compute node. Instead of using a single compute node, a distributed network of compute nodes can be used to speed up the training process.

[0194] Figure 15 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each of the distributed computing nodes may include one or more host processors and general processing nodes (e.g., as in Figure 10 As shown, distributed learning can be performed by model parallelism 1502, data parallelism 1504, or a combination of model and data parallelism 1506.

[0195] In model parallelization 1502, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelization include the ability to scale to extremely large models. Partitioning the computations associated with different layers of a neural network enables training of very large neural networks, where the weights of all layers would not fit in the memory of a single computing node. In some instances, model parallelization can be particularly useful when performing unsupervised training of large neural networks.

[0196] In data parallelization 1504, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different methods for data parallelization are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transmitting parameters from nodes to parameter servers, updates to the model are transmitted. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0197] Combined model and data parallelism 1506 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0198] Distributed training increases overhead relative to training on a single machine. However, each of the parallel processors and GPGPUs described herein can implement various techniques to reduce the overhead of distributed training, including techniques for high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0199] Example Machine Learning Applications

[0200] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from replicating human visual capabilities (e.g., facial recognition) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations caused by objects visible in a video. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously feasible, and enables inference systems to be deployed using low-power parallel processors.

[0201] Parallel processor-accelerated machine learning has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0202] Parallel processor-accelerated deep neural networks enable machine learning approaches to automatic speech recognition (ASR). ASR involves creating functions that compute the most likely speech sequence given a random input sequence. Accelerated machine learning implementations using deep neural networks replace the Hidden Markov Model (HMM) and Gaussian Mixture Model (GMM) previously used for ASR.

[0203] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. The automated learning process can utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0204] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 10 Highly parallel general purpose graphics processing unit 1000 and Figure 11 In contrast, deployed machine learning platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0205] Figure 16 An exemplary inference system-on-chip (SOC) 1600 suitable for performing inference using a trained model is shown. The SOC 1600 may integrate processing components including a media processor 1602, a vision processor 1604, a GPGPU 1606, and a multi-core processor 1608. The SOC 1600 may further include on-chip memory 1605 that implements a shared on-chip data pool accessible by each processing component. The processing components may be optimized for low-power operation to enable deployment to various machine learning platforms including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1600 may be used as part of a master control system for an autonomous vehicle. Where the SOC 1600 is configured for use in an autonomous vehicle, the SOC is designed and configured to be compatible with the relevant functional safety standards of the deployment jurisdiction.

[0206] During operation, the media processor 1602 and the vision processor 1604 can work together to accelerate computer vision operations. The media processor 1602 can implement low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1605. The vision processor 1604 can then parse the decoded video and use the trained image recognition model to perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames. For example, the vision processor 1604 can accelerate the convolution operations of a CNN used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1606.

[0207] The multi-core processor 1608 may include control logic to facilitate sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1602 and the vision processor 1604. The multi-core processor 1608 may also function as an application processor to execute software applications that can utilize the inference computing capabilities of the GPGPU 1606. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1608. Such software may issue computational workloads directly to the GPGPU 1606, or computational workloads may be issued to the multi-core processor 1608, which may offload at least a portion of those operations to the GPGPU 1606.

[0208] GPGPU 1606 may include a compute cluster, such as a low-power configuration of compute clusters 1006A-1006H within a highly parallel general-purpose graphics processing unit 1000. The compute cluster within GPGPU 1606 may support instructions specifically optimized for performing inference computations on trained neural networks. For example, GPGPU 1606 may support instructions for performing low-precision computations (e.g., 8-bit and 4-bit integer vector operations).

[0209] System Overview

[0210] Figure 17 is a block diagram of a processing system 1700 according to an embodiment. In various embodiments, system 1700 includes one or more processors 1702 and one or more graphics processors 1708, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1702 or processor cores 1707. In one embodiment, system 1700 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0211] Embodiments of system 1700 may include or be incorporated into the following: a server-based gaming platform, a gaming console, including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, system 1700 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Data processing system 1700 may also include, be coupled to, or be integrated into the following: a wearable device such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 1700 is a television or set-top box device having one or more processors 1702 and a graphics interface generated by one or more graphics processors 1708.

[0212] In some embodiments, each of the one or more processors 1702 includes one or more processor cores 1707 to process instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1707 is configured to process a specific instruction set 1709. In some embodiments, the instruction set 1709 may be advantageous for complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction set words (VLIW). Each of the multiple processor cores 1707 may process a different instruction set 1709, which may include instructions that facilitate emulation of other instruction sets. The processor cores 1707 may also include other processing devices, such as a digital signal processor (DSP).

[0213] In some embodiments, the processor 1702 includes a cache memory 1704. Depending on the architecture, the processor 1702 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1702. In some embodiments, the processor 1702 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC) (not shown)), which can be shared among the processor cores 1707 using known cache coherence techniques. In addition, a register file 1706 is included in the processor 1702. The register file 1706 may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1702.

[0214] In some embodiments, processor 1702 is coupled to processor bus 1710 to transmit communication signals, such as address, data, or control signals, between processor 1702 and other components in system 1700. In one embodiment, system 1700 utilizes an exemplary "hub" system architecture, including a memory controller hub 1716 and an input / output (I / O) controller hub 1730. Memory controller hub 1716 facilitates communication between memory devices and other components of system 1700, while I / O controller hub (ICH) 1730 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1716 is integrated within the processor.

[0215] Memory device 1720 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as process memory. In one embodiment, memory device 1720 may operate as system memory for system 1700 to store data 1722 and instructions 1721 for use when one or more processors 1702 execute applications or processes. Memory controller hub 1716 is also coupled to an optional external graphics processor 1712, which may communicate with one or more graphics processors 1708 in processor 1702 to perform graphics and media operations.

[0216] In some embodiments, ICH 1730 enables peripheral devices to connect to memory devices 1720 and processor 1702 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 1746, a firmware interface 1728, a wireless transceiver 1726 (e.g., Wi-Fi, Bluetooth), a data storage device 1724 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 1740 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1742 connect input devices, such as a keyboard and mouse 1744 combination. A network controller 1734 may also be coupled to ICH 1730. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1710. It will be appreciated that the illustrated system 1700 is exemplary and not limiting, as other types of differently configured data processing systems may also be used. For example, I / O controller hub 1730 may be integrated within one or more processors 1702 , or memory controller hub 1716 and I / O controller hub 1730 may be integrated into a separate external graphics processor (eg, external graphics processor 1712 ).

[0217] Figure 18is a block diagram of one embodiment of a processor 1800 having one or more processor cores 1802A-1802N, an integrated memory controller 1814, and an integrated graphics processor 1808. The graphics processor 1808 may include an adder circuit 1809 according to an embodiment of the present design (e.g., system 700, adder circuit 750). Elements having the same reference numerals (or names) as elements of any other figure herein Figure 18 Those elements may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1800 may include additional cores, up to and including additional core 1802N, represented by a dashed box. Each of processor cores 1802A-1802N includes one or more internal cache units 1802A-1804N. In some embodiments, each processor core also has access to one or more shared cache units 1806.

[0218] Internal cache units 1804A-1804N and shared cache unit 1806 represent a cache memory hierarchy within processor 1800. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache before external memory being categorized as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1806 and 1804A-1804N.

[0219] In some embodiments, the processor 1800 may further include a set of one or more bus controller units 1816 and a system agent core 1810. The one or more bus controller units 1816 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1810 provides management functions for various processor components. In some embodiments, the system agent core 1810 includes one or more integrated memory controllers 1814 to manage access to various external memory devices (not shown).

[0220] In some embodiments, one or more of the processor cores 1802A-1802N include support for simultaneous multithreading. In such embodiments, the system agent core 1810 includes components for coordinating and operating the cores 1802A-1802N during multithreaded processing. The system agent core 1810 may also include a power control unit (PCU) that includes logic and components to regulate the power state of the processor cores 1802A-1802N and the graphics processor 1808.

[0221] In some embodiments, processor 1800 further includes a graphics processor 1808 to perform graphics processing operations. In some embodiments, graphics processor 1808 is coupled to a set of shared cache units 1806 and a system agent core 1810 including one or more integrated memory controllers 1814. In some embodiments, a display controller 1811 is coupled to graphics processor 1808 to output graphics processing to one or more coupled displays. In some embodiments, display controller 1811 may be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 1808 or system agent core 1810.

[0222] In some embodiments, a ring-based interconnect 1812 is used to couple the internal components of processor 1800. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, graphics processor 1808 is coupled to ring interconnect 1812 via I / O link 1813.

[0223] Exemplary I / O link 1813 represents at least one of a variety of I / O interconnects, including on-package I / O interconnects, that facilitate communication between various processor components and high-performance embedded memory modules 1818 (e.g., eDRAM modules). In some embodiments, each of processor cores 1802A-1802N and graphics processor 1808 uses embedded memory modules 1818 as a shared last-level cache.

[0224] In some embodiments, processor cores 1802A-1802N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1802A-1802N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1802A-1802N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1802A-1802N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with relatively low power consumption. Furthermore, processor 1800 may be implemented on one or more chips or as a SoC integrated circuit having the components described and other components.

[0225] Figure 191 is a block diagram of a graphics processor 1900, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. In some embodiments, graphics processor 1900 includes a memory interface 1914 for accessing memory. Memory interface 1914 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0226] In some embodiments, the graphics processor 1900 also includes a display controller 1902 to drive display output data to a display device 1920. The display controller 1902 includes hardware for one or more overlay planes for displaying and composing multiple layers of video or user interface elements. In some embodiments, the graphics processor 1900 includes a video codec engine 1906 to encode, decode, or transcode media to, from, or between one or more media coding formats, including but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0227] In some embodiments, graphics processor 1900 includes a block image transfer (BLIT) engine 1904 to perform two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1910. In some embodiments, GPE 1910 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0228] In some embodiments, GPE 1910 includes a 3D pipeline 1912 for performing 3D operations (e.g., rendering three-dimensional images and scenes) using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1912 includes programmable and fixed-function elements that perform various tasks within the elements and / or generate execution threads for 3D / media subsystem 1915. While 3D pipeline 1912 can be used to perform media operations, embodiments of GPE 1910 also include a media pipeline 1916 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0229] In some embodiments, media pipeline 1916 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of video codec engine 1906. In some embodiments, media pipeline 1916 further includes a thread generation unit to generate threads for execution on 3D / media subsystem 1915. The generated threads perform computations for the media operations on one or more graphics execution units included in 3D / media subsystem 1915.

[0230] In some embodiments, 3D / media subsystem 1915 includes logic for executing threads generated by 3D pipeline 1912 and media pipeline 1916. In one embodiment, the pipelines send thread execution requests to 3D / media subsystem 1915, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. Execution resources include an array of graphics execution units to handle 3D and media threads. In some embodiments, 3D / media subsystem 1915 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and store output data.

[0231] Graphics processing engine

[0232] Figure 20 is a block diagram of a graphics processing engine 2010 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2010 is Figure 19 The GPE 1910 shown is a version of the GPE 1910. Elements having the same reference numerals (or names) as elements of any other figure herein Figure 20 The elements of may operate or function in any manner similar to, but not limited to, those described elsewhere herein. For example, Figure 19 3D pipeline 1912 and media pipeline 1916. Media pipeline 1916 is optional in some embodiments of GPE 2010 and may not be explicitly included within GPE 2010. For example and in at least one embodiment, separate media and / or graphics processors are coupled to GPE 2010.

[0233] In some embodiments, GPE 2010 is coupled to or includes a command streamer 2003, which provides a command stream to 3D pipeline 1912 and / or media pipeline 1916. In some embodiments, command streamer 2003 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 2003 receives commands from memory and sends them to 3D pipeline 1912 and / or media pipeline 1916. Commands are retrieved directly from a ring buffer, which stores commands for 3D pipeline 1912 and media pipeline 1916. In one embodiment, the ring buffer may further include a batch command buffer for storing batches of multiple commands. Commands for 3D pipeline 1912 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 1912 and / or image data and memory objects for media pipeline 1916. The 3D pipeline 1912 and the media pipeline 1916 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2014 .

[0234] In various embodiments, the 3D pipeline 1912 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2014. The graphics core array 2014 provides a unified block of execution resources. Multipurpose execution logic (e.g., execution units) within the graphics core array 2014 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

[0235] In some embodiments, graphics core array 2014 also includes execution logic to perform media functions, such as video and / or image processing. In one embodiment, the execution unit additionally includes general purpose logic that can be programmed to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can be combined in parallel or in Figure 17 Processor core 1707 or as in Figure 18 The general logic within cores 1802A-1802N performs processing operations.

[0236] Output data generated by threads executing on graphics core array 2014 can be output to memory in unified return buffer (URB) 2018. URB 2018 can store data for multiple threads. In some embodiments, URB 2018 can be used to send data between different threads executing on graphics core array 2014. In some embodiments, URB 2018 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared function logic 2020.

[0237] In some embodiments, graphics core array 2014 is scalable such that the array includes a variable number of graphics cores, each with a variable number of execution units based on the target power and performance level of GPE 2010. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0238] Graphics core array 2014 is coupled to shared function logic 2020, which includes a number of resources shared between the graphics cores in the graphics core array. Shared functions within shared function logic 2020 are hardware logic units that provide specialized, supplemental functionality to graphics core array 2014. In various embodiments, shared function logic 2020 includes, but is not limited to, samplers 2021, math 2022, and inter-thread communication (ITC) 2023 logic. Furthermore, some embodiments implement one or more caches 2025 within shared function logic 2020. Shared functions are implemented where the demand for a given specialized function is insufficient to include within graphics core array 2014. Alternatively, a single instance of that specialized function is implemented as a separate entity within shared function logic 2020 and shared among execution resources within graphics core array 2014. The precise set of functions shared between and included within graphics core array 2014 varies between embodiments.

[0239] Figure 21 is a block diagram of another embodiment of a graphics processor 2100. Elements having the same reference numerals (or names) as elements of any other figure herein Figure 21 The elements of may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0240] In some embodiments, graphics processor 2100 includes ring interconnect 2102, pipeline front end 2104, media engine 2137, and graphics cores 2180A-2180N. In some embodiments, ring interconnect 2102 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0241] In some embodiments, the graphics processor 2100 receives batches of commands via a ring interconnect 2102. Incoming commands are interpreted by a command streamer 2103 in a pipeline front end 2104. In some embodiments, the graphics processor 2100 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2180A-2180N. For 3D geometry processing commands, the command streamer 2103 supplies the commands to a geometry pipeline 2136. For at least some media processing commands, the command streamer 2103 supplies the commands to a video front end 2134, which is coupled to a media engine 2137. In some embodiments, the media engine 2137 includes a video quality engine (VQE) 2130 for video and graphics post-processing and a multi-format encoding / decoding (MFX) 2133 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2136 and the media engine 2137 each generate execution threads for thread execution resources provided by at least one graphics core 2180A.

[0242] In some embodiments, the graphics processor 2100 includes scalable thread execution resources featuring modular cores 2180A-2180N (sometimes referred to as core slices), each of which has multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2100 may have any number of graphics cores 2180A-2180N. In some embodiments, the graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150 and a second sub-core 2160A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2150A). In some embodiments, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each of which includes a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. Each sub-core in the set of first sub-cores 2150A-2150N includes at least a first set of execution units 2152A-2152N and media / texture samplers 2154A-2154N. Each sub-core in the set of second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In some embodiments, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0243] Execution Unit

[0244] Figure 22 2 shows thread execution logic 2200 including an array of processing elements employed in some embodiments. Elements having the same reference numerals (or names) as elements of any other figure herein Figure 22 The elements of may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0245] In some embodiments, thread execution logic 2200 includes a shader processor 2202, a thread dispatcher 2204, an instruction cache 2206, a scalable execution unit array including a plurality of execution units 2208A-2208N, a sampler 2210, a data cache 2212, and a data port 2214. In one embodiment, the scalable execution unit array can be dynamically scaled based on the computational requirements of the workload by enabling or disabling one or more execution units (e.g., any of execution units 2208A, 2208B, 2208C, 2208D through 2208N-1 and 2208N). In one embodiment, the included components are interconnected via an interconnect structure linked to each of the components. In some embodiments, thread execution logic 2200 includes one or more connections to a memory (e.g., system memory or cache memory) through one or more of the instruction cache 2206, the data port 2214, the sampler 2210, and the execution units 2208A-2208N. In some embodiments, each execution unit (e.g., 2208A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements for each thread in parallel. In various embodiments, the array of execution units 2208A-2208N is scalable to include any number of individual execution units.

[0246] In some embodiments, execution units 2208A-2208N are primarily used to execute shader programs. Shader processor 2202 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2204. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units in execution units 2208A-2208N. For example, the geometry pipeline (e.g., Figure 21 2136) can dispatch vertex, tessellation, or geometry shaders to thread execution logic 2200 ( Figure 22 ) for processing. In some embodiments, thread dispatcher 2204 may also process runtime thread generation requests from executing shader programs.

[0247] In some embodiments, the execution units 2208A-2208N support an instruction set that includes inherent support for many standard 3D graphics shader instructions, allowing shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal conversion. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each execution unit 2208A-2208N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations implement an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock for a pipeline capable of integer, single and double precision floating point operations, SIMD branching capabilities, logical operations, transcendental operations, and other tessellation operations. When waiting for data from memory or one of the shared functions, dependency logic within execution units 2208A-2208N puts the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0248] Each execution unit in execution units 2208A-2208N operates on an array of data elements. The number of data elements is the "execution size" or the number of lanes for an instruction. An execution lane is a logical unit used for performing data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, execution units 2208A-2208N support integer and floating point data types. According to an embodiment of the present design, the ALU may include an adder circuit (e.g., system 700, adder circuit 750).

[0249] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit packed data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0250] One or more internal instruction caches (e.g., 2206) are included in the thread execution logic 2200 to cache thread instructions for the instruction unit. In some embodiments, one or more data caches (e.g., 2212) are included to cache thread data during thread execution. In some embodiments, a sampler 2210 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2210 includes dedicated texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0251] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2200 via thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2202 is called to further calculate output information and write the results to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values of various vertex attributes that are interpolated on the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2202 then executes the pixel or fragment shader program provided by the application programming interface (API). To execute the shader program, the shader processor 2202 dispatches threads to execution units (e.g., 2208A) via the thread dispatcher 2204. In some embodiments, the pixel shader 2202 uses texture sampling logic in the sampler 2210 to access texture data stored in a texture map in memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0252] In some embodiments, the data port 2214 provides a memory access mechanism for the thread execution logic 2200 to output processed data to memory for execution on the graphics processor output pipeline. In some embodiments, the data port 2214 includes or is coupled to one or more cache memories (e.g., data cache 2212) to cache data via the data port for memory access.

[0253] Figure 23 2 is a block diagram illustrating a graphics processor instruction format 2300 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2300 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decode once the instruction is processed.

[0254] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 2310. Based on the selected instruction, instruction options, and the number of operands, a 64-bit compressed instruction format 2330 is available for some instructions. The native 128-bit instruction format 2310 provides access to all instruction options, while some options and operations are restricted to the 64-bit instruction format 2330. The native instructions available in the 64-bit instruction format 2330 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values in the index field 2313. The execution unit hardware references a set of compression tables based on the index values and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 2310.

[0255] For each format, the instruction opcode 2312 defines the operation that the execution unit will perform. The execution unit executes each instruction in parallel among multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a simultaneous addition operation on each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction on all data channels of the operand. In some embodiments, the instruction control field 2314 is controlled by certain execution options (such as channel selection (such as prediction) and data channel order (such as swizzle)). For the instructions in the 128-bit instruction format 2310, the exec size field 2316 limits the number of data channels that will be executed in parallel. In some embodiments, the exec size field 2316 is not available for use in the 64-bit compressed instruction format 2330.

[0256] Some execution unit instructions have up to three operands, including two source operands, src0 2320 and src1 2322, and one destination 2318. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implied. Data manipulation instructions may have a third source operand (e.g., src2 2234), where the instruction opcode 2312 determines the number of source operands. The last source operand of an instruction may be an immediate (hard-coded) value passed along with the instruction.

[0257] In some embodiments, the 128-bit instruction format 2310 includes an access / addressing mode field 2326 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0258] In some embodiments, the 128-bit instruction format 2310 includes an access / addressing mode field 2326 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source and destination operands, while when in the second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0259] In one embodiment, the addressing mode portion of the access / addressing mode field 2326 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0260] In some embodiments, instructions are grouped based on the opcode 2312 bit field to simplify opcode decoding 2340. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, the move and logic opcode group 2342 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2342 shares the five most significant bits (MSBs), where move (mov) instructions are in the form of 0000xxxxb, while logic instructions are in the form of 0001xxxxb. The flow control instruction group 2344 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2346 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2348 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2348 performs arithmetic operations in parallel on the data paths. The vector math group 2350 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations.

[0261] Graphics pipeline

[0262] Figure 24 FIG. 2 is a block diagram of a graphics processor 2400 according to another embodiment. Figure 24 The elements of may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0263] In some embodiments, graphics processor 2400 includes a graphics pipeline 2420, a media pipeline 2430, a display engine 2440, thread execution logic 2450, and a render output pipeline 2470. In some embodiments, graphics processor 2400 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 2400 via ring interconnect 2402. In some embodiments, ring interconnect 2402 couples graphics processor 2400 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2402 are interpreted by command streamer 2403, which supplies instructions to individual components of graphics pipeline 2420 or media pipeline 2430.

[0264] In some embodiments, command streamer 2403 directs the operation of vertex fetcher 2405, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2403. In some embodiments, vertex fetcher 2405 provides vertex data to vertex shader 2407, which performs coordinate space transformation and lighting operations for each vertex. In some embodiments, vertex fetcher 2405 and vertex shader 2407 execute vertex processing instructions by dispatching execution threads to execution units 2452A-2452B via thread dispatcher 2431.

[0265] In some embodiments, execution units 2452A-2452B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2452A-2452B have an attached L1 cache 2451 that is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0266] In some embodiments, the graphics pipeline 2420 includes a tessellation component to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2411 configures the tessellation operation. A programmable domain shader 2417 provides back-end evaluation of the tessellation output. The tessellator 2413 operates at the direction of the hull shader 2411 and contains dedicated logic to generate a set of detailed geometric objects based on the coarse geometric model provided as input to the graphics pipeline 2420. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 2411, the tessellator 2413, and the domain shader 2417) can be bypassed.

[0267] In some embodiments, the complete geometric object may be processed by the geometry shader 2419 via one or more threads dispatched to execution units 2452A-2452B, or may proceed directly to the clipper 2429. In some embodiments, the geometry shader operates on entire geometric objects rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2419 receives input from the vertex shader 2407. In some embodiments, if the tessellation unit is disabled, the geometry shader 2419 is programmable by a geometry shader program to perform geometric tessellation.

[0268] Before rasterization, the clipper 2429 processes the vertex data. The clipper 2429 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 2473 in the render output pipeline 2470 dispatches pixel shaders to convert geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2450. In some embodiments, applications can bypass the rasterizer and depth test component 2473 and access unrasterized vertex data via the stream output unit 2423.

[0269] The graphics processor 2400 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to pass through the main components of the processor. In some embodiments, execution units 2452A-2452B and associated caches 2451, texture and media samplers 2454, and texture / sampler caches 2458 are interconnected via data ports 2456 to perform memory access and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2454, caches 2451, 2458, and execution units 2452A-2452B each have a separate memory access path.

[0270] In some embodiments, the render output pipeline 2470 includes a rasterizer and depth test component 2473 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit to perform fixed-function triangle and line rasterization. In some embodiments, an associated render cache 2478 and depth cache 2479 are also available. A pixel operation component 2477 performs pixel-based operations on data, although in some instances, pixel operations associated with 2D operations (e.g., using hybrid bit-block image transfer) are performed by the 2D engine 2441 or instead by the display controller 2443 at display time using an overlay display plane. In some embodiments, a shared L3 cache 2475 is available to all graphics components, allowing data to be shared without using main system memory.

[0271] In some embodiments, the graphics processor media pipeline 2430 includes a media engine 2437 and a video front end 2434. In some embodiments, the video front end 2434 receives pipeline commands from the command streamer 2403. In some embodiments, the media pipeline 2430 includes a separate command streamer. In some embodiments, the video front end 2434 processes media commands before sending them to the media engine 2437. In some embodiments, the media engine 2437 includes thread generation functionality to generate threads for dispatching to the thread execution logic 2450 via the thread dispatcher 2431.

[0272] In some embodiments, the graphics processor 2400 includes a display engine 2440. In some embodiments, the display engine 2440 is external to the graphics processor 2400 and coupled to the graphics processor via a ring interconnect 2402 or some other interconnect bus or structure. In some embodiments, the display engine 2440 includes a 2D engine 2441 and a display controller 2443. In some embodiments, the display engine 2440 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2443 is coupled to a display device (not shown), which can be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0273] In certain embodiments, graphics pipeline 2420 and media pipeline 2430 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not specific to any one application programming interface (API). In certain embodiments, the driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In certain embodiments, support is provided for Open Graphics Library (OpenGL), Open Computing Language (OpenCL) and / or Vulkan graphics and computing APIs all from the Khronos Group. In certain embodiments, support can also be provided for the Direct3D library from Microsoft. In certain embodiments, the combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If a mapping can be made from the pipeline of a future API to the pipeline of a graphics processor, then future APIs with compatible 3D pipelines will also be supported.

[0274] Graphics pipeline programming

[0275] Figure 25A is a block diagram illustrating a graphics processor command format 2500 according to some embodiments. Figure 25B is a block diagram illustrating a graphics processor command sequence 2510 according to an embodiment. Figure 25A The solid-line boxes in show components that are typically included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 25A The exemplary graphics processor command format 2500 includes a data field to identify the target client of the command 2502, a command operation code (opcode) 2504, and associated data for the command 2506. A sub-opcode 2505 and a command size 2508 are also included in some commands.

[0276] In some embodiments, client 2502 specifies the client unit of the graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2504 and, if present, the sub-opcode 2505 to determine the operation to be performed. The client unit uses the information in the data field 2506 to execute the command. For some commands, an explicit command size 2508 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned via multiple double words.

[0277] Figure 25B An exemplary graphics processor command sequence 2510 is shown in the flowchart in FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. For purposes of example only, the sample command sequence is shown and described, as embodiments are not limited to these specific commands or this command sequence. Furthermore, commands may be issued as batched commands within the command sequence, such that the graphics processor will process a sequence of commands at least partially concurrently.

[0278] In some embodiments, graphics processor command sequence 2510 may begin with a pipeline flush command 2512 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, 3D pipeline 2522 and media pipeline 2524 do not operate concurrently. A pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will suspend command processing until the active graphics engine completes pending operations and the associated read cache is invalidated. Optionally, any data in the render cache marked as "dirty" may be flushed to memory. In some embodiments, pipeline flush command 2512 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0279] In some embodiments, a pipeline select command 2513 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 2513 is only required once within an execution context before issuing a pipeline command, unless the context is used to issue commands for both pipelines. In some embodiments, a pipeline flush command 2512 is required immediately before a pipeline switch via a pipeline select command 2513.

[0280] In some embodiments, pipeline control commands 2514 configure the graphics pipeline for operation and are used to program 3D pipeline 2522 and media pipeline 2524. In some embodiments, pipeline control commands 2514 configure the pipeline state for the active pipeline. In one embodiment, pipeline control commands 2514 are used for pipeline synchronization and to flush data from one or more cache memories within the active pipeline before processing a batch of commands.

[0281] In some embodiments, commands for return buffer state 2516 are used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which intermediate data is written during the processor operation. In some embodiments, a graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer state 2516 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0282] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 2520 , the command sequence is clipped to either the 3D pipeline 2522 starting at the 3D pipeline state 2530 or the media pipeline 2524 starting at the media pipeline state 2540 .

[0283] The commands used to configure the 3D pipeline state 2530 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are configured before 3D primitive commands are processed. The values of these commands are determined based at least in part on the specific 3D API in use. In some embodiments, the 3D pipeline state 2530 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0284] In some embodiments, the 3D primitive 2532 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 2532 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2532 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2532 command is used to perform vertex operations on the 3D primitive via a vertex shader. To process the vertex shader, the 3D pipeline 2522 dispatches a shader execution thread to a graphics processor execution unit.

[0285] In some embodiments, the 3D pipeline 2522 is triggered via an execute 2534 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to refresh the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is completed, the resulting geometric object is rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0286] In some embodiments, the graphics processor command sequence 2510 follows the media pipeline 2524 path when performing media operations. Generally, the specific use and manner of programming for the media pipeline 2524 depends on the media or compute operation to be performed. Specific media decoding operations can be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0287] In some embodiments, the media pipeline 2524 is configured in a similar manner to the 3D pipeline 2522. A set of commands for configuring the media pipeline state 2540 is dispatched or placed into the command queue before the media object commands 2542. In some embodiments, the commands for the media pipeline state 2540 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline (e.g., encoding or decoding formats). In some embodiments, the commands for the media pipeline state 2540 also support the use of one or more pointers to "indirect" state elements, which contain batch state settings.

[0288] In some embodiments, media object command 2542 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2542. Once the pipeline state is configured and media object command 2542 is enqueued, media pipeline 2524 is triggered via execute command 2544 or an equivalent execution event (e.g., register write). The output from media pipeline 2524 can then be post-processed by the operations provided by 3D pipeline 2522 or media pipeline 2524. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0289] Graphics software architecture

[0290] Figure 26 An exemplary graphics software architecture for data processing system 2600 is shown in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2610, an operating system 2620, and at least one processor 2630. In some embodiments, processor 2630 includes a graphics processor 2632 and one or more general-purpose processor cores 2634. Graphics application 2610 and operating system 2620 each execute in system memory 2650 of the data processing system.

[0291] In some embodiments, the 3D graphics application 2610 includes one or more shader programs that include shader instructions 2612. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2614 in a machine language suitable for execution by a general-purpose processor core 2634. The application also includes graphics objects 2616 defined by vertex data.

[0292] In some embodiments, operating system 2620 is from Microsoft Corporation 26. The operating system 2620 may include an operating system, a dedicated UNIX-like operating system, or an open source UNIX-like operating system that uses a variant of the Linux kernel. The operating system 2620 may support a graphics API 2622, such as the Direct3D API, the OpenGL API, or the Vulkan API. When using the Direct3D API, the operating system 2620 uses a front-end shader compiler 2624 to compile any shader instructions 2612 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or application of executable shader precompilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2610. In some embodiments, the shader instructions 2612 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0293] In some embodiments, the user-mode graphics driver 2626 includes a backend shader compiler 2627 to convert shader instructions 2612 into hardware-specific representations. When using the OpenGL API, shader instructions 2612 in the GLSL high-level language are passed to the user-mode graphics driver 2626 for compilation. In some embodiments, the user-mode graphics driver 2626 uses operating system kernel-mode functions 2628 to communicate with the kernel-mode graphics driver 2629. In some embodiments, the kernel-mode graphics driver 2629 communicates with the graphics processor 2632 to dispatch commands and instructions.

[0294] IP core implementation

[0295] One or more aspects of at least one embodiment may be implemented by representative code representing and / or defining logic within an integrated circuit (e.g., a processor) stored on a machine-readable medium. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic to perform the techniques described herein. Such representations, referred to as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in connection with any of the embodiments described herein.

[0296] Figure 272 is a block diagram illustrating an IP core development system 2700 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2700 can be used to generate modular, reusable designs that can be incorporated into larger designs, or used to construct an entire integrated circuit (e.g., a SoC integrated circuit). A design facility 2730 can generate a software simulation 2710 of the IP core design in a high-level programming language (e.g., C++). The software simulation 2710 can be used to design, test, and verify the behavior of the IP core using a simulation model 2712. The simulation model 2712 may include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2715 can then be created or synthesized based on the simulation model 2712. The RTL design 2715 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers (including associated logic executed using the modeled digital signals). In addition to the RTL design 2715, lower-level designs at the logic or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation may vary.

[0297] The RTL design 2715 or an equivalent form may be further synthesized by a design facility into a hardware model 2720, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using non-volatile memory 2740 (e.g., a hard drive, flash memory, or any non-volatile storage medium) for delivery to a third-party fabrication facility 2765. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 2750 or a wireless connection 2760. The fabrication facility 2765 may then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0298] Exemplary System-on-Chip Integrated Circuit

[0299] Figures 28-30 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0300] Figure 2828 is an illustration of an exemplary system-on-chip integrated circuit 2800 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 2800 includes one or more application processors 2805 (e.g., CPUs), at least one graphics processor 2810, and may additionally include an image processor 2815 and / or a video processor 2820, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 2800 includes peripheral or bus logic including a USB controller 2825, a UART controller 2830, an SPI / SDIO controller 2835, and an I / O bus. 2 S / I 2 The integrated circuit may include a display device 2845 coupled to a high-definition multimedia interface (HDMI) controller 2850 and a mobile industry processor interface (MIPI) display interface 2855. Storage may be provided by a flash memory subsystem 2860 including flash memory and a flash memory controller. A memory interface for accessing SDRAM or SRAM memory devices may be provided via a memory controller 2865. In addition, some integrated circuits include an embedded security engine 2870.

[0301] Figure 29 FIG2 is an exemplary graphics processor 2910 illustrating a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 2910 may be Figure 28 The graphics processor 2910 includes a vertex processor 2905 and one or more fragment processors 2915A-2915N (e.g., 2915A, 2915B, 2915C, 2915D through 2915N-1 and 2915N). The graphics processor 2910 can execute different shader programs via separate logic, such that the vertex processor 2905 is optimized to perform operations for vertex shader programs while one or more fragment processors 2915A-2915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 2905 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processors 2915A-2915N use the primitives and vertex data generated by the vertex processor 2905 to generate a frame buffer for display on a display device. In one embodiment, the fragment processors 2915A-2915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0302] In addition, the graphics processor 2910 includes one or more memory management units (MMUs) 2920A-2920B, caches 2925A-2925B, and circuit interconnects 2930A-2930B. The one or more MMUs 2920A-2920B provide a virtual physical address mapping for the graphics processor 2910 (including for the vertex processor 2905 and / or fragment processors 2915A-2915N), which can reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 2925A-2925B. In one embodiment, the one or more MMUs 2920-2930B can synchronize with other MMUs in the system, including those with Figure 28 One or more MMUs associated with one or more application processors 2805, image processor 2815, and / or video processor 2820 enable each processor 2805-2820 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 2930A-2930B enable the graphics processor 2910 to interface with other IP cores within the SoC via the SoC's internal bus or via direct connection.

[0303] Figure 30 is a block diagram illustrating an additional exemplary graphics processor 3010 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3010 may be Figure 28 A variation of the graphics processor 2810. The graphics processor 3010 includes Figure 29 One or more MMUs 2920A-2920B, caches 2925A-2925B, and circuit interconnects 2930A-2930B of the integrated circuit 2900.

[0304] The graphics processor 3010 includes one or more shader cores 3015A-3015N (e.g., 3015A, 3015B, 3015C, 3015D, 3015E, 3015F through 3015N-1 and 3015N) that provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code that implements vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary among embodiments and implementations. In addition, the graphics processor 3010 includes an inter-core task manager 3005 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3015A-3015N and a tiling unit 3018 for accelerating tiling operations for tile-based rendering, wherein rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0305] The following examples relate to other embodiments. Example 1 is an apparatus comprising a uniform random number generator (URNG) circuit for generating uniform random numbers and an adder circuit coupled to the URNG circuit. The adder circuit is configured to hardware accelerate the generation of Gaussian random numbers for machine learning.

[0306] In Example 2, the subject matter of Example 1 may optionally include: an adder circuit comprising: a first adder for adding the first and second uniform random numbers from the URNG circuit to generate a first output of the first adder; and a second adder for adding the third uniform random number from the URNG circuit to the first output to generate a first output of the second adder.

[0307] In Example 3, the subject matter of any of Examples 1-2 can optionally include that the adder circuit further includes an Nth adder to add another uniform random number from the URNG circuit to the first output of the previous adder to generate a first Gaussian random number.

[0308] In Example 4, the subject matter of Example 3 can optionally include generating the first Gaussian random number within a time period approximately equal to a time delay of each adder multiplied by the N adders.

[0309] In Example 5, the subject matter of Example 4 can optionally include the first adder adding two additional uniform random numbers to generate a second output of the first adder after the first adder generates the first output.

[0310] In Example 6, the subject matter of Example 5 can optionally include the second adder adding two additional uniform random numbers to generate a second output of the second adder after the second adder generates the first output.

[0311] In Example 7, the subject matter of Example 6 can optionally include the Nth adder adding another uniform random number from the URNG circuit to a second output of a previous adder to generate a second Gaussian random number.

[0312] Example 8 is a method for generating a Gaussian random number, including generating a uniform random number using a uniform random number generator (URNG) circuit, adding a first and a second uniform random number from the URNG circuit using a first adder of the adder circuit to generate a first output of the first adder, and adding a third uniform random number from the URNG circuit to the first output using a second adder of the adder circuit to generate a first output of the second adder.

[0313] In Example 9, the subject matter of Example 8 can optionally include adding, with an Nth adder, another uniform random number from the URNG circuit to a first output of a previous adder to generate a first Gaussian random number for Bayesian-based machine learning.

[0314] In Example 10, the subject matter of Example 9 can optionally include generating the first Gaussian random number within a time period approximately equal to a time delay of each adder multiplied by the N adders.

[0315] In Example 11, the subject matter of Example 10 can optionally include adding, by the first adder, two additional uniform random numbers to generate a second output of the first adder after the first adder generates the first output.

[0316] In Example 12, the subject matter of Example 11 can optionally include adding, by the second adder, two additional uniform random numbers to generate a second output of the second adder after the second adder generates the first output.

[0317] In Example 13, the subject matter of Example 12 can optionally include adding, with an Nth adder, another uniform random number from the URNG circuit and a second output of a previous adder to generate a second Gaussian random number.

[0318] Example 14 is a device comprising a unit for generating a uniform random number using a uniform random number generator (URNG) circuit, a unit for adding first and second uniform random numbers from the URNG circuit to generate a first output of a first adder, and a unit for adding a third uniform random number from the URNG circuit to the first output to generate a first output of a second adder.

[0319] In Example 15, the subject matter of Example 14 may optionally include means for adding, with an Nth adder, another uniform random number from the URNG circuit to the first output of the previous adder to generate a first Gaussian random number for Bayesian-based machine learning.

[0320] In Example 16, the subject matter of Example 15 can optionally include generating the first Gaussian random number within a time period approximately equal to a time delay of each adder multiplied by the N adders.

[0321] In Example 17, the subject matter of Example 16 can optionally include means for adding, using the first adder, two additional uniform random numbers to generate a second output of the first adder after the first adder generates the first output.

[0322] In Example 18, the subject matter of Example 17 can optionally include means for adding, with the second adder, two additional uniform random numbers to generate a second output of the second adder after the second adder generates the first output.

[0323] In Example 19, the subject matter of Example 18 can optionally include means for adding, with an Nth adder, another uniform random number from the URNG circuit and a second output of a previous adder to generate a second Gaussian random number.

[0324] In Example 20, the subject matter of Example 19 can optionally include generating the second Gaussian random number within a time period approximately equal to a time delay of each adder multiplied by the N adders.

[0325] References to "one embodiment," "an embodiment," "example embodiment," "various embodiments," etc., indicate that the embodiments so described may include a particular feature, structure, or characteristic, but not every embodiment is required to include the particular feature, structure, or characteristic. Furthermore, some embodiments may have some, all, or none of the features described for other embodiments.

[0326] The foregoing description and drawings are to be regarded as illustrative rather than restrictive. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. A computing device comprising: A uniform random number generator (URNG) circuit for generating uniform random numbers; as well as an adder circuit coupled to the URNG circuit, the adder circuit configured to hardware accelerate generation of Gaussian random numbers for machine learning, the adder circuit comprising: a first adder for adding the first uniform random number and the second uniform random number from the URNG circuit to generate a first output of the first adder; and a second adder configured to add a third uniform random number from the URNG circuit to the first output to generate a first output of the second adder; The first adder is used to add two other uniform random numbers different from the first uniform random number and the second uniform random number to generate a second output of the first adder, wherein the second output is the next output of the first adder after the first output.

2. The device according to claim 1, wherein The adder circuit further includes: An Nth adder is configured to add another uniform random number from the URNG circuit to the first output of the previous adder to generate a first Gaussian random number.

3. The device according to claim 2, wherein The first Gaussian random number is generated within a time period that is approximately equal to a time delay of each adder multiplied by the N adders.

4. The device according to claim 1, wherein The second adder is configured to add two other uniform random numbers to generate a second output of the second adder after the second adder generates the first output.

5. The device according to claim 4, wherein The Nth adder adds another uniform random number from the URNG circuit to the second output of the previous adder to generate a second Gaussian random number.

6. A method for generating a Gaussian random number, comprising: A uniform random number generator (URNG) circuit is used to generate uniform random numbers. adding, using a first adder of an adder circuit, a first uniform random number and a second uniform random number from the URNG circuit to generate a first output of the first adder; as well as adding, using a second adder of the adder circuit, a third uniform random number from the URNG circuit and the first output to generate a first output of the second adder; The first adder is used to add two other uniform random numbers different from the first uniform random number and the second uniform random number to generate a second output of the first adder, wherein the second output is the next output of the first adder after the first output.

7. The method of claim 6, further comprising: Another uniform random number from the URNG circuit is added to the first output of the previous adder using an Nth adder to generate a first Gaussian random number for Bayesian-based machine learning.

8. The method of claim 7, wherein: The first Gaussian random number is generated within a time period that is approximately equal to a time delay of each adder multiplied by the N adders.

9. The method of claim 6, further comprising: The second adder is used to add two other uniform random numbers after the second adder generates the first output to generate a second output of the second adder.

10. The method of claim 6, further comprising: Another uniform random number from the URNG circuit is added to the second output of the previous adder using an Nth adder to generate a second Gaussian random number.

11. A computing device comprising: a unit for generating uniform random numbers using a uniform random number generator (URNG) circuit; means for adding a first uniform random number and a second uniform random number from the URNG circuit to generate a first output of a first adder; as well as means for adding a third uniform random number from the URNG circuit to the first output using a second adder of the adder circuit to generate a first output of the second adder; The first adder is used to add two other uniform random numbers different from the first uniform random number and the second uniform random number to generate a second output of the first adder, wherein the second output is the next output of the first adder after the first output.

12. The apparatus of claim 11, further comprising: A unit for adding, using an Nth adder, another uniform random number from the URNG circuit to a first output of a previous adder to generate a first Gaussian random number for use in Bayesian-based machine learning.

13. The device of claim 12, wherein: The first Gaussian random number is generated within a time period that is approximately equal to a time delay of each adder multiplied by the N adders.

14. The apparatus of claim 11, further comprising: means for adding, with the second adder, two additional uniform random numbers to generate a second output of the second adder after the second adder generates the first output.

15. The apparatus of claim 14, further comprising: means for adding, using an Nth adder, another uniform random number from the URNG circuit and a second output of a previous adder to generate a second Gaussian random number.

16. The apparatus of claim 15, wherein: The second Gaussian random number is generated within a time period that is approximately equal to the time delay of each adder multiplied by the N adders.

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