Stacked package structure

Abstract

An embodiment of the present invention provides a stacked package structure, comprising: a first package, a plurality of conductive bumps, a second package, and an underfill. The conductive bumps are arranged on the second surface of the first package and are electrically connected to the first package. The second package is arranged on the second surface of the first package through the conductive bumps, and comprises a semiconductor device and an encapsulation material encapsulating the semiconductor device. The shortest distance from the upper surface of the encapsulation material to the upper surface of the semiconductor device is greater than or substantially equal to twice the thickness of the semiconductor device. The underfill is filled between the first package and the second package.

Description

Technical Field

[0001] An embodiment of the present invention relates to a stacked packaging structure. Background Art

[0002] As the demand for smaller electronic products grows, manufacturers and the like in the electronics industry are constantly seeking ways to reduce the size of integrated circuits used in electronic products. To this end, three-dimensional type integrated circuit packaging technology has been developed and used.

[0003] Manufacturing 3D integrated chips requires stacking multiple semiconductor packages, coupling circuits between corresponding packages, and bonding the packages with an electrically insulating adhesive to form a stacked package structure. Subsequent high temperature processing steps, such as curing the electrically insulating adhesive, subject the stacked package structure to mechanical stress, which can cause undesirable side effects such as warping, cracking, delamination, and defect formation. Summary of the invention

[0004] The embodiment of the present invention is directed to a stacked packaging structure, which has a higher finished product yield.

[0005] According to an embodiment of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The conductive bumps are arranged on the second surface of the first package and are electrically connected to the first package. The second package is arranged on the second surface of the first package through the conductive bumps and includes a semiconductor device and an encapsulation material encapsulating the semiconductor device. The shortest distance from the upper surface of the encapsulation material to the upper surface of the semiconductor device is greater than or equal to twice the thickness of the semiconductor device. The underfill is filled between the first package and the second package.

[0006] According to an embodiment of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a rewiring structure. The encapsulated semiconductor device includes a first semiconductor device, a first encapsulation material encapsulating the first semiconductor device, and a plurality of through holes extending through the first encapsulation material. The rewiring structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bump is disposed on a second surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The second surface is opposite to the first surface. The second package is disposed on the second surface of the encapsulated semiconductor device and includes a second semiconductor device and a second encapsulation material encapsulating the second semiconductor device. The shortest distance from the upper surface of the second encapsulation material to the upper surface of the second semiconductor device is greater than or equal to twice the thickness of the second semiconductor device. The underfill is filled between the first package and the second package.

[0007] According to an embodiment of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a rewiring structure, wherein the rewiring structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bump is disposed on a second surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The second package is disposed on the second surface through the conductive bump and includes a plurality of semiconductor devices and an encapsulation material that encapsulates the semiconductor device. The shortest distance from the upper surface of the encapsulation material to the topmost surface of the semiconductor device is greater than or equal to twice the maximum thickness of the semiconductor device. The underfill is filled between the first package and the second package. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the embodiments of the present invention are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figures 1 to 8 Cross-sectional views illustrating intermediate stages in the fabrication of a package-on-package structure according to some exemplary embodiments of the present invention.

[0010] Fig. 9 Depicted is a graph illustrating the relationship between warpage of a second package and underfill failure rate at a specified temperature.

[0011] Fig.10 A graph illustrating the relationship between warpage and underfill failure rate of a second package at another specified temperature is depicted.

[0012] Fig.11 Cross-sectional views illustrating package-on-package structures according to some exemplary embodiments of the present invention.

[0013] Fig.12 Cross-sectional views illustrating package-on-package structures according to some exemplary embodiments of the present invention.

[0014] Description of Figure Numbers

[0015] 10, 10', 10": stacked packaging structure;

[0016] 100: a first package;

[0017] 101: Encapsulated semiconductor devices;

[0018] 110, 110a: a first semiconductor device;

[0019] 112: substrate;

[0020] 113: pad;

[0021] 114: via hole;

[0022] 116, 116a, 143: dielectric layer;

[0023] 120, 120a: first encapsulating material;

[0024] 130: through hole;

[0025] 140, 230: Rewiring structure;

[0026] 142: Re-route the line;

[0027] 144: Under bump metal layer;

[0028] 160: carrier;

[0029] 165: Adhesive layer;

[0030] 170, 170a: insulating layer;

[0031] 172: Opening;

[0032] 182: electrical connector;

[0033] 184: Integrated passive devices;

[0034] 200, 200', 200": second packaging;

[0035] 201: lower surface;

[0036] 210, 210a, 210b, 210c: second semiconductor device;

[0037] 212, 222: upper surface;

[0038] 212a, 212b: top surface;

[0039] 220, 220': second encapsulating material;

[0040] 300: conductive bump;

[0041] 400: bottom filler;

[0042] A1: Central area;

[0043] A2: peripheral area;

[0044] D1, D2, T1, T1': shortest distance;

[0045] S1: first surface;

[0046] S2: second surface;

[0047] T2, T3, T4: thickness. DETAILED DESCRIPTION

[0048] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of the present invention. Of course, these are just examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, embodiments of the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0049] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0050] In addition, for ease of description, terms such as "first", "second", "third", "fourth" and similar terms may be used herein to describe similar or different elements or features as shown in the drawings, and may be used interchangeably depending on the order of existence or the context of description.

[0051] Other features and processes may also be included. For example, a test structure may be included to help verify the testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate that allows testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that have intermediate verification of known good dies to increase yield and reduce costs.

[0052] Figures 1 to 8Cross-sectional views illustrating intermediate stages in manufacturing a package-on-package structure according to some exemplary embodiments of the present invention. It should be noted that embodiments of the present invention will be described with reference to some embodiments under a specific situation, namely a package-on-package (PoP) structure. However, the concepts in the embodiments of the present invention can also be applied to other semiconductor structures or circuits. PoP structures and methods of forming PoP structures are provided according to various embodiments. Intermediate stages of forming a PoP structure are described according to some embodiments. Variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numerals are used to represent similar elements.

[0053] In some embodiments, forming Figure 8 A description of the intermediate stages of the PoP structure 10 shown in FIG. Figure 1 , a carrier 160 is provided, and an adhesive layer 165 may be disposed on the carrier 160. In some embodiments, the carrier 160 may be a glass carrier, a ceramic carrier, or the like. The adhesive layer 165 may be a light to heat conversion release coating (LTHC) or the like. In some embodiments, an insulating layer 170a may be selectively disposed on the carrier 160 or on the adhesive layer 165 (if present). Subsequently, a plurality of through holes 130 are formed on the carrier 160, and the through holes 130 surround a central area A1 where the first semiconductor device 110 is to be disposed. In some embodiments, the through holes 130 are disposed on a peripheral area A2 of the carrier 160 surrounding the central area A1. It should be noted that "center" and "periphery" herein may not be interpreted literally, but may be regarded as spatially relative terms, and the spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. In this embodiment, the via 130 is formed on the insulating layer 170 a on the carrier 160 , but the present invention is not limited thereto. In an alternative embodiment, the insulating layer 170 a and the adhesive layer 165 may be omitted, and the via 130 is directly formed on the carrier 160 .

[0054] In some embodiments, at least one Figure 2The first semiconductor device 110a shown is formed on the carrier 160 and is located in the central area A1. In the present embodiment, the first semiconductor device 110a is formed on the insulating layer 170a located on the carrier 160, but the embodiments of the present invention are not limited thereto. In some embodiments, the first semiconductor device 110a may be a logic chip including a logic circuit therein. In some exemplary embodiments, the number of the first semiconductor device 110a may be multiple, and may be multiple device dies designed for mobile phone applications, and may include, for example, a power management integrated circuit (Power Management Integrated Circuit; PMIC) die and a transceiver (Transceiver; TRX) die. Although only one first semiconductor device 110a is shown, more semiconductor devices may be placed above the carrier 160 and flush with each other.

[0055] In some embodiments, the carrier 160 may include a plurality of central regions A1 arranged in an array, for example. Accordingly, the through hole 130 may be formed to surround each central region A1, and a plurality of first semiconductor devices 110a may be respectively disposed on the plurality of central regions A1, such that the through hole 130 may surround each first semiconductor device 110a. With these arrangements, a plurality of PoP structures may be formed simultaneously. For the sake of brevity and clarity, Figures 1 to 8 Only one of the manufacturing processes of the multiple PoP structures is shown in FIG. Figure 1 One of the plurality of central areas A1 surrounded by some of the plurality of through holes 130 is shown in FIG.

[0056] In some embodiments, the through hole 130 may be preformed and then placed on the carrier 160. In an alternative embodiment, the through hole 130 may be formed by, for example, an electroplating process. The electroplating of the through hole 130 may be performed before the first semiconductor device 110a is placed, and may include the following steps. For example, a seed layer (not shown) is first formed above the carrier 160, a photoresist layer (not shown) is formed and patterned, and electroplating is performed on a portion of the seed layer exposed by the photoresist layer to form the through hole 130. The photoresist layer and the portion of the seed layer covered by the photoresist layer may be removed subsequently. The first semiconductor device 110a may then be placed above the carrier 160. The material of the through hole 130 may include copper, aluminum, or the like. Accordingly, the bottom end of the through hole 130 is substantially flush with the back surface of the first semiconductor device 110a.

[0057] In some exemplary embodiments, a plurality of vias 114 (e.g., copper vias) may be formed on an active surface (e.g., top surface) of the first semiconductor device 110a and electrically coupled to pads 113 on a substrate 112 of the first semiconductor device 110a. In some embodiments, a dielectric layer 116a may be formed on an active surface (e.g., top surface) of the first semiconductor device 110a and may cover the top surfaces of the vias 114. In other embodiments, the top surface of the dielectric layer 116a may be substantially flush with the top surfaces of the vias 114. Alternatively, the dielectric layer 116a may be omitted and the vias 114 may protrude from the active surface of the first semiconductor device 110. In some embodiments, the top end of the via 130 may be substantially flush with the top surface of the via 114. In other embodiments, the top end of the via 130 may be substantially higher than the top surface of the via 114. Alternatively, the top end of the through hole 130 may be substantially lower than the top surface of the via 114 but substantially higher than the bottom surface of the via 114 .

[0058] Subsequently, the first semiconductor device 110a and the through hole 130 on the carrier 160 are encapsulated by the first encapsulation material 120a. In other words, the first encapsulation material 120a is formed on the carrier 160 to encapsulate the through hole 130 at the peripheral area A2 and the first semiconductor device 110a at the central area A1. In some embodiments, the first encapsulation material 120a fills the gap between the first semiconductor device 110a and the through hole 130 and may contact the insulating layer 170a. The first encapsulation material 120a may include a molding compound, an epoxy resin or a resin, etc. In some embodiments, the top surface of the first encapsulation material 120a may be higher than the top of the through hole 130 and the top surface of the dielectric layer 116a. That is, the first encapsulation material 120a covers the top of the through hole 130 and the top surface of the dielectric layer 116a.

[0059] Subsequently, a thinning process (which may be a grinding process) is performed to thin the first encapsulation material 120a (and the dielectric layer 116a) until the top of the through hole 130 and the top surface of the via 114 are exposed. The resulting structure is shown in FIG. Figure 3 Due to the thinning process, the top of the through hole 130 is substantially flush with the top surface of the via 114, and is substantially flush with the top surface of the first encapsulating material 120 and the top surface of the dielectric layer 116, as shown in FIG. Figure 3 Throughout this description, Figure 3The resulting structure including the first semiconductor device 110, the through hole 130, and the first encapsulation material 120 shown in is referred to as an encapsulated semiconductor device 101, which may have a wafer form in the process. Accordingly, in the encapsulated semiconductor device 101, the first semiconductor device 110 is disposed at a central area A1, the through hole 130 extends through the first encapsulation material 120 at a peripheral area A2 surrounding the central area A1, and the first encapsulation material 120 encapsulates the first semiconductor device 110 and the through hole 130. In other words, the first encapsulation material 120 encapsulates the first semiconductor device 110 therein, and the through hole 130 extends through the first encapsulation material 120.

[0060] Next, see Figure 4 , a rewiring structure 140 is formed on a first surface S1 of the encapsulated semiconductor device 101. The rewiring structure 140 is electrically connected to the first semiconductor device 110 and the through hole 130 of the encapsulated semiconductor device 101. In some embodiments, the rewiring structure 140 is formed above the encapsulated semiconductor device 101 to connect to the via 114 of the first semiconductor device 110 and the through hole 130. In some embodiments, the rewiring structure 140 can also interconnect the via 114 with the through hole 130. The rewiring structure 140 can be formed by, for example, the following steps: depositing a conductive layer, patterning the conductive layer to form a rewiring line 142, partially covering the rewiring line 142 with a dielectric layer 143 and filling the gap between the rewiring lines 142, etc. The material of the rewiring line 142 may include a metal or a metal alloy including aluminum, copper, tungsten and / or an alloy thereof. The dielectric layer 143 may be formed by a dielectric material such as an oxide, a nitride, a carbide, a carbonitride, a combination thereof and / or a multilayer thereof. The redistribution line 142 is formed in the dielectric layer 143 and is electrically connected to the first semiconductor device 110 and the via 130. In addition, an under bump metallurgy (UBM) layer 144 may be formed on the redistribution structure 140 by sputtering, evaporation, or electroless plating.

[0061] See also Figure 5According to some exemplary embodiments, at least one of the electrical connectors 182 and at least one integrated passive device (IPD) 184 are disposed on the redistribution wiring structure 140. The formation of the electrical connector 182 may include placing a solder ball on the UBM layer 144 (or on the redistribution wiring structure 140), and then reflowing the solder ball. In an alternative embodiment, the formation of the electrical connector 182 may include performing an electroplating process to form a solder block on the UBM layer 144 (or on the redistribution wiring structure 140), and then reflowing the solder block. The electrical connector 182 may also include a conductive column, or a conductive column with a solder cap, which may also be formed by electroplating. The integrated passive device 184 may be manufactured using standard wafer manufacturing techniques such as thin film and photolithography processes, and may be mounted on the redistribution wiring structure 140 by, for example, flip chip bonding or wire bonding.

[0062] See later Figure 6 , the carrier 160 can be removed. In some embodiments, the carrier 160 is separated from the encapsulated semiconductor device 101 and the insulating layer 170a (if present) by causing the adhesive layer 165 to lose adhesion or reduce adhesion. The adhesive layer 165 can be removed together with the carrier 160. For example, the adhesive layer 165 can be exposed to UV light so that the adhesive layer 165 loses adhesion or reduces adhesion, and the carrier 160 and the adhesive layer 165 can be removed from the encapsulated semiconductor device 101.

[0063] After removing the carrier 160, the bottom end of the through hole 130 is exposed. In the illustrated structure, the bottom end of the through hole 130 is flush with the bottom surface of the first semiconductor device 110 and the bottom surface of the first encapsulation material 120. In an embodiment where the insulating layer 170a is omitted, a grinding process may be performed to slightly grind the bottom surface of the first semiconductor device 110 and the bottom end of the through hole 130. Alternatively, the grinding process may be omitted.

[0064] See also Figure 7 In the embodiment with the insulating layer 170a, a patterning process may be subsequently performed on the insulating layer 170a to form a plurality of openings 172. In this way, an insulating layer 170 having a plurality of openings 172 may be formed. The openings 172 are respectively located on the through holes 130 to expose the bottom ends of the through holes 130. In some embodiments, the openings 172 may be formed by a photolithography process, a laser drilling process, etc. Accordingly, the resulting structure is as follows: Figure 7 The first package 100 is shown in FIG.

[0065] See also Figure 8, a plurality of conductive bumps 300 may be formed on the second surface S2 of the encapsulated semiconductor device 101 of the first package 100 to be electrically connected to the through hole 130 of the first package 100. The second surface S2 is opposite to the first surface S1. That is, the redistribution structure 140 and the conductive bumps 300 are respectively disposed on two opposite surfaces S1 and S2 of the encapsulated semiconductor device 101. In some embodiments, the conductive bumps 300 are disposed in the openings 172 of the insulating layer 170 to be connected to the through holes 130. In some embodiments, the conductive bumps 300 are disposed on the peripheral area A2 of the second surface S2 and surround the central area A1, and the first semiconductor device 110 is located in the central area A1.

[0066] Subsequently, the second package 200 is disposed on the first package 100 and is electrically connected to the through-hole 130 through the conductive bump 300. In some embodiments, the second package 200 is disposed on the second surface S2 of the encapsulated semiconductor device 101 through the conductive bump 300. The second package 200 is mounted on the first package 100 in a manner such that its lower surface 201 faces the second surface S2 of the encapsulated semiconductor device 101. In some embodiments, the second package 200 may be a package, a device die, a passive device, and / or the like. In some embodiments, the stacked package structure 10 may vertically combine discrete memory packages and logic packages, and the second package 200 may be employed in memories such as dynamic random access memory (DRAM) and other memories, but the embodiments of the present invention are not limited thereto.

[0067] Subsequently, the underfill 400 is filled into the gap between the first package 100 and the second package 200 to enhance the strength of the conductive bump 300 and thus enhance the strength of the entire stacked package structure 10. In some embodiments, the underfill 400 covers the central area A1 and the peripheral area A2 and encapsulates the conductive bump 300. The underfill 400 may then be cured by a thermal curing process, and the curing temperature may range from about 100° C. to 150° C. Accordingly, the resulting structure is as shown in FIG. Figure 8 The stacked package structure 10 is shown in FIG.

[0068] In some embodiments, the second package 200 may be mounted on the first package 100 by flip chip bonding, and the second package 200 may include at least one second semiconductor device 210 disposed on a redistribution structure 230 and a second encapsulation material 220 encapsulating the second semiconductor device 210. In some embodiments, the redistribution structure 230 may be a package substrate. In other embodiments, the redistribution structure 230 may be a redistribution layer (RDL) similar to the redistribution structure 140, which is formed by, for example, the following steps: depositing a conductive layer, patterning the conductive layer to form a redistribution line, partially covering the redistribution line with a dielectric layer, and filling the gaps between the redistribution lines.

[0069] Generally, during the bonding process, if the second semiconductor device 210, the second encapsulation material 220, and the redistribution structure 230 have different thermal expansion (CTE) coefficients, different expansion levels occur when the package 200 is heated and when the package 200 is cooled. The different expansion levels exert great stress on the solder ball connectors, which may cause warpage of the second package 200. Additional difficulties arise when flip chip packaging is included in a stacked package configuration. In the stacked package structure 10, two packages 100 and 200, such as application specific integrated circuits (ASICs) and memory packages (such as dynamic random access memories (DRAMs)), may be mounted in a stacked manner. For example, the second package 200 may be larger than the first package 100 and may have an array of conductive bumps 300 around it to form connections to the first package 100. Configurations such as the stacked package structure 10 may increase the likelihood of package warpage.

[0070] Accordingly, when dispensing the bottom filler 400 between the first package 100 and the second package 200 having a warpage profile, the bottom filler 400 may not be able to completely fill the gap, which may result in the formation of voids within the bottom filler 400. In addition, with high temperature curing, the voids within the bottom filler 400 will become larger and rapidly nucleate to cause delamination. Therefore, it is very important to control the warpage profile of the stacked package structure 10 so that the bottom filler 400 fills the gap between the first package 100 and the second package 200 without void formation.

[0071] A series of experiments are conducted to obtain the relationship between the warpage of the package and the failure rate (e.g., cracking or delamination) of the bottom filler 400 during the curing process, and the failure rate (failure rate) of the bottom filler 400 of the stacked package structure 10 caused by different degrees of warpage of the second package 200 can be calculated accordingly. In order to monitor the warpage of the stacked package structure 10, a co-planarity measurement tool can be used, which can use the Shadow Moire' technique to measure the co-planarity of the stacked package structure 10. Of course, the following experimental data and conditions are provided for illustrative purposes only, and the embodiments of the present invention are not limited thereto, but actually cover all changes that are relevant as a result of the teachings provided herein.

[0072] Fig. 9 Depicted is a graph illustrating the relationship between warpage of a second package and underfill failure rate at a specified temperature. Fig.10 A graph is depicted illustrating the relationship between the warpage of the second package and the underfill failure rate at another specified temperature. Fig. 9 In the experiment shown in , the stacked package structure 10 was exposed to a specified temperature of about 100° C. to simulate the curing process of the bottom filler 400. It was found that when the warpage of the second package 200 was substantially equal to or less than about −20 μm, the failure rate of the bottom filler 400 reached 0%. In addition, when the second package 200 was in the form of a concave warpage profile (i.e., the warpage of the second package 200 was a negative value), the failure rate of the bottom filler 400 was less than 10%.

[0073] exist Fig.10 In the experiment shown in , the stacked package structure 10 was exposed to a specified temperature of about 150° C. to simulate the curing process of the bottom filler 400. Similarly, it was found that when the warpage of the second package 200 was substantially equal to or less than about −20 μm, the failure rate of the bottom filler 400 reached 0%. In addition, when the second package 200 was in the form of a concave warpage profile (i.e., the warpage of the second package 200 was a negative value), the failure rate of the bottom filler 400 was also less than 10%.

[0074] In view of this, the warpage profile of the second package 200 can be controlled to be a concave warpage profile to reduce the failure rate of the bottom filler 400. In one embodiment, the lower surface 201 of the second package 200 is curved toward the second surface S2 of the encapsulated semiconductor device 101, and the lower surface 201 is a surface facing the second surface S2. In some embodiments, the shortest distance D1 from the central area A1 of the second surface S2 to the second package 200 is substantially less than the shortest distance D2 from any position on the peripheral area A2 of the second surface S2 to the second package 200. That is, as Figure 8As shown in FIG. 1 , the distance (e.g., gap width) between the first package 100 and the second package 200 gradually decreases from the peripheral area A2 to the central area A1. For example, the shortest distance D1 at the central area A1 may generally range from 30 microns to 60 microns, while the shortest distance D2 at the peripheral area A2 may generally range from 100 microns to 140 microns. Of course, the numerical ranges in the examples are provided for illustrative purposes only, and the embodiments of the present invention are not limited to the examples, but actually encompass all changes that are relevant as a result of the teachings provided herein.

[0075] To achieve the concave warpage profile of the second package 200, the shortest distance T1 from the upper surface 222 of the second encapsulation material 220 to the upper surface 212 of the second semiconductor device 210 is greater than or substantially equal to twice the thickness T2 of the second semiconductor device 210 (i.e., T1≧2×T2). With this configuration, due to the thermal expansion mismatch between the components of the second package 200, the second package 200 will be in the form of a concave warpage profile after the thermal process, so the gap width between the first package 100 and the second package 200 gradually decreases from the peripheral area A2 to the central area A1. As a result, when the bottom filler 400 is dispensed from the peripheral area A2 and flows to the central area A1, the bottom filler 400 can easily fill the gap at the central area A1 due to capillary action without void formation.

[0076] Fig.11 1 is a cross-sectional view illustrating a stacked package structure according to some exemplary embodiments of the present invention. It should be noted that Fig.11 The stacked package structure 10′ shown in FIG. Figure 8 The disclosed stacked package structure 10 has the same or similar features. For the purpose of clarity and simplicity, the detailed description of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. Fig.11 The stacked package structure 10 ′ shown in FIG. Figure 8 The main differences between the stacked package structures 10 shown in FIG.

[0077] In some embodiments, the second package 200' includes a plurality of second semiconductor devices 210a, 210b disposed on a redistribution structure 230 and a second encapsulation material 220 encapsulating the plurality of second semiconductor devices 210a, 210b. In some embodiments, the redistribution structure 230 may be a package substrate. In other embodiments, the redistribution structure 230 may be a redistribution layer (RDL) similar to the redistribution structure 140. In some embodiments, the shortest distance T1 from the upper surface 222 of the second encapsulation material 220 to the topmost surface of the plurality of second semiconductor devices 210a, 210b is greater than or substantially equal to twice the maximum thickness of the plurality of second semiconductor devices 210a, 210b.

[0078] In the present embodiment, the second semiconductor device 210a and the second semiconductor device 210b are arranged on the redistribution structure 230 in a side-by-side manner. The thickness T2 and the thickness T3 of the second semiconductor device 210a and the second semiconductor device 210b may be the same. In this case, the shortest distance T1 from the upper surface 222 to the top surface 212a or the top surface 212b of any one of the second semiconductor device 210a or the second semiconductor device 210b is greater than or substantially equal to twice the thickness T2 or the thickness T3 of any one of the second semiconductor device 210a or the second semiconductor device 210b. In other embodiments, the thickness T2 of the second semiconductor device 210a and the thickness T3 of the second semiconductor device 210b may be different. For example, the thickness T2 of the second semiconductor device 210a is greater than the thickness T3 of the second semiconductor device 210b. In this case, the shortest distance T1 from the upper surface 222 to the top surface 212a of the second semiconductor device 210a is greater than or substantially equal to twice the thickness T2 of the second semiconductor device 210a. Fig.11 Two second semiconductor devices 210 a and 210 b are shown in the figure, but the embodiment of the present invention does not limit the configuration and number of the second semiconductor devices 210 a and 210 b in the second package 200 .

[0079] By this configuration, the second package 200' will be in the form of a concave warpage profile after the thermal process, so the gap width between the first package 100 and the second package 200' gradually decreases from the peripheral area A2 to the central area A1. Thus, when the underfill 400 is dispensed from the peripheral area A2 and flows toward the central area A1, the underfill 400 can easily flow over the central area A1 due to capillary action and fill the gap between the first package 100 and the second package 200' without void formation.

[0080] Fig.121 is a cross-sectional view illustrating a stacked package structure according to some exemplary embodiments of the present invention. It should be noted that Fig.12 The stacked package structure 10" shown in FIG. Figure 8 The disclosed stacked package structure 10 has the same or similar features. For the purpose of clarity and simplicity, the detailed description of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. Fig.12 The stacked package structure 10" shown in FIG. Figure 8 The main differences between the stacked package structures 10 shown in FIG.

[0081] In some embodiments, the second package 200" includes a plurality of second semiconductor devices 210a, 210b, 210c disposed on a redistribution structure 230 and a second encapsulation material 220' encapsulating the plurality of second semiconductor devices 210a, 210b, 210c. In some embodiments, the redistribution structure 230 may be a packaging substrate. In other embodiments, the redistribution structure 230 may be a redistribution layer (RDL) similar to the redistribution structure 140. In some embodiments, the shortest distance T1 from the upper surface 222 of the second encapsulation material 220' to the topmost surface of the plurality of second semiconductor devices 210a, 210b, 210c is greater than or substantially equal to twice the maximum thickness of the plurality of second semiconductor devices 210a, 210b, 210c.

[0082] In the present embodiment, the second semiconductor device 210b and the second semiconductor device 210c are stacked on each other on the redistribution structure 230, and the second semiconductor device 210a is disposed next to the second semiconductor device 210b and the second semiconductor device 210c. The thickness T2, thickness T3, and thickness T4 of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c may be the same. In this case, the shortest distance T1' from the upper surface 222 to the topmost surface 212b of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c is greater than or substantially equal to twice the thickness T2, thickness T3, or thickness T4 of any one of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c. In other embodiments, the thickness T2, thickness T3, and thickness T4 of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c may be different. For example, the thickness T3 of the second semiconductor device 210b is greater than the thickness T4 of the second semiconductor device 210c. In this case, the shortest distance T1' from the upper surface 222 to the topmost surface 212b of the second semiconductor device 210b is greater than or substantially equal to twice the thickness T3 of the second semiconductor device 210b (i.e., if T3 ≥ T4, then T1' ≥ 2 × T3). In this case, the distance T1 from the upper surface 222 to the top surface 212a of the second semiconductor device 210a will also be greater than or substantially equal to twice the thickness T2, because the sum of the thickness T3 and the thickness T4 is greater than the thickness T2. Of course, if the thickness T2 is greater than the sum of the thickness T3 and the thickness T4, the distance T1 from the upper surface 222 to the top surface 212a becomes the shortest distance between the distance T1 and the distance T1', and the shortest distance T1 is critical in determining the warping of the second package 200". It should be noted that the configuration and quantity of the second semiconductor devices 210a, 210b, and 210c in the second package 200" are for illustration only, and the embodiments of the present invention are not limited to this.

[0083] Through this configuration, the second package 200" will be in the form of a concave warping profile after the thermal process, which means that the gap width between the first package 100 and the second package 200" gradually decreases from the peripheral area A2 to the central area A1. Thus, when the bottom filler 400 is distributed from the peripheral area A2 and flows to the central area A1, the bottom filler 400 can easily flow over the central area A1 due to capillary action, and fill the gap between the first package 100 and the second package 200" without forming a void. Therefore, the yield rates of the stacked packaging structure in the embodiment of the present invention are significantly improved.

[0084] Based on the above discussion, it can be seen that embodiments of the present invention provide various advantages. However, it should be understood that not all advantages must be discussed herein, and other embodiments may provide different advantages, and specific advantages are not required for all embodiments.

[0085] According to some embodiments of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The conductive bumps are disposed on a second surface of the first package and are electrically connected to the first package. The second package is disposed on a second surface of the first package through the conductive bumps and includes a semiconductor device and an encapsulation material encapsulating the semiconductor device. The shortest distance from the upper surface of the encapsulation material to the upper surface of the semiconductor device is greater than or equal to twice the thickness of the semiconductor device. The underfill is filled between the first package and the second package.

[0086] According to some embodiments of the present invention, the plurality of conductive bumps are disposed on a peripheral region of the second surface.

[0087] According to some embodiments of the present invention, a lower surface of the second package is bent toward the second surface of the first package, wherein the lower surface faces the second surface.

[0088] According to some embodiments of the present invention, the shortest distance from a central region of the second surface to the second package is shorter than the shortest distance from any position on a peripheral region of the second surface to the second package.

[0089] According to some embodiments of the present invention, the shortest distance from an upper surface of the encapsulation material to an upper surface of the semiconductor device is greater than or equal to twice the thickness of the semiconductor device.

[0090] According to some embodiments of the present invention, the second package includes a plurality of semiconductor devices and the encapsulation material encapsulating the plurality of semiconductor devices.

[0091] According to some embodiments of the present invention, a shortest distance from an upper surface of the encapsulation material to a topmost surface of the plurality of semiconductor devices is greater than or equal to twice a maximum thickness of the plurality of semiconductor devices.

[0092] According to some embodiments of the present invention, the bottom filling glue covers the central area and the peripheral area of ​​the second surface, and encapsulates the plurality of conductive bumps.

[0093] According to some embodiments of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a rewiring structure. The encapsulated semiconductor device includes a first semiconductor device, a first encapsulation material encapsulating the first semiconductor device, and a plurality of through holes extending through the first encapsulation material. The rewiring structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bump is disposed on a second surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The second surface is opposite to the first surface. The second package is disposed on the second surface of the encapsulated semiconductor device and includes a second semiconductor device and a second encapsulation material encapsulating the second semiconductor device. The shortest distance from the upper surface of the second encapsulation material to the upper surface of the second semiconductor device is greater than or equal to twice the thickness of the second semiconductor device. The underfill is filled between the first package and the second package.

[0094] According to some embodiments of the present invention, the shortest distance from a central region of the second surface to the second package is shorter than the shortest distance from any position on a peripheral region of the second surface to the second package.

[0095] According to some embodiments of the present invention, the plurality of conductive bumps are disposed on the peripheral region.

[0096] According to some embodiments of the present invention, the bottom filling glue covers the central area and the peripheral area, and encapsulates the plurality of conductive bumps.

[0097] According to some embodiments of the present invention, the number of the second semiconductor devices is plural, and the second encapsulating material encapsulates the plurality of second semiconductor devices.

[0098] According to some embodiments of the present invention, a shortest distance from an upper surface of the second encapsulating material to a topmost surface of the plurality of second semiconductor devices is greater than or equal to twice a maximum thickness of the plurality of second semiconductor devices.

[0099] According to some embodiments of the present invention, a lower surface of the second package is bent toward the second surface.

[0100] According to some embodiments of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a rewiring structure, wherein the rewiring structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bump is disposed on a second surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The second package is disposed on the second surface through the conductive bump and includes a plurality of semiconductor devices and an encapsulation material that encapsulates the semiconductor device. The shortest distance from the upper surface of the encapsulation material to the topmost surface of the semiconductor device is greater than or equal to twice the maximum thickness of the semiconductor device. The underfill is filled between the first package and the second package.

[0101] According to some embodiments of the present invention, the shortest distance from a central region of the second surface to the second package is shorter than the shortest distance from any position on a peripheral region of the second surface to the second package.

[0102] According to some embodiments of the present invention, a lower surface of the second package is bent toward the second surface.

[0103] According to some embodiments of the present invention, the plurality of semiconductor devices are arranged in a side-by-side manner.

[0104] According to some embodiments of the present invention, the plurality of semiconductor devices are stacked on each other.

[0105] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that they can readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A stacked package structure, comprising: a first package; a plurality of conductive bumps disposed on a surface of the first package and electrically connected to the first package; a second package, disposed on the surface of the first package through the plurality of conductive bumps and comprising a semiconductor device and an encapsulation material encapsulating the semiconductor device, wherein a shortest distance from an upper surface of the encapsulation material to a topmost surface of the semiconductor device is greater than or equal to twice a thickness of the semiconductor device; as well as The bottom filling glue is filled between the first package and the second package. 2 . The package stack structure according to claim 1 , wherein the conductive bumps are disposed on a peripheral area of ​​the surface. 3 . The package stack structure according to claim 1 , wherein a lower surface of the second package is bent toward the surface of the first package, wherein the lower surface faces the surface. 4 . The package stacking structure according to claim 1 , wherein a shortest distance from a central region of the surface to the second package is shorter than a shortest distance from any position on a peripheral region of the surface to the second package. 5 . The package stacking structure according to claim 1 , wherein a distance between the first package and the second package gradually decreases from a peripheral region to a central region of the package stacking structure. 6 . The package stacking structure according to claim 1 , wherein the second package comprises a plurality of semiconductor devices, and the plurality of semiconductor devices are arranged side by side in the encapsulation material. 7 . The package-on-package structure according to claim 6 , wherein at least two semiconductor devices among the plurality of semiconductor devices are stacked on each other and embedded in the encapsulation material. 8 . The stacked package structure according to claim 1 , wherein the bottom filling glue covers the central area and the peripheral area of ​​the surface, and encapsulates the conductive bump.

9. A stacked package structure, comprising: an encapsulated semiconductor device comprising a first semiconductor device, a first encapsulation material encapsulating the first semiconductor device, and a plurality of through holes extending through the first encapsulation material; as well as a redistribution structure disposed on a first surface of the encapsulated semiconductor device and electrically connected to the encapsulated semiconductor device; a plurality of conductive bumps disposed on and electrically connected to a second surface of the encapsulated semiconductor device, wherein the second surface is opposite to the first surface; a second package disposed on a second surface of the encapsulated semiconductor device and comprising a plurality of second semiconductor devices and a second encapsulation material encapsulating the plurality of second semiconductor devices, wherein a shortest distance from an upper surface of the second encapsulation material to a topmost surface of the plurality of second semiconductor devices is greater than or equal to twice a thickness of the plurality of second semiconductor devices; as well as The bottom filling glue is filled between the encapsulated semiconductor device and the second package. 10 . The package stacking structure according to claim 9 , wherein the shortest distance from a central region of the second surface to the second package is shorter than the shortest distance from any position on a peripheral region of the second surface to the second package. The package stacking structure according to claim 10 , wherein the conductive bump is disposed on the peripheral region. 12 . The stacked package structure according to claim 10 , wherein the bottom filling glue covers the central area and the peripheral area, and encapsulates the conductive bump. 13 . The package stacking structure according to claim 9 , wherein the plurality of second semiconductor devices are arranged side by side in the second encapsulation material. 14 . The package-on-package structure according to claim 13 , wherein at least two of the plurality of second semiconductor devices are stacked on each other and embedded in the second encapsulation material. 15 . The package stack structure according to claim 9 , wherein a lower surface of the second package is bent toward the second surface.

16. A stacked package structure, comprising: A first package, comprising an encapsulated semiconductor device and a redistribution structure, wherein the redistribution structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device; a plurality of conductive bumps disposed on a second surface of the encapsulated semiconductor device and electrically connected to the encapsulated semiconductor device; a second package, disposed on the second surface through the conductive bumps and comprising a plurality of semiconductor devices and an encapsulation material encapsulating the semiconductor devices, wherein a shortest distance from an upper surface of the encapsulation material to a topmost surface of the semiconductor device is greater than or equal to twice a maximum thickness of the semiconductor device; as well as The bottom filling glue is filled between the first package and the second package. 17 . The package stacking structure according to claim 16 , wherein the shortest distance from a central region of the second surface to the second package is shorter than the shortest distance from any position on a peripheral region of the second surface to the second package. The package stacking structure according to claim 16 , wherein a lower surface of the second package is bent toward the second surface.

19. The package stack structure according to claim 16, wherein the plurality of semiconductor devices are arranged in a side-by-side manner.

20. The package-on-package structure according to claim 16, wherein the plurality of semiconductor devices are stacked on each other.

21. A stacked package structure, comprising: a first package; A second package is stacked on the first package and electrically connected to the first package, the second package comprising a plurality of semiconductor devices and an encapsulation material encapsulating the plurality of semiconductor devices, wherein the shortest distance from the upper surface of the encapsulation material to the topmost surface of the plurality of semiconductor devices is greater than or equal to twice the maximum thickness of the plurality of semiconductor devices, so that the lower surface of the second package is bent toward the upper surface of the first package, and the lower surface of the second package faces the upper surface of the first package. 22 . The stacked package structure according to claim 21 , further comprising a plurality of conductive bumps disposed between the first package and the second package, wherein the first package is electrically connected to the second package through the plurality of conductive bumps. 23 . The package stacking structure according to claim 21 , wherein a spacing width between the first package and the second package gradually decreases from a peripheral region of the upper surface of the first package to a central region of the upper surface of the first package.

24. The stacked packaging structure according to claim 21, wherein the shortest distance from the central area of ​​the upper surface of the first package to the lower surface of the second package is smaller than the shortest distance from any point in the peripheral area of ​​the upper surface of the first package to the lower surface of the second package. 25 . The package stacking structure according to claim 21 , wherein a distance between the first package and the second package gradually decreases from a peripheral region to a central region of the package stacking structure. 26 . The package-on-package structure according to claim 21 , wherein the second package comprises a plurality of semiconductor devices, and the plurality of semiconductor devices are arranged side by side in the encapsulation material. 27 . The package-on-package structure according to claim 21 , wherein at least two semiconductor devices among the plurality of semiconductor devices are stacked on each other and embedded in the encapsulation material. 28 . The stacked package structure according to claim 21 , further comprising a plurality of conductive bumps and an underfill glue disposed between the first package and the second package, wherein the underfill glue covers a central area and a peripheral area of ​​the surface and encapsulates the conductive bumps.

29. A stacked package structure, comprising: Package substrate; A first semiconductor device is disposed on the packaging substrate; A second semiconductor device is disposed on the packaging substrate, and the second semiconductor device is thicker than the first semiconductor device; as well as An encapsulation material is disposed on the packaging substrate to cover the first semiconductor device and the second semiconductor device, wherein a first portion of the encapsulation material covers an upper surface of the first semiconductor device, a second portion of the encapsulation material covers an upper surface of the second semiconductor device, and a shortest distance from the upper surface of the second portion to the second semiconductor device is greater than or equal to twice the thickness of the second semiconductor device, so that the packaging substrate includes a curved and convex lower surface. 30 . The stacked package structure according to claim 29 , further comprising a plurality of conductive bumps disposed on the lower surface of the package substrate and electrically connected to the package substrate. 31 . The package stack structure according to claim 30 , wherein the conductive bump is disposed on a peripheral area of ​​the lower surface. 32 . The stacked package structure according to claim 30 , wherein the first semiconductor device and the second semiconductor device are disposed side by side on the package substrate. The package stack structure according to claim 30 , wherein the package substrate has a concave warping profile.

34. A stacked package structure, comprising: a first package; A second package is stacked on the first package and electrically connected to the first package, the second package comprising a packaging substrate, a plurality of semiconductor devices disposed on the packaging substrate, and an encapsulation material disposed on the packaging substrate to encapsulate the plurality of semiconductor devices, wherein the shortest distance from the upper surface of the encapsulation material to the topmost surface of the plurality of semiconductor devices is greater than or equal to twice the maximum thickness of the plurality of semiconductor devices, so that the second package has a concave warping profile. 35 . The package stack structure according to claim 34 , wherein the plurality of semiconductor devices comprises a first semiconductor device on the package substrate and a plurality of second semiconductor devices stacked on the package substrate.

36. The stacked packaging structure of claim 35, wherein the shortest distance from the upper surface of the encapsulation material to the upper surface of the upper second semiconductor device among the plurality of second semiconductor devices is greater than or equal to twice the thickness of the upper second semiconductor device among the plurality of second semiconductor devices. 37 . The package-on-package structure of claim 35 , wherein a shortest distance from the upper surface of the encapsulation material to an upper surface of the first semiconductor device is greater than or equal to twice a thickness of the first semiconductor device.

38. A stacked packaging structure according to claim 34, wherein the multiple semiconductor devices include a first semiconductor device arranged on the packaging substrate and a plurality of second semiconductor devices stacked on the packaging substrate, and the upper second semiconductor device among the multiple second semiconductor devices is stacked on the lower second semiconductor device among the multiple second semiconductor devices.

39. A stacked packaging structure according to claim 38, wherein the shortest distance from the upper surface of the encapsulation material to the upper surface of the second semiconductor device in the upper layer among the multiple second semiconductor devices is greater than or equal to twice the thickness of the second semiconductor device in the upper layer among the multiple second semiconductor devices. 40 . The package-on-package structure of claim 38 , wherein a shortest distance from the upper surface of the encapsulation material to an upper surface of the first semiconductor device is greater than or equal to twice a thickness of the first semiconductor device.

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