MOS structure with stepped deep groove shielded gate and manufacturing method

Abstract

The present invention relates to a MOS structure and a manufacturing method thereof, specifically a MOS structure with a stepped deep groove shielded gate and a manufacturing method thereof, belonging to the technical field of manufacturing semiconductor devices. A groove is formed in the N-type epitaxial layer, and the groove extends from the first main surface to the second main surface; the lower inner wall of the groove is stepped to form a stepped shielded gate region, and the stepped shielded gate region includes a shielded gate and a first oxide layer located on both sides of the shielded gate; a gate region is formed at the top of the groove, and the gate region and the shielded gate region are separated by an oxide layer, and the gate region includes a gate conductive polysilicon and a second oxide layer located on both sides of the gate conductive polysilicon; the shielded gate of the MOS structure with a stepped deep groove shielded gate is surrounded by a stepped oxide layer, and a stepped groove is used around the stepped oxide layer, which can optimize the electric field distribution and improve the device withstand voltage.

Description

Technical Field

[0001] The invention relates to a MOS structure and a manufacturing method thereof, in particular to a MOS structure with a stepped deep groove shielding gate and a manufacturing method thereof, belonging to the technical field of manufacturing semiconductor devices. Background Art

[0002] Metal-oxide semiconductor field effect transistor (MOSFET) is a field effect transistor that can be widely used in analog circuits and digital circuits.

[0003] A thick oxide layer is formed on both sides of the shielding gate of a traditional shielded gate MOSFET device, resulting in unsatisfactory charge depletion in the X direction, and then forming an electric field between two peak electric fields in the drift region that is significantly lower. One of the two peak electric fields is at the junction of the P-type body region and the N-type epitaxial layer, and the other is at the bottom of the trench, thereby affecting the device's withstand voltage performance. Summary of the invention

[0004] In order to solve the deficiencies in the prior art, the present invention provides a MOS structure with a stepped deep trench shielded gate, wherein the shielding gate with the stepped deep trench shielded gate MOS structure is surrounded by a stepped oxide layer, and the stepped oxide layer is surrounded by a stepped groove, which can optimize the electric field distribution and reduce the complexity of the process, thereby improving the withstand voltage of high-voltage devices.

[0005] According to the technical solution provided by the present invention, as the first aspect of the present invention:

[0006] A MOS structure with a stepped deep trench shielded gate, characterized in that the MOS structure with a stepped deep trench shielded gate comprises: a semiconductor substrate, the semiconductor substrate comprises an N-type heavily doped substrate and an N-type epitaxial layer located on the N-type heavily doped substrate, the upper surface of the N-type epitaxial layer is the first main surface of the semiconductor substrate, and the lower surface of the N-type heavily doped substrate is the second main surface of the semiconductor substrate;

[0007] A groove is formed in the N-type epitaxial layer, the groove extending from the first main surface to the second main surface; the inner wall of the lower part of the groove is stepped to form a stepped shielding gate region, the stepped shielding gate region includes a shielding gate and a first oxide layer located on both sides of the shielding gate; a gate region is formed at the upper part of the groove, the gate region and the shielding gate region are separated by an oxide layer, the gate region includes a gate conductive polysilicon and a second oxide layer located on both sides of the gate conductive polysilicon;

[0008] A P-type body region is provided in the N-type epitaxial layer on both sides of the groove, an N-type source region is provided on the P-type body region, an insulating dielectric layer is provided on the groove and the N-type source region, source contact holes are provided on both sides of the insulating dielectric layer, the source contact holes are filled with metal, a source metal layer is provided on the insulating dielectric layer, and the source metal layer connects the metals in the two source contact holes.

[0009] Furthermore, the inner side surface and the outer side surface of the first oxide layer are both stepped, and the outer side surface of the shielding grid is also stepped.

[0010] Furthermore, the number of steps of the stepped first oxide layer is 3 to 5, and the thickness of the first oxide layer of each step is equal and is 3000A to 10000A.

[0011] Furthermore, the thickness of the second oxide layer is 1000-2000 Å.

[0012] Furthermore, the number of steps at the lower portion of the stepped groove is 3 to 5, and the height of each step is 1 to 3 μm.

[0013] Furthermore, the depth of the groove is 5-10 μm.

[0014] As a second aspect of the present invention:

[0015] A method for manufacturing a MOS with a stepped deep trench shielded gate, characterized in that the method for manufacturing a MOS with a stepped deep trench shielded gate comprises:

[0016] S1: providing an N-type heavily doped substrate, and growing an N-type epitaxial layer on the N-type heavily doped substrate, wherein the upper surface of the N-type epitaxial layer is a first main surface, and the lower surface is a second main surface;

[0017] S2: etching the first main surface to form a trench in the N-type epitaxial layer, wherein the lower portion of the trench is stepped and the step surface faces upward;

[0018] S3: growing a first oxide layer on the surface of the groove by using a thermal oxidation growth process;

[0019] S4: depositing polysilicon in the lower part of the trench to form a shielding gate;

[0020] S5: etching away the first oxide layer on the upper side surface of the trench;

[0021] S6: growing a second oxide layer on the upper side surface of the trench and the upper surface of the shield gate;

[0022] S7: depositing polysilicon in the upper portion of the trench to form gate conductive polysilicon;

[0023] S8: Under the shielding of the patterned photoresist, firstly implant P-type impurities on one side of the trench to form a P-type body region, and then implant N-type impurities on the P-type body region to form an N-type source region; similarly, firstly implant P-type impurities on one side of the trench to form a P-type body region, and then implant N-type impurities on the P-type body region to form an N-type source region;

[0024] S9: depositing an insulating dielectric layer on the first main surface, etching the insulating dielectric layer, and forming a source contact hole above the P-type body region that penetrates the N-type source region;

[0025] S10: Filling the source contact hole with metal and etching the metal to form a source metal layer.

[0026] Furthermore, the depth of the groove is 5 μm-10 μm, the thickness of the first oxide layer is 3000 Å-10000 Å, and the thickness of the first oxide layer is 1000 Å-2000 Å.

[0027] Further, S2: etching the first main surface to form a trench in the N-type epitaxial layer, wherein the lower portion of the trench is stepped and the step surface faces upward, specifically comprising the following steps:

[0028] S210: etching the first main surface by shielding with the patterned mask layer to form an original trench in the first conductive type epitaxial layer;

[0029] S220: depositing an original protective layer on the sidewall and bottom of the original trench;

[0030] S230: etching away the original protective layer on the bottom surface of the original groove, and the original protective layer on the side surface of the original groove extends downward to contact with the bottom surface of the original groove;

[0031] S240: etching the exposed bottom surface of the original groove to form a primary groove;

[0032] S250: growing a primary protective layer on the surface of the primary groove and in the original protective layer located on the side of the original groove;

[0033] S260: etching away the primary protection layer on the bottom surface of the primary trench, and the primary protection layer on the side surface of the primary trench extends downward to contact with the bottom surface of the primary trench;

[0034] S270: etching the exposed bottom surface of the primary trench to form a secondary trench;

[0035] S280: Etch away all oxide layers to form the final trench.

[0036] Furthermore, after step S270 and before step S280, steps S260 and S270 are repeated to etch away the oxide layer at the bottom of the previous level of grooves, and to etch the exposed portion of the previous level of grooves to form the next level of grooves.

[0037] From the above, it can be seen that the MOS structure and manufacturing method with a stepped deep trench shielded gate provided by the present invention have the following advantages compared with the prior art: in the present invention, the lower side of the trench is stepped, thereby ensuring that the thickness of the first oxide layer on each step is equal and the first oxide layer 420 is also stepped, thereby avoiding multiple etching of the first oxide layer, reducing the complexity of the process and improving the device's withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a structural schematic diagram of the first aspect of the present invention.

[0039] Figure 2 This is a schematic diagram of step S3 in the second aspect of the present invention.

[0040] Figure 3 This is a schematic diagram of step S4 in the second aspect of the present invention.

[0041] Figure 4 This is a schematic diagram of step S5 in the second aspect of the present invention.

[0042] Figure 5 This is a schematic diagram of step S6 in the second aspect of the present invention.

[0043] Figure 6 This is a schematic diagram of step S7 in the second aspect of the present invention.

[0044] Figure 7 This is a schematic diagram of step S8 in the second aspect of the present invention.

[0045] Figure 8 This is a schematic diagram of step S9 in the second aspect of the present invention.

[0046] Fig. 9 It is a schematic diagram of step S210 in the second aspect of the present invention.

[0047] Fig.10 It is a schematic diagram of step S220 in the second aspect of the present invention.

[0048] Fig.11 It is a schematic diagram of step S230 in the second aspect of the present invention.

[0049] Fig.12 It is a schematic diagram of step S240 in the second aspect of the present invention.

[0050] Fig.13It is a schematic diagram of step S250 in the second aspect of the present invention.

[0051] Fig.14 It is a schematic diagram of step S260 in the second aspect of the present invention.

[0052] Fig.15 It is a schematic diagram of step S270 in the second aspect of the present invention.

[0053] Fig.16 It is a schematic diagram of step S280 in the second aspect of the present invention.

[0054] 1. N-type heavily doped substrate, 2. N-type epitaxial layer, 3. Trench, 311. Original trench, 312. Original protection layer, 321. Primary trench, 322. Primary protection layer, 331. Secondary trench, 4. Shielding gate region, 410. Shielding gate, 420. First oxide layer, 5. Gate region, 510. Gate conductive polysilicon, 520. Second oxide layer, 6. P-type body region, 7. N-type source region, 8. Insulating dielectric layer, 9. Source contact hole, 10. Source metal layer. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. The same parts are represented by the same figure numerals. It should be noted that the words "front", "rear", "left", "right", "up" and "down" used in the following description refer to the directions in the accompanying drawings. The words "inside" and "outside" used refer to the direction toward or away from the geometric center of a specific component, respectively.

[0056] A MOS structure with a stepped deep trench shielded gate, the MOS structure with a stepped deep trench shielded gate includes a cell region and a terminal protection zone, the cell region is located in the central region of the device, the terminal protection zone surrounds the cell region, the cell region is formed by a plurality of MOSFET device units connected in parallel; each of the MOSFETs includes a semiconductor substrate, the semiconductor substrate includes an N-type heavily doped substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped substrate 1, the upper surface of the N-type epitaxial layer 2 is a first main surface of the semiconductor substrate, and the lower surface of the N-type heavily doped substrate 1 is a second main surface of the semiconductor substrate A groove 3 is formed in the N-type epitaxial layer 2, and the groove 3 extends from the first main surface to the second main surface; a P-type body region 6 is provided in the N-type epitaxial layer 2 on both sides of the groove 3, and an N-type source region 7 is provided on the P-type body region 6, and an insulating dielectric layer 8 is provided on the groove 3 and the N-type source region 7, and source contact holes 9 are provided on both sides of the insulating dielectric layer 8, and the source contact holes 9 are filled with metal, and a source metal layer 10 is provided on the insulating dielectric layer 8, and the source metal layer 10 connects the metals in the two source contact holes 9, and the source contact hole 9 extends to the P-type body region 6 and contacts the N-type source region 7. Thus, the source metal layer 10 is connected to the P-type body region 6 through the source contact hole 9, and is in ohmic contact with the N-type source region 7.

[0057] The trench 3 is divided into an upper part and a lower part. The inner wall of the lower part of the trench 3 is stepped to form a stepped shielding gate region 4. The upper part of the trench 3 is a gate region 5. The gate region 5 and the shielding gate region 4 are separated by an oxide layer.

[0058] The shielding gate region 4 includes a stepped shielding gate 410 and a stepped first oxide layer 420 located on both sides of the shielding gate 410 . The gate region 5 includes a gate conductive polysilicon 510 and a second oxide layer 520 located on both sides of the gate conductive polysilicon 510 .

[0059] The depth of the groove 3 of the present invention is 5-10 μm, the number of steps at the lower part of the stepped groove 3 is 3-5, and the height of each step is 1-3 μm. The number of steps of the stepped first oxide layer 420 is 3-5, the thickness of the first oxide layer 420 of each step is 3000A-10000A, and the thickness of the second oxide layer 520 is: 1000-2000A.

[0060] It can be understood that in the present invention, the lower side of the groove 3 is stepped, so as to ensure that the thickness of the first oxide layer 420 on each step is equal and the first oxide layer 420 is also stepped, thereby avoiding multiple etching of the first oxide layer 420, reducing the complexity of the process and improving the device's withstand voltage.

[0061] As a second aspect of the present invention:

[0062] A method for manufacturing a MOS having a stepped deep trench shielded gate 410 is provided. The method for manufacturing a MOS having a stepped deep trench shielded gate 410 specifically comprises:

[0063] S1: providing an N-type heavily doped substrate 1, and growing an N-type epitaxial layer 2 on the N-type heavily doped substrate 1, wherein the upper surface of the N-type epitaxial layer 2 is a first main surface, and the lower surface is a second main surface;

[0064] S2: etching the first main surface to form a trench 3 in the N-type epitaxial layer 2, wherein the depth of the trench 3 is 5 μm to 10 μm, and the lower part of the trench 3 is stepped with the step surface facing upward;

[0065] S2: etching the first main surface to form a trench 3 in the N-type epitaxial layer 2, wherein the lower portion of the trench 3 is stepped and the step surface faces upward, specifically comprising the following steps:

[0066] S210: etching the first main surface by shielding with the patterned mask layer to form an original trench 311 in the first conductive type epitaxial layer;

[0067] S220: depositing an original protection layer 312 on the sidewall and bottom of the original trench 311; the material of the original protection layer 312 is preferably silicon nitride;

[0068] S230: etching away the original protection layer 312 on the bottom surface of the original groove 311, and the original protection layer 312 on the side surface of the original groove 311 extends downward to contact with the bottom surface of the original groove 311;

[0069] S240: Etching the exposed bottom surface of the original groove 311 to form a primary groove 321; due to the protection of the sidewall by the protection layer 312, only the bottom of the original groove is etched, thereby forming a stepped groove 321.

[0070] S250: growing a primary protective layer 322 on the surface of the primary groove 321 and in the original protective layer 312 located on the side of the original groove 311; the material of the primary protective layer 322 is preferably silicon nitride;

[0071] S260: etching away the primary protection layer 322 on the bottom surface of the primary trench 321 , and the primary protection layer 322 on the side surface of the primary trench 321 extends downward to contact with the bottom surface of the primary trench 321 ;

[0072] S270: etching the exposed bottom surface of the primary trench 321 to form a secondary trench 331;

[0073] S280: etching away all oxide layers to form a final trench 3;

[0074] S3: using a thermal oxidation growth process to grow a first oxide layer 420 on the surface of the groove 3, wherein the thickness of the first oxide layer 420 is 3000 Å to 10000 Å;

[0075] S4: depositing polysilicon in the trench 3, and etching back the polysilicon, leaving only the polysilicon at the bottom of the trench 3 to form a shielding gate 410;

[0076] S5: etching away the first oxide layer 420 on the upper side surface of the trench 3 using a wet etching process;

[0077] S6: growing a second oxide layer 520 on the upper side surface of the trench 3 and the upper surface of the shield gate 410, wherein the thickness of the first oxide layer 420 is 1000A-2000A;

[0078] S7: depositing polysilicon in the upper portion of the trench 3 to form gate conductive polysilicon 510;

[0079] S8: Under the shielding of the patterned photoresist, firstly implant P-type impurities on one side of the trench 3 to form a P-type body region 6, and then implant N-type impurities on the P-type body region 6 to form an N-type source region 7; similarly, firstly implant P-type impurities on one side of the trench 3 to form a P-type body region 6, and then implant N-type impurities on the P-type body region 6 to form an N-type source region 7;

[0080] S9: depositing an insulating dielectric layer 8 on the first main surface, etching the insulating dielectric layer 8, and forming a source contact hole 9 above the P-type body region 6 and penetrating the N-type source region 7;

[0081] S10: Filling the source contact hole 9 with metal and etching the metal to form source metal.

[0082] It should be explained that after step S270 and before step S280, steps S260 and S270 are repeated to etch away the oxide layer on the bottom surface of the previous level groove 3 and to etch the exposed portion of the previous level groove 3 to form the next level groove 3.

[0083] It can be understood that in the present invention, the lower side of the groove 3 is stepped, so as to ensure that the thickness of the first oxide layer 420 on each step is equal and the first oxide layer 420 is also stepped, thereby avoiding multiple etching of the first oxide layer 420, reducing the complexity of the process and improving the device's withstand voltage.

[0084] Those skilled in the art should understand that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a MOS with a stepped deep trench shielded gate. It is characterized in that The manufacturing method of the MOS with stepped deep trench shielded gate comprises: S1: providing an N-type heavily doped substrate (1), and growing an N-type epitaxial layer (2) on the N-type heavily doped substrate (1), wherein the upper surface of the N-type epitaxial layer (2) is a first main surface, and the lower surface is a second main surface; S2: etching the first main surface to form a trench (3) in the N-type epitaxial layer (2), wherein the lower portion of the trench (3) is in a stepped shape with the step surface facing upwards; S3: using a thermal oxygen growth process to grow a first oxide layer (420) on the surface of the groove (3); S4: depositing polysilicon in the lower part of the trench (3) to form a shielding gate (410); S5: etching away the first oxide layer (420) on the upper side surface of the trench (3); S6: growing a second oxide layer (520) on the upper side surface of the trench (3) and the upper surface of the shielding gate (410); S7: depositing polysilicon in the upper portion of the trench (3) to form gate conductive polysilicon (510); S8: Under the cover of the patterned photoresist, firstly inject P-type impurities into one side of the trench (3) to form a P-type body region (6), and then inject N-type impurities into the P-type body region (6) to form an N-type source region (7); similarly, firstly inject P-type impurities into one side of the trench (3) to form a P-type body region (6), and then inject N-type impurities into the P-type body region (6) to form an N-type source region (7); S9: depositing an insulating dielectric layer (8) on the first main surface, etching the insulating dielectric layer (8), and forming a source contact hole (9) above the P-type body region (6) and penetrating the N-type source region (7); S10: filling the source contact hole (9) with metal, and etching the metal to form a source metal layer (10); The S2 specifically includes the following steps: S210: etching the first main surface by shielding with the patterned mask layer to form an original trench (311) in the first conductive type epitaxial layer; S220: depositing an original protective layer (312) on the sidewalls and bottom of the original groove (311); S230: etching away the original protective layer (312) on the bottom surface of the original groove (311), so that the original protective layer (312) on the side surface of the original groove (311) extends downward to contact with the bottom surface of the original groove (311); S240: etching the exposed bottom surface of the original groove (311) to form a primary groove (321); S250: growing a primary protective layer (322) on the surface of the primary groove (321) and in the original protective layer (312) located on the side of the original groove (311); S260: etching away the primary protective layer (322) on the bottom surface of the primary groove (321), so that the primary protective layer (322) on the side surface of the primary groove (321) extends downward to contact with the bottom surface of the primary groove (321); S270: etching the exposed bottom surface of the primary groove (321) to form a secondary groove (331); S280: Etching away all oxide layers to form the final trench (3).

2. The method for manufacturing a shielded gate MOS with a stepped deep trench as claimed in claim 1, It is characterized in that The depth of the groove (3) is 5 μm to 10 μm, the thickness of the first oxide layer (420) is 3000 Å to 10000 Å, and the thickness of the first oxide layer (420) is 1000 Å to 2000 Å.

3. The method for manufacturing a shielded gate MOS with a stepped deep trench as claimed in claim 1, It is characterized in that After step S270 and before step S280, steps S260 and S270 are repeated to etch away the oxide layer on the bottom surface of the previous level groove (3), and to etch the exposed portion of the previous level groove (3) to form the next level groove (3).

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