Method of forming a semiconductor device

Abstract

Etchants are used to remove semiconductor material. In some embodiments, an oxidizing agent is added to the etchant to react with the surrounding semiconductor material and form a protective layer. The use of the protective layer helps to avoid damage from other components in the etchant.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to an etching solution composition for removing a dummy gate. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers onto a semiconductor substrate. The layers are then patterned using photolithography to form circuit components and units on the substrate.

[0003] In the semiconductor industry, the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, and the like) is continuously improved by continuously reducing the minimum structural dimensions to integrate more components within a given area. However, as the minimum structural dimensions decrease, additional problems arise that need to be solved. Summary of the Invention

[0004] One embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a dummy gate on a semiconductor fin; and removing the dummy gate from the semiconductor fin using a first etching solution, wherein the first etching solution comprises: a solvent, a first etchant in the solvent, and an oxidant in the solvent. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a diagram illustrating forming a dummy gate on a semiconductor fin in some embodiments.

[0006] Figure 2A and 2B FIG. 4 is a diagram showing the formation of source / drain regions in some embodiments.

[0007] Figure 3A and 3B FIG. 4 is a diagram showing removal of a dummy gate in some embodiments.

[0008] Figure 4A and 4B FIG. 4 is a diagram illustrating forming a replacement gate in some embodiments.

[0009] Description of Reference Numerals

[0010] B-B' line segment.

[0011] H1 First height.

[0012] T1 first thickness.

[0013] W1 first width.

[0014] 100 semiconductor devices.

[0015] 101 substrate.

[0016] 103 groove.

[0017] 105 First Isolation Area.

[0018] 107 fins.

[0019] 109 dummy gate dielectric layer.

[0020] 111 dummy gate.

[0021] 113 first spacer.

[0022] 115 stack.

[0023] 117 Gate pin.

[0024] 201 Source / drain region.

[0025] 203 interlayer dielectric layer.

[0026] 301 wet etching solution.

[0027] 303 arrows.

[0028] 305 protected area.

[0029] 401 Gate Stack.

[0030] 403 first dielectric material.

[0031] 405 First metal material.

[0032] 407 Second metal material.

[0033] 409 Third metal material.

[0034] 411 cap layer. DETAILED DESCRIPTION

[0035] It is understood that the different embodiments or examples provided below may implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify the present invention rather than to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by other additional components rather than in direct contact. In addition, numbers may be repeated in various examples of the present disclosure, but these repetitions are only used to simplify and explain more clearly, and do not mean that units with the same numbers between different embodiments and / or settings have the same correspondence.

[0036] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify the description of an element relative to another element in a drawing. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or other angles, so directional terms are used only to describe the orientation shown.

[0037] The following embodiments relate to a replacement gate FinFET fabricated at a sub-10nm process node, but are not limited thereto and the embodiments described herein may be used in a wide variety of configurations and structures.

[0038] Figure 1 FIG2 is a perspective view of a semiconductor device 100, such as a fin field-effect transistor (FFET) device. In one embodiment, semiconductor device 100 includes a substrate 101 having a trench 103 formed therein. Substrate 101 may be a silicon substrate, but other substrates such as semiconductor-on-insulator (SIO), strained SIO, and silicon-germanium-on-insulator (SiGe-on-insulator) may also be used. Substrate 101 may be a p-type semiconductor, but in other embodiments, substrate 101 may be an n-type semiconductor.

[0039] The first trench 103 may be formed in the initial step of forming the first isolation region 105. The first trench 103 may be formed by using a masking layer (not shown). Figure 1 ) in conjunction with a suitable etching process. For example, the shielding layer can be a hard mask comprising silicon nitride, which can be formed by a chemical vapor deposition process. However, other materials such as oxides, oxynitrides, silicon carbide, combinations thereof, or the like can also be used, and the formation process can also be other processes such as plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or a nitridation step after forming silicon oxide. Once the shielding layer is formed, a suitable photolithography process can be performed to pattern the shielding layer to expose those portions of the substrate 101 that are to be removed (for forming the first trench 103).

[0040] However, as is known to those skilled in the art, the above-described process and materials for forming the shielding layer are not the only methods for protecting portions of the substrate 101 and exposing other portions of the substrate 101 to form the first trench 103. Any suitable process, such as patterning and developing a photoresist, may be used to expose portions of the substrate 101 that will be removed to form the first trench 103. All such methods are fully encompassed within the scope of the embodiments of the present invention.

[0041] Once the masking layer is formed and patterned, a first trench 103 is formed in the substrate 101. Although any suitable process may be used, a suitable process such as reactive ion etching is used to remove the exposed substrate 101 in order to form the first trench 103 in the substrate 101. In one embodiment, the first depth of the first trench 103 from the surface of the substrate 101 may be less than about For example,

[0042] However, those skilled in the art will appreciate that the above process for forming the first trench 103 is only one possible process and not the only embodiment. In fact, any suitable process for forming the first trench 103 may be used, including any number of masking and removal steps.

[0043] In addition to forming the first trench 103, the masking and etching process also forms fins 107 from those portions of the substrate 101 that are not removed. For ease of illustration, the fins 107 are separated from the substrate 101 by a dotted line in the figures, but this separation is physically unnecessary. These fins 107, as described below, can be used to form the channel region of a multi-gate fin field effect transistor device. Although Figure 1 Only three fins 107 formed from substrate 101 are shown, but any number of fins 107 may be used.

[0044] The width of the fins 107 on the surface of the substrate 101 can be between about 5 nm and about 80 nm, such as about 30 nm. Furthermore, the distance between the fins 107 can be between about 10 nm and about 100 nm, such as about 50 nm. Arranging the fins 107 in this manner allows the fins 107 to form separate channel regions while still being close enough to share a common gate (as further described below).

[0045] Once the first trench 103 and the fin 107 are formed, a dielectric material may be filled into the first trench 103 and the dielectric material in the first trench 103 may be recessed to form the first isolation region 105. The dielectric material may be an oxide material, a high-density plasma oxide, or the like. After an optional cleaning step and a step of lining the first trench 103, the dielectric material may be formed using chemical vapor deposition (e.g., a high aspect ratio process), high-density plasma chemical vapor deposition, or other suitable methods known in the art.

[0046] The first trench 103 and the substrate 101 may be overfilled with a dielectric material, and then the excess material outside the first trench 103 and the fin 107 may be removed by chemical mechanical polishing, etching, a combination thereof, or a similar suitable process, thereby filling the first trench 103. In one embodiment, the removal process also removes any dielectric material on the fin 107, so that the step of removing the dielectric material exposes the surface of the fin 107 for subsequent processing steps.

[0047] Once the dielectric material is filled into the first trench 103, the dielectric material may then be recessed from the surface of the fin 107. The recessing step may expose at least a portion of the sidewalls of the fin 107 adjacent to the upper surface of the fin 107. The dielectric material may be recessed by wet etching, such as immersing the upper surface of the fin 107 in an etchant such as hydrofluoric acid, although other etchants (such as hydrogen) or methods (such as reactive ion etching, dry etching with ammonia / nitrogen trifluoride as an etchant, chemical oxide removal, or dry chemical cleaning) may also be used. The dielectric material may be recessed from the surface of the fin 107 by a distance between about to about Between, such as In addition, the recessing step also removes the dielectric material remaining on the fin 107 to ensure that the fin 107 is exposed for subsequent processing.

[0048] However, as known to those skilled in the art, the above steps may only be a portion of the entire process for filling and recessing the dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap filling step, a combination of the above, or similar methods may also be used to form the dielectric material and fill the first trench 103 with the dielectric material. All possible process steps are fully included in the scope of the embodiments of the present invention.

[0049] After forming the first isolation region 105, a dummy gate dielectric layer 109, a dummy gate 111 on the dummy gate dielectric layer 109, and a first spacer 113 may be formed on each fin 107. In one embodiment, the dummy gate dielectric layer 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other known method for forming a gate dielectric layer in the art. The thickness of the dummy gate dielectric layer 109 may be between about 100 and 100 nm. to about Between (as agreed ), depending on the technique used to form the dummy gate dielectric layer. However, any suitable thickness may be used.

[0050] The dummy gate dielectric layer 109 may include a material such as silicon dioxide or silicon oxynitride, and its thickness may be between about to about Between (as agreed The dummy gate dielectric layer 109 may be composed of a high dielectric constant material (a material with a dielectric constant greater than about 5), such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or a combination thereof, with an equivalent oxide thickness between about to about Between (such as less than or equal to about In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k dielectric materials may also be used for the dummy gate dielectric layer 109 .

[0051] The dummy gate 111 may comprise a conductive material, which may be tungsten, aluminum, copper, aluminum copper, tungsten, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, a combination thereof, or the like. The dummy gate 111 may be deposited by chemical vapor deposition, sputtering deposition, or other known techniques for depositing conductive materials. The thickness of the dummy gate 111 may be between about to about The upper surface of the dummy gate 111 may have a non-planar upper surface, and the upper surface of the dummy gate 111 may be planarized before patterning the dummy gate 111 or etching the gate. At this time, ions may or may not be introduced into the dummy gate 111. For example, ions may be introduced by ion implantation technology.

[0052] Once the dummy gate 111 is formed, the dummy gate 111 may be patterned to form a series of stacks 115 on the fin 107. The stacks 115 may define multiple channel regions below the dummy gate dielectric layer 109 on each side of the fin 107. The stacks 115 may be formed by depositing and patterning a gate mask (not shown). Figure 1 The gate shield can be formed by combining conventional shielding and sacrificial materials such as, but not limited to, silicon oxide, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon oxycarbide, and / or silicon nitride, and can be deposited to a thickness of about 1000 nm. to about A dry etching process may be used to etch the dummy gate 111 to form a patterned stack 115 .

[0053] In one embodiment, the patterned stack 115 may have a first width W1, which allows subsequent processing to effectively remove the dummy gate 111 and replace it with a gate. As such, the precise width depends at least in part on the device design, and the first width W1 may be between about to about Between, such as However, any suitable size may be used.

[0054] Furthermore, patterning the dummy gate 111 may create gate pins 117 (e.g., poly pins). Specifically, the shape of the fin 107 and process variations may cause variations in etching, resulting in unintended portions of dummy gate 111 material remaining and bridging the corner between the dummy gate dielectric layer 109 on the fin 107 and the remaining material of the dummy gate 111. These gate pins 117 may misalign the subsequent spacer material (described below), potentially causing subsequent etchant to diffuse toward the fin 107.

[0055] Once the stack 115 is patterned, first spacers 113 may be formed. The first spacers 113 may be formed on both sides of the stack 115. The first spacers 113 are typically formed by conformally depositing a spacer layer (not shown) on a previously formed structure. Figure 1 ). The spacer layer may comprise silicon nitride, oxynitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, oxide, or the like, and may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or other methods known in the art. The spacer layer and the dielectric material in the first isolation region 105 may be the same material, or may be different materials with different etching characteristics. The first spacers 113 may then be patterned to form the first spacers 113, for example, by removing the spacer layer from the horizontal surfaces of the structure through one or more etching passes.

[0056] In one embodiment, the first spacer 113 may have a first thickness T1, which helps to protect the source / drain regions (not shown) formed subsequently. Figure 1 , but will be paired with Figure 2A As described below), the first thickness T1 is still small enough to reduce the overall device size. Thus, in some embodiments, the first thickness T1 may be between about to about Between, such as However, any suitable thickness may be used.

[0057] like Figure 2A and 2B As shown, the exposed portions of the dummy gate dielectric layer 109 and the fin 107 that are not protected by the stack 115 and the first spacer 113 are removed, and the source / drain regions 201 are regrown. Figure 2B It is along Figure 2A In one embodiment, the exposed portion of the dummy gate dielectric layer 109 may be removed using any suitable method, such as wet etching or dry etching, where the etchant is selective to the material of the dummy gate dielectric layer 109 to expose the underlying material of the fin 107. However, any suitable removal method may be used.

[0058] The step of removing the fin 107 from those areas not protected by the stack 115 and the first spacer 113 can be a reactive ion etch using the stack 115 and the first spacer 113 as a hard mask, or any other suitable removal process. The removal step can be continued until the fin 107 is coplanar with the surface of the first isolation region 105 (as shown), or is below the plane of the first isolation region 105.

[0059] Once these portions of the fins 107 are removed, a hard mask (not shown) is placed and patterned to cover the dummy gates 111 to prevent growth, and the source / drain regions 201 can be regrown to contact each fin 107. In one embodiment, the source / drain regions 201 can be regrown. In some embodiments, the source / drain regions 201 can be regrown to form a stressor layer that can apply stress to the channel region of the fin 107 below the stack 115. In one embodiment, when the fin 107 comprises silicon and the fin field-effect transistor is a p-type device, the source / drain regions 201 can be regrown by selectively epitaxially depositing a material (e.g., doped silicon such as silicon phosphide, or a material with a different lattice constant than the channel region, such as silicon germanium). In other embodiments, the material of the source / drain regions 201 may include gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, indium antimonide, gallium arsenide phosphide, aluminum gallium nitride, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, combinations thereof, or the like. The epitaxial growth process may utilize precursors such as silane, dichlorosilane, germanium, or the like and may last from about 5 minutes to about 120 minutes (e.g., about 30 minutes).

[0060] In one embodiment, the thickness of the source / drain region 201 may be between about to about and the first height H1 on the first isolation region 105 may be between about to about Between (as agreed In this embodiment, the source / drain regions 201 may have a height above the upper surface of the first isolation region 105 ranging from about 5 nm to about 250 nm, such as about 100 nm. However, any suitable height may be used.

[0061] Once the source / drain regions 201 are formed, appropriate dopants may be implanted into the fins 107 to implant dopants into the source / drain regions 201. For example, p-type dopants such as boron, gallium, indium, or the like may be implanted to form a p-type metal oxide semiconductor device. On the other hand, n-type dopants such as phosphorus, arsenic, antimony, or the like may be implanted to form an n-type metal oxide semiconductor device. These dopant implantation methods may utilize the stack 115 and the first spacer 113 as a mask. It should be noted that those skilled in the art will appreciate that many other processes, steps, or similar methods may be used to implant dopants. For example, those skilled in the art will appreciate that various implantation methods utilize various combinations of spacers and liner layers to form source / drain regions of specific shapes or characteristics for specific purposes. Any of these processes may be used to implant dopants, and the foregoing is not intended to limit the embodiments to the foregoing steps.

[0062] Furthermore, when forming the source / drain regions 201, the hard mask covering the dummy gate 111 is removed. In one embodiment, a wet etch process or a dry etch process that is selective to the material of the hard mask can be used to remove the hard mask. However, any suitable removal process can be used.

[0063] like Figure 2A As shown, an interlayer dielectric layer 203 is also formed on the stack 115 and the source / drain region 201. Figure 2A The interlayer dielectric layer 203 may include a material such as borophosphosilicate glass, but any suitable dielectric material may be used. The interlayer dielectric layer 203 may be formed by plasma enhanced chemical vapor deposition, but may also be formed by other processes such as low pressure chemical vapor deposition. The thickness of the interlayer dielectric layer 203 may be between about to about Once the interlayer dielectric layer 203 is formed, a planarization process such as a chemical mechanical polishing process may be used to planarize the interlayer dielectric layer 203 and the first spacers 113. However, any suitable process may be used.

[0064] like Figure 3A and 3B As shown, the dummy gate 111 is removed from between the first spacers 113. In one embodiment, the step of removing the dummy gate 111 may be performed by a wet etching process, wherein the wet etching solution 301 used can remove the material (e.g., silicon) of the dummy gate 111 and protect the source / drain regions 201 formed by the epitaxial process.

[0065] In one embodiment, the wet etching solution 301 includes a solvent, an etchant, a selective oxidant, and a wetting agent. In one embodiment, the solvent serves as a mixing and delivery system, effectively placing and removing the wet etching solution 301 so that the wet etching solution 301 contacts the dummy gate 111 and protects surrounding materials, such as oxides. For example, the solvent can be a bulky glycol molecule, such as ethylene glycol, diethylene glycol, triethylene glycol, ethylene glycol butyl ether, carbitol, combinations thereof, or the like. However, any suitable solvent may be used.

[0066] In addition to the solvent, the wet etching solution 301 may also include a non-hydrocarbon solvent to facilitate the placement of the wet etching solution 301. In one embodiment, the non-hydrocarbon solvent may include water, such as deionized water (e.g., ultrapure deionized water). However, any suitable non-hydrocarbon solvent may be used.

[0067] The etchant is used to actually remove the material of the dummy gate 111, such as silicon. In certain embodiments, a multi-component base, such as a strong base and a weak base, may be used. For example, the strong base may be tetramethylammonium hydroxide, ammonium hydroxide, potassium hydroxide, a combination thereof, or the like, which will dissociate in a solvent or a non-hydrocarbon solvent to generate OH. - However, any suitable strong etchant may be used.

[0068] In certain embodiments, tetramethylammonium hydroxide or ammonium hydroxide dissociates to produce OH - ions, and OH - The ions will react with the material of the dummy gate 111 (eg, silicon) to remove the material of the dummy gate 111. In a specific embodiment, the material of the dummy gate 111 is silicon, and silicon will react with OH in the wet etching solution. - The ions react with a non-hydrocarbon solvent (such as water) as shown in the following redox reaction.

[0069] Si+2OH - →Si(OH)2 2+ +4e Formula 1

[0070] Si(OH)2 2+ +4H2O+4e→Si(OH)6 2- +2H2 Formula 2

[0071] The exposed material of the dummy gate 111 may be removed by using a strong alkaline component of the etchant.

[0072] However, it may be difficult to control the etching rate when using strong etchants, which may cause additional damage such as over-etching. Therefore, in order to help adjust the etching rate of the wet etching solution, a weak base can be used. In a particular embodiment, the weak base can be an alkaline component with large steric hindrance to buffer the wet etching solution and replenish the OH consumed by the reaction with silicon. -ions (see Formula 1). For example, embodiments with large steric barriers can hinder strong bases from approaching the surface of the dummy gate 111. Weak bases can hinder, rather than prevent, strong bases from approaching the surface of the dummy gate 111 to help adjust the chemical reaction so that the weak base concentration can effectively control the etching rate of the wet etching solution.

[0073] In certain embodiments, the weak base is different from the strong base. Thus, the weak base depends at least in part on the material of the strong base. In embodiments where the strong base is tetramethylammonium hydroxide or aluminum hydroxide, the weak base may be an amine such as monoethanolamine (volume 10 ... / molecule), triethanolamine (volume is / molecule), tetrabutylammonium hydroxide, trimethylphenylammonium hydroxide, combinations thereof, or the like. In addition, in some embodiments, the strong base is not tetramethylammonium hydroxide, and the weak base may be tetramethylammonium hydroxide (whose volume is / molecule). These chemicals may have the following structures:

[0074]

[0075] However, any suitable weak base may be used.

[0076] However, the etchant used has low selectivity between the material of the dummy gate 111 (e.g., polysilicon) and the material of the source / drain regions 201 (e.g., silicon phosphide). Consequently, when removing the dummy gate 111, the wet etching solution 301 contacts the first spacer 113 and the dummy gate dielectric layer 109. The etchant in the wet etching solution 301 diffuses (as indicated by arrows 303) through the first spacer 113 and the dummy gate dielectric layer 109 and contacts the material of the source / drain regions 201. When the etching selectivity between the material of the dummy gate (e.g., polysilicon) and the material of the source / drain regions 201 (e.g., silicon phosphide) is low, this contact can damage the source / drain regions, requiring a reduction in the overall process tolerance to avoid such damage.

[0077] Thus, to help protect the material (e.g., silicon phosphide) of the source / drain regions 201, an oxidizing agent may be added to the wet etching solution 301 to selectively oxidize the material (e.g., silicon phosphide) of the source / drain regions 201. In one embodiment, the oxidizing agent diffuses through the first spacer 113 along with the strong base and contacts the material of the source / drain regions 201. However, the oxidizing agent, together with the material of the source / drain regions 201, forms a protective area 305 in the source / drain regions 201 adjacent to the first spacer 113 without damaging the material of the source / drain regions 201.

[0078] For example, an oxidant in one embodiment can react with the material of the source / drain region 201 (e.g., silicon phosphide) to form an oxide protection zone 305. This protection zone 305 can provide strong electron acceptor molecules that, through oxidation, passivate the surface, slowing or preventing further diffusion of the etchant into the source / drain region 201. By providing electron acceptor molecules, electrons from the oxidation step will recombine with the electron acceptors and become unavailable for the subsequent reduction step. Reducing or eliminating electrons in the reduction step can reduce or eliminate etchant diffusion damage to the source / drain region 201.

[0079] Thus, the oxidant depends at least in part on the material of the source / drain region 201. In a specific embodiment, the material of the source / drain region 201 is silicon phosphide, and the oxidant can be an N-oxide derivative such as N-methylmorpholine-N-oxide (CAS No. 7529-22-8), 4-methylpyridine-N-oxide, pyridine-N-oxide, combinations thereof, or the like. These compounds can have the following structures:

[0080]

[0081] However, any suitable oxidizing agent may be used.

[0082] In addition, the wet etching solution 301 may optionally contain other additives to aid in the etching process. In one embodiment, a surfactant may be used to enhance the wettability of the wet etching solution 301. For example, the wet etching solution 301 may be a diol molecule having a bulky structure, such as ethylene glycol, diethylene glycol, triethylene glycol, ethylene glycol butyl ether, carbitol, combinations thereof, or the like. These surfactants may have the following structures:

[0083]

[0084] In one embodiment, the wet etching solution 301 can be formed by mixing each individual component into a solvent. For example, some embodiments may include a strong base and a weak base in the solvent, with the strong base concentration ranging from about 0.5% to about 3% (e.g., about 1.3%) and the weak base concentration ranging from about 0.1% to about 20% (e.g., about 5%). Furthermore, the oxidant concentration may be between about 5% and about 20%, such as between about 10% and about 15%. Finally, the solvent concentration may be between about 49.55% and about 75%, such as between about 59.55% and about 70%, such as about 65%, and the non-hydrocarbon solvent concentration may be between about 18.45% and about 23.9%, such as about 18.9%. However, any suitable concentration may be used.

[0085] In a specific embodiment, the oxidant concentration may be about 5%, the strong base concentration may be about 1.3%, the weak base concentration may be about 5%, the solvent concentration may be about 70%, and the non-hydrocarbon solvent concentration may be about 18.45%. Using these concentrations, the etching rate of amorphous silicon may be about / minute, while the native oxide resistance is about 130 minutes. In addition, the thickness of the protection zone 305 is about

[0086] In another specific embodiment, the oxidant concentration may be about 10%, the strong base concentration may be about 1.3%, the weak base concentration may be about 5%, the solvent concentration may be about 65%, and the non-hydrocarbon solvent concentration may be about 18.45%. Using these concentrations, the etching rate of amorphous silicon may be about / minute, while the native oxide resistance is about 270 minutes. In addition, the thickness of the protection zone 305 is about

[0087] In another specific embodiment, the oxidant concentration may be about 15%, the strong base concentration may be about 1.3%, the weak base concentration may be about 5%, the solvent concentration may be about 59.55%, and the non-hydrocarbon solvent concentration may be about 18.9%. Using these concentrations, the etching rate of amorphous silicon may be about / minute, while the native oxide resistance is about 270 minutes. In addition, the thickness of the protection zone 305 is about

[0088] In another specific embodiment, the oxidant concentration may be about 20%, the strong base concentration may be about 1.3%, the weak base concentration may be about 5%, the solvent concentration may be about 49.55%, and the non-hydrocarbon solvent concentration may be about 23.9%. Using these concentrations, the etching rate of amorphous silicon may be about / min, while the native oxide resistance is about 250 min. In addition, the thickness of the protection zone 305 is about

[0089] For comparison, the wet etching solution with a concentration of 1.3% tetramethylammonium hydroxide has an etching rate of about / minute, while the native oxide resistance is about 5 minutes. In addition, in one embodiment, no oxidant is used, the strong base concentration is about 1.3%, the weak base concentration is about 5%, the solvent concentration is about 75%, and the non-hydrocarbon solvent concentration is about 18.45%, then the amorphous silicon etching rate is about / minute, the native oxide resistance is about 120 minutes, and the thickness of the protection zone 305 is about When the etching rate is between about / minute to about The etch rate for amorphous silicon is between 1000 nm and 1000 nm per minute, which is high enough to etch efficiently while still achieving the desired native oxide resistance improvement.

[0090] Once the wet etching solution 301 is prepared, it can be brought into contact with the material of the dummy gate 111. In one embodiment, an immersion method can be performed to immerse the structure including the material of the dummy gate 111 into a bath of the wet etching solution 301, so that the wet etching solution 301 contacts the material of the dummy gate 111. However, other processes can also be used to bring the wet etching solution 301 into contact with the material of the dummy gate 111, such as a mixing process, a spraying process, a combination thereof, or the like.

[0091] Furthermore, the wet etching process temperature using the wet etching solution 301 may be between about 25° C. and about 70° C., such as about 50° C. Furthermore, the wet etching process may continue until the dummy gate 111 (e.g., amorphous silicon) is removed and the dummy gate dielectric layer 109 is exposed, which may take about 120 seconds to about 600 seconds (e.g., about 360 seconds). However, any suitable temperature and time may be used.

[0092] When a wet etching solution 301 is used in the wet etching process, the wet etching solution 301 can remove the material of the dummy gate 111. Furthermore, during the wet etching process, the wet etching solution 301 diffuses through the dummy gate dielectric layer 109 and contacts the source / drain regions 201. However, in the presence of an oxidizing agent (e.g., N-methylmorpholine-N-oxide), the material of the source / drain regions 201 (e.g., silicon phosphide) can react with the oxidizing agent to form a protective region 305, for example, oxidizing the material of the source / drain regions 201. This protective region 305 prevents additional damage caused by the diffusion of residual components in the wet etching solution 301.

[0093] In certain embodiments, a protection zone 305 may be formed along the interface between the dummy gate dielectric layer 109 and the source / drain region 201. For example, the protection zone 305 may extend outward from the dummy gate dielectric layer 109 and have a second thickness T2. The second thickness T2 may be between about to about Between, such as However, any suitable thickness may be used.

[0094] like Figure 4A and 4B As shown, once the material (eg, polysilicon) of the dummy gate 111 is removed using a wet etching solution 301 , material is refilled into the opening left by the removal step to form a gate stack 401 . Figure 4B It is along Figure 4A If necessary, a wet etching process may be used to remove the exposed portion of the dummy gate dielectric layer 109, and the wet etching process may include an etchant that is selective for the material of the dummy gate 111. However, any suitable removal process may be used.

[0095] Once the dummy gate 111 is removed, a gate stack 401 may be deposited. In a specific embodiment, the gate stack 401 includes a first dielectric material 403, a first metal material 405, a second metal material 407, and a third metal material 409. In one embodiment, the first dielectric material 403 is a high dielectric constant material such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, combinations thereof, or the like, and may be deposited by atomic layer deposition, chemical vapor deposition, or the like. The first dielectric material 403 may be deposited to a thickness between about 1000 Å and 2000 Å. to about However, any suitable material and thickness may be used.

[0096] The first metal material 405 may be adjacent to the first dielectric material 403, and the composition of the first metal material 405 may be a metal material such as titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations thereof, or the like. The deposition process of the first metal material 405 may be atomic layer deposition, chemical vapor deposition, sputtering, or the like, and the deposition thickness may be between about 1000 Å and 2000 Å. to about However, the first metal material 405 can be deposited using any suitable deposition process or thickness.

[0097] The second metal material 407 may be adjacent to the first metal material 405. In certain embodiments, the second metal material 407 may be similar to the first metal material 405. For example, the second metal material 407 may be composed of a metal material such as titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. Furthermore, the deposition process of the second metal material 407 may be atomic layer deposition, chemical vapor deposition, sputtering, or the like, and the deposition thickness thereof may be between about 100 and 200 nm. to about However, the second metal material 407 can be deposited using any suitable deposition process or thickness.

[0098] The opening remaining after the dummy gate 111 is removed is filled with a third metal material 409. In one embodiment, the third metal material 409 is a metal material such as tungsten, aluminum, copper, aluminum copper, tungsten, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, a combination thereof, or the like, and the deposition process thereof may be atomic layer deposition, chemical vapor deposition, sputtering, or the like to fill or overfill the opening remaining after the dummy gate 111 is removed. In a specific embodiment, the deposition thickness of the third metal material 409 is between about to about However, the third metal material 409 may be made of any suitable material, deposition process, or deposition thickness.

[0099] Once the opening left by removing the dummy gate 111 is filled, the material filling the opening can be planarized to remove any material outside the opening left by removing the dummy gate 111. In certain embodiments, the removal step can utilize a planarization process such as chemical mechanical polishing. However, any suitable planarization and removal process can be used.

[0100] After forming and planarizing the material of gate stack 401, the material of gate stack 401 is recessed and covered with capping layer 411. In one embodiment, the method for recessing the material of gate stack 401 may utilize a wet or dry etching process, wherein the etchant employed is selective for the material of gate stack 401. In one embodiment, the recessing distance of gate stack 401 may be between approximately 5 nm and approximately 150 nm, such as approximately 120 nm. However, any suitable recessing process and distance may be utilized.

[0101] Once the gate stack 401 material is recessed, a capping layer 411 may be deposited and the capping layer 411 and the first spacer 113 may be planarized. In one embodiment, the capping layer 411 may be made of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon oxycarbide, combinations thereof, or the like, and may be deposited by atomic layer deposition, chemical vapor deposition, sputtering, or the like. The capping layer 411 may be deposited to a thickness between about to about Then, a planarization process such as chemical mechanical polishing (CMP) may be used to planarize the cap layer 411 so that the cap layer 411 and the first spacer 113 are coplanar.

[0102] Furthermore, after the gate stack 401 is completed, additional steps may be performed. For example, conductive contacts may be formed to contact the gate stack 401 with the source / drain regions 201, and additional metallization layers may be formed on the gate stack 401 and the source / drain regions 201. However, any suitable additional processes may also be performed.

[0103] In one embodiment, a method for forming a semiconductor device includes forming a dummy gate on a semiconductor fin; and removing the dummy gate from the semiconductor fin using a first etching solution, wherein the first etching solution includes a solvent, a first etchant in the solvent, and an oxidant in the solvent. In one embodiment, the oxidant is N-methylmorpholine-N-oxide. In one embodiment, the first etchant includes a strong base and a weak base. In one embodiment, the strong base is tetramethylammonium hydroxide. In one embodiment, the weak base is monoethanolamine. In one embodiment, the solvent includes ethylene glycol. In one embodiment, the first etching solution also includes a non-hydrocarbon solvent.

[0104] In another embodiment, a method of forming a semiconductor device includes: depositing a dummy gate dielectric layer adjacent to a semiconductor fin; depositing a dummy gate adjacent to the semiconductor fin; depositing a spacer adjacent to the dummy gate dielectric layer; replacing a portion of the semiconductor fin with a source / drain region; and diffusing an oxidant through the dummy gate dielectric layer to form a guard region from a portion of the source / drain region. In one embodiment, the thickness of the guard region is between about to about In one embodiment, the protection zone comprises an oxide of silicon phosphide. In one embodiment, the oxidant applied to the dummy gate dielectric layer is in a wet etching solution. In one embodiment, the wet etching solution diffuses through the dummy gate to contact the source / drain region. In one embodiment, the wet etching solution removes the dummy gate at a rate between about / minute to about In one embodiment, the rate at which the wet etching solution removes the dummy gate is about / minute.

[0105] In another embodiment, a method of forming a semiconductor device includes: forming an epitaxial region adjacent to a semiconductor fin; and applying a wet etching solution to an amorphous silicon region on the semiconductor fin, wherein an oxidant in the wet etching solution diffuses through the dielectric material to react with the epitaxial region and reduce the etchant that diffuses into the epitaxial region. In one embodiment, the epitaxial region includes silicon phosphide. In one embodiment, the protective layer formed by the reaction with the epitaxial region has a thickness between about to about In one embodiment, the oxidizing agent comprises pyridine-N-oxide. In one embodiment, the wet etching solution further comprises: a strong base having a first concentration of approximately 1.3%; a weak base having a second concentration of approximately 5%; a solvent having a third concentration between approximately 49.55% and approximately 75%; and a non-hydrocarbon solvent having a fourth concentration between approximately 18.45% and approximately 23.9%. In one embodiment, the oxidizing agent concentration is approximately 10%.

[0106] The features of the above-described embodiments will facilitate understanding of the present disclosure by those skilled in the art. Those skilled in the art will appreciate that the present disclosure may be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present disclosure and may be altered, substituted, or modified without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device, wherein: It includes: forming a dummy gate on a semiconductor fin; and The dummy gate is removed from the semiconductor fin using a first etching solution, wherein the first etching solution diffuses through the dummy gate to form a protection zone on a portion of a source / drain region. Furthermore, the first etching solution includes: a solvent, a first etchant in the solvent, wherein the first etchant includes a strong base and a weak base, and an oxidant in the solvent.

2. The method for forming a semiconductor device according to claim 1, wherein: The strong base is tetramethylammonium hydroxide.

3. The method for forming a semiconductor device according to claim 2, wherein: The weak base is monoethanolamine.

4. The method for forming a semiconductor device according to claim 1, wherein: It also includes: depositing a dummy gate dielectric layer adjacent to the semiconductor fin; depositing a spacer adjacent to the dummy gate dielectric layer; and A portion of the semiconductor fin is replaced with the source / drain region.

5. The method for forming a semiconductor device according to claim 4, wherein: The first etching solution also diffuses through the spacer.

6. The method for forming a semiconductor device according to claim 5, wherein: The protection zone comprises silicon phosphide oxide.

7. The method for forming a semiconductor device according to claim 4, wherein: The oxidizing agent includes N-oxide derivatives.

8. The method for forming a semiconductor device according to claim 4, wherein: The first etching solution further includes a surfactant.

9. A method of forming a semiconductor device, wherein: It includes: forming a dummy gate on a semiconductor fin; forming an epitaxial region adjacent to the semiconductor fin; and removing the dummy gate from the semiconductor fin using a first etching solution, wherein the first etching solution diffuses through the dummy gate to react with the epitaxial region, Furthermore, the first etching solution includes: a solvent, a first etchant in the solvent, wherein the first etchant includes a strong base and a weak base, and an oxidant in the solvent.

10. The method for forming a semiconductor device according to claim 9, wherein: The first etching solution reacts with the epitaxial region to form a protection layer on the epitaxial region.

11. The method for forming a semiconductor device according to claim 10, wherein: The thickness of the protective layer is between to between.

12. The method for forming a semiconductor device according to claim 10, wherein: The protection layer reduces diffusion of the first etchant into the epitaxial region.

13. The method for forming a semiconductor device according to claim 9, wherein: The oxidizing agent includes N-oxide derivatives.

14. The method for forming a semiconductor device according to claim 9, wherein: Also includes: Depositing a dummy gate dielectric layer adjacent to the semiconductor fin, the dummy gate comprising an amorphous silicon region on the dummy gate dielectric layer; depositing a spacer adjacent to the dummy gate dielectric layer; and A portion of the semiconductor fin is replaced with the epitaxial region.

15. The method for forming a semiconductor device according to claim 9, wherein: The solvent includes ethylene glycol.

16. A method of forming a semiconductor device, wherein: It includes: depositing a dummy gate dielectric layer adjacent to a semiconductor fin; depositing a dummy gate adjacent to the semiconductor fin; depositing a spacer adjacent to the dummy gate dielectric layer; replacing a portion of the semiconductor fin with a source / drain region; and An oxidant is diffused through the dummy gate dielectric layer to form a protection zone from a portion of the source / drain region.

17. The method for forming a semiconductor device according to claim 16, wherein: The thickness of the protection zone is between to between.

18. The method for forming a semiconductor device according to claim 16, wherein: The protection zone comprises silicon phosphide oxide.

19. The method for forming a semiconductor device according to claim 16, wherein: The oxidizing agent applied to the dummy gate dielectric layer is in a wet etching solution.

20. The method for forming a semiconductor device according to claim 19, wherein: The wet etching solution diffuses through the dummy gate to contact the source / drain region.

21. The method for forming a semiconductor device according to claim 19, wherein: The wet etching solution removes the dummy gate at a rate between / minute to / minutes.

22. The method for forming a semiconductor device according to claim 21, wherein: The rate at which the wet etching solution removes the dummy gate is / minute.

23. A method of forming a semiconductor device, wherein: It includes: forming an epitaxial region adjacent to a semiconductor fin; and A wet etching solution is applied to an amorphous silicon region on the semiconductor fin, and an oxidant in the wet etching solution diffuses through a dielectric material to react with the epitaxial region and reduce a plurality of etchants diffused into the epitaxial region.

24. The method for forming a semiconductor device according to claim 23, wherein: The epitaxial region includes silicon phosphide.

25. The method for forming a semiconductor device according to claim 23, wherein: The thickness of the protective layer generated by the reaction with the epitaxial region is between to between.

26. The method for forming a semiconductor device according to claim 23, wherein: The oxidizing agent includes pyridine-N-oxide.

27. The method for forming a semiconductor device according to claim 23, wherein: The wet etching solution further comprises: a strong base having a first concentration of 1.3%; a weak base, the second concentration of which is 5%; a solvent having a third concentration ranging from 49.55% to 75%; and A non-hydrocarbon solvent has a fourth concentration ranging from 18.45% to 23.9%.

28. The method for forming a semiconductor device according to claim 27, wherein: The concentration of the oxidizing agent was 10%.

29. A method of forming a semiconductor device, wherein: It includes: A dummy gate structure is formed, and the steps of forming the dummy gate structure include: depositing a dummy gate dielectric layer on a semiconductor region, depositing a dummy gate on the dummy gate dielectric layer, and forming a spacer along the dummy gate dielectric layer and the side of the dummy gate; etching a portion of the semiconductor region adjacent to the dummy gate structure; epitaxially growing a source / drain region in the etched portion of the semiconductor region; and A wet etching solution is applied to the dummy gate structure, the wet etching solution diffuses through the spacer, and the wet etching solution reacts with the source / drain region.

30. The method for forming a semiconductor device according to claim 29, wherein: The wet etching solution oxidizes a portion of the source / drain region in contact with the spacer.

31. The method for forming a semiconductor device according to claim 29, wherein: The wet etching solution comprises: a solvent; an etchant; and Oxidizing agent.

32. The method for forming a semiconductor device according to claim 31, wherein: The etchant includes a strong base and a weak base.

33. The method for forming a semiconductor device according to claim 31, wherein: The oxidizing agent includes N-oxide derivatives.

34. The method for forming a semiconductor device according to claim 29, wherein: The semiconductor region includes a semiconductor fin.

35. The method for forming a semiconductor device according to claim 29, wherein: The step of applying the wet etching solution etches the material of the dummy gate and also includes forming a gate stack on the semiconductor region.

36. A method of forming a semiconductor device, wherein: It includes: depositing a dummy gate dielectric layer adjacent to a semiconductor fin; depositing a dummy gate adjacent to the semiconductor fin; depositing a spacer adjacent to the dummy gate dielectric layer; replacing a portion of the semiconductor fin with a source / drain region, wherein the source / drain region comprises silicon phosphide; and A wet etching solution is applied to an amorphous silicon region on the semiconductor fin, wherein the step of applying the wet etching solution includes diffusing an oxidant through the dummy gate dielectric layer to form a protection area from a portion of the source / drain region, and the oxidant reacts with the material of the source / drain region to reduce the etchant diffused into the source / drain region.

37. The method for forming a semiconductor device according to claim 36, wherein: The protection zone comprises silicon phosphide oxide.

38. The method for forming a semiconductor device according to claim 36, wherein: The thickness of the protective layer formed by the reaction with the material of the source / drain region is between to between.

39. The method for forming a semiconductor device according to claim 36, wherein: The oxidizing agent includes pyridine-N-oxide.

40. The method for forming a semiconductor device according to claim 36, wherein: The wet etching solution further comprises: a strong base having a first concentration of 1.3%; a weak base, the second concentration of which is 5%; a solvent having a third concentration ranging from 49.55% to 75%; and A non-hydrocarbon solvent has a fourth concentration ranging from 18.45% to 23.9%.

41. The method for forming a semiconductor device according to claim 40, wherein: The concentration of the oxidizing agent was 10%.

42. A method of forming a semiconductor device, wherein: It includes: A dummy gate structure is formed, wherein the steps of forming the dummy gate structure include: depositing a dummy gate dielectric layer adjacent to a semiconductor fin, depositing a dummy gate adjacent to the semiconductor fin, and depositing a spacer adjacent to the dummy gate dielectric layer; Replacing a portion of the semiconductor fin with a source / drain region, wherein the step of replacing the portion of the semiconductor fin with the source / drain region includes: etching the portion of the semiconductor fin, and epitaxially growing the source / drain region in the etched portion of the semiconductor fin; and A wet etching solution is applied to the dummy gate structure, and the step of applying the wet etching solution includes diffusing an oxidant through the dummy gate dielectric layer and through the spacer to form a protection area from a portion of the source / drain region, and the wet etching solution reacts with the source / drain region.

43. The method for forming a semiconductor device according to claim 42, wherein: The wet etching solution oxidizes the portion of the source / drain region contacting the spacer.

44. The method for forming a semiconductor device according to claim 42, wherein: The wet etching solution comprises: A solvent, an etchant, and The oxidant.

45. The method for forming a semiconductor device according to claim 44, wherein: The etchant includes a strong base and a weak base.

46. ​​The method for forming a semiconductor device according to claim 44, wherein: The oxidizing agent includes N-oxide derivatives.

47. The method for forming a semiconductor device according to claim 42, wherein: Applying the wet etching solution etches the dummy gate material and also includes forming a gate stack on the semiconductor fin.

48. The method for forming a semiconductor device according to claim 42, wherein: The concentration of the oxidant in the wet etching solution is between 5% and 20%.

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