Patterned die pad for packaged vertical semiconductor devices

Abstract

The present application relates to a patterned die pad for a packaged vertical semiconductor device and discloses a method for semiconductor device packaging for forming a packaged semiconductor device (100), the method comprising providing (i) a vertical power semiconductor device die (120) and (ii) a lead frame, the vertical power semiconductor device die (120) comprising a semiconductor substrate (105) comprising a control node, a source or emitter on the top side or the bottom side of the substrate, and a drain or collector on the other of the top side and the bottom side, and a back side metal (BSM) layer (111) on the bottom side. The lead frame includes a patterned die pad (140) including a common continuous base (140a) and a two-dimensional array (140b) of spaced-apart posts (141a, 141b, 141c, 141d) extending upward from the base, with individual solder caps (146a, 146b, 146c, 146d) on top of the posts. A BSM layer is placed on the solder caps, and a reflow process bonds the BSM layer to the solder caps.

Description

Technical Field

[0001] The present disclosure relates to packaging of vertical current power semiconductor devices. Background Art

[0002] Some packaged power semiconductor device dies utilize vertical current in operation, which passes through a semiconductor substrate (e.g., silicon) to a drain (or source) contact on the bottom side of the die, and then through a die pad, which may be exposed to electrical contact and enhance cooling below the semiconductor substrate. The current path may also be outward from an unexposed die pad to a substrate pin, such as using a bond wire from the die pad to the substrate pin. There may be other ways to direct a conductive path from the die pad to the outside of the package, such as bonding wires or fusing some leads to the die pad itself. For example, a vertical power semiconductor device die may include a metal oxide semiconductor field effect transistor (MOSFET) (which typically includes a planar gate or a trench gate), a vertical bipolar device, or an insulated gate bipolar transistor (IGBT).

[0003] In this power device arrangement, the die attach material in series in the current path of the device is important and therefore needs to be conductive. Due to material and process limitations, such conductive die attach materials (e.g., epoxy filled with solder or metal (e.g., silver), or sintered materials (e.g., silver sintered materials or copper sintered materials)) may crack or delaminate, including during reliability testing involving thermal cycling.

[0004] Thermal cycling can involve subjecting the device to alternating environments of high temperature (e.g., 150°C) and low temperature (-65°C), and can also undergo power cycling in which the device is allowed to turn on and off repeatedly. In the case of packaged power MOSFETs, damage to the conductive die attach material can cause the on-resistance (RDSon) of the device and the conductive die attach material thermal resistance to increase. This RDSon increase can result in higher power dissipation, resulting in temperatures above the allowed reliable limits, and ultimately can lead to electrical failure of the device. Summary of the invention

[0005] This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described in the following Detailed Description including the provided figures. This Summary is not intended to limit the scope of the claimed subject matter.

[0006] The disclosed patterned die pad for packaged vertical semiconductor power devices solves the problem of vertical current induced electrical performance drift of the device due to die attach (e.g., solder, filled epoxy die attach, or sintering material) damage during thermal cycling by creating a two-dimensional array of low stress joints (referred to herein as "pillars", each pillar including a solder cap). The array of pillars can be etched from a conventional continuous lead frame die pad with a conventional uniform die pad thickness, and each pillar can then be capped with solder.

[0007] For example, the pillars may be formed by a lead frame etching process, and solder may be deposited on the pillars using solder printing or plating, and a backside die attach may be formed by a reflow process. The pillars have a smaller area than conventional continuous lead frame pads with uniform pad thickness, which reduces the risk of cracking of the die attach material compared to conventional solder joints, as demonstrated by simulations performed.

[0008] The disclosed arrangement can use lead-free alloys for solder caps, such as SAC305, which contains 96.5% tin, 3% silver and 0.5% copper, and the disclosed arrangement does not require any advanced material development. An important design feature of the present invention is to produce a small enough pillar area to reduce the risk of cracking while still being manufacturable, such as pillars with diameters of 25μm to 1mm. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0010] Figure 1A is a cross-sectional view of a packaged semiconductor device including a vertical power semiconductor die, the vertical power semiconductor die including a semiconductor substrate on a patterned die pad, the patterned die pad including a common continuous base and a two-dimensional array of spaced-apart posts extending upward from the base, with individual solder caps on top of the posts.

[0011] Figure 1B is a cross-sectional view of a basic example vertical current power MOSFET device, which can be Figure 1A The vertical power semiconductor die shown in .

[0012] Figure 2 An example clip quad flat no-lead (QFN) device that may benefit from the disclosed patterned die pad is shown.

[0013] Figure 3Simulation results for a flip-chip-on-lead device are shown showing the relationship between solder damage (in arbitrary units) caused by plastic work increment and pillar diameter (in μm) as a function of die pad pillar diameter. In these simulations, the pillars are patterned on a silicon die. DETAILED DESCRIPTION

[0014] Example embodiments are described with reference to the accompanying drawings, in which the same reference numerals are used to represent similar or equivalent elements. The illustrated ordering of actions or events should not be considered limiting, as some actions or events may occur in different orders and / or simultaneously with other actions or events. In addition, some of the actions or events shown may not be required to implement methods according to the present disclosure.

[0015] Figure 1A 1 is a cross-sectional view of a packaged semiconductor device 100 including a vertical power semiconductor die 120 that includes a semiconductor substrate 105. The vertical power semiconductor die 120 includes a control node (e.g., a gate for a MOS device or a base for a bipolar device) (shown with a bonding pad (BP) 131b coupled to the control node), a source or emitter on the top side of the die (shown as BP 131a to a first current path (CP) node, and may alternatively be on the bottom side of the substrate 105), and a drain or collector on the other of the top and bottom sides (shown as a second CP node contact 132 on the bottom side). The vertical power semiconductor die 120 may include a MOS device (which typically includes a planar gate or trench gate device), a vertical bipolar device, or an IGBT.

[0016] A backside metal (BSM) layer 111 is on the bottom side of the die on a patterned die pad 140 that includes a common continuous base 140a and a two-dimensional array 140b of spaced-apart posts (shown as 141a, 141b, 141c, and 141d) extending upward from the base 140a, with a separate solder cap 146a, 146b, 146c, and 146d on top of each post. The BSM layer 111 may include silver, which is typically a good candidate for connection to solder, but other metals may be present between the silicon and the silver to create good adhesion and a stable structure. The solder caps 146a, 146b, 146c, and 146d are shown as lampshade shapes with a wider base and a narrower top with curved sidewalls. Although not shown in Figure 1A, but the solder caps 146a, 146b, 146c, and 146d may be offset (i.e., misaligned) relative to the tops of the pillars 141a, 141b. The thickness of the solder caps 146a, 146b, 146c, and 146d is typically 5 μm to 100 μm, such as 5 μm to 50 μm. Bond wires 138, 139 are shown as connecting between BP 131b and BP 131a on the top side of the vertical power semiconductor die 120 and the corresponding QFN perimeter lands (shown as 147 and 148). As shown in FIG. Figure 1A As an alternative to the bond wires and perimeter pads shown, clips may be used, as described below. Figure 2 A molding material 125 (eg, epoxy filled with filler particles) is positioned around the die 120 and the patterned die pad 140 .

[0017] Figure 1B Yes, it can be Figure 1A 1. A cross-sectional view of a basic example vertical current power MOSFET device 170 of a vertical power semiconductor die 120 in FIG. The actual structure of a real power MOSFET is typically more complex and includes various other structures, including, for example, trenches for a gate or for a field plate. The MOSFET device 170 includes an N+ source 178 formed in a p-well 177 formed in the substrate 105.

[0018] The drain of the MOSFET device 170, shown as D, is from the central area under the gate electrode 175 on the gate dielectric 176 to the bottom of the die with the BSM layer 111 thereon. The channel 171 is shown to be horizontal under the gate electrode 175 on the gate dielectric 176, but is shorter than a conventional MOSFET, and the current flow is shown to be vertical between the channel 171 and the drain contact at the BSM layer 111. The provision of a short channel 171 means low on-resistance, which is a characteristic of a power device.

[0019] Solder caps 146a, 146b, 146c and 146d can be formed using solder paste, solder paste can be printed using a stencil, or solder paste can be plated on the column and reflowed. For tin-silver-copper (SnAgCu, 'SAC') alloys, the reflow process of joining the BSM layer 111 to the solder cap can use, for example, a peak temperature of about 260°C. The solder cap can be connected to the BSM layer 111 and the lead frame during reflow, but the plated solder can undergo other flow processes. Solder generally forms a metal-to-metal connection with the BSM layer 111 and the column. The process can be performed in various ways. For example, solder is plated on the column, solder is printed on the column, solder is printed on the BSM layer (using a flip-chip die), and solder is plated on the BSM layer. In all cases, the last step does include a reflow process (melting temperature of the solder) to create a connection with another surface.

[0020] The disclosed semiconductor device packaging method generally uses a copper (Cu) panel substrate, which forms the raw material of the lead frame strip. The panel substrate is subjected to a selective wet etching process in order to perform the above process when manufacturing several units at the same time.

[0021] The raw material of the lead frame strip is typically coated with a photoimageable solder mask layer (e.g., a photoimageable epoxy) by spin coating the solder mask. The photoimageable etch-resistant mask layer is then imaged using a photolithography tool. This is typically accomplished by exposing the photoimageable mask to ultraviolet light masked by an optical tool and then developing the solder mask. The photoimageable mask is thereby patterned to provide pits in which the upper and lower surfaces of the lead frame strip are exposed. Thus, the lead frame strip is selectively masked by the photoimageable mask.

[0022] The lead frame strip is then etched by, for example, immersion or pressurized jet etching, and the photoimageable mask is stripped to provide the disclosed patterned lead frame. The process can be a standard etching lead frame process (half etching) for QFN lead frames. The resulting lead frame strip includes a plurality of units, each of which includes a patterned die attach pad that is generally centrally positioned. The die attach pad includes a continuous portion on one side of the die attach pad and a plurality of posts extending from the continuous portion to the opposite side of the die attach pad. Each unit also includes a plurality of contact pads (or leads) surrounding the die attach pad. As an example, bonding wires will be used to connect to these leads from the top of the die.

[0023] Figure 2 An example clip QFN power converter device 200 that can benefit from the disclosed patterned die pad is shown. A control MOS field effect transistor (FET) 210 is stacked on a synchronous (sync) MOSFET 220. The control FET chip 210 can have a smaller area relative to the synchronous FET chip 220. The QFN metal lead frame has a generally rectangular disclosed patterned die pad 201, which is intended to be a heat sink for the clip QFN power converter device 200. Leads 202a and 202b are positioned in a straight line along two opposite sides of the patterned die pad 201. The die pad 201 can be a patterned die pad as disclosed herein. The other pad side can remain free of leads. The stacking of FET chips is achieved by a so-called source-down configuration.

[0024] The source of the sync FET 220 is soldered to the patterned die pad 201 via a solder layer 221. The first clip 240 is soldered to the drain of the sync FET 220 via a solder layer 222, which has the source of the control FET 210 attached via the solder layer 221. Thus, the first clip 240 serves as a switch node terminal for the power converter. The second clip 260 is connected to the drain of the control FET 210 via a solder layer 212. The first clip 240 and the second clip 260 may be patterned clips as disclosed herein. The second clip 260 is attached to the lead 202b of the lead frame and is thus connected to the V IN The power converter device 200 can be effectively operated at a frequency of 500kHz to about 5MHz.

[0025] Advantages of the disclosed patterned die pad include enabling a simple lead-free die attach solution without using any new processes. The die pad etch for forming the pillars can be part of a standard lead frame half-etch process. Standard printing and reflow processes can be used to attach the silicon die to the BSM layer 111. Although a potential disadvantage of the disclosed patterned die pad having a reduced connection area to the BSM layer 111 of the die is a higher series resistance compared to a uniform (unpatterned) die pad using a silver-filled epoxy die attach material, the solder cap has a 25°C resistivity of approximately 15 μ-ohm-cm compared to silver-filled epoxy, which has a 25°C resistivity of typically greater than 50 μ-ohm-cm. In addition, the solder cap thickness as described above can be in the range of 5 μm to 25 μm, compared to epoxy, which typically requires at least about 50 μm. Therefore, no significant resistance increase is expected when implementing the disclosed patterned die pad.

[0026] Example

[0027] The disclosed embodiments of the present invention are further illustrated by the following specific examples, which should not be construed as limiting the scope or content of the present disclosure in any way.

[0028] Figure 3 Simulation results on a flip chip leaded device are shown showing the relationship between solder damage caused by plastic work increment (in MPa) and post diameter (in μm) as a function of die pad copper post size and shape. The lower the plastic work increment, the better. The stress reduction is believed to be achieved due to the reduced die pad contact area with the BSM layer 111 of the die caused by the posts spanning the reduced area compared to a conventional unpatterned die pad. This results in less impact of coefficient of thermal expansion (CTE) mismatch (e.g., between the silicon die and the copper die pad).

[0029] Those skilled in the art to which the present disclosure relates will appreciate that many other embodiments and variations of the embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the present disclosure. For example, the disclosed aspects may also be applied to a simple switch that turns on and conducts DC current.

Claims

1. A method for packaging a vertical power semiconductor device, comprising: Providing (i) a vertical power semiconductor device die and (ii) a lead frame, wherein the vertical power semiconductor device die includes a semiconductor substrate including a control node, a source or emitter on a top side or a bottom side of the substrate, and a drain or collector on the other of the top side and the bottom side, a backside metal layer (BSM layer) on the bottom side, and the lead frame includes a patterned die pad, wherein the patterned die pad includes a common continuous base and a two-dimensional array of spaced-apart pillars extending upward from the base, and having individual solder caps on top of the pillars; placing the BSM layer on the weld cap; as well as A reflow process is performed to bond the BSM layer to the solder cap. 2 . The method for packaging a vertical power semiconductor device according to claim 1 , wherein the solder cap has a thickness of 5 μm to 50 μm. 3 . The method of packaging a vertical power semiconductor device of claim 1 , wherein the top of the pillar is narrower than the bottom of the pillar. 4 . The method of packaging a vertical power semiconductor device according to claim 3 , wherein the sidewalls of the pillars are curved. 5 . The method of packaging a vertical power semiconductor device according to claim 1 , wherein the vertical power semiconductor device die comprises a metal oxide semiconductor field effect transistor (MOSFET). 6 . The method of packaging a vertical power semiconductor device according to claim 1 , wherein the solder cap comprises a lead-free solder composition. 7 . The method of packaging a vertical power semiconductor device of claim 1 , further comprising etching an unpatterned die pad to form the patterned die pad and solder printing the solder cap on the post. 8 . The method of packaging a vertical power semiconductor device according to claim 7 , wherein the etching comprises a half-etching process.

9. The method of packaging a vertical power semiconductor device of claim 1, wherein the lead frame comprises a plurality of lead fingers or perimeter pads, the method further comprising placing bonding wires between bonding pads connected to nodes on a die of the vertical power semiconductor device and the plurality of lead fingers or perimeter pads.

10. The method of packaging a vertical power semiconductor device of claim 1, wherein the semiconductor substrate comprises silicon and the die pad comprises copper.

11. A method for packaging a vertical power semiconductor device, comprising: Providing (i) a vertical power semiconductor device die and (ii) a lead frame, wherein the vertical power semiconductor device die includes a semiconductor substrate including a control node, a source or emitter on a top side or a bottom side of the substrate, and a drain or collector on the other of the top side and the bottom side, a backside metal layer (BSM layer) on the bottom side, and the lead frame includes a patterned die pad, wherein the patterned die pad includes a common continuous base and a two-dimensional array of spaced-apart pillars extending upward from the base, and having a separate solder cap on the top of the pillar, wherein the total area at the top of the pillar excluding the solder cap is 10% to 70% of the area of ​​the base; placing the BSM layer on the weld cap; as well as A reflow process is performed to bond the BSM layer to the solder cap.

12. A packaged vertical power semiconductor device, comprising: A vertical power semiconductor die comprising a semiconductor substrate including a control node, a source or emitter on a top side or a bottom side of said substrate, and a drain or collector on the other of said top side and said bottom side, and a backside metal layer, i.e., a BSM layer, on said bottom side; A lead frame comprising a patterned die pad including a common continuous base and a two-dimensional array of spaced-apart posts extending upwardly from the base with individual solder caps on top of the posts, Wherein the BSM layer is bonded to the weld cap.

13. The packaged vertical power semiconductor device of claim 12, wherein the solder cap comprises a lead-free composition. 14 . The packaged vertical power semiconductor device of claim 12 , wherein the solder cap has a thickness of 5 μm to 50 μm.

15. The packaged vertical power semiconductor device of claim 12, wherein the top of the pillar is narrower than the bottom of the pillar.

16. The packaged vertical power semiconductor device of claim 12, wherein sidewalls of the pillars are curved.

17. The packaged vertical power semiconductor device of claim 12, wherein the semiconductor substrate comprises silicon and the die pad comprises copper.

18. A quad flat no-lead package (QFN package) including a vertical power semiconductor die, comprising: The vertical power semiconductor die comprises a semiconductor substrate including a control node, a source or emitter on a top side or a bottom side of the substrate, and a drain or collector on the other of the top side and the bottom side, and a backside metal layer, i.e., a BSM layer, on the bottom side; a lead frame comprising a patterned die pad including a common continuous base and a two-dimensional array of spaced-apart posts extending upwardly from the base with individual solder caps on top of the posts, wherein the BSM layer is bonded to the solder caps; Bond wires are coupled between bond pads on the top side of the vertical power semiconductor die and perimeter pads of the QFN package.

19. A clipped quad flat no-lead device, i.e., a clipped QFN device, comprising: The vertical power semiconductor die comprises a semiconductor substrate including a control node, a source or emitter on a top side or a bottom side of the substrate, and a drain or collector on the other of the top side and the bottom side, and a backside metal layer, i.e., a BSM layer, on the bottom side; A lead frame includes a patterned die pad including a common continuous base and a two-dimensional array of spaced-apart posts extending upwardly from the base with separate solder caps on top of the posts, wherein the BSM layer is bonded to the solder caps.

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