Semiconductor memory device and method of operating the same

Abstract

The present disclosure provides a semiconductor memory device and a method for operating the semiconductor memory device. The semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word lines and bit lines, each of the plurality of memory blocks is divided into a plurality of row blocks by row block equal bits of row addresses, and each of the row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes the physical row address of the memory cell storing or outputting data based on the column address received by a write command or a read command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0053515 filed on May 10, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to memory devices, and more particularly, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Art

[0004] Semiconductor chips are manufactured through semiconductor manufacturing processes and then tested by test equipment in a wafer, chip or packaged state. The defective portion of the defective chip is identified through testing, and if some memory cells are defective, repairs are performed to save the semiconductor chip. Currently, the size of semiconductor chips such as dynamic random access memory (DRAM) has been continuously reduced through fine processing, and therefore, the possibility of errors in the manufacturing process has also increased. In addition, if defects are not detected during the initial testing process, errors may occur during the operation of the chip. Summary of the invention

[0005] Example embodiments may provide a semiconductor memory device capable of increasing flexibility of a column repair operation.

[0006] Example embodiments may provide a method of operating a semiconductor memory device capable of increasing flexibility of a column repair operation.

[0007] According to an exemplary embodiment, the present disclosure relates to a semiconductor memory device, including: a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word lines and bit lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by at least one row block equal bit corresponding to a portion of bits of a row address, and each of the plurality of row blocks includes a plurality of sub-array blocks arranged in a first direction; a row decoder configured to: activate a first word line in a first row block among the plurality of row blocks in response to a row address; and activate the first word line in a first row block when the first row block includes at least one defective cell. a second word line in a second row block among the plurality of row blocks, the second row block being different from the first row block; and outputting a row block information signal indicating whether the second word line is activated, wherein the first row block is associated with a first segment among the plurality of segments, the second row block is associated with a second segment among the plurality of segments, the second segment being different from the first segment, and the plurality of memory blocks are divided into the plurality of segments in a second direction intersecting the first direction; and a column decoder configured to repair a first bit line coupled to the at least one defective cell using one of a first spare bit line in the first segment and a second spare bit line in the second segment in response to a column address and the row block information signal.

[0008] According to an exemplary embodiment, the present disclosure relates to a semiconductor memory device, including: a memory cell array, which includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word lines and bit lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by row block equal bits corresponding to a portion of bits of a row address, and each of the plurality of row blocks includes a plurality of sub-array blocks arranged in a first direction; and an address decoder, which is configured to change a physical row address of a memory cell storing or outputting data based on a column address received through a write command or a read command.

[0009] According to an exemplary embodiment, the present disclosure relates to a method for operating a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array, which includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word lines and bit lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by row block equal bits corresponding to a portion of bits of a row address, and each of the plurality of row blocks includes a plurality of sub-array blocks arranged in a first direction, the method including: activating a first word line in a first row block among the plurality of row blocks by a row decoder in response to a row address; activating a second word line in a second row block among the plurality of row blocks that is different from the first row block when the first row block includes at least one defective cell; and repairing a first bit line coupled to the at least one defective cell by using one of a first spare bit line in a first segment among a plurality of segments and a second spare bit line in a second segment among the plurality of segments by a column decoder in response to a column address and a row block information signal, wherein the row block information signal indicates that the first row block includes the at least one defective cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0012] Figure 2 A semiconductor memory device performing a column repair operation according to example embodiments is illustrated.

[0013] Figure 3 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a semiconductor memory device in FIG.

[0014] Figure 4 Shows Figure 3 An example of a first memory block in an example semiconductor memory device.

[0015] Figure 5 Shows Figure 3 1 and 2. The relationship between column selection lines and bit lines is shown in an example semiconductor memory device.

[0016] Figure 6 Shows Figure 3 A memory cell array, a row decoder, and a column decoder in an example semiconductor memory device.

[0017] Fig. 7A is a diagram showing a method according to an example embodiment Figure 6 0026] Block diagram of a first row of fuse circuits in a row block of fuse circuits.

[0018] Figure 7B Shows Fig. 7A An example of a row block information storage table in the first row block fuse circuit.

[0019] Figure 8 Shows Fig. 7A Example of a row address in .

[0020] Fig. 9 is a diagram showing a method according to an example embodiment Figure 6 Block diagram of a first repair circuit in the repair circuit.

[0021] Fig.10 is a diagram showing a method according to an example embodiment Figure 6 Block diagram of a first sub-column decoder of a sub-column decoder in FIG.

[0022] Fig.11 Shows Figure 6 An example of transferring a first enable signal and a second enable signal in a semiconductor memory device.

[0023] Fig.12 According to an exemplary embodiment, Figure 6 a portion of a memory cell array;

[0024] Fig.13 is a diagram showing a method according to an exemplary embodiment Fig.12 Circuit diagram of the bit line sense amplifier in FIG.

[0025] Fig.14 Shows Fig.12 Local sense amplifier circuit in

[0026] Fig.15 Shows Fig.12 Another example of a bit line sense amplifier region in FIG.

[0027] Fig.16 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of another example of a semiconductor memory device in FIG.

[0028] Fig.17 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0029] Fig.18A and Fig.18B A method of operating a semiconductor memory device according to example embodiments is illustrated.

[0030] Fig. 18C Shows Fig.18A and Fig.18B Access to the memory cells in.

[0031] Fig.19 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0032] Fig. 20 According to an exemplary embodiment, Fig.19 A cross-sectional view of a 3D chip structure of a semiconductor memory device. DETAILED DESCRIPTION

[0033] Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown.

[0034] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0035] Reference Figure 1 , the memory system 20 may include a memory controller 100 and a semiconductor memory device 200 .

[0036] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 may write data into the semiconductor memory device 200 in response to a request from the external host, or read data from the semiconductor memory device 200. In addition, the memory controller 100 may issue an operation command to the semiconductor memory device 200 to control the semiconductor memory device 200.

[0037] In some embodiments, the semiconductor memory device 200 is a memory device including a dynamic memory cell, such as a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or a LPDDR5 SDRAM.

[0038] The memory controller 100 transmits a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device 200 , and exchanges data DQ with the semiconductor memory device 200 .

[0039] The semiconductor memory device 200 includes a memory cell array (MCA) 300 and an address decoder ADEC that stores data DQ received from the memory controller 100. The address decoder ADEC may include a row decoder (RD) 261 and a column decoder (CD) 271.

[0040] The memory cell array 300 may include a plurality of memory blocks, and each of the memory blocks may be divided into a plurality of row blocks by row block equalization bits corresponding to a portion of bits of a row address included in the address ADDR. The row decoder 261 may activate a first word line in a first row block in response to the row address, may activate a second word line in a second row block different from the first row block when the first row block includes at least one defective cell, and may provide a row block information signal indicating that the second word line is activated to the column decoder 271. In an example embodiment, the first row block and the second row block may be in the same memory block.

[0041] The first row block may be associated with a first segment among the multiple segments, the second row block may be associated with a second segment among the multiple segments, the second segment is different from the first segment, and the multiple memory blocks may be divided into the multiple segments in a second direction intersecting the first direction.

[0042] The column decoder 271 can repair the first bit line coupled to the at least one defective cell using one of the first spare bit line in the first section and the second spare bit line in the second section in response to the column address and the row block information signal in the address ADDR. For example, the address decoder ADEC can change the physical row address of the memory cell storing or outputting data based on the column address. In this embodiment, the semiconductor memory device 200 can increase the flexibility of the column repair operation.

[0043] Figure 2 A semiconductor memory device performing a column repair operation according to example embodiments is illustrated.

[0044] Figure 2 shows the address decoder ADEC pair included in Figure 1 A column repair operation is performed on the memory blocks MB in the memory cell array 300 in FIG.

[0045] Reference Figure 2 , the memory block MB is divided into a plurality of segments SEG1 to SEG8. When the word line WLi in the segment SEG4 is coupled to a defective cell, the defective cell in the segment SEG4 is repaired using a spare cell coupled to the word line WLj in the segment SEG5, rather than repairing the defective cell in the segment SEG4 using a spare cell coupled to the word line WLi in the segment SEG4. When the spare cell in the segment SEG4 cannot repair the defective cell in the segment SEG4, a repair operation may be performed by borrowing a spare cell in another segment. In the described embodiment, the semiconductor memory device 200 may increase the flexibility and yield of column repair operations.

[0046] exist Figure 2In the embodiment, the memory cell coupled to the bit line can be selected by the column selection line CSL, and the spare normal cell coupled to the spare bit line can be selected by the spare column selection line SCSL. Figure 2 In the example of , a defective memory cell in segment SEG4 coupled to word line WLi and selected by column selection line CSL is repaired (REP) by a spare normal memory cell in segment SEG5 coupled to word line WLj and selected by spare column selection line SCSL.

[0047] Figure 3 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a semiconductor memory device in FIG.

[0048] Reference Figure 3 , the semiconductor memory device 200 a includes a memory cell array 300 a , a row decoder 261 , a column decoder 271 , and a peripheral circuit 201 .

[0049] The memory cell array 300a may include a plurality of memory blocks MB1 to MBk (where k is an integer greater than 1), and each of the memory blocks MB1 to MBk includes a memory cell coupled to a word line WL and a bit line BL and a spare memory cell coupled to the word line WL and at least one spare bit line SBL. The memory blocks MB1 to MBk share the word line WL but do not share the bit line BL and the spare bit line SBL. For example, each of the word lines WL may be connected to all memory blocks MB1 to MBk, while the bit line BL and the spare bit line SBL may be connected only to one corresponding memory block MB of the memory blocks MB1 to MBk. The data associated with each of the memory blocks MB1 to MBk may be input / output through the corresponding input / output pads (not shown) of the memory cell array 300a.

[0050] The semiconductor memory device 200a may receive an activation command before receiving a write command or a read command from an external device (e.g., a memory controller or a test device). All memory cells connected to the word line WL of the semiconductor memory device 200a identified by the activation command may be selected based on the activation command. Next, if the semiconductor memory device 200a receives a write command or a read command, a plurality of bit lines BL may be selected. In an embodiment, one or more bit lines BL shown in the memory blocks MB1 to MBk may be selected by a write command or a read command. Data input / output may be performed on the memory cells coupled to the selected bit lines BL.

[0051] Parity data for error correction of data stored in at least one of the memory blocks MB1 to MBk may be stored in some of the memory blocks MB1 to MBk.

[0052] The column decoder 271 may be connected to the memory cell array 300a through a column select line CSL and a spare column select line SCSL. The column decoder 271 may select the column select line CSL or the spare column select line SCSL based on a write command or a read command. If the column decoder 271 selects the column select line CSL, the corresponding bit line BL is selected. When the column decoder 271 selects the spare column select line SCSL, the corresponding spare bit line SBL is selected.

[0053] The peripheral circuit 201 may include a command / address pad (CMD / ADDR) 203, an input / output data (DQ) pad 205, and an error correction code (ECC) engine 280. In some embodiments, the ECC engine 280 may not be included in the peripheral circuit 201. The peripheral circuit 201 may receive a command CMD and an address ADDR from an external device (e.g., the memory controller 100), and may exchange data DQ with the external device (e.g., the memory controller 100).

[0054] The peripheral circuit 201 may provide a column address CADDR to the column decoder 271 according to a command CMD received from an external device (e.g., the memory controller 100), and may provide a row address RADDR to the row decoder 261. The peripheral circuit 201 may provide input data DQ to the column decoder 271 in response to a write command, or may receive output data DQ from the column decoder 271 in response to a read command. The input data may be input to the peripheral circuit 201 through the input / output data (DQ) pad 205. The output data may be output to the memory controller 100 through the input / output data (DQ) pad 205.

[0055] The ECC engine 280 may perform ECC encoding on the input data to generate parity data. The ECC engine 280 may store the input data and the parity data in the memory blocks MB1 to MBk. The ECC engine 280 may perform ECC decoding on the data read from the memory blocks MB1 to MBk to correct at least one error in the read data. The ECC engine 280 may send the corrected data to the memory controller 100 through the input / output data (DQ) pad 205.

[0056] The row decoder 261 may activate a first word line WL in a first row block indicated by the row address RADDR in response to the row address RADDR, may activate a second word line WL in a second row block different from the first row block when the first row block includes at least one defective cell, and may output a row block information signal RBIN indicating that the second word line WL is activated. The row decoder 261 may include a row block information circuit 400, and the row block information circuit 400 may store row block information of each row block of the memory blocks MB1 to MBk, and may output the row block information signal RBIN to the column decoder 271 based on the activation of the second word line WL.

[0057] Figure 4 Shows Figure 3 An example of a first memory block in a semiconductor memory device.

[0058] Reference Figure 4 , the first memory block MB1 includes a normal cell area NCR and a spare cell area SCR. The normal cell area NCR includes a plurality of word lines WL1 to WLm (m is a natural number greater than two), a plurality of bit lines BL1 to BLn (n is a natural number greater than two), and a plurality of memory cells MC arranged at the intersections between the word lines WL1 to WLm and the bit lines BL1 to BLn. The spare cell area SCR includes a plurality of spare bit lines SBL1 to SBLy (y is a natural number greater than two), word lines WL1 to WLm, and a plurality of spare memory cells SMC arranged at the intersections between the word lines WL1 to WLm and the spare bit lines SBL1 to SBLy.

[0059] The word lines WL1 to WLm extend transversely in a first direction D1, and the bit lines BL1 to BLn and the spare bit lines SBL1 to SBLy may extend longitudinally in a second direction D2 intersecting the first direction D1. The first memory block MB1 may be divided into a plurality of sections by the section-equal bit of the row address in the second direction D2. For example, the word lines WL1 to WLm of the first memory block MB1 may constitute sections identified by the section-equal bit of the row address.

[0060] In an exemplary embodiment, the other memory blocks MB of the memory blocks MB2 to MBk may include only the normal cell region NCR and may not include the spare cell region SCR.

[0061] Figure 5 Shows Figure 3 The relationship between the column selection line CSL and the bit line BL is shown.

[0062] exist Figure 5 In the embodiment, for ease of illustration, only the first memory block MB1 is shown in detail. Each of the memory blocks MB2 to MBk may be constructed and / or implemented in the same manner as the first memory block MB1. Figure 5 Only one word line WL is shown, and Figure 3 The peripheral circuit 201 and the row decoder 261 in.

[0063] The column decoder 271 may select a column selection line CSL of each of the memory blocks MB1 to MBk based on a write command or a read command. Each of the column selection lines CSL may be connected to a plurality of bit lines BL through a switch SW1. The column decoder 271 may selectively select a spare column selection line SCSL of each of the memory blocks MB1 to MBk based on a write command or a read command instead of the column selection line CSL. The spare column selection line SCSL may be connected to a spare bit line SBL through a switch SW2.

[0064] Figure 6 Shows Figure 3 A memory cell array, a row decoder and a column decoder in a semiconductor memory device.

[0065] Reference Figure 6 , in the memory cell array 300a, I sub-array blocks SCB may be arranged in columns 1 to I in a first direction D1, and J sub-array blocks SCB may be arranged in rows 1 to J in a second direction D2, the second direction being substantially perpendicular to the first direction D1. For example, the memory cell array 300a may include sub-array blocks SCB 1,1 To SCB I,J The sub-array blocks SCB arranged in the first direction D1 in any of rows 1 to J may be referred to as row blocks. For example, the sub-array block SCB in row 1 may be the 1st row block, the sub-array block SCB in row 2 may be the 2nd row block, the sub-array block SCB in row 3 may be the 3rd row block, and so on. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells may be arranged in each of the sub-array blocks SCB.

[0066] exist Figure 6 In the embodiment, one sub-array block SCB in the second direction D2 may correspond to a memory segment, and all sub-array blocks SCB in the first direction D1 may correspond to row blocks.

[0067] Although not shown, the memory cell array 300a may be divided into a plurality of memory blocks in a first direction D1, each of the memory blocks in the first direction D1 includes one or more sub-array blocks, and each of the memory blocks may be divided into a plurality of sections in a second direction D2, each of the memory blocks in the second direction D2 may be composed of one or more sub-array blocks. In some embodiments, each of the plurality of sections may include at least one sub-array block SCB.

[0068] I+1 sub-word line driver areas SWB may be arranged between sub-array blocks SCB in a first direction D1. Each sub-array block SCB in the first direction D1 may correspond to a segment of each of the memory blocks. The sub-word line drivers may be arranged in the sub-word line driver areas SWB. J+1 bit line sense amplifier areas BLSAB may be arranged between the sub-array blocks SCB in, for example, a second direction D2. A bit line sense amplifier for sensing data stored in a memory cell may be arranged in the bit line sense amplifier area BLSAB.

[0069] A plurality of junction regions CONJ may be arranged adjacent to the sub word line driver region SWB and the bit line sense amplifier region BLSAB. In some embodiments, the plurality of junction regions CONJ may be adjacent to the sub word line driver region SWB and the bit line sense amplifier region BLSAB of the first row of the memory cell array 300a. A voltage generator is arranged in each of the junction regions CONJ.

[0070] The row decoder 261 includes a row block information circuit 400, which may include a plurality of row block fuse circuits (RBFC) 40_1 to 40_J corresponding to row blocks in the second direction D2. The row block fuse circuits (RBFC) 40_1 to 40_J may output a row block information signal RBIN to the column decoder 271 in response to a row block identity bit of the row address RADDR.

[0071] The column decoder 271 may include a plurality of sub-column decoders (SCD) 55_1 to 55_I and a plurality of repair circuits 50_1 to 50_I. Each of the sub-column decoders 55_1 to 55_I may be connected to a corresponding one of the memory sub-array blocks SCB, and each of the plurality of repair circuits 50_1 to 50_I may correspond to one of the plurality of sub-column decoders 55_1 to 55_I. Each of the repair circuits 50_1 to 50_I may selectively activate the first repair signal CREN1 and the second repair signal CREN2 in response to the column address CADDR and the row block information signal RBIN to provide the first repair signal CREN1 and the second repair signal CREN2 to a corresponding one of the sub-column decoders 55_1 to 55_I. In response to the first repair signal CREN1 and the second repair signal CREN2, each of the sub-column decoders 55_1 to 55_I may select a column selection line CSL or a spare column selection line SCSL, and may individually activate the second enable signals OENY_1 to OENY_I. When the first and second repair signals CREN1 and CREN2 are deactivated by the repair circuits 50_1 to 50_I, each of the sub-column decoders 55_1 to 55_I may select the column selection line CSL without activating the second enable signals OENY_1 to OENY_I.

[0072] When the first repair signal CREN1 is activated, the second repair signal CREN2 is deactivated, and each of the second enable signals OENY_1 to OENY_I is deactivated, each of the sub-column decoders 55_1 to 55_I may select a spare column selection line SCSL to input / output data through a spare bit line SBL coupled to the spare column selection line SCSL, the spare column selection line SCSL being located in the same segment as the segment including the memory cell indicated by the row address RADDR. When the first repair signal CREN1 is deactivated, the second repair signal CREN2 is activated, and each of the second enable signals OENY_1 to OENY_I is activated, each of the sub-column decoders 55_1 to 55_I may select a spare column selection line SCSL to input / output data through a spare bit line SBL coupled to the spare column selection line SCSL, the spare column selection line SCSL being located in a segment different from the segment including the memory cell indicated by the row address RADDR.

[0073] Fig. 7A is a diagram showing a method according to an example embodiment Figure 6 4 is a block diagram of a first row fuse circuit 40_1 of a row block fuse circuit in FIG.

[0074] Each of the row block fuse circuits 40_2 to 40_J may have substantially the same configuration as that of the first row block fuse circuit 40_1 .

[0075] Reference Fig. 7A , the first row block fuse circuit 40_1 may include a pre-decoder 405 , a row block information storage table 410 , a row block address comparator 425 , and a signal generator 430 .

[0076] The predecoder 405 decodes the row address RADDR to provide the decoded row address DRA to the corresponding sub word line driver arranged in the sub word line driver area SWB. In response to the decoded row address DRA provided by the predecoder 405, the corresponding sub word line driver may activate the word line corresponding to the decoded row address DRA.

[0077] The row block information storage table 410 may store a defective row block address FBRB associated with a defective row block (the defective row block includes at least one defective cell), row block address information of the corresponding row block, replacement row block information RRBI for determining whether to activate the second word line, and a master fuse bit MF indicating whether the corresponding row block can be used as a replacement row block.

[0078] The row block information storage table 410 may provide the defective row block address FBRB to the row block address comparator 425, and the row block comparator 425 may compare the row block equality bit BRB received from the pre-decoder 405 with the defective row block address FBRB to provide the row block information table 410 and the signal generator 430 with a row block match signal RBMTH indicating a comparison result of the row block equality bit BRB with the defective row block address FBRB. The row block equality bit BRB may include some upper bits of the row address RADDR. For example, as combined with Figure 8 As discussed above, when the row address RADDR includes m bits, the upper r bits of the row address RADDR may correspond to the row block equality bits BRB.

[0079] The row block information storage table 410 may provide the signal generator 430 with replacement row block information RRBI and the master fuse bits MF of the row block including the second word line in response to the row block match signal RBMTH.

[0080] The signal generator 430 may output a row block information signal RBIN_1 and a first enable signal OENX_1 in response to the row block match signal RBMTH and the replacement row block information RRBI. The row block information signal RBIN_1 may indicate that the second word line in the second row block is activated and that the corresponding first row block includes a defective cell. The first enable signal OENX_1 may determine the activation of a local sense amplifier circuit associated with the second section including the second row block. The signal generator 430 may provide the row block information signal RBIN_1 to the column decoder 271, and may provide the first enable signal OENX_1 to the corresponding bit line sense amplifier region.

[0081] Figure 7B Shows Fig. 7A An example of a row block information storage table 410 in a first row block fuse circuit.

[0082] Reference Figure 7B The row block information storage table 410 includes an anti-fuse array 411 , a control unit 412 , a sensing unit 413 , and a register unit 414 .

[0083] The antifuse array 411 includes p*q antifuses (AF) connected to the intersections of p rows and q columns, respectively. The antifuse array 411 includes p word lines AWL1 to AWLp for accessing the antifuses (AF) arranged in p rows, and q bit lines ABL1 to ABLq arranged to correspond to q columns to deliver information read from the antifuses (AF).

[0084] The control unit 412 programs the defective row block address FBRB, the replacement row block information RRBI, and the main fuse bit MF in the antifuse array 411, or the control unit 412 reads the defective row block address FBRB, the replacement row block information RRBI, and the main fuse bit MF from the antifuse array 411. The sensing unit 413 can sense and amplify the defective row block address FBRB, the replacement row block information RRBI, and the main fuse bit MF received from the antifuse array 411, and output the amplified result. The register unit 414 can temporarily store the defective row block address FBRB, the replacement row block information RRBI, and the main fuse bit MF received from the sensing unit 413. The register unit 414 outputs the defective row block address FBRB to the row block address comparator 425, and outputs the replacement row block information RRBI and / or the main fuse bit MF to the signal generator 430.

[0085] Figure 8 Shows Fig. 7A Example of a row address in .

[0086] exist Figure 8 In the example, it is assumed that the row address RADDR includes 16 bits A0 to A15.

[0087] Reference Figure 8 , upper 3 bits A15 to A13 of the row address RADDR may be indicated as a row block equality bit BRB. In this case, the row block equality bit BRB includes 3 bits, and the memory blocks MB1 to MBk may be divided into eight row blocks arranged in the first direction D1.

[0088] Fig. 9 is a diagram showing a method according to an example embodiment Figure 6 0014 is a block diagram of a first repair circuit 50_1 of the repair circuit in FIG.

[0089] Each of the repair circuits 50_2 to 50_J may have substantially the same configuration as that of the first repair circuit 50_1 .

[0090] Reference Fig. 9 , the first repair circuit 50_1 includes a fail address storage table 510 , a column address comparator 515 , a fuse circuit 520 , a signal generator 530 and a repair signal generator 540 .

[0091] The fail address storage table 510 may store the fail column address information FCAI associated with the column address information of the defective cells of the corresponding memory block, and may send the fail column address information FCAI to the column address comparator 515. The column address comparator 515 may compare the column address CADDR with the fail column address information FCAI received from the fail address storage table 510 to output a column match signal CMTH to the fuse circuit 520 and the repair signal generator 540. The column match signal CMTH may indicate whether the column address CADDR matches the fail column address information FCAI. The fail address storage table 510 may be compared with the fail column address information FCAI received from the fail address storage table 510. Figure 7B The row block information storage table 410 has a similar structure.

[0092] The fuse circuit 520 includes a plurality of fuse groups 521, 522, and 523. The fuse groups 521, 522, and 523 may correspond to the sections constituting the corresponding memory blocks. Each of the plurality of fuse groups 521, 522, and 523 may include a first region 521a and a second region 521b. The first region 521a may store spare bit line information SBI of spare bit lines to repair defective cells in each of the sections in the corresponding memory block, and the second region 521b may store a master fuse bit MFB associated with the availability of spare bit lines of the corresponding sections (i.e., the availability of spare bit lines in different sections). In response to the column matching signal CMTH, the fuse circuit 520 may provide the spare bit line information SBI and the master fuse bit MFB to the signal generator 530, and may provide the master fuse bit MFB to the repair signal generator 540.

[0093] The signal generator 530 may generate the internal enable signal IOENY_1 associated with activation of the second word line based on the row block information RBIN, the spare bit line information SBI, and the master fuse bit MFB. The signal generator 530 may generate the local enable signal LEN based on the row block information RBIN, the spare bit line information SBI, and the master fuse bit MFB.

[0094] The repair signal generator 540 may selectively activate each of the first repair signal CREN1 and the second repair signal CREN2 based on the column match signal CMTH and the master fuse bit MFB. For example, when the column match signal CMTH indicates that the column address CADDR does not match the failure column address information FCAI, the repair signal generator 540 deactivates both the first repair signal CREN1 and the second repair signal CREN2 by applying a low-level voltage signal. When both the first repair signal CREN1 and the second repair signal CREN2 are deactivated, Figure 6 The first sub-column decoder 55_1 in the embodiment may activate the column selection line CSL.

[0095] For example, when the column match signal CMTH indicates that the column address CADDR matches the failure column address information FCAI, and the master fuse bit MFB has a low level indicating that the spare bit line in the corresponding segment is available, the repair signal generator 540 activates the first repair signal CREN1 by applying a high level voltage signal and deactivates the second repair signal CREN2 by applying a low level voltage signal. In this case, Figure 6 The first sub-column decoder 55_1 in selects the spare column selection line SCSL, and the selected spare column selection line SCSL in turn selects the spare bit lines in the first section.

[0096] For example, when the column match signal CMTH indicates that the column address CADDR matches the failure column address information FCAI, and the master fuse bit MFB has a high level voltage indicating that the spare bit line in the corresponding segment is unavailable, the repair signal generator 540 deactivates the first repair signal CREN1 by applying a low level voltage signal and activates the second repair signal CREN2 by applying a high level voltage signal, and the signal generator 530 activates the internal enable signal IOENY_1. In this case, Figure 6 The first sub-column decoder 55_1 in the second section selects the spare column selection line SCSL, and the spare bit line in the second section can be selected through the spare column selection line SCSL and the internal enable signal IOENY_1.

[0097] Fig.10 is a diagram showing a method according to an example embodiment Figure 6 1 is a block diagram of a first sub-column decoder 55_1 of a sub-column decoder in FIG.

[0098] Each of the sub-column decoders 55_2 to 55_J may have substantially the same construction as that of the first sub-column decoder 55_1 .

[0099] Reference Fig.10 , the first sub-column decoder 55_1 may include a column selection line (CSL) driver 560 and a spare column selection line (SCSL) driver 565 .

[0100] The column selection line driver 560 may select one of the column selection lines CSL in response to the column address CADDR and the column match signal CMTH. When the column match signal CMTH is at a high level CMTH, the column selection line driver 560 does not select the column selection line CSL. In this way, the column selection line driver 560 may first receive the column match signal CMTH before selecting any column selection line CSL.

[0101] The spare column selection line driver 565 may select the spare column selection line SCSL in response to the column matching signal CMTH, the first repair signal CREN1, the second repair signal CREN2 and the internal enable signal IOENY_1, and may selectively activate the second enable signal OENY_1 indicating whether a spare bit line in a corresponding segment is available.

[0102] Fig.11 The first enable signals OENX_1 to OENX_J and the second enable signals OENY_1 to OENY_I are shown in FIG. Figure 6 transferred in a semiconductor memory device.

[0103] Reference Fig.11 , the row decoder 261 transfers the first enable signals OENX_1 to OENX_J in a first direction D1 relative to the memory cell array 300a, and the column decoder 271 transfers the second enable signals OENY_1 to OENY_I in a second direction D2 relative to the memory cell array 300a based on the row block information RBIN received from the row decoder 261. The first enable signals OENX_1 to OENX_J and the second enable signals OENY_1 to OENY_I are transferred to the bit line sense amplifier area BLSAB in the corresponding segment (e.g., the memory sub-array block SCB), and activation of the local sense amplifier circuit associated with the corresponding segment may be determined. In an example embodiment, the column decoder 271 may transfer the local enable signal LEN to the bit line sense amplifier area BLSAB in the corresponding segment (e.g., the memory sub-array block SCB), instead of transferring the second enable signals OENY_1 to OENY_I.

[0104] Fig.12 According to an exemplary embodiment, Figure 6 A portion of a memory cell array.

[0105] Reference Figure 6 and Fig.12 , in a portion 390 ( Figure 6 ), a sub-array block SCB, a bit line sense amplifier region BLSAB, a sub-word line driver region SWB and a connection region CONJ are arranged.

[0106] The sub-array block SCB includes a plurality of word lines WL1 to WL4 extending in a row direction (a first direction D1) and a plurality of bit line pairs BL1 to BL2 and BLB1 to BLB2 extending in a column direction (a second direction D2). The sub-array block SCB includes a plurality of memory cells MC arranged at intersections between the word lines WL1 to WL4 and the bit line pairs BL1 to BL2 and BLB1 to BLB2.

[0107] Continue to refer to Fig.12 , the sub-word line driver area SWB includes a plurality of sub-word line drivers (SWD) 571, 572, 573, and 574 that drive the word lines WL1 to WL4, respectively. The sub-word line drivers (SWD) 571, 572, 573, and 574 may be arranged in different areas relative to the sub-array block SCB. For example, the sub-word line drivers 571 and 572 may be arranged in the sub-word line driver area SWB on the left side (in this example) relative to the sub-array block SCB. In addition, the sub-word line drivers 573 and 574 may be arranged in the sub-word line driver area SWB on the right side (in this example) relative to the sub-array block SCB.

[0108] The bit line sense amplifier area BLSAB includes bit line sense amplifiers BLSA 650 and 650a coupled to the bit line pairs BL1 to BL2 and BLB1 to BLB2, local sense amplifier circuits 700 and 700a, and logic gates 750. For example, the bit line sense amplifier BLSA 650 is coupled to the bit lines BL1 and BLB1 and the local sense amplifier circuit 700, and the bit line sense amplifier BLSA 650a is coupled to the bit lines BL2 and BLB2 and the local sense amplifier circuit 700a. The bit line sense amplifiers 650 and 650a may sense and amplify a voltage difference between the corresponding bit line pairs BL and BLB (e.g., between the bit lines BL1 and BLB1 or between the bit lines BL2 and BLB2) to provide the amplified voltage difference to the corresponding local I / O line pairs LIO and LIOB. For example, with respect to the bit lines BL1 and BLB1 , the amplified voltage difference may be provided to LIO1 and LIOB1 , and with respect to the bit lines BL2 and BLB2 , the amplified voltage difference may be provided to LIO2 and LIOB2 .

[0109] The local sense amplifier circuit 700 controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIO1B in response to the local enable signal LEN1 and the local control signal LCTL, and the local sense amplifier circuit 700a controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIO1B in response to the corresponding local enable signal ( Fig.12 ) and the corresponding local control signal ( Fig.121 and 10 (not shown) control the connection between the local I / O line pair LIO2 and LIOB2 and the global I / O line pair GIO2 and GIOB2. The local sense amplifier circuit 700a may be configured to operate similarly to the local sense amplifier circuit 700. In some embodiments, the local enable signal LEN1 and the local control signal LCTL may be the same for both the local sense amplifier circuit 700 and the local sense amplifier circuit 700a. In other embodiments, the local enable signal LEN1 and the local control signal LCTL provided to the local sense amplifier circuit 700 may be different from the local enable signal and the local control signal provided to the local sense amplifier circuit 700a.

[0110] The logic gate 750 may receive a first enable signal OENX_u corresponding to one of the first enable signals OENX_1 to OENX_J and a second enable signal OENY_v corresponding to one of the second enable signals OENY_1 to OENY_I. The logic gate 750 performs a logic operation on the first enable signal OENX_u and the second enable signal OENY_v, and provides a local enable signal LEN1 to the local sense amplifier circuit 700 based on the logic operation performed on the first enable signal OENX_u and the second enable signal OENY_v. The logic gate 750 may include an exclusive OR (XOR) gate, and the logic operation may correspond to an exclusive OR (XOR) operation. For example, when a bit line in the first segment is repaired using a spare bit line in the second segment, a local sense amplifier circuit associated with the first segment may be deactivated, and a local sense amplifier circuit associated with the second segment may be activated.

[0111] like Fig.12 As shown, the bit line sense amplifiers 650 and 650a may be alternately arranged at the upper and lower parts of the sub-array block SCB. The junction area CONJ is arranged adjacent to the bit line sense amplifier area BLSAB, the sub-word line driver area SWB and the sub-array block SCB. A plurality of voltage generators 610, 620, 630 and 640 may be arranged in the junction area CONJ.

[0112] exist Fig.12 , memory cells MC coupled to word lines WL1 to WL4 and bit line pairs BL1 to BL2 and BLB1 to BLB2 are shown. Although not shown, the sub-array block SCB may include spare cells coupled to word lines WL1 to WL4 and at least one spare bit line.

[0113] Fig.13 is a diagram showing a method according to an exemplary embodiment Fig.12 Circuit diagram of the bit line sense amplifier in FIG.

[0114] Reference Fig.13, a bit line sense amplifier (BLSA) 650 is coupled to the bit lines BL1 and BLB1 of each of the memory cells 660 and 670 in the memory cell array 300. The memory cell 660 may correspond to a memory cell MC of the sub-array block SCB located at the intersection of the bit line BL1 and the word line WL1, and the memory cell 670 may correspond to a memory cell MC of the sub-array block SCB located at the intersection of the bit line BLB1 and the word line WL2. Fig.12 The line sense amplifier 650 shown includes an N-type sense amplifier 651, a P-type sense amplifier 652, a precharge circuit 653, column selection switches 654a and 654b, an N-type sense amplifier (NSA) driver 655 and a P-type sense amplifier (PSA) driver 656.

[0115] The N-type sense amplifier 651 discharges the low-level bit lines of the bit lines (or, bit line pairs) BL1 and BLB1 to a low level in a sensing operation. The N-type sense amplifier 651 includes two n-channel metal oxide semiconductor (NMOS) transistors NM1 and NM2. The gate of the NMOS transistor NM1 is connected to the bit line (second bit line) BLB1, and the drain of the NMOS transistor NM1 is connected to the bit line (first bit line) BL1, and the source of the NMOS transistor NM1 is connected to the sense enable line LAB. The gate of the NMOS transistor NM2 is connected to the bit line BL1, the drain is connected to the sense enable line LAB, and the source is connected to the bit line BLB1. The N-type sense amplifier 651 connects the low-level bit line to the sense enable line LAB. The sense enable line LAB is connected to the ground voltage VSS.

[0116] The P-type sense amplifier 652 charges the high voltage bit line of the bit lines BL1 and BLB1 to a source voltage VDD level in a sensing operation. The P-type sense amplifier 652 includes two p-channel metal oxide semiconductor (PMOS) transistors PM1 and PM2. The gate of the PMOS transistor PM1 is connected to the bit line BLB1, the source is connected to the bit line BL1, and the drain is connected to the sense enable line LA. The gate of the PMOS transistor PM2 is connected to the bit line BL1, the source is connected to the sense enable line LA, and the drain is connected to the bit line BLB1.

[0117] The P-type sense amplifier 652 charges the high voltage bit lines of the bit lines BL1 and BLB1 using the power supply voltage VDD supplied to the sense enable line LA.

[0118] The PSA driver 656 provides the charging voltage VDD to the sensing enable line LA. Therefore, the transistor PM2 is turned off because the gate of the transistor PM2 is coupled to the bit line BL1 with the voltage increased by the charge sharing.

[0119] The precharge circuit 653 precharges the bit lines BL1 and BLB1 with half voltage VDD / 2 in response to the control signal PEQ in the sensing operation. When the control signal PEQ is activated, the precharge circuit 653 supplies the bit line precharge voltage VBL to the bit lines BL1 and BLB1. The bit line precharge voltage VBL may be half voltage VDD / 2. The bit lines BL1 and BLB1 are connected so that their voltages are balanced. If the bit lines BL1 and BLB1 are charged by the bit line precharge voltage VBL, the control signal PEQ is not activated. The precharge circuit 653 includes NMOS transistors N3, N4 and N5.

[0120] The column selection switches 654a and 654b provide the data sensed by the N-type sense amplifier 651 and the P-type sense amplifier 652 to the input / output lines LIO1 and LIOB1 in response to the column selection signal CSL. The column selection switches 654a and 654b are turned on so that the sensed data is transferred to the input / output lines LIO1 and LIOB1. For example, in a read operation when the sensing levels of the N-type sense amplifier 651 and the P-type sense amplifier 652 are stable, the column selection signal CSL is activated. Then, the column selection switches 654a and 654b are turned on so that the sensed data is transferred to the local I / O line pair LIO1 and LIOB1. When the charges of the bit lines BL1 and BLB1 are shared with the input / output lines LIO1 and LIOB1, the voltages of the bit lines BL1 and BLB1 change. The column selection switches 654a and 654b include NMOS transistors N6 and N7, respectively.

[0121] The NSA driver 655 provides a driving signal to the sensing enable line LAB of the N-type sense amplifier 651. The NSA driver 655 receives a signal from the bit line control signal generator 520 ( Fig. 9 ) receives the control signal LANG. Based on the control signal LANG, the NSA driver 655 grounds the sense enable line LAB. The NSA driver 655 includes a grounding transistor N1 to control the voltage of the sense enable line LAB. The PSA driver 656 provides the charging voltage VDD to the sense enable line LA of the P-type sense amplifier 652. The PSA driver 656 is controlled by the control signal LAPG from the bit line control signal generator 520. The control signals LAPG and LANG are complementary to each other.

[0122] Fig.14 Shows Fig.12 The local sense amplifier circuit in.

[0123] Reference Fig.14 , the local sense amplifier circuit 700 includes a local sense amplifier 710 , a local I / O line controller 720 , and an activation control circuit 730 .

[0124] The activation control circuit 730 performs an XOR operation on each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 and the local enable signal LEN1, and outputs the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4, respectively. Therefore, each logic level of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 may be the same or opposite to each logic level of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 according to the logic level of the local enable signal LEN1. The activation control circuit 730 includes first to third gates 731, 732, and 733.

[0125] The local sense amplifier 710 amplifies a voltage difference between the local I / O line pair LIO1 and LIOB1 in response to a second local sense enable signal PLSAEN2 to provide the amplified voltage difference to the global I / O line pair GIO1 and GIOB1. The local I / O line controller 720 includes first to fourth NMOS transistors 721, 722, 723, and 724, and controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1 in response to a third connection control signal PMUXON3 and a fourth connection control signal PMUXON4.

[0126] For example, when each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 is at a high level and the local enable signal LEN1 is at a high level, each of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 becomes a low level. Therefore, the local sense amplifier 710 is disabled, and the local I / O line controller 720 cuts off the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1.

[0127] For example, when each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 is a high level and the local enable signal LEN1 is a low level, each of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 becomes a high level. Therefore, the local sense amplifier 710 is enabled, and the local I / O line controller 720 provides connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1.

[0128] Fig.15 Shows Fig.12 Another example of a bit line sense amplifier region in FIG.

[0129] exist Fig.15 middle, Fig. 9 The signal generator 530 in FIG. 2 directly applies the local enable signal LEN21 to the local sense amplifier circuit 700 arranged in the bit line sense amplifier region BLSAB_1. In this case, the column decoder 271 provides the local enable signal LEN21, and the row decoder 261 does not provide the first enable signal.

[0130] Fig.16 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of another example of a semiconductor memory device in FIG.

[0131] Reference Fig.16 , the semiconductor memory device 200b includes a control logic circuit 210, an address register 220, a block control logic 230, a refresh counter 245, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300b, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, an ECC engine 280 and a data I / O buffer 295.

[0132] The memory cell array 300b includes first to eighth block arrays 310 to 380. The row decoder 260 includes first to eighth block row decoders 260a to 260h coupled to the first to eighth block arrays 310 to 380, respectively, the column decoder 270 includes first to eighth block column decoders 270a to 270h coupled to the first to eighth block arrays 310 to 380, respectively, and the sense amplifier unit 285 includes first to eighth block sense amplifiers 285a to 285h coupled to the first to eighth block arrays 310 to 380, respectively. The first to eighth block arrays 310 to 380, the first to eighth block row decoders 260a to 260h, the first to eighth block column decoders 270a to 270h, and the first to eighth block sense amplifiers 285a to 285h may form the first to eighth blocks. Each of the first to eighth block arrays 310 to 380 includes a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BL.

[0133] The address register 220 receives an address ADDR including a block address BANK_ADDR, a row address RADDR, and a column address CADDR from the memory controller 100. The address register 220 provides the received block address BANK_ADDR to the block control logic 230, provides the received row address RADDR to the row address multiplexer 240, and provides the received column address CADDR to the column address latch 250.

[0134] The block control logic 230 generates a block control signal in response to the block address BANK_ADDR, activates one of the first to eighth block row decoders 260a to 260h corresponding to the block address BANK_ADDR in response to the block control signal, and activates one of the first to eighth block column decoders 270a to 270h corresponding to the block address BANK_ADDR in response to the block control signal.

[0135] The row address multiplexer 240 receives the row address RADDR from the address register 220 and receives the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 selectively outputs the row address RADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 is applied to the first to eighth block row decoders 260a to 260h.

[0136] One of the first to eighth block row decoders 260a to 260h that is activated by the block control logic 230 decodes the row address RA output from the row address multiplexer 240 and activates the word line corresponding to the row address RA. For example, the activated block row decoder applies a word line driving voltage to the word line corresponding to the row address RA. In addition, the activated block row decoder activates the spare word line corresponding to the spare row address SRA output from the row block information circuit 400 of the activated block row decoder while activating the word line corresponding to the row address RA.

[0137] The column address latch 250 receives the column address CADDR from the address register 220 and temporarily stores the received column address CADDR. For example, the column address latch 250 may temporarily store the received column address CADDR in an internal memory of the column address latch 250. In some embodiments, in burst mode, the column address latch 250 generates a column address that increases relative to the received column address CADDR. The column address latch 250 applies the temporarily stored or generated column address CADDR to the first to eighth block column decoders 270a to 270h.

[0138] An activated one of the first to eighth block column decoders 270a to 270h activates a sense amplifier corresponding to the block address BANK_ADDR and the column address CADDR through the I / O gating circuit 290. The I / O gating circuit 290 includes a circuit for gating input / output data, and also includes a read data latch for storing data output from the first to eighth block arrays 310 to 380 and a write driver for writing data to the first to eighth block arrays 310 to 380.

[0139] The codeword CW read from one of the first to eighth block arrays 310 to 380 from which data is read is sensed by a sense amplifier coupled to the one block array and stored in a read data latch of the I / O gating circuit 290. After ECC decoding is performed on the codeword CW by the ECC engine 280, the codeword CW stored in the read data latch may be provided to the memory controller 100 via the data I / O buffer 295. After ECC encoding is performed on the data DQ by the ECC engine 280, the data DQ to be written in one of the first to eighth block arrays 310 to 380, provided from the memory controller 100 to the data I / O buffer 295, is written in one block array by a write driver of the I / O gating circuit 290.

[0140] The data I / O buffer 295 may provide data DQ from the memory controller 100 to the ECC engine 280 in a write operation of the semiconductor memory device 200 b based on the clock signal CLK, and may provide data DQ from the ECC engine 280 to the memory controller 100 in a read operation of the semiconductor memory device 200 b.

[0141] In a write operation, the ECC engine 280 may generate parity bits based on the data DQ from the data I / O buffer 295, and may provide a codeword CW including the data DQ and the parity bits to the I / O gating circuit 290. The I / O gating circuit 290 may write the codeword CW into a block array.

[0142] In a read operation, the ECC engine 280 may receive a codeword CW read from a block array from the I / O gating circuit 290. The ECC engine 280 may perform ECC decoding on the data DQ based on the parity bits in the codeword CW, may correct at least one error bit in the data DQ, and may provide the corrected data to the data I / O buffer 295.

[0143] The control logic circuit 210 may control the operation of the semiconductor memory device 200b. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200b to perform a write operation or a read operation. The control logic circuit 210 includes a decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200b.

[0144] Each of the first to eighth block arrays 310 to 380 may include a plurality of memory blocks, and divides the memory blocks into a plurality of row blocks based on the row block equality bit of the row address RADDR. Each of the first to eighth block row decoders 260a to 260h may use Figure 6 The row decoder 261 in the embodiment of the present invention can provide the row block information signal to a corresponding one of the first to eighth block column decoders 270a to 270h. Each of the first to eighth block column decoders 270a to 270h can adopt Figure 6 The column decoder 271 in the memory block may be used to repair the bit line coupled to the defective cell in the first segment using the spare bit line in the second segment based on the column address CADDR and the row block information signal. In example embodiments, the first segment and the second segment may be located in the same memory block.

[0145] Fig.17 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0146] Reference Figures 2 to 17 In a method of operating a semiconductor memory device 200, the semiconductor memory device 200 includes a memory cell array having a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word lines and bit lines, each of the plurality of memory blocks is divided into a plurality of row blocks by row block equal bits corresponding to a portion of bits of a row address, and each of the row blocks includes a plurality of sub-array blocks arranged in a first direction, a row decoder 261 activates a first word line in a first row block in response to a row address RADDR, and activates a second word line in a second row block different from the first row block when the first row block includes at least one defective cell (S110).

[0147] The column decoder 271 repairs a first bit line coupled to at least one defective cell using one of a first spare bit line in the first section and a second spare bit line in the second section in response to a column address CADDR and a row block information signal RBIN indicating that the first row block includes at least one defective cell (S120).

[0148] Fig.18A and Fig.18B A method of operating a semiconductor memory device according to example embodiments is illustrated.

[0149] Reference Figures 2 to 16 , Fig.18A and Fig.18B , the semiconductor memory device 200 receives an activation command and a first row address indicating a word line included in a first row block (S210). The row block information circuit 400 in the row decoder 261 determines whether to activate a second word line included in a second row block (S220). When the word line is not activated (No in S220), the row decoder 261 activates the first word line (S240), and the column decoder 271 receives a column address through a write command or a read command (S260).

[0150] When the first row block includes at least one defective cell and the word line is to be activated (Yes in S220), the row decoder 261 activates the first word line and the second word line (S230) and the column decoder 271 receives the column address through a write command or a read command (S250). A corresponding repair circuit (e.g., one of the repair circuits 50_1 to 50_I) in the column decoder 271 determines whether the column address CADDR matches the defective column address of the bit line coupled to the at least one defective cell (S270).

[0151] When the column address CADDR matches the defective column address (Yes in S270), the corresponding repair circuit in the column decoder 271 determines to use the spare bit line in the second segment by referring to the fuse circuit 520. When the spare bit line in the second segment is to be used (Yes in S280), the corresponding repair circuit in the column decoder 271 activates the second repair signal CREN2 and activates the corresponding second enable signal OENY, and the corresponding sub-column decoder (for example, one of the sub-column decoders 55_1 to 55_I) selects the spare column selection line SCSL and performs a column redundancy operation by using a spare cell coupled to the second word line and the spare bit line (S310). For example, the corresponding sub-column decoder selects the spare column selection line SCSL to input / output data through the spare bit line in the second segment. When the spare bit line in the second segment is not used (No in S280), the corresponding repair circuit in the column decoder 271 activates the first repair signal CREN1, and the corresponding sub-column decoder selects the spare column selection line SCSL, and performs a column redundancy operation by utilizing the spare cell coupled to the first word line and the spare bit line (S320).

[0152] When the column address CADDR does not match the defective column address (No in S270), the defective cell is not coupled to the first word line. Therefore, the column decoder 271 accesses the memory cell indicated by the row address RADDR and the column address CADDR (S330).

[0153] Fig. 18C Shown in Fig.18A and Fig.18B access memory cells.

[0154] exist Fig. 18C , it is assumed that the first memory block MB1 is divided into a plurality of segments SEG1 to SEG8.

[0155] Reference Fig. 18C , since the memory cell corresponding to the column selection line CSL1 in the first segment SEG4 is a normal cell, the memory cell coupled to the word line WLa is selected through the column selection line CSL1. Since the memory cell corresponding to the column selection line CSL2 in the first segment SEG4 is a defective cell, the defective cell coupled to the word line WLa is repaired using the spare memory cell coupled to the word line WLa and selected through the spare column selection line SCSL1, as indicated by reference numeral 581. Since the memory cell corresponding to the column selection line CSL3 in the first segment SEG4 is a defective cell, the defective cell coupled to the word line WLa is repaired using the spare memory cell coupled to the word line WLb in the second segment SEG5 and selected through the spare column selection line SCSL2, as indicated by reference numeral 582.

[0156] Therefore, according to example embodiments, when a row block including a segment includes at least one defective cell and a spare bit line in the same segment is unavailable, the column decoder can repair a bit line coupled to a defective memory cell using a spare bit line in a different segment. The column decoder selects a spare bit line to input / output data through the spare bit line in a different segment. Therefore, the semiconductor memory device 200 can increase flexibility and productivity of a column repair operation.

[0157] Fig.19 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0158] Reference Fig.19 , a semiconductor memory device 800 may include a first group of chips 810 and a second group of chips 820 that provide soft error analysis and correction functions in a stacked chip structure.

[0159] The first group of chips 810 may include at least one buffer chip. The second group of chips 820 may include a plurality of memory chips 820-1 to 820-s stacked on the first group of chips 810, and data may be transferred through a plurality of through silicon vias (TSV) lines extending from the memory chip 820-s through the intermediate memory chips 820-s-1 to 820-1 to the first group of chips 810.

[0160] At least one of the memory chips 820-1 to 820-s may include a first type error correction code (ECC) engine 822 that generates transmission parity bits based on transmission data to be sent to the first group chip 810. The first type ECC engine 822 may be referred to as a "unit core ECC engine."

[0161] The buffer chip 810 may include a second type ECC engine 812, and when a transmission error is detected from the transmission data received through the TSV line, the second type ECC engine 812 corrects the transmission error using the transmission parity bit and generates error-corrected data. The second type ECC engine 812 may be referred to as a "via ECC engine". The buffer chip 810 may include an address decoder 814, and the address decoder 814 may adopt Figure 6 The row decoder 261 and column decoder 271 in.

[0162] The semiconductor memory device 800 may be a stacked chip type memory device or a stacked memory device that transfers data and control signals through TSV lines. The TSV lines may also be referred to as “through electrodes”.

[0163] The first type ECC engine 822 may perform error correction on data output from the memory chip 820 - s before transmitting the transmission data.

[0164] Through the above description, the TSV line group 832 formed in one memory chip 820-r may include a plurality of TSV lines L1 to Ls, and the parity TSV line group 834 may include a plurality of TSV lines L10 to Lt. The TSV lines L1 to Ls of the data TSV line group 832 and the parity TSV lines L10 to Lt of the parity TSV line group 834 may be connected to micro bumps MCB formed correspondingly in the memory chips 820-1 to 820-s.

[0165] At least one of the memory chips 820 - 1 to 820 - s may include DRAM cells, each of which includes at least one access transistor and one storage capacitor.

[0166] The semiconductor memory device 800 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a memory controller through a data bus B10. The buffer chip 810 may be connected to the memory controller through the data bus B10.

[0167] The first type ECC engine 822, denoted as a unit core ECC engine, may output transmission parity bits and transmission data through the parity TSV line group 834 and the data TSV line group 832, respectively. The output transmission data may be data in which errors are corrected by the first type ECC engine 822.

[0168] The second type ECC engine 812, denoted as a via ECC engine, may determine whether a transmission error occurs in the transmission data received through the data TSV line group 832 based on the transmission parity bit received through the parity TSV line group 834. When a transmission error is detected, the second type ECC engine 812 may correct the transmission error of the transmission data using the transmission parity bit. When the transmission error is uncorrectable, the second type ECC engine 812 may output information indicating that an uncorrectable data error occurs.

[0169] Fig. 20 According to an exemplary embodiment, Fig.19 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0170] Fig. 20 A 3D chip structure 900 is shown in which a host and a high bandwidth memory (HBM) are directly connected without an intermediate layer.

[0171] Reference Fig. 20 , a host chip 920 such as a system chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU) may be arranged on a printed circuit board (PCB) 910 using flip chip bumps FB. The memory chips D11 to D14 may be stacked on the host chip 920 to implement a system such as Fig.19The HBM structure of the second group of chips 820. Fig. 20 In, omitted Fig.19 The buffer chip 810 or logic chip of the host chip 910 may be formed in the memory chip D11 or the host chip 910. However, the buffer chip 810 or the logic chip may be arranged between the memory chip D11 and the host chip 910. In order to implement the HBM (820) structure, the TSV line may be formed in the memory chips D11 to D14. For example, the TSV line may be formed to extend from the memory chip D14 to the memory chips D13, D12, and D11. The TSV line may be electrically connected to the micro-bump MCB placed between the memory chips.

[0172] Aspects of the inventive concept may be applied to a system utilizing a semiconductor memory device.

[0173] The above exemplary embodiments are shown and are not to be construed as limiting. Although some exemplary embodiments are described, it should be readily understood by those skilled in the art that many modifications are possible in the exemplary embodiments without essentially departing from the novel teachings and advantages of the inventive concept. Therefore, all these modifications are intended to be included within the scope of the inventive concept defined in the claims.

Claims

1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word lines and bit lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by at least one row block equal bit corresponding to a portion of bits of a row address, and each of the plurality of row blocks includes a plurality of sub-array blocks arranged in a first direction; The row decoder is constructed as: activating a first word line in a first row block of the plurality of row blocks in response to the row address; When the first row block includes at least one defective cell, activating a second word line in a second row block among the plurality of row blocks, the second row block being different from the first row block; and outputting a row block information signal indicating whether the second word line is activated, wherein the first row block is associated with a first segment of a plurality of segments, the second row block is associated with a second segment of the plurality of segments, the second segment is different from the first segment, and the plurality of memory blocks are divided into the plurality of segments in a second direction intersecting the first direction; and A column decoder is configured to receive the row block information signal and repair a first bit line coupled to the at least one defective cell using one of a first spare bit line in the first section and a second spare bit line in the second section in response to a column address and the row block information signal.

2. The semiconductor memory device according to claim 1, in, Each of the plurality of sections includes a plurality of bit lines and at least one spare bit line, wherein the row address is received via an activation command, and The column address is received through a write command or a read command.

3. The semiconductor memory device according to claim 1, in, The row decoder includes a plurality of row block fuse circuits, each row block fuse circuit corresponding to one of the plurality of row blocks, and Wherein, each of the plurality of row block fuse circuits comprises: a row block information storage table configured to store: a defective row block address associated with a defective row block, the defective row block including the at least one defective cell; row block address information of a corresponding row block; replacement row block information for determining whether to activate the second word line and a master fuse bit, the master fuse bit indicating whether the corresponding row block can be used as a replacement row block; a row block comparator configured to compare the at least one row block equality bit with the defective row block address to output a row block match signal; and a signal generator configured to provide the column decoder with a row block information signal associated with the row block match signal, and configured to output a first activation signal associated with activation of the second word line based on the row block match signal and the replacement row block information, The row block information storage table is configured to provide the replacement row block information to the signal generator in response to the row block matching signal.

4. The semiconductor memory device according to claim 1, wherein: The column decoder comprises: a plurality of sub-column decoders corresponding to the plurality of memory blocks; and a plurality of repair circuits corresponding to the plurality of sub-column decoders, and Each of the plurality of repair circuits is configured to apply a first repair signal, a second repair signal, and an internal enable signal to a corresponding sub-column decoder of the plurality of sub-column decoders, the internal enable signal being associated with activation of the second word line.

5. The semiconductor memory device according to claim 4, wherein: A repair circuit among the multiple repair circuits corresponding to a first memory block among the multiple memory blocks is configured to repair the first bit line with the first spare bit line by activating the first repair signal, and is configured to repair the first bit line with the second spare bit line by activating the second repair signal.

6. The semiconductor memory device according to claim 4, wherein: Each of the plurality of repair circuits comprises: a fail address storage table configured to store fail column address information associated with column address information of defective cells of corresponding memory blocks of the plurality of memory blocks; a column address comparator configured to compare the column address with the failed column address information to output a column match signal indicating whether the column address matches the failed column address information; a fuse circuit comprising a plurality of fuse sets, wherein each of the plurality of fuse sets stores: spare bit line information regarding spare bit lines for each of the sectors in a corresponding memory block; and a master fuse bit associated with availability of spare bit lines for the corresponding sector; a signal generator configured to generate the internal enable signal associated with activation of the second word line based on the row block information signal, the spare bit line information, and the master fuse bit; and A repair signal generator is configured to selectively activate the first repair signal and the second repair signal based on the column matching signal and the master fuse bit.

7. The semiconductor memory device according to claim 4, wherein: Each of the plurality of sub-column decoders comprises: a column selection line driver configured to select a column selection line in response to the column address and a column matching signal output by a corresponding repair circuit of the plurality of repair circuits to select the first bit line in the first section; and A spare column selection line driver is constructed to selectively activate a second enable signal associated with the second segment, and is constructed to select a spare column selection line in response to the column matching signal, the first repair signal, the second repair signal and the internal enable signal to input and output data through the first spare bit line in the first segment or the second spare bit line in the second segment.

8. The semiconductor memory device according to claim 7, wherein: The column selection line driver is configured to select a column selection line corresponding to the column address when the column match signal indicates that the column address does not match the fail column address information.

9. The semiconductor memory device according to claim 7, wherein: The spare column selection line driver is constructed to deactivate the second enable signal and to select the spare column selection line to input and output data through the first spare bit line in the first segment when the column match signal indicates that the column address matches the failed column address information and the first repair signal is activated.

10. The semiconductor memory device according to claim 7, wherein: The spare column selection line driver is constructed to deactivate the second enable signal and to select the spare column selection line to input and output data through the second spare bit line in the second segment when the column match signal indicates that the column address matches the failed column address information and the second repair signal is activated.

11. The semiconductor memory device according to claim 4, in, The plurality of segments are arranged in the first direction and the second direction of the substrate, and Wherein, the memory cell array further comprises: a plurality of sub-word line driver regions arranged between the plurality of segments in a first direction; a plurality of bit line sense amplifier regions arranged between the plurality of segments in the second direction; and A plurality of local sense amplifier circuits are arranged in the plurality of bit line sense amplifier regions.

12. The semiconductor memory device according to claim 11, wherein The memory cell array further comprises: A logic gate is configured to perform a logic operation on a first enable signal and a second enable signal associated with activation of the second segment to provide a local enable signal to a corresponding local sense amplifier circuit of the plurality of local sense amplifier circuits.

13. The semiconductor memory device according to claim 12, wherein: The corresponding local sense amplifier circuit corresponding to the second section is activated, and data is input and output through the second spare bit line in the second section.

14. The semiconductor memory device according to claim 1, further comprising: a peripheral circuit configured to control the row decoder and the column decoder in response to a command and an address received from an external device, The peripheral circuit includes an ECC engine configured to perform ECC encoding on data to be stored in the memory cell array and to perform ECC decoding on data read from the memory cell array.

15. The semiconductor memory device according to claim 14, wherein: The peripheral circuit is configured to control repair of a first bit line through one of the first spare bit line and the second spare bit line based on an error correction capability of the error correction code engine.

16. The semiconductor memory device according to claim 1, comprising: A first group of chips including at least one buffer chip; as well as a second group of chips, comprising a plurality of memory chips, wherein the plurality of memory chips are stacked on the first group of chips and are configured to transmit data through a plurality of through silicon vias, Each of the plurality of memory chips comprises a plurality of dynamic memory cells, and Wherein, the at least one buffer chip includes the row decoder and the column decoder.

17. A semiconductor memory device comprising: a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word lines and bit lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by row block equal bits corresponding to a portion of bits of a row address, and each of the plurality of row blocks includes a plurality of sub-array blocks arranged in a first direction; and an address decoder configured to change a physical row address of a memory cell storing or outputting data based on a column address received through a write command or a read command, Wherein, the address decoder comprises: The row decoder is constructed as: activating a first word line in a first row block of the plurality of row blocks in response to the row address; When the first row block includes at least one defective cell, activating a second word line in a second row block different from the first row block among the plurality of row blocks, and outputting a row block information signal indicating whether the second word line is activated, wherein the first row block is associated with a first segment of a plurality of segments, the second row block is associated with a second segment of the plurality of segments that is different from the first segment, and the plurality of memory blocks are divided into the plurality of segments in a second direction intersecting the first direction; and A column decoder is configured to receive the row block information signal output from the row decoder and repair a first bit line coupled to the at least one defective cell using one of a first spare bit line in the first section and a second spare bit line in the second section in response to a column address and the row block information signal.

18. The semiconductor memory device according to claim 17, in, The row address is received via an activate command.

19. A method of operating a semiconductor memory device, wherein: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word lines and bit lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by row block equal bits corresponding to a portion of bits of a row address, and each of the plurality of row blocks includes a plurality of sub-array blocks arranged in a first direction, the method comprising: activating, by a row decoder, a first word line in a first row block among the plurality of row blocks in response to the row address; When the first row block includes at least one defective cell, activating a second word line in a second row block different from the first row block among the plurality of row blocks; outputting a row block information signal through the row decoder, the row block information signal indicating whether the second word line in the second row block has been activated; receiving the row block information signal through a column decoder; repairing a first bit line coupled to the at least one defective cell by using one of a first spare bit line in a first segment of the plurality of segments and a second spare bit line in a second segment of the plurality of segments through the column decoder in response to a column address and the row block information signal, The row block information signal indicates that the first row block includes the at least one defective cell.

20. The method according to claim 19, in, The first row block is associated with the first segment of the plurality of segments, the second row block is associated with the second segment of the plurality of segments that is different from the first segment, and the plurality of memory blocks are divided into the plurality of segments in a second direction intersecting the first direction, Each of the plurality of sections includes a plurality of bit lines and at least one spare bit line. wherein the row address is received via an activation command, and The column address is received through a write command or a read command.

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