Wire bond package with monolithically exposed heatsink and leads

Abstract

A semiconductor device package is disclosed, comprising a conductive die pad having a die attachment surface and an outer surface. A semiconductor die is mounted on the die attachment surface. An encapsulation material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulation material, and bends toward a lower side of the encapsulation material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulation material, and bends toward a lower side of the encapsulation material. A first lateral portion of the first lead intersecting the first sidewall is vertically offset from a second lateral portion of the second lead intersecting the second sidewall.

Description

Technical Field

[0001] The present invention relates generally to semiconductor device packaging, and more particularly to a semiconductor package having a thermally conductive heat sink and a corresponding method of manufacturing the semiconductor package. Background Art

[0002] Semiconductor packages are commonly used to house and protect semiconductor die from a variety of different semiconductor technologies including silicon, silicon carbide (SiC), gallium nitride (GaN), etc. These semiconductor dies can be configured to have a variety of different device types, such as microprocessors, discrete devices, amplifiers, controllers, sensors, etc. In a semiconductor package, the semiconductor die is mounted to a die pad. The semiconductor package typically includes an electrically insulating encapsulation material such as plastic or ceramic, which seals and protects the integrated circuit from moisture and dust particles. Conductive leads are connected to various terminals of the encapsulated integrated circuit (or multiple circuits) and are accessible from the outside of the semiconductor package. In a so-called lead frame type package, the die pad and leads are provided together from a lead frame.

[0003] In some package designs, the die pad portion of the lead frame is configured as a so-called "heat sink" or "heat fin." These die pads are designed to draw heat from the integrated circuit during operation of the integrated circuit and transfer that heat to an external heat dissipation element, such as an external heat sink. Typically, the heat sink is formed from a thermally conductive material (e.g., metal). In some package configurations, the package die pad also serves as an electrical terminal that provides a reference potential (e.g., ground) to the encapsulated integrated circuit (or circuits).

[0004] In some package designs, the package die pad has a so-called sunken configuration. According to this design, the die pad (i.e., the portion of the package on which the semiconductor die is mounted) is located between bent leads that bend downward as they approach the die pad. An example of this design is described in U.S. Patent Publication No. 2010 / 0193920 A1 to Poh, which is incorporated by reference in its entirety.

[0005] Designers are continually seeking improvements in package design. One notable design consideration that has received considerable attention is the total footprint of the package. As technology advances, there is a strong desire to reduce the size and / or cost of most electronic components. Another notable design consideration is heat dissipation. As devices become faster and more powerful while becoming smaller, the amount of heat dissipated per unit area of ​​modern semiconductor devices continues to increase. As a result, greater emphasis is placed on cooling solutions to prevent modern integrated circuits from malfunctioning or degrading performance due to overheating. The desire to reduce the total footprint of a package often conflicts with the desire to increase the heat dissipation capabilities of a semiconductor package because larger heat sinks are conventionally used to provide more cooling. Summary of the invention

[0006] A semiconductor device package is disclosed. According to an embodiment, the semiconductor device package includes a conductive die pad having a die attachment surface and an outer surface opposite to the die attachment surface. The semiconductor die is mounted on the die attachment surface. The encapsulation material encapsulates the semiconductor die, and the outer surface of the die pad is exposed on the upper side of the encapsulation material body. The first lead directly contacts the die pad, extends away from the first side wall of the encapsulation material, and bends toward the lower side of the encapsulation material body opposite to the upper side. The second lead is electrically connected to a terminal of the semiconductor die, extends away from the second side wall of the encapsulation material opposite to the first side wall, and bends toward the lower side of the encapsulation material body. The first lateral portion of the first lead intersecting the first side wall is vertically offset from the second lateral portion of the second lead intersecting the second side wall.

[0007] According to another embodiment, a semiconductor device package includes a semiconductor die. An encapsulation material encapsulates the semiconductor die. An integrally formed conductive structure provides a die pad and a first lead for the semiconductor device package. The second lead is partially encapsulated by the encapsulation material body and is separated from the die pad. The semiconductor die includes a first terminal facing the die pad and electrically connected to the die pad and a second terminal facing away from the die pad and electrically connected to the second lead. The first and second leads intersect with the first and second side walls of the encapsulation material facing opposite directions at positions vertically offset from each other.

[0008] A method for forming a semiconductor device package is disclosed. According to an embodiment, the method includes providing a conductive die pad having a die attachment surface and an outer surface opposite to the die attachment surface. The semiconductor die is mounted on the die attachment surface. An encapsulation material is formed, the encapsulation material encapsulates the semiconductor die, and the outer surface of the die pad is exposed on the upper side of the encapsulation material. A first lead is provided, the first lead directly contacts the die pad, extends away from a first side wall of the encapsulation material body, and bends toward a lower side of the encapsulation material opposite to the upper side. A second lead is provided, the second lead is electrically connected to a terminal of the semiconductor die, extends away from a second side wall of the encapsulation material opposite to the first side wall, and bends toward the lower side of the encapsulation material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The elements in the figures are not necessarily drawn to scale relative to each other. Similar reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the figures and described in detail in the following description.

[0010] Figure 1 A cross-sectional view of a semiconductor device package according to an embodiment is depicted.

[0011] Figure 2 (include Figure 2 A and Figure 2 B) depicts the Figure 1 Semiconductor device packaging. Figure 2 A depicts a semiconductor device package from a plan view perspective. Figure 2 B depicts a semiconductor device package from a perspective view.

[0012] Figure 3 Depicted is a cross-sectional view of a semiconductor device package according to another embodiment.

[0013] Figure 4 A lead frame for use in a method of forming a packaged semiconductor device according to an embodiment is depicted.

[0014] Figure 5 Mounting a semiconductor die on a lead frame in a method of forming a packaged semiconductor device according to an embodiment is depicted.

[0015] Figure 6 Providing bond wires electrically connecting terminals of a semiconductor die to a lead frame in a method of forming a packaged semiconductor device according to an embodiment is depicted.

[0016] Figure 7 Depicted is vertically offsetting a first portion of a lead frame from a second portion of a lead frame prior to encapsulation in a method of forming a packaged semiconductor device according to an embodiment.

[0017] Figure 8 Depicted is encapsulating a semiconductor die and wire bonding in a method of forming a packaged semiconductor device according to an embodiment.

[0018] Fig. 9 Trimming semiconductor leads in a method of forming a packaged semiconductor device according to an embodiment is depicted. DETAILED DESCRIPTION

[0019] Embodiments of packaged semiconductor devices are described herein. Packaged semiconductor devices have several significant advantages, for example, packaged semiconductor devices maximize the ratio between the heat sink area and the main volume of the encapsulation material. This can be attributed to the provision of a monolithic die pad and leads exposed to the entire upper surface of the package. In addition, the packaged semiconductor device also maximizes the ratio between the size of the die and the overall size of the encapsulation material. For example, according to an advantageous embodiment, the heat sink of the package extends completely to the sidewalls of the semiconductor material. This design allows the semiconductor die to be positioned very close to the side of the package. As a result, a more favorable compromise between heat dissipation and space utilization is achieved compared to the so-called sunken design, which requires a spacing between the die pad and the edge of the encapsulation material of the sunken (bent) portion of the leads.

[0020] The space efficiency and high thermal performance of the presently disclosed embodiments are particularly due to the vertical offset lead design. Advantageously, the technology described herein produces the vertical offset lead design using a single lead frame. In one example, a packaged semiconductor device includes first and second leads extending away from the package in opposite directions and vertically offset from each other. The first and second leads each include a lateral portion that intersects the main body of the package at different vertical positions. For example, the first lead may intersect the main body of the package at a higher position (i.e., a position closer to the upper side of the package than the second lead). The vertical positioning of the first lead allows the heat sink to extend directly from the inside of the package along a single plane to meet the first lead at the side wall of the main body of the package. In an advantageous embodiment, the heat sink and the first lead are part of a single, integrally formed metal structure. The inward-facing surface of the structure provides a large die attachment surface extending to the side wall of the main body of the package. The outward-facing surface of the structure is exposed at the upper surface of the package and provides a large surface area for mounting a heat sink thereon.

[0021] Reference Figure 1 , Figure 1A semiconductor device package 100 according to an embodiment is depicted. The semiconductor device package 100 includes at least one semiconductor die 102. In general, the semiconductor die 102 can be configured as any type of transistor, such as a MOSFET (metal oxide semiconductor field effect transistor), an LDMOS (laterally diffused metal oxide semiconductor) device, a HEMT (high electron mobility transistor) device, etc. More specifically, the semiconductor die 102 can be configured as any of a wide range of various devices, such as a diode, a thyristor, etc. The semiconductor die 102 can be configured as a vertical device that is configured to conduct in a direction perpendicular to the upper and lower surfaces 104, 106 of the semiconductor die 102, or the semiconductor die 102 can be configured as a lateral device that is configured to conduct in a direction parallel to the upper and lower surfaces 104, 106 of the semiconductor die 102. Furthermore, instead of the single semiconductor die 102 shown in the depicted embodiment, the packaged semiconductor device may include any number of the semiconductor dies 102 described above, eg, one, two, three, four, etc.

[0022] For the following discussion, the semiconductor die 102 is configured as a vertical transistor having a drain terminal 108 disposed on a lower surface 106 of the semiconductor die 102 and a gate terminal and a source terminal 110, 112 disposed on an upper surface 104 of the semiconductor die 102. The drain terminal 108 directly faces a conductive die pad 114 and is electrically connected to the conductive die pad 114. An adhesive 109 such as solder, sinter, or conductive glue may be provided between or around the drain terminal 108 to provide the connection. The source and gate terminals 110, 112 are electrically connected to conductive leads 116 via conductive bonding wires 115. In Figure 1 In FIG. 1 , a connection between the gate terminal 112 and one of the conductive leads 116 is shown. In another cross section of the device, a similar connection between the source terminal 110 and one of the conductive leads 116 is provided.

[0023] The semiconductor device package 100 includes an electrically insulating encapsulant body 118. The encapsulant body 118 encapsulates the semiconductor die 102 using an electrically insulating material such as ceramic, plastic, etc. In one example, the material can be molded, for example, by an injection or transfer molding process. The encapsulant body 118 completely covers the semiconductor die 102 to protect the semiconductor die 102 and any associated electrical connections to the semiconductor die 102 from the external environment.

[0024] The encapsulation body 118 includes an upper side 120 and a lower side 122 opposite to the upper side 120. Both the upper side 120 and the lower side 122 of the encapsulation body 118 can be substantially planar surfaces. The first and second side walls 124, 126 of the encapsulation body 118 are arranged to be opposite to each other and extend between the upper side and the lower side 120, 122. In the following description, the vertical direction (V) of the semiconductor device package 100 refers to a direction substantially perpendicular to the upper side and the lower side 120, 122 of the encapsulation body 118. In addition, the lateral direction (L) refers to a direction perpendicular to the vertical direction (V), that is, a direction substantially parallel to the upper side and the lower side 120, 122 of the encapsulation body 118.

[0025] The die pad 114 is an electrically conductive structure, and optionally a thermally conductive structure. The die pad 114 includes a die attach surface 128 and an outer surface 130 opposite the die attach surface 128. Both the die attach surface 128 and the outer surface 130 can be substantially planar. That is, each of the two surfaces can extend along a single plane. The semiconductor die 102 is mounted on the die attach surface 128 using a conductive adhesive (e.g., solder) that provides adhesion and electrical connection between the drain terminal 108 and the die pad 114. In this configuration, the die pad 114 can be configured as a so-called heat sink, wherein a cooling device such as a heat sink (not shown) is placed directly on top of the device package and is used to remove the heat generated by the semiconductor die 102 during operation of the semiconductor device package 100.

[0026] The semiconductor device package 100 includes a first conductive lead 132. The first lead 132 directly contacts the die pad 114. Thus, the first lead 132 is directly electrically connected to the drain terminal 108 of the semiconductor die 102 via the die pad 114. In addition, the electrical connection is provided without using any intermediate electrical connection mechanism (e.g., bonding wires, ribbons, etc.). According to an embodiment, the first lead 132 and the die pad 114 are part of a single, integrally formed structure. That is, the first lead 132 and the die pad 114 are formed of a continuous piece of conductive material (e.g., metal). Alternatively, the first lead 132 can be a discrete structure attached to the die pad 114 using a conductive adhesive (e.g., solder, sinter, etc.).

[0027] The first lead 132 extends away from the first sidewall 124 of the encapsulation body 118 and bends toward the lower side 122 of the encapsulation body 118. More specifically, the first lead 132 includes a first lateral portion 134 that intersects the first sidewall 124 and extends away from the first sidewall 124 in a lateral direction (L). That is, the first lateral portion 134 is oriented to be lateral relative to the first sidewall 124. The first lead 132 further includes a first vertical portion 136. The first vertical portion 136 forms a bend that intersects the first lateral portion 134. That is, the first vertical portion 136 is directly adjacent to the first lateral portion 134 and forms an angle with the first lateral portion 134. The first vertical portion 136 extends substantially vertically (that is, in a vertical direction (V)) toward the lower side 122 of the semiconductor device package 100. That is, the first vertical portion 136 is positioned transversely relative to the upper and lower sides 120, 122 of the enclosure body 118. In one embodiment, the first lateral portion 134 is substantially parallel to the upper side 120 of the enclosure body 118, and the first vertical portion 136 is substantially perpendicular to the upper side 120 of the enclosure body 118. More generally, if the first lead 132 has a bent lead configuration, the first lateral portion 134 and the first vertical portion 136 can be oriented at different angles relative to each other and relative to the first sidewall 124.

[0028] The semiconductor device package 100 includes a second conductive lead 138. The second lead 138 extends away from the second sidewall 126 of the encapsulation body 118 and bends toward the lower side 122 of the encapsulation body 118. More specifically, the second lead 138 includes a second lateral portion 140 that intersects the second sidewall and extends away from the second sidewall in a lateral direction (L). That is, the second lateral portion 140 is oriented to be lateral relative to the second sidewall 126. The second lead 138 further includes a second vertical portion 142. The second vertical portion 142 forms a bend that intersects the second lateral portion 140. That is, the second vertical portion 142 is directly adjacent to the second lateral portion 140 and forms an angle with the second lateral portion 140. The second vertical portion 142 extends vertically (that is, in a vertical direction (V)) toward the lower side 122 of the semiconductor device package 100. That is, the second vertical portion 142 is oriented to be transverse relative to the upper and lower sides 120, 122 of the enclosure body 118. In one embodiment, the second transverse portion 140 is substantially parallel to the upper side 120 of the enclosure body 118, and the second vertical portion 142 is substantially perpendicular to the upper side 120 of the enclosure body 118. More generally, if the second transverse portion 140 has a transverse component extending thereto and the second vertical portion 142 has a vertical component extending thereto, the second transverse portion 140 and the second vertical portion 142 can be oriented to be at different angles relative to each other and relative to the second sidewall 126.

[0029] Optionally, the first lead 132 may include a third lateral portion 144 that forms an angled intersection with the first vertical portion 136 and extends laterally away from the first sidewall 124 of the package body 118. Similarly, the second lead 138 may include a fourth lateral portion 146 that forms an angled intersection with the second vertical portion 142 and extends laterally away from the second sidewall 126 of the package body 118. The third and fourth lateral portions 144, 146 may be parallel or nearly parallel to the lower side 122 of the package body 118. This lead configuration creates one example of a so-called "surface-mount" package type configuration. Other possible examples of so-called "surface mount packages" are J and C type lead configurations. In another example, the third and fourth lateral portions 144, 146 may be omitted, and optionally, the first and second vertical portions 136, 142 may extend beyond the lower side 122 of the package body 118. This lead configuration creates a so-called "through-hole" package type configuration. More generally, the semiconductor device package 100 may have any bent lead configuration.

[0030] The first lateral portion 134 of the first lead 132 is vertically offset from the second lateral portion 140 of the second lead 138. This means that a distance 148 between the first lateral portion 134 and the underside 122 of the encapsulation body 118 is different from a distance 150 between the second lateral portion 140 and the underside 122 of the encapsulation body 118. The distance 148 between the first lateral portion 134 and the underside 122 of the encapsulation body 118 is measured from a location 149 where the lower surface of the first lateral portion 134 intersects the first sidewall 124. The distance 150 between the second lateral portion 140 and the underside 122 of the encapsulation body 118 is measured from a location 151 where the lower surface of the second lateral portion 138 intersects the second sidewall 126.

[0031] In the depicted embodiment, the leads 116 are vertically offset such that the first lateral portion 134 of the first lead 132 is vertically spaced farther from the underside 122 of the enclosure body 118 than the second lateral portion 140 of the second lead 138 is vertically spaced farther from the underside 122 of the enclosure body 118 .

[0032] In the depicted embodiment, the first lateral portion 134 intersects the first sidewall 124 at an upper corner of the packaged semiconductor device 100. In other words, the first lateral portion 134 is vertically spaced as close as possible to the upper side 120 of the encapsulation body 118. In the case where the first lateral portion 134 is oriented parallel to the upper side 120 of the encapsulation body 118, this means that the upper surface of the first lateral portion 134 is coplanar with the upper side 120 of the encapsulation body 118.

[0033] According to an embodiment, the second lateral portion 140 intersects the second sidewall 126 approximately around the center of the second sidewall 126. This means that the upper surface of the second lateral portion 140 is vertically offset from the upper side 120 of the enclosure body 118 by approximately the same distance as the lower surface of the second lateral portion 140 is vertically offset from the lower side 122 of the enclosure body 118. More generally, the second lateral portion 140 can intersect the second sidewall 126 at any location that is vertically offset from the intersection between the first lateral portion 134 and the first sidewall 124.

[0034] According to an embodiment, the vertical displacement of the first lead 132 is greater than the vertical displacement of the second lead 138. This means that the distance between the uppermost surface 152 of the first lead 132 and the lowermost surface 154 of the first lead 132 (measured in the vertical direction (V)) is greater than the distance between the uppermost surface 156 of the second lead 138 and the lowermost surface 158 of the second lead 138 (measured in the vertical direction (V)). In the depicted embodiment, the vertical displacement of the first lead 132 is attributable to the vertical extension of the first vertical portion 136 of the first lead 132, and the vertical displacement of the second lead 138 is attributable to the vertical extension of the second vertical portion 142 of the second lead 138. The difference in vertical extension creates a different vertical displacement because other portions of the lead 116 do not have any vertical component. More generally, the vertical displacement of any portion of the leads may be tailored so that both the first and second leads 136 , 138 extend to at least the underside 122 of the encapsulation body 118 .

[0035] The die pad includes first and second vertical edge sides 160, 162, which are opposite to each other and extend between the die attach surface 128 and the outer surface 130. The first vertical edge side 160 is exposed from the first side wall 124 of the encapsulation body 118. That is, the die pad 114 extends laterally from within the encapsulation body 118 to at least reach the first side wall 124. For example, the first vertical edge side 160 can be substantially coplanar with the first side wall. Alternatively, the first vertical edge side 160 can extend beyond the first side wall. A second vertical edge side 162 of the die pad 114, which is opposite to the first vertical edge side 160, is insulated from the second side wall 126 by a portion of the electrically insulating encapsulation body 118. That is, the die pad 114 does not extend laterally from within the encapsulation body 118 to reach the second side wall 126.

[0036] According to an embodiment, the die attach surface 128 is a substantially planar surface that extends completely from the second vertical edge side 162 to the first sidewall 124 of the encapsulation body 118 along a single plane. Thus, the available area for mounting the semiconductor die 102 extends completely from the second vertical edge side 162 of the die pad 114 to the first sidewall 124 of the encapsulation body 118. As a result, the semiconductor device package 100 provides improved space efficiency compared to so-called recessed configurations that require lateral areas on either side of the encapsulated die pad 114 for wire and wire bonding connections. In fact, as shown in the figure, the semiconductor die 102 can be positioned very close to the first sidewall 124. The distance between the semiconductor die 102 and the first sidewall 124 is only limited by the amount of distance required to form the encapsulation material between the semiconductor die 102 and the first sidewall 124, which is a function of the molding process.

[0037] In the depicted embodiment, the thickness of the die pad 114 is substantially uniform along the lateral portion extending from the second vertical edge side 162 to the first vertical edge side 160. That is, the die pad 114 is provided by a piece of conductive material of substantially uniform thickness. This can be viewed as a "single gauge" design. The thickness of the die pad 114 refers to the distance between the die attachment surface 128 and the outer surface 130 measured in the vertical direction (V). In this embodiment, the outer surface 130 of the die pad 114 extends completely from the second vertical edge side 162 to the first side wall 124 of the encapsulation body 118. As a result, the available cooling surface area of ​​the design is advantageously increased compared to conventional designs in which the encapsulation material is provided between the heat sink and the package edge at the surface (e.g., for adhesion to the heat sink).

[0038] Reference Figure 2 , Figure 2 Reference is shown from different top side angles Figure 1 1. The semiconductor device package 100 is described as an embodiment of the semiconductor device package 100. It can be seen that the semiconductor device package 100 includes an integrally formed conductive structure 164 disposed at the upper side 120 of the package body 118. The integrally formed conductive structure 164 provides a die pad 114 for mounting the semiconductor die 102, as previously described with reference to FIG. Figure 11 and 12. In addition, the integrally formed structure provides a plurality of first leads 132 of the same shape extending away from the first side wall 124 of the encapsulation body 118. Since each of these first leads 132 is part of the same structure, they provide a single package terminal (e.g., drain) of the packaged semiconductor device 100. In this example, the integrally formed conductive structure 164 is configured so that the first vertical edge side 160 extends beyond the first side wall 124 of the encapsulation body 118. The semiconductor device package 100 further includes a plurality of second leads 138 of the same shape extending away from the second side wall 126 of the encapsulation body 118. Each of these second leads 138 is separated from the die pad 114, and they are separated from each other. That is, the first lateral portion 134 of each of these leads extends into the encapsulation body 118, is encapsulated by the encapsulation material, and is electrically insulated from other lead portions and from the integrally formed conductive structure 164 by the molding material. As a result, different ones of the second leads 138 may provide different package terminals (eg, source and drain) by using bonding wires.

[0039] Reference Figure 3 , Figure 3 A semiconductor device package 100 according to another embodiment is depicted. The semiconductor device package 100 is similar to the semiconductor device package 100 of FIG. Figure 1 The semiconductor device packages 100 described are identical except for the configuration of the die pad 114. However Figure 1 Embodiments include a die pad 114 having a so-called "single gauge" design, Figure 3 An embodiment includes a die pad 114 having a so-called "double gauge" design. According to this design, the die pad 114 includes a thicker central portion 166 and a thinner first outer portion 168. The central portion 166 extends laterally from the second vertical edge side 162 to the first outer portion 168. The first outer portion 168 extends laterally from the central portion 166 to the first vertical edge side 160. The central portion 166 has a greater thickness than the first outer portion 168. According to an embodiment, the central portion 166 has a uniform thickness that is greater than the uniform thickness of the outer portions 168. The thickness of the outer portion 168 can be substantially similar or identical to the thickness of the first lead 132. In this embodiment, the outer surface 130 of the die pad 114 is exposed from the encapsulation body 118 at the central portion 166, and an area of ​​encapsulation material is provided between the first outer portion 168 and the upper side 120 of the encapsulation body 118.

[0040] Reference Figure 4 , Figure 4A lead frame 200 used in a method of forming a semiconductor device package 100 according to an embodiment is depicted. The lead frame 200 may be formed of a conductive material. Exemplary materials of the lead frame 200 include metals such as copper, aluminum, nickel, iron, zinc, and the like, and alloys thereof. The lead frame 200 may be formed of a layer of sheet metal, and the features depicted and described herein may be formed using conventional techniques such as stamping and etching. The lead frame 200 may be part of a lead frame strip comprising a plurality of identically configured lead frames 200 so that a plurality of semiconductor device packages 100 may be formed in parallel.

[0041] The lead frame 200 includes a first lead frame portion 202. The first lead frame portion 202 includes the die pad 114 described previously. The die pad 114 may have a Figure 1 The "single-gauge configuration" described or previously referred to Figure 3 The "double-regular" configuration described. In addition, the first lead frame portion 202 includes a first group 206 of leads 116. The first group 206 of leads is defined by regularly spaced windows in the first lead frame portion 202. The first group 206 of leads is directly connected to the die pad 114 at the first vertical edge side 160 of the die pad 114. In this example, the first group 206 of leads 116 and the die pad 114 are part of a continuous structure formed as a whole. The first group 206 of leads extends away from a first side of the die pad 114.

[0042] The lead frame 200 further includes a second lead frame portion 204. The second lead frame portion 204 includes a second group 208 of leads. The second group 208 of leads are defined by regularly spaced windows in the second lead frame portion 204. The second lead frame portion 204 further includes a baffle portion 210 that spans the regularly spaced windows. The second lead frame portion 204 is arranged to be laterally spaced from the die pad 114. That is, a gap is provided between the die pad 114 and the end of the second lead frame portion 204 so that the two structures do not contact each other. The second lead frame portion 204 is arranged so that the second group 208 of leads extend away from the second vertical edge side 162 of the die pad 114. That is, the second lead frame portion 204 is arranged so that the second group 208 of leads extend away from the die pad 114 in a direction opposite to the first group 206 of leads.

[0043] Reference Figure 5 , the semiconductor die 102 is mounted on the die pad 114 of the lead frame 200. The semiconductor die 102 is mounted with the gate and source terminals 110, 112 facing away from the die pad 114. In addition, the drain terminal 108 faces and is electrically connected to the die pad 114. This can be done using conductive bonding techniques such as diffusion solder, glue bonding, etc.

[0044] Reference Figure 6 , the semiconductor die 102 is electrically connected to the second set 208 of leads. More specifically, the first set 210 of bonding wires electrically connects the source terminal 110 of the semiconductor die 102 to a plurality of leads in the second set 208 of leads. The second bonding wire 212 electrically connects the gate terminal 112 of the semiconductor die 102 to one of the leads in the second set 208 of leads that is isolated from the other leads. The bonding wires of the first and second sets 210, 212 may be formed and attached according to known techniques.

[0045] Reference Figure 7 ,from Figure 6 The cross section AA' identified in FIG. 1 shows the lead frame 200. The lead frame 200 has been positioned so that the second lead frame portion 204 is vertically offset from the first lead frame portion 202. The vertical offset may correspond to the vertical offset distance between the first lateral portion 134 of the first lead 132 and the second lateral portion 140 of the second lead 138, as previously described. The vertical offset is provided at any time prior to encapsulation of the semiconductor die 102 in the process discussed immediately below.

[0046] Reference Figure 8 , performing an encapsulation process. According to the technology, an electrically insulating encapsulant material 214 is formed on the first lead frame portion 202 to encapsulate the semiconductor die 102 and the bonding wires. The electrically insulating encapsulant material 214 is formed to have the geometry of the encapsulant body 118 as described above. This can be done according to any of a wide range of known techniques (including injection or transfer molding techniques). The encapsulant material 214 can include a wide range of various electrically insulating materials, such as ceramics, epoxy resin materials, and thermosetting plastics, to name just a few examples. The encapsulation process is performed so that the encapsulant material 214 covers a portion of the first lead frame portion 202 extending at least to the first edge side of the die pad 114. In addition, the encapsulation process is performed so that the encapsulant material 214 covers a portion of the second lead frame portion 204. In this way, the ends of the second group 208 leads are encapsulated by the encapsulant material 214 and adhered to the encapsulant material 214.

[0047] Reference Fig. 9 Specifically, the baffle portion 210 is cut across the regularly spaced windows. After the baffle trimming is performed, the lead trimming process can be performed, thereby Fig. 9 1 and 2. The first and second cut lines 216, 218 shown in FIG. 2 cut the first and second leadframe portions 202, 204. As a result, the device includes clearly defined leads extending away from either side of the encapsulation body 118. In addition, the leads connected to the gate terminal of the semiconductor die 102 are isolated from the other leads.

[0048] After performing the lead trimming process described above, a lead bending process may be performed. The lead bending process may be performed so that the first group 206 leads have the configuration of the first leads 132 described above. In addition, the lead bending process may also be performed so that the second group 208 leads may have the configuration of the second leads 138 described above.

[0049] An embodiment of a semiconductor device package includes a conductive die pad having a die attachment surface and an outer surface opposite to the die attachment surface. The semiconductor die is mounted on the die attachment surface. An encapsulation material encapsulates the semiconductor die, and the outer surface of the die pad is exposed on the upper side of the encapsulation material. A first lead directly contacts the die pad, extends away from a first side wall of the encapsulation material, and bends toward a lower side of the encapsulation material opposite to the upper side. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second side wall of the encapsulation material opposite to the first side wall, and bends toward the lower side of the encapsulation material. A first lateral portion of the first lead intersecting the first side wall is vertically offset from a second lateral portion of the second lead intersecting the second side wall.

[0050] According to an embodiment that can be combined with any other embodiment, the first lead also includes a first vertical portion forming a bend intersecting the first lateral portion and extending vertically toward the lower side of the package, wherein the second lead also includes a second vertical portion forming a bend intersecting the second lateral portion and extending vertically toward the lower side of the package, wherein the vertical extension of the first vertical portion is greater than the vertical extension of the second vertical portion.

[0051] According to an embodiment that can be combined with any other embodiment, the first lateral portion intersects the first side wall at an upper corner of the packaged device so that the upper surface of the first lead in the first lateral portion is coplanar with the upper side of the encapsulation material, and wherein the second lateral portion intersects the second side wall so that the upper surface of the second lead in the second lateral portion is vertically offset from the upper side of the encapsulation material.

[0052] According to an embodiment which can be combined with any other embodiment, the die pad comprises first and second vertical edge sides opposite to each other and extending between the die attach surface and the outer surface, and wherein the first vertical edge side is exposed from the first sidewall of the encapsulation material. According to any embodiment of the semiconductor device package, the second vertical edge side is insulated from the second sidewall by a portion of the encapsulation material, and wherein the die attach surface extends completely from the second vertical edge side to the first sidewall of the encapsulation material along a single plane. According to an embodiment of the semiconductor device package, the first lateral portion of the first lead and the die pad are integrally formed together.

[0053] According to an embodiment which can be combined with any other embodiment, a thickness of the die pad is substantially uniform along a lateral portion extending from the second vertical edge side to the first sidewall.

[0054] According to an embodiment which can be combined with any other embodiment, the die pad comprises a central portion and a first outer portion extending laterally from the central portion to the first sidewall of the encapsulation material, wherein the die pad has a greater thickness in the central portion than in the first outer portion.

[0055] According to an embodiment that can be combined with any other embodiment, the semiconductor die includes a first terminal directly facing the die pad and electrically connected to the die pad, and a second terminal arranged on an opposite side of the semiconductor die opposite to the first terminal, and wherein a second lateral portion of the second lead is electrically connected to the second terminal of the semiconductor die through a conductive line.

[0056] An embodiment of a semiconductor device package includes a semiconductor die. An encapsulation material encapsulates the semiconductor die. An integrally formed conductive structure provides a die pad and a first lead for the semiconductor device package. The second lead is partially encapsulated by the encapsulation material and is separated from the die pad. The semiconductor die includes a first terminal facing the die pad and electrically connected to the die pad and a second terminal facing away from the die pad and electrically connected to the second lead. The first and second leads intersect with the first and second side walls of the encapsulation material facing opposite directions at positions vertically offset from each other.

[0057] According to an embodiment, which can be combined with any other embodiment, a vertical displacement of the first lead is greater than a vertical displacement of the second lead.

[0058] According to an embodiment which can be combined with any other embodiment, the integrally formed conductive structure comprises a substantially uniform thickness portion providing the die pad and a first lateral portion of the first lead intersecting the first sidewall and extending away from the first sidewall.

[0059] According to an embodiment, which can be combined with any other embodiment, an outer surface of the substantially uniform thickness portion is exposed from the encapsulation material and is coplanar with an upper side of the encapsulation material.

[0060] According to an embodiment that can be combined with any other embodiment, the integrally formed conductive structure includes a thicker central portion and a thinner first outer portion, wherein an outer surface of the thicker central portion is exposed from the encapsulation material and is coplanar with an upper side of the encapsulation material, and wherein the thinner first outer portion extends to the first side wall.

[0061] According to an embodiment which can be combined with any other embodiment, the second lead is electrically connected to the second terminal by a conductive bonding wire.

[0062] An embodiment of a method for forming a semiconductor device package includes providing a conductive die pad having a die attachment surface and an outer surface opposite to the die attachment surface. A semiconductor die is mounted on the die attachment surface. An encapsulation material is formed, the encapsulation material encapsulates the semiconductor die, and the outer surface of the die pad is exposed on the upper side of the encapsulation material. A first lead is provided, the first lead directly contacts the die pad, extends away from a first side wall of the encapsulation material, and bends toward a lower side of the encapsulation material opposite to the upper side. A second lead is provided, the second lead is electrically connected to a terminal of the semiconductor die, extends away from a second side wall of the encapsulation material opposite to the first side wall, and bends toward the lower side of the encapsulation material.

[0063] According to an embodiment that can be combined with any other embodiment, forming a semiconductor device package includes providing a single lead frame including a first lead frame portion and a second lead frame portion, the first lead frame portion including a die pad and a first group of leads connected to and extending away from a first side of the die pad, the second lead frame portion including a second group of leads; and arranging the second lead frame portion to be laterally spaced apart from the die pad so that the second group of leads extend away from a second side of the die pad opposite to the first side; wherein the first lead is provided from the first group of leads, and wherein the second lead is provided from the second group of leads.

[0064] According to an embodiment, which can be combined with any other embodiment, the second leadframe portion is vertically offset from the first leadframe portion during the forming of the encapsulation material.

[0065] According to an embodiment that can be combined with any other embodiment, after mounting the semiconductor die to the die attachment surface, the method also includes providing a conductive bonding wire that electrically connects a terminal of the semiconductor die to a second lead; and forming an encapsulation material on the lead frame so that the encapsulation material encapsulates the bonding wire and extends to the first side of the die pad and the second group of leads.

[0066] According to an embodiment that can be combined with any other embodiment, after forming the electrically insulating encapsulation material, the method also includes bending the first lead so that the first lead includes a first vertical portion that forms a bend intersecting the first lateral portion and extending toward the lower side of the package; and bending the second lead so that the second lead includes a second vertical portion that forms a bend intersecting the second lateral portion and extending toward the lower side of the package, and wherein the vertical extension of the first vertical portion is greater than the vertical extension of the second vertical portion.

[0067] The term "substantially" includes absolute compliance as well as minor deviations from absolute compliance due to manufacturing process variations, assembly, and other factors that may cause deviations from the ideal. The term "substantially" includes any such deviations as long as the deviations are within process tolerances to achieve practical compliance and the components described herein are able to operate according to the application requirements.

[0068] In the context of this specification, the terms "heat sink" or "heat plate" or "heat sink" are interchangeable and each refers to a thermally conductive element configured to draw heat away from a heat source (eg, an active semiconductor die).

[0069] Spatially relative terms (e.g., "under," "below," "lower," "above," "above," "upper," etc.) are used for convenience of description to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device in addition to orientations that are different from those depicted in the figures. In addition, terms such as "first," "second," etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the description, similar terms refer to similar elements.

[0070] As used herein, the terms "having", "containing", "including", "comprising", etc. are open terms indicating the presence of stated elements or features, but do not exclude more elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0071] It will be appreciated that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0072] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent embodiments may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adjustments or changes to the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device package, comprising: a die pad comprising a die attach surface and an outer surface opposite the die attach surface; a semiconductor die mounted on the die attach surface; an encapsulant material encapsulating the semiconductor die and exposing the outer surface of the die pad at an upper side of the encapsulant material; a first lead directly contacting the die pad, extending away from a first sidewall of the encapsulation material, and bending toward a lower side of the encapsulation material opposite the upper side; as well as a second lead electrically connected to a terminal of the semiconductor die, extending away from a second sidewall of the encapsulation material opposite the first sidewall, and bending toward the underside of the encapsulation material; wherein a first lateral portion of the first lead intersecting the first side wall is vertically offset from a second lateral portion of the second lead intersecting the second side wall, wherein the die pad comprises a first vertical edge side and a second vertical edge side opposite to each other and extending between the die attach surface and the outer surface, and wherein the first vertical edge side is exposed from the first sidewall of the encapsulation material, and Wherein, the die attach surface extends completely along a single plane from the second vertical edge side to the first sidewall of the encapsulation material.

2. The semiconductor device package according to claim 1, wherein: The first lead also includes a first vertical portion that forms a bend that intersects the first lateral portion and extends vertically toward the lower side of the package, wherein the second lead also includes a second vertical portion that forms a bend that intersects the second lateral portion and extends vertically toward the lower side of the package, and wherein the vertical extension of the first vertical portion is greater than the vertical extension of the second vertical portion.

3. The semiconductor device package according to claim 2, wherein: The first lateral portion intersects the first side wall at an upper corner of the package so that an upper surface of the first lead in the first lateral portion is coplanar with the upper side of the encapsulation material, and wherein the second lateral portion intersects the second side wall so that an upper surface of the second lead in the second lateral portion is vertically offset from the upper side of the encapsulation material.

4. The semiconductor device package according to claim 1, wherein: The second vertical edge side is insulated from the second sidewall by portions of the encapsulation material.

5. The semiconductor device package according to claim 4, wherein: The first lateral portion of the first lead and the die pad are integrally formed together.

6. The semiconductor device package according to claim 4, wherein: The thickness of the die pad is substantially uniform along a lateral portion extending from the second vertical edge side to the first sidewall.

7. The semiconductor device package according to claim 4, wherein: The die pad includes a central portion and a first outer portion extending laterally from the central portion to the first sidewall of the encapsulation material, wherein a thickness of the die pad in the central portion is greater than a thickness of the die pad in the first outer portion.

8. The semiconductor device package according to claim 1, wherein: The semiconductor die includes a first terminal directly facing the die pad and electrically connected to the die pad, and a second terminal arranged on a side of the semiconductor die opposite to the first terminal, and wherein the second lateral portion of the second lead is an encapsulation material electrically connected to the second terminal of the semiconductor die through a conductive wire.

9. A semiconductor device package, comprising: Semiconductor die; an encapsulant material encapsulating the semiconductor die; an integrally formed conductive structure providing a die pad and a first lead for the semiconductor device package, wherein the die pad includes a die attach surface and an outer surface opposite the die attach surface, the semiconductor die being mounted on the die attach surface; a second lead partially encapsulated by the encapsulation material and separated from the die pad; wherein the semiconductor die comprises a first terminal facing the die pad and electrically connected to the die pad and a second terminal facing away from the first terminal and electrically connected to the second lead, wherein the first lead and the second lead intersect with a first side wall and a second side wall of the encapsulation material facing opposite directions at positions vertically offset from each other, respectively, wherein the die pad comprises a first vertical edge side and a second vertical edge side opposite to each other and extending between the die attach surface and the outer surface, and wherein the first vertical edge side is exposed from the first sidewall of the encapsulation material, and Wherein, the die attach surface extends completely along a single plane from the second vertical edge side to the first sidewall of the encapsulation material.

10. The semiconductor device package according to claim 9, wherein: The vertical offset of the first lead is greater than the vertical offset of the second lead.

11. The semiconductor device package according to claim 9, wherein: The integrally formed conductive structure includes a substantially uniform thickness portion providing a first lateral portion of the die pad and the first lead that intersects the first sidewall and extends away from the first sidewall.

12. The semiconductor device package according to claim 11, wherein: An outer surface of the substantially uniform thickness portion is exposed from the enclosure material and is coplanar with an upper side of the enclosure material.

13. The semiconductor device package according to claim 9, wherein: The integrally formed conductive structure includes a thicker central portion and a thinner first outer portion, wherein an outer surface of the thicker central portion is exposed from the encapsulation material and is coplanar with an upper side of the encapsulation material, and wherein the thinner first outer portion extends to the first sidewall.

14. The semiconductor device package according to claim 13, wherein: The second lead is electrically connected to the second terminal through a conductive bonding wire.

15. A method of forming a semiconductor device package, the method comprising: providing an electrically conductive die pad including a die attach surface and an outer surface opposite the die attach surface; mounting a semiconductor die on the die attach surface; forming an encapsulant material, the encapsulant material encapsulating the semiconductor die and exposing the outer surface of the die pad at an upper side of the encapsulant material; providing a first lead directly contacting the die pad, extending away from a first sidewall of the encapsulation material, and bending toward a lower side of the encapsulation material opposite the upper side; and providing a second lead electrically connected to a terminal of the semiconductor die, extending away from a second sidewall of the encapsulation material opposite the first sidewall, and bending toward the underside of the encapsulation material; wherein the first lead includes a first lateral portion intersecting the first side wall, wherein the second lead includes a second lateral portion intersecting the second side wall, and wherein the first lead and the second lead are provided such that the first lateral portion and the second lateral portion are vertically offset from each other, wherein the die pad comprises a first vertical edge side and a second vertical edge side opposite to each other and extending between the die attach surface and the outer surface, and wherein the first vertical edge side is exposed from the first sidewall of the encapsulation material, and Wherein, the die attach surface extends completely along a single plane from the second vertical edge side to the first sidewall of the encapsulation material.

16. The method according to claim 15, wherein: Forming the semiconductor device package includes: providing a single lead frame including a first lead frame portion including the die pad and a first set of leads connected to a first side of the die pad and extending away from the first side of the die pad, and a second lead frame portion including a second set of leads, disposing the second lead frame portion to be laterally spaced apart from the die pad such that the second set of leads extends away from a second side of the die pad opposite the first side; wherein the first lead is provided from the first set of leads, and Wherein, the second lead is provided from the second group of leads.

17. The method according to claim 16, wherein: During formation of the encapsulation material, the second leadframe portion is vertically offset from the first leadframe portion.

18. The method of claim 16, further comprising, after mounting the semiconductor die to the die attach surface: electrically providing a conductive bond wire electrically connecting the terminal of the semiconductor die to the second lead; and The encapsulation material is formed on the lead frame such that the encapsulation material encapsulates the bond wires and extends to the first side of the die pad and the second set of leads.

19. The method according to claim 18, further comprising, after forming the encapsulation material: bending the first lead so that the first lead includes a first vertical portion forming a bend intersecting the first lateral portion and extending toward the underside of the package; and bending the second lead so that the second lead includes a second vertical portion forming a bend intersecting the second lateral portion and extending toward the underside of the package, and in, The vertical extension of the first vertical portion is greater than the vertical extension of the second vertical portion.

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